2 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
4 FILE_LICENCE ( GPL2_OR_LATER );
6 /* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
7 #define LINUX_OUT_MACROS
11 #include <ipxe/ethernet.h>
15 /* Condensed operations for readability */
16 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
17 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
19 #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
20 #define RX_RING_SIZE 2
22 #define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
30 #define EPIC_DEBUG 0 /* debug level */
32 /* The EPIC100 Rx and Tx buffer descriptors. */
35 unsigned long bufaddr;
36 unsigned long buflength;
39 /* description of the tx descriptors control bits commonly used */
40 #define TD_STDFLAGS TD_LASTDESC
44 unsigned long bufaddr;
45 unsigned long buflength;
49 #define delay(nanosec) do { int _i = 3; while (--_i > 0) \
50 { __SLOW_DOWN_IO; }} while (0)
52 static void epic100_open(void);
53 static void epic100_init_ring(void);
54 static void epic100_disable(struct nic *nic);
55 static int epic100_poll(struct nic *nic, int retrieve);
56 static void epic100_transmit(struct nic *nic, const char *destaddr,
57 unsigned int type, unsigned int len, const char *data);
59 static int read_eeprom(int location);
61 static int mii_read(int phy_id, int location);
62 static void epic100_irq(struct nic *nic, irq_action_t action);
64 static struct nic_operations epic100_operations;
84 static unsigned int cur_rx, cur_tx; /* The next free ring entry */
86 static unsigned short eeprom[64];
88 static signed char phys[4]; /* MII device addresses. */
90 struct epic_rx_desc rx_ring[RX_RING_SIZE]
91 __attribute__ ((aligned(4)));
92 struct epic_tx_desc tx_ring[TX_RING_SIZE]
93 __attribute__ ((aligned(4)));
94 unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
95 unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
96 } epic100_bufs __shared;
97 #define rx_ring epic100_bufs.rx_ring
98 #define tx_ring epic100_bufs.tx_ring
99 #define rx_packet epic100_bufs.rx_packet
100 #define tx_packet epic100_bufs.tx_packet
102 /***********************************************************************/
103 /* Externally visible functions */
104 /***********************************************************************/
108 epic100_probe ( struct nic *nic, struct pci_device *pci ) {
112 unsigned int phy, phy_idx;
114 if (pci->ioaddr == 0)
117 /* Ideally we would detect all network cards in slot order. That would
118 be best done a central PCI probe dispatch, which wouldn't work
119 well with the current structure. So instead we detect just the
120 Epic cards in slot order. */
122 ioaddr = pci->ioaddr;
125 nic->ioaddr = pci->ioaddr & ~3;
127 /* compute all used static epic100 registers address */
128 command = ioaddr + COMMAND; /* Control Register */
129 intstat = ioaddr + INTSTAT; /* Interrupt Status */
130 intmask = ioaddr + INTMASK; /* Interrupt Mask */
131 genctl = ioaddr + GENCTL; /* General Control */
132 eectl = ioaddr + EECTL; /* EEPROM Control */
133 test = ioaddr + TEST; /* Test register (clocks) */
134 mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
135 mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
136 lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
137 mc0 = ioaddr + MC0; /* Multicast Control */
138 rxcon = ioaddr + RXCON; /* Receive Control */
139 txcon = ioaddr + TXCON; /* Transmit Control */
140 prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
141 ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
142 eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
144 /* Reset the chip & bring it out of low-power mode. */
145 outl(GC_SOFT_RESET, genctl);
147 /* Disable ALL interrupts by setting the interrupt mask. */
148 outl(INTR_DISABLE, intmask);
151 * set the internal clocks:
152 * Application Note 7.15 says:
153 * In order to set the CLOCK TEST bit in the TEST register,
154 * perform the following:
156 * Write 0x0008 to the test register at least sixteen
159 * The CLOCK TEST bit is Write-Only. Writing it several times
160 * consecutively insures a successful write to the bit...
163 for (i = 0; i < 16; i++) {
164 outl(0x00000008, test);
169 unsigned short sum = 0;
170 unsigned short value;
171 for (i = 0; i < 64; i++) {
172 value = read_eeprom(i);
179 printf("EEPROM contents\n");
180 for (i = 0; i < 64; i++) {
181 printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
186 /* This could also be read from the EEPROM. */
187 ap = (unsigned short*)nic->node_addr;
188 for (i = 0; i < 3; i++)
189 *ap++ = inw(lan0 + i*4);
191 DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
193 /* Find the connected MII xcvrs. */
194 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
195 int mii_status = mii_read(phy, 0);
197 if (mii_status != 0xffff && mii_status != 0x0000) {
198 phys[phy_idx++] = phy;
200 printf("MII transceiver found at address %d.\n", phy);
206 printf("***WARNING***: No MII transceiver found!\n");
208 /* Use the known PHY address of the EPII. */
213 nic->nic_op = &epic100_operations;
218 static void set_rx_mode(void)
220 unsigned char mc_filter[8];
222 memset(mc_filter, 0xff, sizeof(mc_filter));
224 for(i = 0; i < 4; i++)
225 outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
237 /* Pull the chip out of low-power mode, and set for PCI read multiple. */
238 outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
240 outl(TX_FIFO_THRESH, eththr);
242 tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
244 mii_reg5 = mii_read(phys[0], 5);
245 if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
246 printf(" full-duplex mode");
247 tmp |= TC_LM_FULL_DPX;
253 /* Give address of RX and TX ring to the chip */
254 outl(virt_to_le32desc(&rx_ring), prcdar);
255 outl(virt_to_le32desc(&tx_ring), ptcdar);
257 /* Start the chip's Rx process: receive unicast and broadcast */
259 outl(CR_START_RX | CR_QUEUE_RX, command);
264 /* Initialize the Rx and Tx rings. */
266 epic100_init_ring(void)
272 for (i = 0; i < RX_RING_SIZE; i++) {
273 rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
274 rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
275 rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
276 rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
278 /* Mark the last entry as wrapping the ring. */
279 rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
282 *The Tx buffer descriptor is filled in as needed,
283 * but we do need to clear the ownership bit.
286 for (i = 0; i < TX_RING_SIZE; i++) {
287 tx_ring[i].status = 0x0000; /* Owned by CPU */
288 tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
289 tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
290 tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
292 tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
295 /* function: epic100_transmit
296 * This transmits a packet.
298 * Arguments: char d[6]: destination ethernet address.
299 * unsigned short t: ethernet protocol type.
300 * unsigned short s: size of the data-part of the packet.
301 * char *p: the data for the packet.
305 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
306 unsigned int len, const char *data)
308 unsigned short nstype;
313 /* Calculate the next Tx descriptor entry. */
314 entry = cur_tx % TX_RING_SIZE;
316 if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
317 printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
318 tx_ring[entry].status);
324 txp = tx_packet + (entry * PKT_BUF_SZ);
326 memcpy(txp, destaddr, ETH_ALEN);
327 memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
328 nstype = htons(type);
329 memcpy(txp + 12, (char*)&nstype, 2);
330 memcpy(txp + ETH_HLEN, data, len);
334 while(len < ETH_ZLEN)
337 * Caution: the write order is important here,
338 * set the base address with the "ownership"
342 tx_ring[entry].buflength |= cpu_to_le32(len);
343 tx_ring[entry].status = cpu_to_le32(len << 16) |
344 cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
348 /* Trigger an immediate transmit demand. */
349 outl(CR_QUEUE_TX, command);
352 /* timeout 10 ms for transmit */
353 while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
354 ct + 10*1000 < currticks())
357 if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
358 printf("Oops, transmitter timeout, status=%4.4lX\n",
359 tx_ring[entry].status);
362 /* function: epic100_poll / eth_poll
363 * This receives a packet from the network.
367 * returns: 1 if a packet was received.
368 * 0 if no packet was received.
370 * returns the packet in the array nic->packet.
371 * returns the length of the packet in nic->packetlen.
375 epic100_poll(struct nic *nic, int retrieve)
379 unsigned long status;
380 entry = cur_rx % RX_RING_SIZE;
382 if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
385 if ( ! retrieve ) return 1;
387 status = le32_to_cpu(rx_ring[entry].status);
388 /* We own the next entry, it's a new packet. Send it up. */
391 printf("epic_poll: entry %d status %hX\n", entry, status);
395 if (status & 0x2000) {
396 printf("epic_poll: Giant packet\n");
398 } else if (status & 0x0006) {
399 /* Rx Frame errors are counted in hardware. */
400 printf("epic_poll: Frame received with errors\n");
403 /* Omit the four octet CRC from the length. */
404 nic->packetlen = (status >> 16) - 4;
405 memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
409 /* Clear all error sources. */
410 outl(status & INTR_CLEARERRS, intstat);
412 /* Give the descriptor back to the chip */
413 rx_ring[entry].status = RRING_OWN;
415 /* Restart Receiver */
416 outl(CR_START_RX | CR_QUEUE_RX, command);
422 static void epic100_disable ( struct nic *nic __unused ) {
423 /* Soft reset the chip. */
424 outl(GC_SOFT_RESET, genctl);
427 static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
440 /* Serial EEPROM section. */
442 /* EEPROM_Ctrl bits. */
443 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
444 #define EE_CS 0x02 /* EEPROM chip select. */
445 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
446 #define EE_WRITE_0 0x01
447 #define EE_WRITE_1 0x09
448 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
449 #define EE_ENB (0x0001 | EE_CS)
451 /* The EEPROM commands include the alway-set leading bit. */
452 #define EE_WRITE_CMD (5 << 6)
453 #define EE_READ_CMD (6 << 6)
454 #define EE_ERASE_CMD (7 << 6)
456 #define eeprom_delay(n) delay(n)
459 read_eeprom(int location)
463 int read_cmd = location | EE_READ_CMD;
465 outl(EE_ENB & ~EE_CS, eectl);
468 /* Shift the read command bits out. */
469 for (i = 10; i >= 0; i--) {
470 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
471 outl(EE_ENB | dataval, eectl);
473 outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
475 outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
480 for (i = 16; i > 0; i--) {
481 outl(EE_ENB | EE_SHIFT_CLK, eectl);
483 retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
488 /* Terminate the EEPROM access. */
489 outl(EE_ENB & ~EE_CS, eectl);
496 #define MII_WRITEOP 2
499 mii_read(int phy_id, int location)
503 outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
504 /* Typical operation takes < 50 ticks. */
506 for (i = 4000; i > 0; i--)
507 if ((inl(mmctl) & MII_READOP) == 0)
512 static struct nic_operations epic100_operations = {
513 .connect = dummy_connect,
514 .poll = epic100_poll,
515 .transmit = epic100_transmit,
520 static struct pci_device_id epic100_nics[] = {
521 PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII", 0), /* SMC 83c170 EPIC/100 */
522 PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0),
525 PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
527 DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
528 epic100_probe, epic100_disable );