2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 FILE_LICENCE ( BSD2 );
36 /* Keep all ath9k files under one errfile ID */
38 #define ERRFILE ERRFILE_ath9k
40 #define ATHEROS_VENDOR_ID 0x168c
42 #define AR5416_DEVID_PCI 0x0023
43 #define AR5416_DEVID_PCIE 0x0024
44 #define AR9160_DEVID_PCI 0x0027
45 #define AR9280_DEVID_PCI 0x0029
46 #define AR9280_DEVID_PCIE 0x002a
47 #define AR9285_DEVID_PCIE 0x002b
48 #define AR2427_DEVID_PCIE 0x002c
49 #define AR9287_DEVID_PCI 0x002d
50 #define AR9287_DEVID_PCIE 0x002e
51 #define AR9300_DEVID_PCIE 0x0030
52 #define AR9300_DEVID_AR9340 0x0031
53 #define AR9300_DEVID_AR9485_PCIE 0x0032
55 #define AR5416_AR9100_DEVID 0x000b
57 #define AR_SUBVENDOR_ID_NOG 0x0e11
58 #define AR_SUBVENDOR_ID_NEW_A 0x7065
59 #define AR5416_MAGIC 0x19641014
61 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
62 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
63 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
65 #define AR9300_NUM_BT_WEIGHTS 4
66 #define AR9300_NUM_WLAN_WEIGHTS 4
68 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
70 #define ATH_DEFAULT_NOISE_FLOOR -95
72 #define ATH9K_RSSI_BAD -128
74 #define ATH9K_NUM_CHANNELS 38
76 /* Register read/write primitives */
77 #define REG_WRITE(_ah, _reg, _val) \
78 (_ah)->reg_ops.write((_ah), (_val), (_reg))
80 #define REG_READ(_ah, _reg) \
81 (_ah)->reg_ops.read((_ah), (_reg))
83 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
84 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
86 #define REG_RMW(_ah, _reg, _set, _clr) \
87 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
89 #define ENABLE_REGWRITE_BUFFER(_ah) \
91 if ((_ah)->reg_ops.enable_write_buffer) \
92 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 #define REGWRITE_BUFFER_FLUSH(_ah) \
97 if ((_ah)->reg_ops.write_flush) \
98 (_ah)->reg_ops.write_flush((_ah)); \
101 #define SM(_v, _f) (((_v) << _f##_S) & _f)
102 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
103 #define REG_RMW_FIELD(_a, _r, _f, _v) \
104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
105 #define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
107 #define REG_SET_BIT(_a, _r, _f) \
108 REG_RMW(_a, _r, (_f), 0)
109 #define REG_CLR_BIT(_a, _r, _f) \
110 REG_RMW(_a, _r, 0, (_f))
112 #define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
130 #define AR_GPIOD_MASK 0x00001FFF
131 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
133 #define BASE_ACTIVATE_DELAY 100
134 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
135 #define COEF_SCALE_S 24
136 #define HT40_CHANNEL_CENTER_SHIFT 10
138 #define ATH9K_ANTENNA0_CHAINMASK 0x1
139 #define ATH9K_ANTENNA1_CHAINMASK 0x2
141 #define ATH9K_NUM_DMA_DEBUG_REGS 8
142 #define ATH9K_NUM_QUEUES 10
144 #define MAX_RATE_POWER 63
145 #define AH_WAIT_TIMEOUT 100000 /* (us) */
146 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
147 #define AH_TIME_QUANTUM 10
148 #define AR_KEYTABLE_SIZE 128
149 #define POWER_UP_TIME 10000
150 #define SPUR_RSSI_THRESH 40
152 #define CAB_TIMEOUT_VAL 10
153 #define BEACON_TIMEOUT_VAL 10
154 #define MIN_BEACON_TIMEOUT_VAL 1
157 #define INIT_CONFIG_STATUS 0x00000000
158 #define INIT_RSSI_THR 0x00000700
159 #define INIT_BCON_CNTRL_REG 0x00000000
161 #define TU_TO_USEC(_tu) ((_tu) << 10)
163 #define ATH9K_HW_RX_HP_QDEPTH 16
164 #define ATH9K_HW_RX_LP_QDEPTH 128
166 #define PAPRD_GAIN_TABLE_ENTRIES 32
167 #define PAPRD_TABLE_SZ 24
169 enum ath_hw_txq_subtype {
173 enum ath_ini_subsys {
181 ATH9K_HW_CAP_HT = BIT(0),
182 ATH9K_HW_CAP_RFSILENT = BIT(1),
183 ATH9K_HW_CAP_CST = BIT(2),
184 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
185 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
186 ATH9K_HW_CAP_EDMA = BIT(6),
187 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
188 ATH9K_HW_CAP_LDPC = BIT(8),
189 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
190 ATH9K_HW_CAP_SGI_20 = BIT(10),
191 ATH9K_HW_CAP_PAPRD = BIT(11),
192 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
193 ATH9K_HW_CAP_2GHZ = BIT(13),
194 ATH9K_HW_CAP_5GHZ = BIT(14),
195 ATH9K_HW_CAP_APM = BIT(15),
198 struct ath9k_hw_capabilities {
199 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
212 int pcie_lcr_extsync_en;
215 struct ath9k_ops_config {
216 int dma_beacon_response_time;
217 int sw_beacon_response_time;
218 int additional_swba_backoff;
220 u32 cwm_ignore_extcca;
221 u8 pcie_powersave_enable;
232 int serialize_regmode;
233 int rx_intr_mitigation;
234 int tx_intr_mitigation;
235 #define SPUR_DISABLE 0
236 #define SPUR_ENABLE_IOCTL 1
237 #define SPUR_ENABLE_EEPROM 2
238 #define AR_SPUR_5413_1 1640
239 #define AR_SPUR_5413_2 1200
240 #define AR_NO_SPUR 0x8000
241 #define AR_BASE_FREQ_2GHZ 2300
242 #define AR_BASE_FREQ_5GHZ 4900
243 #define AR_SPUR_FEEQ_BOUND_HT40 19
244 #define AR_SPUR_FEEQ_BOUND_HT20 10
246 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
248 u16 ani_poll_interval; /* ANI poll interval in ms */
252 ATH9K_INT_RX = 0x00000001,
253 ATH9K_INT_RXDESC = 0x00000002,
254 ATH9K_INT_RXHP = 0x00000001,
255 ATH9K_INT_RXLP = 0x00000002,
256 ATH9K_INT_RXNOFRM = 0x00000008,
257 ATH9K_INT_RXEOL = 0x00000010,
258 ATH9K_INT_RXORN = 0x00000020,
259 ATH9K_INT_TX = 0x00000040,
260 ATH9K_INT_TXDESC = 0x00000080,
261 ATH9K_INT_TIM_TIMER = 0x00000100,
262 ATH9K_INT_BB_WATCHDOG = 0x00000400,
263 ATH9K_INT_TXURN = 0x00000800,
264 ATH9K_INT_MIB = 0x00001000,
265 ATH9K_INT_RXPHY = 0x00004000,
266 ATH9K_INT_RXKCM = 0x00008000,
267 ATH9K_INT_SWBA = 0x00010000,
268 ATH9K_INT_BMISS = 0x00040000,
269 ATH9K_INT_BNR = 0x00100000,
270 ATH9K_INT_TIM = 0x00200000,
271 ATH9K_INT_DTIM = 0x00400000,
272 ATH9K_INT_DTIMSYNC = 0x00800000,
273 ATH9K_INT_GPIO = 0x01000000,
274 ATH9K_INT_CABEND = 0x02000000,
275 ATH9K_INT_TSFOOR = 0x04000000,
276 ATH9K_INT_GENTIMER = 0x08000000,
277 ATH9K_INT_CST = 0x10000000,
278 ATH9K_INT_GTT = 0x20000000,
279 ATH9K_INT_FATAL = 0x40000000,
280 ATH9K_INT_GLOBAL = 0x80000000,
281 ATH9K_INT_BMISC = ATH9K_INT_TIM |
286 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
298 ATH9K_INT_NOCARD = 0xffffffff
301 #define CHANNEL_CW_INT 0x00002
302 #define CHANNEL_CCK 0x00020
303 #define CHANNEL_OFDM 0x00040
304 #define CHANNEL_2GHZ 0x00080
305 #define CHANNEL_5GHZ 0x00100
306 #define CHANNEL_PASSIVE 0x00200
307 #define CHANNEL_DYN 0x00400
308 #define CHANNEL_HALF 0x04000
309 #define CHANNEL_QUARTER 0x08000
310 #define CHANNEL_HT20 0x10000
311 #define CHANNEL_HT40PLUS 0x20000
312 #define CHANNEL_HT40MINUS 0x40000
314 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
315 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
316 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
317 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
318 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
319 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
320 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
321 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
322 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
323 #define CHANNEL_ALL \
332 struct ath9k_hw_cal_data {
340 int nfcal_interference;
341 u16 small_signal_gain[AR9300_MAX_CHAINS];
342 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
343 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
346 struct ath9k_channel {
347 struct net80211_channel *chan;
348 struct ar5416AniState ani;
355 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
356 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
357 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
358 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
359 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
360 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
361 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
362 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
363 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
364 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
365 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
366 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
368 /* These macros check chanmode and not channelFlags */
369 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
370 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
371 ((_c)->chanmode == CHANNEL_G_HT20))
372 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
373 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
374 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
375 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
376 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
378 enum ath9k_power_mode {
381 ATH9K_PM_NETWORK_SLEEP,
385 enum ath9k_tp_scale {
386 ATH9K_TP_SCALE_MAX = 0,
394 SER_REG_MODE_OFF = 0,
396 SER_REG_MODE_AUTO = 2,
399 enum ath9k_rx_qtype {
405 struct ath9k_beacon_state {
409 #define ATH9K_BEACON_PERIOD 0x0000ffff
410 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
413 u16 bs_cfpmaxduration;
416 u16 bs_bmissthreshold;
417 u32 bs_sleepduration;
418 u32 bs_tsfoor_threshold;
421 struct chan_centers {
428 ATH9K_RESET_POWER_ON,
433 struct ath9k_hw_version {
443 enum ath_usb_dev usbdev;
446 /* Generic TSF timer definitions */
448 #define ATH_MAX_GEN_TIMER 16
450 #define AR_GENTMR_BIT(_index) (1 << (_index))
453 * Using de Bruijin sequence to look up 1's index in a 32 bit number
454 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
456 #define debruijn32 0x077CB531U
458 struct ath_gen_timer_configuration {
465 struct ath_gen_timer {
466 void (*trigger)(void *arg);
467 void (*overflow)(void *arg);
472 struct ath_gen_timer_table {
473 u32 gen_timer_index[32];
474 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
476 unsigned long timer_bits;
481 struct ath_hw_antcomb_conf {
492 * struct ath_hw_radar_conf - radar detection initialization parameters
494 * @pulse_inband: threshold for checking the ratio of in-band power
495 * to total power for short radar pulses (half dB steps)
496 * @pulse_inband_step: threshold for checking an in-band power to total
497 * power ratio increase for short radar pulses (half dB steps)
498 * @pulse_height: threshold for detecting the beginning of a short
499 * radar pulse (dB step)
500 * @pulse_rssi: threshold for detecting if a short radar pulse is
502 * @pulse_maxlen: maximum pulse length (0.8 us steps)
504 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
505 * @radar_inband: threshold for checking the ratio of in-band power
506 * to total power for long radar pulses (half dB steps)
507 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
509 * @ext_channel: enable extension channel radar detection
511 struct ath_hw_radar_conf {
512 unsigned int pulse_inband;
513 unsigned int pulse_inband_step;
514 unsigned int pulse_height;
515 unsigned int pulse_rssi;
516 unsigned int pulse_maxlen;
518 unsigned int radar_rssi;
519 unsigned int radar_inband;
526 * struct ath_hw_private_ops - callbacks used internally by hardware code
528 * This structure contains private callbacks designed to only be used internally
529 * by the hardware core.
531 * @init_cal_settings: setup types of calibrations supported
532 * @init_cal: starts actual calibration
534 * @init_mode_regs: Initializes mode registers
535 * @init_mode_gain_regs: Initialize TX/RX gain registers
537 * @rf_set_freq: change frequency
538 * @spur_mitigate_freq: spur mitigation
539 * @rf_alloc_ext_banks:
540 * @rf_free_ext_banks:
542 * @compute_pll_control: compute the PLL control value to use for
543 * AR_RTC_PLL_CONTROL for a given channel
544 * @setup_calibration: set up calibration
545 * @iscal_supported: used to query if a type of calibration is supported
547 * @ani_cache_ini_regs: cache the values for ANI from the initial
548 * register settings through the register initialization.
550 struct ath_hw_private_ops {
551 /* Calibration ops */
552 void (*init_cal_settings)(struct ath_hw *ah);
553 int (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
555 void (*init_mode_regs)(struct ath_hw *ah);
556 void (*init_mode_gain_regs)(struct ath_hw *ah);
557 void (*setup_calibration)(struct ath_hw *ah,
558 struct ath9k_cal_list *currCal);
561 int (*rf_set_freq)(struct ath_hw *ah,
562 struct ath9k_channel *chan);
563 void (*spur_mitigate_freq)(struct ath_hw *ah,
564 struct ath9k_channel *chan);
565 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
566 void (*rf_free_ext_banks)(struct ath_hw *ah);
567 int (*set_rf_regs)(struct ath_hw *ah,
568 struct ath9k_channel *chan,
570 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
571 void (*init_bb)(struct ath_hw *ah,
572 struct ath9k_channel *chan);
573 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
574 void (*olc_init)(struct ath_hw *ah);
575 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
576 void (*mark_phy_inactive)(struct ath_hw *ah);
577 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
578 int (*rfbus_req)(struct ath_hw *ah);
579 void (*rfbus_done)(struct ath_hw *ah);
580 void (*restore_chainmask)(struct ath_hw *ah);
581 void (*set_diversity)(struct ath_hw *ah, int value);
582 u32 (*compute_pll_control)(struct ath_hw *ah,
583 struct ath9k_channel *chan);
584 int (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
586 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
587 void (*set_radar_params)(struct ath_hw *ah,
588 struct ath_hw_radar_conf *conf);
591 void (*ani_cache_ini_regs)(struct ath_hw *ah);
595 * struct ath_hw_ops - callbacks used by hardware code and driver code
597 * This structure contains callbacks designed to to be used internally by
598 * hardware code and also by the lower level driver.
600 * @config_pci_powersave:
601 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
604 void (*config_pci_powersave)(struct ath_hw *ah,
607 void (*rx_enable)(struct ath_hw *ah);
608 void (*set_desc_link)(void *ds, u32 link);
609 void (*get_desc_link)(void *ds, u32 **link);
610 int (*calibrate)(struct ath_hw *ah,
611 struct ath9k_channel *chan,
614 int (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
615 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
616 int is_firstseg, int is_is_lastseg,
617 const void *ds0, u32 buf_addr,
619 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
620 struct ath_tx_status *ts);
621 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
622 u32 pktLen, enum ath9k_pkt_type type,
623 u32 txPower, u32 keyIx,
624 enum ath9k_key_type keyType,
626 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
628 u32 durUpdateEn, u32 rtsctsRate,
630 struct ath9k_11n_rate_series series[],
631 u32 nseries, u32 flags);
632 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
634 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
636 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
637 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
638 void (*set_clrdmask)(struct ath_hw *ah, void *ds, int val);
639 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
640 struct ath_hw_antcomb_conf *antconf);
641 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
642 struct ath_hw_antcomb_conf *antconf);
646 struct ath_nf_limits {
653 #define AH_USE_EEPROM 0x1
654 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
657 struct ath_ops reg_ops;
659 struct net80211_device *dev;
660 struct ath_common common;
661 struct ath9k_hw_version hw_version;
662 struct ath9k_ops_config config;
663 struct ath9k_hw_capabilities caps;
664 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
665 struct ath9k_channel *curchan;
668 struct ar5416_eeprom_def def;
669 struct ar5416_eeprom_4k map4k;
670 struct ar9287_eeprom map9287;
671 struct ar9300_eeprom ar9300_eep;
673 const struct eeprom_ops *eep_ops;
678 int need_an_top2_fixup;
682 struct ath_nf_limits nf_2g;
683 struct ath_nf_limits nf_5g;
691 enum ath9k_power_mode power_mode;
693 struct ath9k_hw_cal_data *caldata;
694 struct ath9k_pacal_info pacal_info;
695 struct ar5416Stats stats;
696 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
698 int16_t curchan_rad_index;
700 enum ath9k_int imask;
702 u32 txok_interrupt_mask;
703 u32 txerr_interrupt_mask;
704 u32 txdesc_interrupt_mask;
705 u32 txeol_interrupt_mask;
706 u32 txurn_interrupt_mask;
712 struct ath9k_cal_list iq_caldata;
713 struct ath9k_cal_list adcgain_caldata;
714 struct ath9k_cal_list adcdc_caldata;
715 struct ath9k_cal_list tempCompCalData;
716 struct ath9k_cal_list *cal_list;
717 struct ath9k_cal_list *cal_list_last;
718 struct ath9k_cal_list *cal_list_curr;
719 #define totalPowerMeasI meas0.unsign
720 #define totalPowerMeasQ meas1.unsign
721 #define totalIqCorrMeas meas2.sign
722 #define totalAdcIOddPhase meas0.unsign
723 #define totalAdcIEvenPhase meas1.unsign
724 #define totalAdcQOddPhase meas2.unsign
725 #define totalAdcQEvenPhase meas3.unsign
726 #define totalAdcDcOffsetIOddPhase meas0.sign
727 #define totalAdcDcOffsetIEvenPhase meas1.sign
728 #define totalAdcDcOffsetQOddPhase meas2.sign
729 #define totalAdcDcOffsetQEvenPhase meas3.sign
731 u32 unsign[AR5416_MAX_CHAINS];
732 int32_t sign[AR5416_MAX_CHAINS];
735 u32 unsign[AR5416_MAX_CHAINS];
736 int32_t sign[AR5416_MAX_CHAINS];
739 u32 unsign[AR5416_MAX_CHAINS];
740 int32_t sign[AR5416_MAX_CHAINS];
743 u32 unsign[AR5416_MAX_CHAINS];
744 int32_t sign[AR5416_MAX_CHAINS];
748 u32 sta_id1_defaults;
754 } enable_32kHz_clock;
756 /* Private to hardware code */
757 struct ath_hw_private_ops private_ops;
758 /* Accessed by the lower level driver */
759 struct ath_hw_ops ops;
761 /* Used to program the radio on non single-chip devices */
762 u32 *analogBank0Data;
763 u32 *analogBank1Data;
764 u32 *analogBank2Data;
765 u32 *analogBank3Data;
766 u32 *analogBank6Data;
767 u32 *analogBank6TPCData;
768 u32 *analogBank7Data;
780 int totalSizeDesired[5];
784 enum ath9k_ani_cmd ani_function;
790 struct ath_hw_radar_conf radar_conf;
792 u32 originalGain[22];
799 struct ar5416IniArray iniModes;
800 struct ar5416IniArray iniCommon;
801 struct ar5416IniArray iniBank0;
802 struct ar5416IniArray iniBB_RfGain;
803 struct ar5416IniArray iniBank1;
804 struct ar5416IniArray iniBank2;
805 struct ar5416IniArray iniBank3;
806 struct ar5416IniArray iniBank6;
807 struct ar5416IniArray iniBank6TPC;
808 struct ar5416IniArray iniBank7;
809 struct ar5416IniArray iniAddac;
810 struct ar5416IniArray iniPcieSerdes;
811 struct ar5416IniArray iniPcieSerdesLowPower;
812 struct ar5416IniArray iniModesAdditional;
813 struct ar5416IniArray iniModesAdditional_40M;
814 struct ar5416IniArray iniModesRxGain;
815 struct ar5416IniArray iniModesTxGain;
816 struct ar5416IniArray iniModes_9271_1_0_only;
817 struct ar5416IniArray iniCckfirNormal;
818 struct ar5416IniArray iniCckfirJapan2484;
819 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
820 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
821 struct ar5416IniArray iniModes_9271_ANI_reg;
822 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
823 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
825 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
826 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
827 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
828 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
830 u32 intr_gen_timer_trigger;
831 u32 intr_gen_timer_thresh;
832 struct ath_gen_timer_table hw_gen_timers;
834 struct ar9003_txs *ts_ring;
841 unsigned int paprd_target_power;
842 unsigned int paprd_training_power;
843 unsigned int paprd_ratemask;
844 unsigned int paprd_ratemask_ht40;
845 int paprd_table_write_done;
846 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
847 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
849 * Store the permanent value of Reg 0x4004in WARegVal
850 * so we dont have to R/M/W. We should not be reading
851 * this register when in sleep states.
855 /* Enterprise mode cap */
862 enum ath_bus_type ath_bus_type;
863 void (*read_cachesize)(struct ath_common *common, int *csz);
864 int (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
865 void (*bt_coex_prep)(struct ath_common *common);
866 void (*extn_synch_en)(struct ath_common *common);
869 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
874 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
876 return &(ath9k_hw_common(ah)->regulatory);
879 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
881 return &ah->private_ops;
884 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
889 static inline u8 get_streams(int mask)
891 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
894 /* Initialization, Detach, Reset */
895 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
896 void ath9k_hw_deinit(struct ath_hw *ah);
897 int ath9k_hw_init(struct ath_hw *ah);
898 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
899 struct ath9k_hw_cal_data *caldata, int bChannelChange);
900 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
901 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
903 /* GPIO / RFKILL / Antennae */
904 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
905 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
906 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
908 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
909 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
910 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
912 /* General Operation */
913 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
914 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
915 int column, unsigned int *writecnt);
916 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
917 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
919 u32 frameLen, u16 rateix, int shortPreamble);
920 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
921 struct ath9k_channel *chan,
922 struct chan_centers *centers);
923 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
924 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
925 int ath9k_hw_phy_disable(struct ath_hw *ah);
926 int ath9k_hw_disable(struct ath_hw *ah);
927 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test);
928 void ath9k_hw_setopmode(struct ath_hw *ah);
929 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
930 void ath9k_hw_setbssidmask(struct ath_hw *ah);
931 void ath9k_hw_write_associd(struct ath_hw *ah);
932 void ath9k_hw_init_global_settings(struct ath_hw *ah);
933 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
934 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
935 int ath9k_hw_check_alive(struct ath_hw *ah);
937 int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
939 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
942 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
945 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
946 u32 *coef_mantissa, u32 *coef_exponent);
949 * Code Specific to AR5008, AR9001 or AR9002,
950 * we stuff these here to avoid callbacks for AR9003.
952 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
953 int ar9002_hw_rf_claim(struct ath_hw *ah);
954 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
955 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
956 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
959 * Code specific to AR9003, we stuff these here to avoid callbacks
962 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
964 /* Hardware family op attach helpers */
965 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
966 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
967 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
969 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
970 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
972 void ar9002_hw_attach_ops(struct ath_hw *ah);
973 void ar9003_hw_attach_ops(struct ath_hw *ah);
975 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
977 * ANI work can be shared between all families but a next
978 * generation implementation of ANI will be used only for AR9003 only
979 * for now as the other families still need to be tested with the same
980 * next generation ANI. Feel free to start testing it though for the
981 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
983 extern int modparam_force_new_ani;
984 void ath9k_ani_reset(struct ath_hw *ah, int is_scanning);
985 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
986 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
988 #define ATH_PCIE_CAP_LINK_CTRL 0x70
989 #define ATH_PCIE_CAP_LINK_L0S 1
990 #define ATH_PCIE_CAP_LINK_L1 2
992 #define ATH9K_CLOCK_RATE_CCK 22
993 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
994 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
995 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44