qemu/roms/ipxe/src/drivers/net/ath/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
   5  * Original from Linux kernel 3.0.1
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef EEPROM_H
  21 #define EEPROM_H
  22
  23 FILE_LICENCE ( BSD2 );
  24
  25 #define AR_EEPROM_MODAL_SPURS   5
  26
  27 #include "../ath.h"
  28 #include "ar9003_eeprom.h"
  29
  30 #if __BYTE_ORDER == __BIG_ENDIAN
  31 #define AR5416_EEPROM_MAGIC 0x5aa5
  32 #else
  33 #define AR5416_EEPROM_MAGIC 0xa55a
  34 #endif
  35
  36 #define CTRY_DEBUG   0x1ff
  37 #define CTRY_DEFAULT 0
  38
  39 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  40 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  41 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  42 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  43 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  44 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  45 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  46 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  47 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  48
  49 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  50 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  51 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  52 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  53 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  54 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  55
  56 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  57 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  58
  59 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  60 #define AR5416_EEPROM_S             2
  61 #define AR5416_EEPROM_OFFSET        0x2000
  62 #define AR5416_EEPROM_MAX           0xae0
  63
  64 #define AR5416_EEPROM_START_ADDR \
  65         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  66
  67 #define SD_NO_CTL               0xE0
  68 #define NO_CTL                  0xff
  69 #define CTL_MODE_M              0xf
  70 #define CTL_11A                 0
  71 #define CTL_11B                 1
  72 #define CTL_11G                 2
  73 #define CTL_2GHT20              5
  74 #define CTL_5GHT20              6
  75 #define CTL_2GHT40              7
  76 #define CTL_5GHT40              8
  77
  78 #define EXT_ADDITIVE (0x8000)
  79 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  80 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  81 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  82
  83 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  84 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  85
  86 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  87 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  88
  89 /*
  90  * For AR9285 and later chipsets, the following bits are not being programmed
  91  * in EEPROM and so need to be enabled always.
  92  *
  93  * Bit 0: en_fcc_mid
  94  * Bit 1: en_jap_mid
  95  * Bit 2: en_fcc_dfs_ht40
  96  * Bit 3: en_jap_ht40
  97  * Bit 4: en_jap_dfs_ht40
  98  */
  99 #define AR9285_RDEXT_DEFAULT    0x1F
 100
 101 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
 102 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
 103 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
 104
 105 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 106 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
 107                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 108 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
 109                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 110
 111 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 112 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 113 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 114 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 115
 116 #define EEP_RFSILENT_ENABLED        0x0001
 117 #define EEP_RFSILENT_ENABLED_S      0
 118 #define EEP_RFSILENT_POLARITY       0x0002
 119 #define EEP_RFSILENT_POLARITY_S     1
 120 #define EEP_RFSILENT_GPIO_SEL       0x001c
 121 #define EEP_RFSILENT_GPIO_SEL_S     2
 122
 123 #define AR5416_OPFLAGS_11A           0x01
 124 #define AR5416_OPFLAGS_11G           0x02
 125 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 126 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 127 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 128 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 129
 130 #define AR5416_EEP_NO_BACK_VER       0x1
 131 #define AR5416_EEP_VER               0xE
 132 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 133 #define AR5416_EEP_MINOR_VER_2       0x2
 134 #define AR5416_EEP_MINOR_VER_3       0x3
 135 #define AR5416_EEP_MINOR_VER_7       0x7
 136 #define AR5416_EEP_MINOR_VER_9       0x9
 137 #define AR5416_EEP_MINOR_VER_16      0x10
 138 #define AR5416_EEP_MINOR_VER_17      0x11
 139 #define AR5416_EEP_MINOR_VER_19      0x13
 140 #define AR5416_EEP_MINOR_VER_20      0x14
 141 #define AR5416_EEP_MINOR_VER_21      0x15
 142 #define AR5416_EEP_MINOR_VER_22      0x16
 143
 144 #define AR5416_NUM_5G_CAL_PIERS         8
 145 #define AR5416_NUM_2G_CAL_PIERS         4
 146 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 147 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 148 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 149 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 150 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 151 #define AR5416_NUM_CTLS                 24
 152 #define AR5416_NUM_BAND_EDGES           8
 153 #define AR5416_NUM_PD_GAINS             4
 154 #define AR5416_PD_GAINS_IN_MASK         4
 155 #define AR5416_PD_GAIN_ICEPTS           5
 156 #define AR5416_NUM_PDADC_VALUES         128
 157 #define AR5416_BCHAN_UNUSED             0xFF
 158 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 159 #define AR5416_MAX_CHAINS               3
 160 #define AR9300_MAX_CHAINS               3
 161 #define AR5416_PWR_TABLE_OFFSET_DB     -5
 162
 163 /* Rx gain type values */
 164 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 165 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 166 #define AR5416_EEP_RXGAIN_ORIG             2
 167
 168 /* Tx gain type values */
 169 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 170 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 171
 172 #define AR5416_EEP4K_START_LOC                64
 173 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 174 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 175 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 176 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 177 #define AR5416_EEP4K_NUM_CTLS                 12
 178 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 179 #define AR5416_EEP4K_NUM_PD_GAINS             2
 180 #define AR5416_EEP4K_MAX_CHAINS               1
 181
 182 #define AR9280_TX_GAIN_TABLE_SIZE 22
 183
 184 #define AR9287_EEP_VER               0xE
 185 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
 186 #define AR9287_EEP_MINOR_VER_1       0x1
 187 #define AR9287_EEP_MINOR_VER_2       0x2
 188 #define AR9287_EEP_MINOR_VER_3       0x3
 189 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
 190 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
 191 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
 192
 193 #define AR9287_EEP_START_LOC            128
 194 #define AR9287_HTC_EEP_START_LOC        256
 195 #define AR9287_NUM_2G_CAL_PIERS         3
 196 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
 197 #define AR9287_NUM_2G_20_TARGET_POWERS  3
 198 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 199 #define AR9287_NUM_CTLS                 12
 200 #define AR9287_NUM_BAND_EDGES           4
 201 #define AR9287_PD_GAIN_ICEPTS           1
 202 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 203 #define AR9287_EEPMISC_WOW              0x02
 204 #define AR9287_MAX_CHAINS               2
 205 #define AR9287_ANT_16S                  32
 206
 207 #define AR9287_DATA_SZ                  32
 208
 209 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 210
 211 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 212
 213 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
 214 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
 215
 216 #define LNA_CTL_BUF_MODE        BIT(0)
 217 #define LNA_CTL_ISEL_LO         BIT(1)
 218 #define LNA_CTL_ISEL_HI         BIT(2)
 219 #define LNA_CTL_BUF_IN          BIT(3)
 220 #define LNA_CTL_FEM_BAND        BIT(4)
 221 #define LNA_CTL_LOCAL_BIAS      BIT(5)
 222 #define LNA_CTL_FORCE_XPA       BIT(6)
 223 #define LNA_CTL_USE_ANT1        BIT(7)
 224
 225 enum eeprom_param {
 226         EEP_NFTHRESH_5,
 227         EEP_NFTHRESH_2,
 228         EEP_MAC_MSW,
 229         EEP_MAC_MID,
 230         EEP_MAC_LSW,
 231         EEP_REG_0,
 232         EEP_REG_1,
 233         EEP_OP_CAP,
 234         EEP_OP_MODE,
 235         EEP_RF_SILENT,
 236         EEP_OB_5,
 237         EEP_DB_5,
 238         EEP_OB_2,
 239         EEP_DB_2,
 240         EEP_MINOR_REV,
 241         EEP_TX_MASK,
 242         EEP_RX_MASK,
 243         EEP_FSTCLK_5G,
 244         EEP_RXGAIN_TYPE,
 245         EEP_OL_PWRCTRL,
 246         EEP_TXGAIN_TYPE,
 247         EEP_RC_CHAIN_MASK,
 248         EEP_DAC_HPWR_5G,
 249         EEP_FRAC_N_5G,
 250         EEP_DEV_TYPE,
 251         EEP_TEMPSENSE_SLOPE,
 252         EEP_TEMPSENSE_SLOPE_PAL_ON,
 253         EEP_PWR_TABLE_OFFSET,
 254         EEP_DRIVE_STRENGTH,
 255         EEP_INTERNAL_REGULATOR,
 256         EEP_SWREG,
 257         EEP_PAPRD,
 258         EEP_MODAL_VER,
 259         EEP_ANT_DIV_CTL1,
 260         EEP_CHAIN_MASK_REDUCE
 261 };
 262
 263 enum ar5416_rates {
 264         rate6mb, rate9mb, rate12mb, rate18mb,
 265         rate24mb, rate36mb, rate48mb, rate54mb,
 266         rate1l, rate2l, rate2s, rate5_5l,
 267         rate5_5s, rate11l, rate11s, rateXr,
 268         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 269         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 270         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 271         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 272         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 273         Ar5416RateSize
 274 };
 275
 276 enum ath9k_hal_freq_band {
 277         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 278         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 279 };
 280
 281 struct base_eep_header {
 282         u16 length;
 283         u16 checksum;
 284         u16 version;
 285         u8 opCapFlags;
 286         u8 eepMisc;
 287         u16 regDmn[2];
 288         u8 macAddr[6];
 289         u8 rxMask;
 290         u8 txMask;
 291         u16 rfSilent;
 292         u16 blueToothOptions;
 293         u16 deviceCap;
 294         u32 binBuildNumber;
 295         u8 deviceType;
 296         u8 pwdclkind;
 297         u8 fastClk5g;
 298         u8 divChain;
 299         u8 rxGainType;
 300         u8 dacHiPwrMode_5G;
 301         u8 openLoopPwrCntl;
 302         u8 dacLpMode;
 303         u8 txGainType;
 304         u8 rcChainMask;
 305         u8 desiredScaleCCK;
 306         u8 pwr_table_offset;
 307         u8 frac_n_5g;
 308         u8 futureBase_3[21];
 309 } __attribute__((packed));
 310
 311 struct base_eep_header_4k {
 312         u16 length;
 313         u16 checksum;
 314         u16 version;
 315         u8 opCapFlags;
 316         u8 eepMisc;
 317         u16 regDmn[2];
 318         u8 macAddr[6];
 319         u8 rxMask;
 320         u8 txMask;
 321         u16 rfSilent;
 322         u16 blueToothOptions;
 323         u16 deviceCap;
 324         u32 binBuildNumber;
 325         u8 deviceType;
 326         u8 txGainType;
 327 } __attribute__((packed));
 328
 329
 330 struct spur_chan {
 331         u16 spurChan;
 332         u8 spurRangeLow;
 333         u8 spurRangeHigh;
 334 } __attribute__((packed));
 335
 336 struct modal_eep_header {
 337         u32 antCtrlChain[AR5416_MAX_CHAINS];
 338         u32 antCtrlCommon;
 339         u8 antennaGainCh[AR5416_MAX_CHAINS];
 340         u8 switchSettling;
 341         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 342         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 343         u8 adcDesiredSize;
 344         u8 pgaDesiredSize;
 345         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 346         u8 txEndToXpaOff;
 347         u8 txEndToRxOn;
 348         u8 txFrameToXpaOn;
 349         u8 thresh62;
 350         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 351         u8 xpdGain;
 352         u8 xpd;
 353         u8 iqCalICh[AR5416_MAX_CHAINS];
 354         u8 iqCalQCh[AR5416_MAX_CHAINS];
 355         u8 pdGainOverlap;
 356         u8 ob;
 357         u8 db;
 358         u8 xpaBiasLvl;
 359         u8 pwrDecreaseFor2Chain;
 360         u8 pwrDecreaseFor3Chain;
 361         u8 txFrameToDataStart;
 362         u8 txFrameToPaOn;
 363         u8 ht40PowerIncForPdadc;
 364         u8 bswAtten[AR5416_MAX_CHAINS];
 365         u8 bswMargin[AR5416_MAX_CHAINS];
 366         u8 swSettleHt40;
 367         u8 xatten2Db[AR5416_MAX_CHAINS];
 368         u8 xatten2Margin[AR5416_MAX_CHAINS];
 369         u8 ob_ch1;
 370         u8 db_ch1;
 371         u8 lna_ctl;
 372         u8 miscBits;
 373         u16 xpaBiasLvlFreq[3];
 374         u8 futureModal[6];
 375
 376         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 377 } __attribute__((packed));
 378
 379 struct calDataPerFreqOpLoop {
 380         u8 pwrPdg[2][5];
 381         u8 vpdPdg[2][5];
 382         u8 pcdac[2][5];
 383         u8 empty[2][5];
 384 } __attribute__((packed));
 385
 386 struct modal_eep_4k_header {
 387         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 388         u32 antCtrlCommon;
 389         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 390         u8 switchSettling;
 391         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 392         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 393         u8 adcDesiredSize;
 394         u8 pgaDesiredSize;
 395         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 396         u8 txEndToXpaOff;
 397         u8 txEndToRxOn;
 398         u8 txFrameToXpaOn;
 399         u8 thresh62;
 400         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 401         u8 xpdGain;
 402         u8 xpd;
 403         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 404         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 405         u8 pdGainOverlap;
 406 #ifdef __BIG_ENDIAN_BITFIELD
 407         u8 ob_1:4, ob_0:4;
 408         u8 db1_1:4, db1_0:4;
 409 #else
 410         u8 ob_0:4, ob_1:4;
 411         u8 db1_0:4, db1_1:4;
 412 #endif
 413         u8 xpaBiasLvl;
 414         u8 txFrameToDataStart;
 415         u8 txFrameToPaOn;
 416         u8 ht40PowerIncForPdadc;
 417         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
 418         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
 419         u8 swSettleHt40;
 420         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 421         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 422 #ifdef __BIG_ENDIAN_BITFIELD
 423         u8 db2_1:4, db2_0:4;
 424 #else
 425         u8 db2_0:4, db2_1:4;
 426 #endif
 427         u8 version;
 428 #ifdef __BIG_ENDIAN_BITFIELD
 429         u8 ob_3:4, ob_2:4;
 430         u8 antdiv_ctl1:4, ob_4:4;
 431         u8 db1_3:4, db1_2:4;
 432         u8 antdiv_ctl2:4, db1_4:4;
 433         u8 db2_2:4, db2_3:4;
 434         u8 reserved:4, db2_4:4;
 435 #else
 436         u8 ob_2:4, ob_3:4;
 437         u8 ob_4:4, antdiv_ctl1:4;
 438         u8 db1_2:4, db1_3:4;
 439         u8 db1_4:4, antdiv_ctl2:4;
 440         u8 db2_2:4, db2_3:4;
 441         u8 db2_4:4, reserved:4;
 442 #endif
 443         u8 tx_diversity;
 444         u8 flc_pwr_thresh;
 445         u8 bb_scale_smrt_antenna;
 446 #define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
 447         u8 futureModal[1];
 448         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 449 } __attribute__((packed));
 450
 451 struct base_eep_ar9287_header {
 452         u16 length;
 453         u16 checksum;
 454         u16 version;
 455         u8 opCapFlags;
 456         u8 eepMisc;
 457         u16 regDmn[2];
 458         u8 macAddr[6];
 459         u8 rxMask;
 460         u8 txMask;
 461         u16 rfSilent;
 462         u16 blueToothOptions;
 463         u16 deviceCap;
 464         u32 binBuildNumber;
 465         u8 deviceType;
 466         u8 openLoopPwrCntl;
 467         int8_t pwrTableOffset;
 468         int8_t tempSensSlope;
 469         int8_t tempSensSlopePalOn;
 470         u8 futureBase[29];
 471 } __attribute__((packed));
 472
 473 struct modal_eep_ar9287_header {
 474         u32 antCtrlChain[AR9287_MAX_CHAINS];
 475         u32 antCtrlCommon;
 476         int8_t antennaGainCh[AR9287_MAX_CHAINS];
 477         u8 switchSettling;
 478         u8 txRxAttenCh[AR9287_MAX_CHAINS];
 479         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
 480         int8_t adcDesiredSize;
 481         u8 txEndToXpaOff;
 482         u8 txEndToRxOn;
 483         u8 txFrameToXpaOn;
 484         u8 thresh62;
 485         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
 486         u8 xpdGain;
 487         u8 xpd;
 488         int8_t iqCalICh[AR9287_MAX_CHAINS];
 489         int8_t iqCalQCh[AR9287_MAX_CHAINS];
 490         u8 pdGainOverlap;
 491         u8 xpaBiasLvl;
 492         u8 txFrameToDataStart;
 493         u8 txFrameToPaOn;
 494         u8 ht40PowerIncForPdadc;
 495         u8 bswAtten[AR9287_MAX_CHAINS];
 496         u8 bswMargin[AR9287_MAX_CHAINS];
 497         u8 swSettleHt40;
 498         u8 version;
 499         u8 db1;
 500         u8 db2;
 501         u8 ob_cck;
 502         u8 ob_psk;
 503         u8 ob_qam;
 504         u8 ob_pal_off;
 505         u8 futureModal[30];
 506         struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 507 } __attribute__((packed));
 508
 509 struct cal_data_per_freq {
 510         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 511         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 512 } __attribute__((packed));
 513
 514 struct cal_data_per_freq_4k {
 515         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 516         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 517 } __attribute__((packed));
 518
 519 struct cal_target_power_leg {
 520         u8 bChannel;
 521         u8 tPow2x[4];
 522 } __attribute__((packed));
 523
 524 struct cal_target_power_ht {
 525         u8 bChannel;
 526         u8 tPow2x[8];
 527 } __attribute__((packed));
 528
 529 struct cal_ctl_edges {
 530         u8 bChannel;
 531         u8 ctl;
 532 } __attribute__((packed));
 533
 534 struct cal_data_op_loop_ar9287 {
 535         u8 pwrPdg[2][5];
 536         u8 vpdPdg[2][5];
 537         u8 pcdac[2][5];
 538         u8 empty[2][5];
 539 } __attribute__((packed));
 540
 541 struct cal_data_per_freq_ar9287 {
 542         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 543         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 544 } __attribute__((packed));
 545
 546 union cal_data_per_freq_ar9287_u {
 547         struct cal_data_op_loop_ar9287 calDataOpen;
 548         struct cal_data_per_freq_ar9287 calDataClose;
 549 } __attribute__((packed));
 550
 551 struct cal_ctl_data_ar9287 {
 552         struct cal_ctl_edges
 553         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
 554 } __attribute__((packed));
 555
 556 struct cal_ctl_data {
 557         struct cal_ctl_edges
 558         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 559 } __attribute__((packed));
 560
 561 struct cal_ctl_data_4k {
 562         struct cal_ctl_edges
 563         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 564 } __attribute__((packed));
 565
 566 struct ar5416_eeprom_def {
 567         struct base_eep_header baseEepHeader;
 568         u8 custData[64];
 569         struct modal_eep_header modalHeader[2];
 570         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 571         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 572         struct cal_data_per_freq
 573          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 574         struct cal_data_per_freq
 575          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 576         struct cal_target_power_leg
 577          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 578         struct cal_target_power_ht
 579          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 580         struct cal_target_power_ht
 581          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 582         struct cal_target_power_leg
 583          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 584         struct cal_target_power_leg
 585          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 586         struct cal_target_power_ht
 587          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 588         struct cal_target_power_ht
 589          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 590         u8 ctlIndex[AR5416_NUM_CTLS];
 591         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 592         u8 padding;
 593 } __attribute__((packed));
 594
 595 struct ar5416_eeprom_4k {
 596         struct base_eep_header_4k baseEepHeader;
 597         u8 custData[20];
 598         struct modal_eep_4k_header modalHeader;
 599         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 600         struct cal_data_per_freq_4k
 601         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 602         struct cal_target_power_leg
 603         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 604         struct cal_target_power_leg
 605         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 606         struct cal_target_power_ht
 607         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 608         struct cal_target_power_ht
 609         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 610         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 611         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 612         u8 padding;
 613 } __attribute__((packed));
 614
 615 struct ar9287_eeprom {
 616         struct base_eep_ar9287_header baseEepHeader;
 617         u8 custData[AR9287_DATA_SZ];
 618         struct modal_eep_ar9287_header modalHeader;
 619         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
 620         union cal_data_per_freq_ar9287_u
 621         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
 622         struct cal_target_power_leg
 623         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
 624         struct cal_target_power_leg
 625         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
 626         struct cal_target_power_ht
 627         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
 628         struct cal_target_power_ht
 629         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
 630         u8 ctlIndex[AR9287_NUM_CTLS];
 631         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
 632         u8 padding;
 633 } __attribute__((packed));
 634
 635 enum reg_ext_bitmap {
 636         REG_EXT_FCC_MIDBAND = 0,
 637         REG_EXT_JAPAN_MIDBAND = 1,
 638         REG_EXT_FCC_DFS_HT40 = 2,
 639         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 640         REG_EXT_JAPAN_DFS_HT40 = 4
 641 };
 642
 643 struct ath9k_country_entry {
 644         u16 countryCode;
 645         u16 regDmnEnum;
 646         u16 regDmn5G;
 647         u16 regDmn2G;
 648         u8 isMultidomain;
 649         u8 iso[3];
 650 };
 651
 652 struct eeprom_ops {
 653         int (*check_eeprom)(struct ath_hw *hw);
 654         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 655         int (*fill_eeprom)(struct ath_hw *hw);
 656         int (*get_eeprom_ver)(struct ath_hw *hw);
 657         int (*get_eeprom_rev)(struct ath_hw *hw);
 658         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 659         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 660         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 661                            u16 cfgCtl, u8 twiceAntennaReduction,
 662                            u8 twiceMaxRegulatoryPower, u8 powerLimit,
 663                            int test);
 664         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, int is2GHz);
 665 };
 666
 667 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
 668 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
 669                                u32 shift, u32 val);
 670 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 671                              int16_t targetLeft,
 672                              int16_t targetRight);
 673 int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
 674                                     u16 *indexL, u16 *indexR);
 675 int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
 676 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
 677                                   int eep_start_loc, int size);
 678 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
 679                              u8 *pVpdList, u16 numIntercepts,
 680                              u8 *pRetVpdList);
 681 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 682                                        struct ath9k_channel *chan,
 683                                        struct cal_target_power_leg *powInfo,
 684                                        u16 numChannels,
 685                                        struct cal_target_power_leg *pNewPower,
 686                                        u16 numRates, int isExtTarget);
 687 void ath9k_hw_get_target_powers(struct ath_hw *ah,
 688                                 struct ath9k_channel *chan,
 689                                 struct cal_target_power_ht *powInfo,
 690                                 u16 numChannels,
 691                                 struct cal_target_power_ht *pNewPower,
 692                                 u16 numRates, int isHt40Target);
 693 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 694                                 int is2GHz, int num_band_edges);
 695 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 696 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 697
 698 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
 699                                 struct ath9k_channel *chan,
 700                                 void *pRawDataSet,
 701                                 u8 *bChans, u16 availPiers,
 702                                 u16 tPdGainOverlap,
 703                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 704                                 u16 numXpdGains);
 705
 706 #define ar5416_get_ntxchains(_txchainmask)                      \
 707         (((_txchainmask >> 2) & 1) +                            \
 708          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 709
 710 extern const struct eeprom_ops eep_def_ops;
 711 extern const struct eeprom_ops eep_4k_ops;
 712 extern const struct eeprom_ops eep_ar9287_ops;
 713 extern const struct eeprom_ops eep_ar9287_ops;
 714 extern const struct eeprom_ops eep_ar9300_ops;
 715
 716 #endif /* EEPROM_H */