qemu/roms/ipxe/src/drivers/net/ath/ath9k/ath9k_eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
   5  * Original from Linux kernel 3.0.1
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #include <ipxe/io.h>
  21
  22 #include "hw.h"
  23 #include "ar9002_phy.h"
  24
  25 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  26 {
  27         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  28 }
  29
  30 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  31 {
  32         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  33 }
  34
  35 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  36
  37 static int __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  38 {
  39         struct ath_common *common = ath9k_hw_common(ah);
  40         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  41         unsigned int addr;
  42         int eep_start_loc = 64;
  43
  44         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  45                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  46                         DBG("ath9k: "
  47                                 "Unable to read eeprom region\n");
  48                         return 0;
  49                 }
  50                 eep_data++;
  51         }
  52
  53         return 1;
  54 }
  55
  56 static int __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
  57 {
  58         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  59
  60         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
  61
  62         return 1;
  63 }
  64
  65 static int ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  66 {
  67         struct ath_common *common = ath9k_hw_common(ah);
  68
  69         if (!ath9k_hw_use_flash(ah)) {
  70                 DBG2("ath9k: "
  71                         "Reading from EEPROM, not flash\n");
  72         }
  73
  74         if (common->bus_ops->ath_bus_type == ATH_USB)
  75                 return __ath9k_hw_usb_4k_fill_eeprom(ah);
  76         else
  77                 return __ath9k_hw_4k_fill_eeprom(ah);
  78 }
  79
  80 #undef SIZE_EEPROM_4K
  81
  82 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  83 {
  84 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  85         struct ath_common *common = ath9k_hw_common(ah);
  86         struct ar5416_eeprom_4k *eep =
  87                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  88         u16 *eepdata, temp, magic, magic2;
  89         u32 sum = 0, el;
  90         int need_swap = 0;
  91         unsigned int i, addr;
  92
  93
  94         if (!ath9k_hw_use_flash(ah)) {
  95                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  96                                          &magic)) {
  97                         DBG("ath9k: Reading Magic # failed\n");
  98                         return 0;
  99                 }
 100
 101                 DBG2("ath9k: "
 102                         "Read Magic = 0x%04X\n", magic);
 103
 104                 if (magic != AR5416_EEPROM_MAGIC) {
 105                         magic2 = swab16(magic);
 106
 107                         if (magic2 == AR5416_EEPROM_MAGIC) {
 108                                 need_swap = 1;
 109                                 eepdata = (u16 *) (&ah->eeprom);
 110
 111                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 112                                         temp = swab16(*eepdata);
 113                                         *eepdata = temp;
 114                                         eepdata++;
 115                                 }
 116                         } else {
 117                                 DBG("ath9k: "
 118                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 119                                 return -EINVAL;
 120                         }
 121                 }
 122         }
 123
 124         DBG2("ath9k: need_swap = %s.\n",
 125                 need_swap ? "True" : "False");
 126
 127         if (need_swap)
 128                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 129         else
 130                 el = ah->eeprom.map4k.baseEepHeader.length;
 131
 132         if (el > sizeof(struct ar5416_eeprom_4k))
 133                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 134         else
 135                 el = el / sizeof(u16);
 136
 137         eepdata = (u16 *)(&ah->eeprom);
 138
 139         for (i = 0; i < el; i++)
 140                 sum ^= *eepdata++;
 141
 142         if (need_swap) {
 143                 u32 integer;
 144                 u16 word;
 145
 146                 DBG("ath9k: "
 147                         "EEPROM Endianness is not native.. Changing\n");
 148
 149                 word = swab16(eep->baseEepHeader.length);
 150                 eep->baseEepHeader.length = word;
 151
 152                 word = swab16(eep->baseEepHeader.checksum);
 153                 eep->baseEepHeader.checksum = word;
 154
 155                 word = swab16(eep->baseEepHeader.version);
 156                 eep->baseEepHeader.version = word;
 157
 158                 word = swab16(eep->baseEepHeader.regDmn[0]);
 159                 eep->baseEepHeader.regDmn[0] = word;
 160
 161                 word = swab16(eep->baseEepHeader.regDmn[1]);
 162                 eep->baseEepHeader.regDmn[1] = word;
 163
 164                 word = swab16(eep->baseEepHeader.rfSilent);
 165                 eep->baseEepHeader.rfSilent = word;
 166
 167                 word = swab16(eep->baseEepHeader.blueToothOptions);
 168                 eep->baseEepHeader.blueToothOptions = word;
 169
 170                 word = swab16(eep->baseEepHeader.deviceCap);
 171                 eep->baseEepHeader.deviceCap = word;
 172
 173                 integer = swab32(eep->modalHeader.antCtrlCommon);
 174                 eep->modalHeader.antCtrlCommon = integer;
 175
 176                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 177                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 178                         eep->modalHeader.antCtrlChain[i] = integer;
 179                 }
 180
 181                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 182                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 183                         eep->modalHeader.spurChans[i].spurChan = word;
 184                 }
 185         }
 186
 187         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 188             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 189                 DBG("ath9k: Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 190                         sum, ah->eep_ops->get_eeprom_ver(ah));
 191                 return -EINVAL;
 192         }
 193
 194         return 0;
 195 #undef EEPROM_4K_SIZE
 196 }
 197
 198 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 199                                   enum eeprom_param param)
 200 {
 201         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 202         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 203         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 204         u16 ver_minor;
 205
 206         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 207
 208         switch (param) {
 209         case EEP_NFTHRESH_2:
 210                 return pModal->noiseFloorThreshCh[0];
 211         case EEP_MAC_LSW:
 212                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 213         case EEP_MAC_MID:
 214                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 215         case EEP_MAC_MSW:
 216                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 217         case EEP_REG_0:
 218                 return pBase->regDmn[0];
 219         case EEP_REG_1:
 220                 return pBase->regDmn[1];
 221         case EEP_OP_CAP:
 222                 return pBase->deviceCap;
 223         case EEP_OP_MODE:
 224                 return pBase->opCapFlags;
 225         case EEP_RF_SILENT:
 226                 return pBase->rfSilent;
 227         case EEP_OB_2:
 228                 return pModal->ob_0;
 229         case EEP_DB_2:
 230                 return pModal->db1_1;
 231         case EEP_MINOR_REV:
 232                 return ver_minor;
 233         case EEP_TX_MASK:
 234                 return pBase->txMask;
 235         case EEP_RX_MASK:
 236                 return pBase->rxMask;
 237         case EEP_FRAC_N_5G:
 238                 return 0;
 239         case EEP_PWR_TABLE_OFFSET:
 240                 return AR5416_PWR_TABLE_OFFSET_DB;
 241         case EEP_MODAL_VER:
 242                 return pModal->version;
 243         case EEP_ANT_DIV_CTL1:
 244                 return pModal->antdiv_ctl1;
 245         case EEP_TXGAIN_TYPE:
 246                 if (ver_minor >= AR5416_EEP_MINOR_VER_19)
 247                         return pBase->txGainType;
 248                 else
 249                         return AR5416_EEP_TXGAIN_ORIGINAL;
 250         default:
 251                 return 0;
 252         }
 253 }
 254
 255 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 256                                   struct ath9k_channel *chan,
 257                                   int16_t *pTxPowerIndexOffset)
 258 {
 259         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 260         struct cal_data_per_freq_4k *pRawDataset;
 261         u8 *pCalBChans = NULL;
 262         u16 pdGainOverlap_t2;
 263         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 264         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 265         u16 numPiers, i, j;
 266         u16 numXpdGain, xpdMask;
 267         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 268         u32 reg32, regOffset, regChainOffset;
 269
 270         xpdMask = pEepData->modalHeader.xpdGain;
 271
 272         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 273             AR5416_EEP_MINOR_VER_2) {
 274                 pdGainOverlap_t2 =
 275                         pEepData->modalHeader.pdGainOverlap;
 276         } else {
 277                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 278                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 279         }
 280
 281         pCalBChans = pEepData->calFreqPier2G;
 282         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 283
 284         numXpdGain = 0;
 285
 286         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 287                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 288                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 289                                 break;
 290                         xpdGainValues[numXpdGain] =
 291                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 292                         numXpdGain++;
 293                 }
 294         }
 295
 296         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 297                       (numXpdGain - 1) & 0x3);
 298         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 299                       xpdGainValues[0]);
 300         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 301                       xpdGainValues[1]);
 302         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 303
 304         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 305                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 306                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 307                     (i != 0)) {
 308                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 309                 } else
 310                         regChainOffset = i * 0x1000;
 311
 312                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 313                         pRawDataset = pEepData->calPierData2G[i];
 314
 315                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
 316                                             pRawDataset, pCalBChans,
 317                                             numPiers, pdGainOverlap_t2,
 318                                             gainBoundaries,
 319                                             pdadcValues, numXpdGain);
 320
 321                         ENABLE_REGWRITE_BUFFER(ah);
 322
 323                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 324                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 325                                           SM(pdGainOverlap_t2,
 326                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 327                                           | SM(gainBoundaries[0],
 328                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 329                                           | SM(gainBoundaries[1],
 330                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 331                                           | SM(gainBoundaries[2],
 332                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 333                                           | SM(gainBoundaries[3],
 334                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 335                         }
 336
 337                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 338                         for (j = 0; j < 32; j++) {
 339                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 340                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 341                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 342                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 343                                 REG_WRITE(ah, regOffset, reg32);
 344
 345                                 DBG2("ath9k: "
 346                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 347                                         i, regChainOffset, regOffset,
 348                                         reg32);
 349                                 DBG2("ath9k: "
 350                                         "PDADC: Chain %d | "
 351                                         "PDADC %3d Value %3d | "
 352                                         "PDADC %3d Value %3d | "
 353                                         "PDADC %3d Value %3d | "
 354                                         "PDADC %3d Value %3d |\n",
 355                                         i, 4 * j, pdadcValues[4 * j],
 356                                         4 * j + 1, pdadcValues[4 * j + 1],
 357                                         4 * j + 2, pdadcValues[4 * j + 2],
 358                                         4 * j + 3, pdadcValues[4 * j + 3]);
 359
 360                                 regOffset += 4;
 361                         }
 362
 363                         REGWRITE_BUFFER_FLUSH(ah);
 364                 }
 365         }
 366
 367         *pTxPowerIndexOffset = 0;
 368 }
 369
 370 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 371                                                  struct ath9k_channel *chan,
 372                                                  int16_t *ratesArray,
 373                                                  u16 cfgCtl,
 374                                                  u16 AntennaReduction,
 375                                                  u16 twiceMaxRegulatoryPower,
 376                                                  u16 powerLimit)
 377 {
 378 #define CMP_TEST_GRP \
 379         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 380          pEepData->ctlIndex[i])                                         \
 381         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 382             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 383
 384         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 385         unsigned int i;
 386         int16_t twiceLargestAntenna;
 387         u16 twiceMinEdgePower;
 388         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 389         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 390         u16 numCtlModes;
 391         const u16 *pCtlMode;
 392         u16 ctlMode, freq;
 393         struct chan_centers centers;
 394         struct cal_ctl_data_4k *rep;
 395         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 396         static const u16 tpScaleReductionTable[5] =
 397                 { 0, 3, 6, 9, MAX_RATE_POWER };
 398         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 399                 0, { 0, 0, 0, 0}
 400         };
 401         struct cal_target_power_leg targetPowerOfdmExt = {
 402                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 403                 0, { 0, 0, 0, 0 }
 404         };
 405         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 406                 0, {0, 0, 0, 0}
 407         };
 408         static const u16 ctlModesFor11g[] = {
 409                 CTL_11B, CTL_11G, CTL_2GHT20,
 410                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 411         };
 412
 413         ath9k_hw_get_channel_centers(ah, chan, &centers);
 414
 415         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 416         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 417                                            twiceLargestAntenna, 0);
 418
 419         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 420         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 421                 maxRegAllowedPower -=
 422                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 423         }
 424
 425         scaledPower = min(powerLimit, maxRegAllowedPower);
 426         scaledPower = max((u16)0, scaledPower);
 427
 428         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 429         pCtlMode = ctlModesFor11g;
 430
 431         ath9k_hw_get_legacy_target_powers(ah, chan,
 432                         pEepData->calTargetPowerCck,
 433                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 434                         &targetPowerCck, 4, 0);
 435         ath9k_hw_get_legacy_target_powers(ah, chan,
 436                         pEepData->calTargetPower2G,
 437                         AR5416_NUM_2G_20_TARGET_POWERS,
 438                         &targetPowerOfdm, 4, 0);
 439         ath9k_hw_get_target_powers(ah, chan,
 440                         pEepData->calTargetPower2GHT20,
 441                         AR5416_NUM_2G_20_TARGET_POWERS,
 442                         &targetPowerHt20, 8, 0);
 443
 444         if (IS_CHAN_HT40(chan)) {
 445                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 446                 ath9k_hw_get_target_powers(ah, chan,
 447                                 pEepData->calTargetPower2GHT40,
 448                                 AR5416_NUM_2G_40_TARGET_POWERS,
 449                                 &targetPowerHt40, 8, 1);
 450                 ath9k_hw_get_legacy_target_powers(ah, chan,
 451                                 pEepData->calTargetPowerCck,
 452                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 453                                 &targetPowerCckExt, 4, 1);
 454                 ath9k_hw_get_legacy_target_powers(ah, chan,
 455                                 pEepData->calTargetPower2G,
 456                                 AR5416_NUM_2G_20_TARGET_POWERS,
 457                                 &targetPowerOfdmExt, 4, 1);
 458         }
 459
 460         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 461                 int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 462                         (pCtlMode[ctlMode] == CTL_2GHT40);
 463
 464                 if (isHt40CtlMode)
 465                         freq = centers.synth_center;
 466                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 467                         freq = centers.ext_center;
 468                 else
 469                         freq = centers.ctl_center;
 470
 471                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 472                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 473                         twiceMaxEdgePower = MAX_RATE_POWER;
 474
 475                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 476                              pEepData->ctlIndex[i]; i++) {
 477
 478                         if (CMP_TEST_GRP) {
 479                                 rep = &(pEepData->ctlData[i]);
 480
 481                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 482                                         freq,
 483                                         rep->ctlEdges[
 484                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 485                                         IS_CHAN_2GHZ(chan),
 486                                         AR5416_EEP4K_NUM_BAND_EDGES);
 487
 488                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 489                                         twiceMaxEdgePower =
 490                                                 min(twiceMaxEdgePower,
 491                                                     twiceMinEdgePower);
 492                                 } else {
 493                                         twiceMaxEdgePower = twiceMinEdgePower;
 494                                         break;
 495                                 }
 496                         }
 497                 }
 498
 499                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 500
 501                 switch (pCtlMode[ctlMode]) {
 502                 case CTL_11B:
 503                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 504                                 targetPowerCck.tPow2x[i] =
 505                                         min((u16)targetPowerCck.tPow2x[i],
 506                                             minCtlPower);
 507                         }
 508                         break;
 509                 case CTL_11G:
 510                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 511                                 targetPowerOfdm.tPow2x[i] =
 512                                         min((u16)targetPowerOfdm.tPow2x[i],
 513                                             minCtlPower);
 514                         }
 515                         break;
 516                 case CTL_2GHT20:
 517                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 518                                 targetPowerHt20.tPow2x[i] =
 519                                         min((u16)targetPowerHt20.tPow2x[i],
 520                                             minCtlPower);
 521                         }
 522                         break;
 523                 case CTL_11B_EXT:
 524                         targetPowerCckExt.tPow2x[0] =
 525                                 min((u16)targetPowerCckExt.tPow2x[0],
 526                                     minCtlPower);
 527                         break;
 528                 case CTL_11G_EXT:
 529                         targetPowerOfdmExt.tPow2x[0] =
 530                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 531                                     minCtlPower);
 532                         break;
 533                 case CTL_2GHT40:
 534                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 535                                 targetPowerHt40.tPow2x[i] =
 536                                         min((u16)targetPowerHt40.tPow2x[i],
 537                                             minCtlPower);
 538                         }
 539                         break;
 540                 default:
 541                         break;
 542                 }
 543         }
 544
 545         ratesArray[rate6mb] =
 546         ratesArray[rate9mb] =
 547         ratesArray[rate12mb] =
 548         ratesArray[rate18mb] =
 549         ratesArray[rate24mb] =
 550         targetPowerOfdm.tPow2x[0];
 551
 552         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 553         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 554         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 555         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 556
 557         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 558                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 559
 560         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 561         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 562         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 563         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 564
 565         if (IS_CHAN_HT40(chan)) {
 566                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 567                         ratesArray[rateHt40_0 + i] =
 568                                 targetPowerHt40.tPow2x[i];
 569                 }
 570                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 571                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 572                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 573                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 574         }
 575
 576 #undef CMP_TEST_GRP
 577 }
 578
 579 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 580                                     struct ath9k_channel *chan,
 581                                     u16 cfgCtl,
 582                                     u8 twiceAntennaReduction,
 583                                     u8 twiceMaxRegulatoryPower,
 584                                     u8 powerLimit, int test)
 585 {
 586         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 587         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 588         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 589         int16_t ratesArray[Ar5416RateSize];
 590         int16_t txPowerIndexOffset = 0;
 591         u8 ht40PowerIncForPdadc = 2;
 592         unsigned int i;
 593
 594         memset(ratesArray, 0, sizeof(ratesArray));
 595
 596         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 597             AR5416_EEP_MINOR_VER_2) {
 598                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 599         }
 600
 601         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 602                                              &ratesArray[0], cfgCtl,
 603                                              twiceAntennaReduction,
 604                                              twiceMaxRegulatoryPower,
 605                                              powerLimit);
 606
 607         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 608
 609         regulatory->max_power_level = 0;
 610         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 611                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
 612                 if (ratesArray[i] > MAX_RATE_POWER)
 613                         ratesArray[i] = MAX_RATE_POWER;
 614
 615                 if (ratesArray[i] > regulatory->max_power_level)
 616                         regulatory->max_power_level = ratesArray[i];
 617         }
 618
 619         if (test)
 620             return;
 621
 622         /* Update regulatory */
 623         i = rate6mb;
 624         if (IS_CHAN_HT40(chan))
 625                 i = rateHt40_0;
 626         else if (IS_CHAN_HT20(chan))
 627                 i = rateHt20_0;
 628
 629         regulatory->max_power_level = ratesArray[i];
 630
 631         if (AR_SREV_9280_20_OR_LATER(ah)) {
 632                 for (i = 0; i < Ar5416RateSize; i++)
 633                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 634         }
 635
 636         ENABLE_REGWRITE_BUFFER(ah);
 637
 638         /* OFDM power per rate */
 639         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 640                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 641                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 642                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 643                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 644         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 645                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 646                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 647                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 648                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 649
 650         /* CCK power per rate */
 651         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 652                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 653                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 654                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 655                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 656         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 657                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 658                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 659                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 660                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 661
 662         /* HT20 power per rate */
 663         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 664                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 665                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 666                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 667                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 668         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 669                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 670                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 671                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 672                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 673
 674         /* HT40 power per rate */
 675         if (IS_CHAN_HT40(chan)) {
 676                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 677                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 678                                        ht40PowerIncForPdadc, 24)
 679                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 680                                          ht40PowerIncForPdadc, 16)
 681                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 682                                          ht40PowerIncForPdadc, 8)
 683                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 684                                          ht40PowerIncForPdadc, 0));
 685                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 686                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 687                                        ht40PowerIncForPdadc, 24)
 688                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 689                                          ht40PowerIncForPdadc, 16)
 690                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 691                                          ht40PowerIncForPdadc, 8)
 692                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 693                                          ht40PowerIncForPdadc, 0));
 694                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 695                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 696                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 697                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 698                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 699         }
 700
 701         REGWRITE_BUFFER_FLUSH(ah);
 702 }
 703
 704 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
 705                                   struct ath9k_channel *chan __unused)
 706 {
 707         struct modal_eep_4k_header *pModal;
 708         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 709         u8 biaslevel;
 710
 711         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 712                 return;
 713
 714         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 715                 return;
 716
 717         pModal = &eep->modalHeader;
 718
 719         if (pModal->xpaBiasLvl != 0xff) {
 720                 biaslevel = pModal->xpaBiasLvl;
 721                 INI_RA(&ah->iniAddac, 7, 1) =
 722                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
 723         }
 724 }
 725
 726 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 727                                  struct modal_eep_4k_header *pModal,
 728                                  struct ar5416_eeprom_4k *eep,
 729                                  u8 txRxAttenLocal)
 730 {
 731         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 732                   pModal->antCtrlChain[0]);
 733
 734         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 735                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 736                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 737                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 738                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 739                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 740
 741         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 742             AR5416_EEP_MINOR_VER_3) {
 743                 txRxAttenLocal = pModal->txRxAttenCh[0];
 744
 745                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 746                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 747                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 748                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 749                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 750                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 751                               pModal->xatten2Margin[0]);
 752                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 753                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 754
 755                 /* Set the block 1 value to block 0 value */
 756                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 757                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 758                               pModal->bswMargin[0]);
 759                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 760                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 761                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 762                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 763                               pModal->xatten2Margin[0]);
 764                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 765                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 766                               pModal->xatten2Db[0]);
 767         }
 768
 769         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 770                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 771         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 772                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 773
 774         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 775                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 776         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 777                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 778 }
 779
 780 /*
 781  * Read EEPROM header info and program the device for correct operation
 782  * given the channel value.
 783  */
 784 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 785                                          struct ath9k_channel *chan)
 786 {
 787         struct modal_eep_4k_header *pModal;
 788         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 789         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 790         u8 txRxAttenLocal;
 791         u8 ob[5], db1[5], db2[5];
 792         u8 ant_div_control1, ant_div_control2;
 793         u32 regVal;
 794
 795         pModal = &eep->modalHeader;
 796         txRxAttenLocal = 23;
 797
 798         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 799
 800         /* Single chain for 4K EEPROM*/
 801         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 802
 803         /* Initialize Ant Diversity settings from EEPROM */
 804         if (pModal->version >= 3) {
 805                 ant_div_control1 = pModal->antdiv_ctl1;
 806                 ant_div_control2 = pModal->antdiv_ctl2;
 807
 808                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 809                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 810
 811                 regVal |= SM(ant_div_control1,
 812                              AR_PHY_9285_ANT_DIV_CTL);
 813                 regVal |= SM(ant_div_control2,
 814                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 815                 regVal |= SM((ant_div_control2 >> 2),
 816                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 817                 regVal |= SM((ant_div_control1 >> 1),
 818                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 819                 regVal |= SM((ant_div_control1 >> 2),
 820                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 821
 822
 823                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 824                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 825                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 826                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 827                 regVal |= SM((ant_div_control1 >> 3),
 828                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 829
 830                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 831                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 832         }
 833
 834         if (pModal->version >= 2) {
 835                 ob[0] = pModal->ob_0;
 836                 ob[1] = pModal->ob_1;
 837                 ob[2] = pModal->ob_2;
 838                 ob[3] = pModal->ob_3;
 839                 ob[4] = pModal->ob_4;
 840
 841                 db1[0] = pModal->db1_0;
 842                 db1[1] = pModal->db1_1;
 843                 db1[2] = pModal->db1_2;
 844                 db1[3] = pModal->db1_3;
 845                 db1[4] = pModal->db1_4;
 846
 847                 db2[0] = pModal->db2_0;
 848                 db2[1] = pModal->db2_1;
 849                 db2[2] = pModal->db2_2;
 850                 db2[3] = pModal->db2_3;
 851                 db2[4] = pModal->db2_4;
 852         } else if (pModal->version == 1) {
 853                 ob[0] = pModal->ob_0;
 854                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 855                 db1[0] = pModal->db1_0;
 856                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 857                 db2[0] = pModal->db2_0;
 858                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 859         } else {
 860                 int i;
 861
 862                 for (i = 0; i < 5; i++) {
 863                         ob[i] = pModal->ob_0;
 864                         db1[i] = pModal->db1_0;
 865                         db2[i] = pModal->db1_0;
 866                 }
 867         }
 868
 869         if (AR_SREV_9271(ah)) {
 870                 ath9k_hw_analog_shift_rmw(ah,
 871                                           AR9285_AN_RF2G3,
 872                                           AR9271_AN_RF2G3_OB_cck,
 873                                           AR9271_AN_RF2G3_OB_cck_S,
 874                                           ob[0]);
 875                 ath9k_hw_analog_shift_rmw(ah,
 876                                           AR9285_AN_RF2G3,
 877                                           AR9271_AN_RF2G3_OB_psk,
 878                                           AR9271_AN_RF2G3_OB_psk_S,
 879                                           ob[1]);
 880                 ath9k_hw_analog_shift_rmw(ah,
 881                                           AR9285_AN_RF2G3,
 882                                           AR9271_AN_RF2G3_OB_qam,
 883                                           AR9271_AN_RF2G3_OB_qam_S,
 884                                           ob[2]);
 885                 ath9k_hw_analog_shift_rmw(ah,
 886                                           AR9285_AN_RF2G3,
 887                                           AR9271_AN_RF2G3_DB_1,
 888                                           AR9271_AN_RF2G3_DB_1_S,
 889                                           db1[0]);
 890                 ath9k_hw_analog_shift_rmw(ah,
 891                                           AR9285_AN_RF2G4,
 892                                           AR9271_AN_RF2G4_DB_2,
 893                                           AR9271_AN_RF2G4_DB_2_S,
 894                                           db2[0]);
 895         } else {
 896                 ath9k_hw_analog_shift_rmw(ah,
 897                                           AR9285_AN_RF2G3,
 898                                           AR9285_AN_RF2G3_OB_0,
 899                                           AR9285_AN_RF2G3_OB_0_S,
 900                                           ob[0]);
 901                 ath9k_hw_analog_shift_rmw(ah,
 902                                           AR9285_AN_RF2G3,
 903                                           AR9285_AN_RF2G3_OB_1,
 904                                           AR9285_AN_RF2G3_OB_1_S,
 905                                           ob[1]);
 906                 ath9k_hw_analog_shift_rmw(ah,
 907                                           AR9285_AN_RF2G3,
 908                                           AR9285_AN_RF2G3_OB_2,
 909                                           AR9285_AN_RF2G3_OB_2_S,
 910                                           ob[2]);
 911                 ath9k_hw_analog_shift_rmw(ah,
 912                                           AR9285_AN_RF2G3,
 913                                           AR9285_AN_RF2G3_OB_3,
 914                                           AR9285_AN_RF2G3_OB_3_S,
 915                                           ob[3]);
 916                 ath9k_hw_analog_shift_rmw(ah,
 917                                           AR9285_AN_RF2G3,
 918                                           AR9285_AN_RF2G3_OB_4,
 919                                           AR9285_AN_RF2G3_OB_4_S,
 920                                           ob[4]);
 921
 922                 ath9k_hw_analog_shift_rmw(ah,
 923                                           AR9285_AN_RF2G3,
 924                                           AR9285_AN_RF2G3_DB1_0,
 925                                           AR9285_AN_RF2G3_DB1_0_S,
 926                                           db1[0]);
 927                 ath9k_hw_analog_shift_rmw(ah,
 928                                           AR9285_AN_RF2G3,
 929                                           AR9285_AN_RF2G3_DB1_1,
 930                                           AR9285_AN_RF2G3_DB1_1_S,
 931                                           db1[1]);
 932                 ath9k_hw_analog_shift_rmw(ah,
 933                                           AR9285_AN_RF2G3,
 934                                           AR9285_AN_RF2G3_DB1_2,
 935                                           AR9285_AN_RF2G3_DB1_2_S,
 936                                           db1[2]);
 937                 ath9k_hw_analog_shift_rmw(ah,
 938                                           AR9285_AN_RF2G4,
 939                                           AR9285_AN_RF2G4_DB1_3,
 940                                           AR9285_AN_RF2G4_DB1_3_S,
 941                                           db1[3]);
 942                 ath9k_hw_analog_shift_rmw(ah,
 943                                           AR9285_AN_RF2G4,
 944                                           AR9285_AN_RF2G4_DB1_4,
 945                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
 946
 947                 ath9k_hw_analog_shift_rmw(ah,
 948                                           AR9285_AN_RF2G4,
 949                                           AR9285_AN_RF2G4_DB2_0,
 950                                           AR9285_AN_RF2G4_DB2_0_S,
 951                                           db2[0]);
 952                 ath9k_hw_analog_shift_rmw(ah,
 953                                           AR9285_AN_RF2G4,
 954                                           AR9285_AN_RF2G4_DB2_1,
 955                                           AR9285_AN_RF2G4_DB2_1_S,
 956                                           db2[1]);
 957                 ath9k_hw_analog_shift_rmw(ah,
 958                                           AR9285_AN_RF2G4,
 959                                           AR9285_AN_RF2G4_DB2_2,
 960                                           AR9285_AN_RF2G4_DB2_2_S,
 961                                           db2[2]);
 962                 ath9k_hw_analog_shift_rmw(ah,
 963                                           AR9285_AN_RF2G4,
 964                                           AR9285_AN_RF2G4_DB2_3,
 965                                           AR9285_AN_RF2G4_DB2_3_S,
 966                                           db2[3]);
 967                 ath9k_hw_analog_shift_rmw(ah,
 968                                           AR9285_AN_RF2G4,
 969                                           AR9285_AN_RF2G4_DB2_4,
 970                                           AR9285_AN_RF2G4_DB2_4_S,
 971                                           db2[4]);
 972         }
 973
 974
 975         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 976                       pModal->switchSettling);
 977         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 978                       pModal->adcDesiredSize);
 979
 980         REG_WRITE(ah, AR_PHY_RF_CTL4,
 981                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
 982                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
 983                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
 984                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 985
 986         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 987                       pModal->txEndToRxOn);
 988
 989         if (AR_SREV_9271_10(ah))
 990                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 991                               pModal->txEndToRxOn);
 992         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 993                       pModal->thresh62);
 994         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
 995                       pModal->thresh62);
 996
 997         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 998                                                 AR5416_EEP_MINOR_VER_2) {
 999                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1000                               pModal->txFrameToDataStart);
1001                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1002                               pModal->txFrameToPaOn);
1003         }
1004
1005         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1006                                                 AR5416_EEP_MINOR_VER_3) {
1007                 if (IS_CHAN_HT40(chan))
1008                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1009                                       AR_PHY_SETTLING_SWITCH,
1010                                       pModal->swSettleHt40);
1011         }
1012         if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
1013                 u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1014                                 EEP_4K_BB_DESIRED_SCALE_MASK);
1015                 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1016                         u32 pwrctrl, mask, clr;
1017
1018                         mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1019                         pwrctrl = mask * bb_desired_scale;
1020                         clr = mask * 0x1f;
1021                         REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1022                         REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1023                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1024
1025                         mask = BIT(0)|BIT(5)|BIT(15);
1026                         pwrctrl = mask * bb_desired_scale;
1027                         clr = mask * 0x1f;
1028                         REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1029
1030                         mask = BIT(0)|BIT(5);
1031                         pwrctrl = mask * bb_desired_scale;
1032                         clr = mask * 0x1f;
1033                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1034                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1035                 }
1036         }
1037 }
1038
1039 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, int is2GHz)
1040 {
1041 #define EEP_MAP4K_SPURCHAN \
1042         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1043
1044         u16 spur_val = AR_NO_SPUR;
1045
1046         DBG2("ath9k: "
1047                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1048                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1049
1050         switch (ah->config.spurmode) {
1051         case SPUR_DISABLE:
1052                 break;
1053         case SPUR_ENABLE_IOCTL:
1054                 spur_val = ah->config.spurchans[i][is2GHz];
1055                 DBG2("ath9k: "
1056                         "Getting spur val from new loc. %d\n", spur_val);
1057                 break;
1058         case SPUR_ENABLE_EEPROM:
1059                 spur_val = EEP_MAP4K_SPURCHAN;
1060                 break;
1061         }
1062
1063         return spur_val;
1064
1065 #undef EEP_MAP4K_SPURCHAN
1066 }
1067
1068 const struct eeprom_ops eep_4k_ops = {
1069         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1070         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1071         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1072         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1073         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1074         .set_board_values       = ath9k_hw_4k_set_board_values,
1075         .set_addac              = ath9k_hw_4k_set_addac,
1076         .set_txpower            = ath9k_hw_4k_set_txpower,
1077         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1078 };