qemu/roms/ipxe/src/drivers/net/ath/ath9k/ath9k_ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
   5  * Original from Linux kernel 3.0.1
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #include <ipxe/io.h>
  21 #include <ipxe/malloc.h>
  22
  23 #include "hw.h"
  24 #include "ar9003_phy.h"
  25 #include "ar9003_eeprom.h"
  26
  27 #define COMP_HDR_LEN 4
  28 #define COMP_CKSUM_LEN 2
  29
  30 #define AR_CH0_TOP (0x00016288)
  31 #define AR_CH0_TOP_XPABIASLVL (0x300)
  32 #define AR_CH0_TOP_XPABIASLVL_S (8)
  33
  34 #define AR_CH0_THERM (0x00016290)
  35 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
  36 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
  37 #define AR_CH0_THERM_XPASHORT2GND 0x4
  38 #define AR_CH0_THERM_XPASHORT2GND_S 2
  39
  40 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  41 #define AR_SWITCH_TABLE_COM_ALL_S (0)
  42
  43 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
  44 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
  45
  46 #define AR_SWITCH_TABLE_ALL (0xfff)
  47 #define AR_SWITCH_TABLE_ALL_S (0)
  48
  49 #define LE16(x) (uint16_t)(x)
  50 #define LE32(x) (uint32_t)(x)
  51
  52 /* Local defines to distinguish between extension and control CTL's */
  53 #define EXT_ADDITIVE (0x8000)
  54 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  55 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  56 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  57 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  58 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
  59 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  60 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  61 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  62
  63 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  64 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  65
  66 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  67
  68 #define EEPROM_DATA_LEN_9485    1088
  69
  70 static int ar9003_hw_power_interpolate(int32_t x,
  71                                        int32_t *px, int32_t *py, uint16_t np);
  72
  73
  74 static const struct ar9300_eeprom ar9300_default = {
  75         .eepromVersion = 2,
  76         .templateVersion = 2,
  77         .macAddr = {1, 2, 3, 4, 5, 6},
  78         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  79                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  80         .baseEepHeader = {
  81                 .regDmn = { LE16(0), LE16(0x1f) },
  82                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  83                 .opCapFlags = {
  84                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  85                         .eepMisc = 0,
  86                 },
  87                 .rfSilent = 0,
  88                 .blueToothOptions = 0,
  89                 .deviceCap = 0,
  90                 .deviceType = 5, /* takes lower byte in eeprom location */
  91                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  92                 .params_for_tuning_caps = {0, 0},
  93                 .featureEnable = 0x0c,
  94                  /*
  95                   * bit0 - enable tx temp comp - disabled
  96                   * bit1 - enable tx volt comp - disabled
  97                   * bit2 - enable fastClock - enabled
  98                   * bit3 - enable doubling - enabled
  99                   * bit4 - enable internal regulator - disabled
 100                   * bit5 - enable pa predistortion - disabled
 101                   */
 102                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 103                 .eepromWriteEnableGpio = 3,
 104                 .wlanDisableGpio = 0,
 105                 .wlanLedGpio = 8,
 106                 .rxBandSelectGpio = 0xff,
 107                 .txrxgain = 0,
 108                 .swreg = 0,
 109          },
 110         .modalHeader2G = {
 111         /* ar9300_modal_eep_header  2g */
 112                 /* 4 idle,t1,t2,b(4 bits per setting) */
 113                 .antCtrlCommon = LE32(0x110),
 114                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 115                 .antCtrlCommon2 = LE32(0x22222),
 116
 117                 /*
 118                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 119                  * rx1, rx12, b (2 bits each)
 120                  */
 121                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 122
 123                 /*
 124                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 125                  * for ar9280 (0xa20c/b20c 5:0)
 126                  */
 127                 .xatten1DB = {0, 0, 0},
 128
 129                 /*
 130                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 131                  * for ar9280 (0xa20c/b20c 16:12
 132                  */
 133                 .xatten1Margin = {0, 0, 0},
 134                 .tempSlope = 36,
 135                 .voltSlope = 0,
 136
 137                 /*
 138                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 139                  * channels in usual fbin coding format
 140                  */
 141                 .spurChans = {0, 0, 0, 0, 0},
 142
 143                 /*
 144                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 145                  * if the register is per chain
 146                  */
 147                 .noiseFloorThreshCh = {-1, 0, 0},
 148                 .ob = {1, 1, 1},/* 3 chain */
 149                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 150                 .db_stage3 = {0, 0, 0},
 151                 .db_stage4 = {0, 0, 0},
 152                 .xpaBiasLvl = 0,
 153                 .txFrameToDataStart = 0x0e,
 154                 .txFrameToPaOn = 0x0e,
 155                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 156                 .antennaGain = 0,
 157                 .switchSettling = 0x2c,
 158                 .adcDesiredSize = -30,
 159                 .txEndToXpaOff = 0,
 160                 .txEndToRxOn = 0x2,
 161                 .txFrameToXpaOn = 0xe,
 162                 .thresh62 = 28,
 163                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 164                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 165                 .futureModal = {
 166                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 167                 },
 168          },
 169         .base_ext1 = {
 170                 .ant_div_control = 0,
 171                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 172         },
 173         .calFreqPier2G = {
 174                 FREQ2FBIN(2412, 1),
 175                 FREQ2FBIN(2437, 1),
 176                 FREQ2FBIN(2472, 1),
 177          },
 178         /* ar9300_cal_data_per_freq_op_loop 2g */
 179         .calPierData2G = {
 180                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 181                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 182                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 183          },
 184         .calTarget_freqbin_Cck = {
 185                 FREQ2FBIN(2412, 1),
 186                 FREQ2FBIN(2484, 1),
 187          },
 188         .calTarget_freqbin_2G = {
 189                 FREQ2FBIN(2412, 1),
 190                 FREQ2FBIN(2437, 1),
 191                 FREQ2FBIN(2472, 1)
 192          },
 193         .calTarget_freqbin_2GHT20 = {
 194                 FREQ2FBIN(2412, 1),
 195                 FREQ2FBIN(2437, 1),
 196                 FREQ2FBIN(2472, 1)
 197          },
 198         .calTarget_freqbin_2GHT40 = {
 199                 FREQ2FBIN(2412, 1),
 200                 FREQ2FBIN(2437, 1),
 201                 FREQ2FBIN(2472, 1)
 202          },
 203         .calTargetPowerCck = {
 204                  /* 1L-5L,5S,11L,11S */
 205                  { {36, 36, 36, 36} },
 206                  { {36, 36, 36, 36} },
 207         },
 208         .calTargetPower2G = {
 209                  /* 6-24,36,48,54 */
 210                  { {32, 32, 28, 24} },
 211                  { {32, 32, 28, 24} },
 212                  { {32, 32, 28, 24} },
 213         },
 214         .calTargetPower2GHT20 = {
 215                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 216                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 217                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 218         },
 219         .calTargetPower2GHT40 = {
 220                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 221                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 222                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 223         },
 224         .ctlIndex_2G =  {
 225                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 226                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 227         },
 228         .ctl_freqbin_2G = {
 229                 {
 230                         FREQ2FBIN(2412, 1),
 231                         FREQ2FBIN(2417, 1),
 232                         FREQ2FBIN(2457, 1),
 233                         FREQ2FBIN(2462, 1)
 234                 },
 235                 {
 236                         FREQ2FBIN(2412, 1),
 237                         FREQ2FBIN(2417, 1),
 238                         FREQ2FBIN(2462, 1),
 239                         0xFF,
 240                 },
 241
 242                 {
 243                         FREQ2FBIN(2412, 1),
 244                         FREQ2FBIN(2417, 1),
 245                         FREQ2FBIN(2462, 1),
 246                         0xFF,
 247                 },
 248                 {
 249                         FREQ2FBIN(2422, 1),
 250                         FREQ2FBIN(2427, 1),
 251                         FREQ2FBIN(2447, 1),
 252                         FREQ2FBIN(2452, 1)
 253                 },
 254
 255                 {
 256                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 257                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 258                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 259                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 260                 },
 261
 262                 {
 263                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 264                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 265                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 266                         0,
 267                 },
 268
 269                 {
 270                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 271                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 272                         FREQ2FBIN(2472, 1),
 273                         0,
 274                 },
 275
 276                 {
 277                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 278                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 279                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 280                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 281                 },
 282
 283                 {
 284                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 285                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 286                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 287                 },
 288
 289                 {
 290                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 291                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 292                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 293                         0
 294                 },
 295
 296                 {
 297                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 298                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 299                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 300                         0
 301                 },
 302
 303                 {
 304                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 305                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 306                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 307                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 308                 }
 309          },
 310         .ctlPowerData_2G = {
 311                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 312                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 313                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 314
 315                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 316                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 317                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 318
 319                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 320                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 321                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 322
 323                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 324                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 325                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 326          },
 327         .modalHeader5G = {
 328                 /* 4 idle,t1,t2,b (4 bits per setting) */
 329                 .antCtrlCommon = LE32(0x110),
 330                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 331                 .antCtrlCommon2 = LE32(0x22222),
 332                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 333                 .antCtrlChain = {
 334                         LE16(0x000), LE16(0x000), LE16(0x000),
 335                 },
 336                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 337                 .xatten1DB = {0, 0, 0},
 338
 339                 /*
 340                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 341                  * for merlin (0xa20c/b20c 16:12
 342                  */
 343                 .xatten1Margin = {0, 0, 0},
 344                 .tempSlope = 68,
 345                 .voltSlope = 0,
 346                 /* spurChans spur channels in usual fbin coding format */
 347                 .spurChans = {0, 0, 0, 0, 0},
 348                 /* noiseFloorThreshCh Check if the register is per chain */
 349                 .noiseFloorThreshCh = {-1, 0, 0},
 350                 .ob = {3, 3, 3}, /* 3 chain */
 351                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 352                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 353                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 354                 .xpaBiasLvl = 0,
 355                 .txFrameToDataStart = 0x0e,
 356                 .txFrameToPaOn = 0x0e,
 357                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 358                 .antennaGain = 0,
 359                 .switchSettling = 0x2d,
 360                 .adcDesiredSize = -30,
 361                 .txEndToXpaOff = 0,
 362                 .txEndToRxOn = 0x2,
 363                 .txFrameToXpaOn = 0xe,
 364                 .thresh62 = 28,
 365                 .papdRateMaskHt20 = LE32(0x0c80c080),
 366                 .papdRateMaskHt40 = LE32(0x0080c080),
 367                 .futureModal = {
 368                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 369                 },
 370          },
 371         .base_ext2 = {
 372                 .tempSlopeLow = 0,
 373                 .tempSlopeHigh = 0,
 374                 .xatten1DBLow = {0, 0, 0},
 375                 .xatten1MarginLow = {0, 0, 0},
 376                 .xatten1DBHigh = {0, 0, 0},
 377                 .xatten1MarginHigh = {0, 0, 0}
 378         },
 379         .calFreqPier5G = {
 380                 FREQ2FBIN(5180, 0),
 381                 FREQ2FBIN(5220, 0),
 382                 FREQ2FBIN(5320, 0),
 383                 FREQ2FBIN(5400, 0),
 384                 FREQ2FBIN(5500, 0),
 385                 FREQ2FBIN(5600, 0),
 386                 FREQ2FBIN(5725, 0),
 387                 FREQ2FBIN(5825, 0)
 388         },
 389         .calPierData5G = {
 390                         {
 391                                 {0, 0, 0, 0, 0, 0},
 392                                 {0, 0, 0, 0, 0, 0},
 393                                 {0, 0, 0, 0, 0, 0},
 394                                 {0, 0, 0, 0, 0, 0},
 395                                 {0, 0, 0, 0, 0, 0},
 396                                 {0, 0, 0, 0, 0, 0},
 397                                 {0, 0, 0, 0, 0, 0},
 398                                 {0, 0, 0, 0, 0, 0},
 399                         },
 400                         {
 401                                 {0, 0, 0, 0, 0, 0},
 402                                 {0, 0, 0, 0, 0, 0},
 403                                 {0, 0, 0, 0, 0, 0},
 404                                 {0, 0, 0, 0, 0, 0},
 405                                 {0, 0, 0, 0, 0, 0},
 406                                 {0, 0, 0, 0, 0, 0},
 407                                 {0, 0, 0, 0, 0, 0},
 408                                 {0, 0, 0, 0, 0, 0},
 409                         },
 410                         {
 411                                 {0, 0, 0, 0, 0, 0},
 412                                 {0, 0, 0, 0, 0, 0},
 413                                 {0, 0, 0, 0, 0, 0},
 414                                 {0, 0, 0, 0, 0, 0},
 415                                 {0, 0, 0, 0, 0, 0},
 416                                 {0, 0, 0, 0, 0, 0},
 417                                 {0, 0, 0, 0, 0, 0},
 418                                 {0, 0, 0, 0, 0, 0},
 419                         },
 420
 421         },
 422         .calTarget_freqbin_5G = {
 423                 FREQ2FBIN(5180, 0),
 424                 FREQ2FBIN(5220, 0),
 425                 FREQ2FBIN(5320, 0),
 426                 FREQ2FBIN(5400, 0),
 427                 FREQ2FBIN(5500, 0),
 428                 FREQ2FBIN(5600, 0),
 429                 FREQ2FBIN(5725, 0),
 430                 FREQ2FBIN(5825, 0)
 431         },
 432         .calTarget_freqbin_5GHT20 = {
 433                 FREQ2FBIN(5180, 0),
 434                 FREQ2FBIN(5240, 0),
 435                 FREQ2FBIN(5320, 0),
 436                 FREQ2FBIN(5500, 0),
 437                 FREQ2FBIN(5700, 0),
 438                 FREQ2FBIN(5745, 0),
 439                 FREQ2FBIN(5725, 0),
 440                 FREQ2FBIN(5825, 0)
 441         },
 442         .calTarget_freqbin_5GHT40 = {
 443                 FREQ2FBIN(5180, 0),
 444                 FREQ2FBIN(5240, 0),
 445                 FREQ2FBIN(5320, 0),
 446                 FREQ2FBIN(5500, 0),
 447                 FREQ2FBIN(5700, 0),
 448                 FREQ2FBIN(5745, 0),
 449                 FREQ2FBIN(5725, 0),
 450                 FREQ2FBIN(5825, 0)
 451          },
 452         .calTargetPower5G = {
 453                 /* 6-24,36,48,54 */
 454                 { {20, 20, 20, 10} },
 455                 { {20, 20, 20, 10} },
 456                 { {20, 20, 20, 10} },
 457                 { {20, 20, 20, 10} },
 458                 { {20, 20, 20, 10} },
 459                 { {20, 20, 20, 10} },
 460                 { {20, 20, 20, 10} },
 461                 { {20, 20, 20, 10} },
 462          },
 463         .calTargetPower5GHT20 = {
 464                 /*
 465                  * 0_8_16,1-3_9-11_17-19,
 466                  * 4,5,6,7,12,13,14,15,20,21,22,23
 467                  */
 468                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 469                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 470                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 471                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 472                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 473                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 474                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 475                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 476          },
 477         .calTargetPower5GHT40 =  {
 478                 /*
 479                  * 0_8_16,1-3_9-11_17-19,
 480                  * 4,5,6,7,12,13,14,15,20,21,22,23
 481                  */
 482                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 483                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 484                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 485                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 486                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 487                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 488                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 489                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 490          },
 491         .ctlIndex_5G =  {
 492                 0x10, 0x16, 0x18, 0x40, 0x46,
 493                 0x48, 0x30, 0x36, 0x38
 494         },
 495         .ctl_freqbin_5G =  {
 496                 {
 497                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 498                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 499                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 500                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 501                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 502                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 503                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 504                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 505                 },
 506                 {
 507                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 508                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 509                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 510                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 511                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 512                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 513                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 514                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 515                 },
 516
 517                 {
 518                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 519                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 520                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 521                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 522                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 523                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 524                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 525                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 526                 },
 527
 528                 {
 529                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 530                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 531                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 532                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 533                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 534                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 535                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 536                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 537                 },
 538
 539                 {
 540                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 541                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 542                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 543                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 544                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 545                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 546                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 547                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 548                 },
 549
 550                 {
 551                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 552                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 553                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 554                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 555                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 556                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 557                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 558                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 559                 },
 560
 561                 {
 562                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 563                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 564                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 565                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 566                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 567                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 568                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 569                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 570                 },
 571
 572                 {
 573                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 574                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 575                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 576                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 577                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 578                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 579                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 580                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 581                 },
 582
 583                 {
 584                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 585                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 586                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 587                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 588                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 589                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 590                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 591                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 592                 }
 593          },
 594         .ctlPowerData_5G = {
 595                 {
 596                         {
 597                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 598                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 599                         }
 600                 },
 601                 {
 602                         {
 603                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 604                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 605                         }
 606                 },
 607                 {
 608                         {
 609                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 610                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 611                         }
 612                 },
 613                 {
 614                         {
 615                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 616                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 617                         }
 618                 },
 619                 {
 620                         {
 621                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 622                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 623                         }
 624                 },
 625                 {
 626                         {
 627                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 628                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 629                         }
 630                 },
 631                 {
 632                         {
 633                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 634                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 635                         }
 636                 },
 637                 {
 638                         {
 639                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 640                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 641                         }
 642                 },
 643                 {
 644                         {
 645                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 646                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 647                         }
 648                 },
 649          }
 650 };
 651
 652 static const struct ar9300_eeprom ar9300_x113 = {
 653         .eepromVersion = 2,
 654         .templateVersion = 6,
 655         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 656         .custData = {"x113-023-f0000"},
 657         .baseEepHeader = {
 658                 .regDmn = { LE16(0), LE16(0x1f) },
 659                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 660                 .opCapFlags = {
 661                         .opFlags = AR5416_OPFLAGS_11A,
 662                         .eepMisc = 0,
 663                 },
 664                 .rfSilent = 0,
 665                 .blueToothOptions = 0,
 666                 .deviceCap = 0,
 667                 .deviceType = 5, /* takes lower byte in eeprom location */
 668                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 669                 .params_for_tuning_caps = {0, 0},
 670                 .featureEnable = 0x0d,
 671                  /*
 672                   * bit0 - enable tx temp comp - disabled
 673                   * bit1 - enable tx volt comp - disabled
 674                   * bit2 - enable fastClock - enabled
 675                   * bit3 - enable doubling - enabled
 676                   * bit4 - enable internal regulator - disabled
 677                   * bit5 - enable pa predistortion - disabled
 678                   */
 679                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 680                 .eepromWriteEnableGpio = 6,
 681                 .wlanDisableGpio = 0,
 682                 .wlanLedGpio = 8,
 683                 .rxBandSelectGpio = 0xff,
 684                 .txrxgain = 0x21,
 685                 .swreg = 0,
 686          },
 687         .modalHeader2G = {
 688         /* ar9300_modal_eep_header  2g */
 689                 /* 4 idle,t1,t2,b(4 bits per setting) */
 690                 .antCtrlCommon = LE32(0x110),
 691                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 692                 .antCtrlCommon2 = LE32(0x44444),
 693
 694                 /*
 695                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 696                  * rx1, rx12, b (2 bits each)
 697                  */
 698                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 699
 700                 /*
 701                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 702                  * for ar9280 (0xa20c/b20c 5:0)
 703                  */
 704                 .xatten1DB = {0, 0, 0},
 705
 706                 /*
 707                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 708                  * for ar9280 (0xa20c/b20c 16:12
 709                  */
 710                 .xatten1Margin = {0, 0, 0},
 711                 .tempSlope = 25,
 712                 .voltSlope = 0,
 713
 714                 /*
 715                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 716                  * channels in usual fbin coding format
 717                  */
 718                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 719
 720                 /*
 721                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 722                  * if the register is per chain
 723                  */
 724                 .noiseFloorThreshCh = {-1, 0, 0},
 725                 .ob = {1, 1, 1},/* 3 chain */
 726                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 727                 .db_stage3 = {0, 0, 0},
 728                 .db_stage4 = {0, 0, 0},
 729                 .xpaBiasLvl = 0,
 730                 .txFrameToDataStart = 0x0e,
 731                 .txFrameToPaOn = 0x0e,
 732                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 733                 .antennaGain = 0,
 734                 .switchSettling = 0x2c,
 735                 .adcDesiredSize = -30,
 736                 .txEndToXpaOff = 0,
 737                 .txEndToRxOn = 0x2,
 738                 .txFrameToXpaOn = 0xe,
 739                 .thresh62 = 28,
 740                 .papdRateMaskHt20 = LE32(0x0c80c080),
 741                 .papdRateMaskHt40 = LE32(0x0080c080),
 742                 .futureModal = {
 743                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 744                 },
 745          },
 746          .base_ext1 = {
 747                 .ant_div_control = 0,
 748                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 749          },
 750         .calFreqPier2G = {
 751                 FREQ2FBIN(2412, 1),
 752                 FREQ2FBIN(2437, 1),
 753                 FREQ2FBIN(2472, 1),
 754          },
 755         /* ar9300_cal_data_per_freq_op_loop 2g */
 756         .calPierData2G = {
 757                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 758                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 759                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 760          },
 761         .calTarget_freqbin_Cck = {
 762                 FREQ2FBIN(2412, 1),
 763                 FREQ2FBIN(2472, 1),
 764          },
 765         .calTarget_freqbin_2G = {
 766                 FREQ2FBIN(2412, 1),
 767                 FREQ2FBIN(2437, 1),
 768                 FREQ2FBIN(2472, 1)
 769          },
 770         .calTarget_freqbin_2GHT20 = {
 771                 FREQ2FBIN(2412, 1),
 772                 FREQ2FBIN(2437, 1),
 773                 FREQ2FBIN(2472, 1)
 774          },
 775         .calTarget_freqbin_2GHT40 = {
 776                 FREQ2FBIN(2412, 1),
 777                 FREQ2FBIN(2437, 1),
 778                 FREQ2FBIN(2472, 1)
 779          },
 780         .calTargetPowerCck = {
 781                  /* 1L-5L,5S,11L,11S */
 782                  { {34, 34, 34, 34} },
 783                  { {34, 34, 34, 34} },
 784         },
 785         .calTargetPower2G = {
 786                  /* 6-24,36,48,54 */
 787                  { {34, 34, 32, 32} },
 788                  { {34, 34, 32, 32} },
 789                  { {34, 34, 32, 32} },
 790         },
 791         .calTargetPower2GHT20 = {
 792                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 793                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 794                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 795         },
 796         .calTargetPower2GHT40 = {
 797                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 798                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 799                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 800         },
 801         .ctlIndex_2G =  {
 802                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 803                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 804         },
 805         .ctl_freqbin_2G = {
 806                 {
 807                         FREQ2FBIN(2412, 1),
 808                         FREQ2FBIN(2417, 1),
 809                         FREQ2FBIN(2457, 1),
 810                         FREQ2FBIN(2462, 1)
 811                 },
 812                 {
 813                         FREQ2FBIN(2412, 1),
 814                         FREQ2FBIN(2417, 1),
 815                         FREQ2FBIN(2462, 1),
 816                         0xFF,
 817                 },
 818
 819                 {
 820                         FREQ2FBIN(2412, 1),
 821                         FREQ2FBIN(2417, 1),
 822                         FREQ2FBIN(2462, 1),
 823                         0xFF,
 824                 },
 825                 {
 826                         FREQ2FBIN(2422, 1),
 827                         FREQ2FBIN(2427, 1),
 828                         FREQ2FBIN(2447, 1),
 829                         FREQ2FBIN(2452, 1)
 830                 },
 831
 832                 {
 833                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 834                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 835                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 836                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 837                 },
 838
 839                 {
 840                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 841                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 842                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 843                         0,
 844                 },
 845
 846                 {
 847                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 848                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 849                         FREQ2FBIN(2472, 1),
 850                         0,
 851                 },
 852
 853                 {
 854                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 855                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 856                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 857                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 858                 },
 859
 860                 {
 861                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 862                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 863                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 864                 },
 865
 866                 {
 867                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 868                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 869                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 870                         0
 871                 },
 872
 873                 {
 874                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 875                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 876                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 877                         0
 878                 },
 879
 880                 {
 881                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 882                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 883                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 884                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 885                 }
 886          },
 887         .ctlPowerData_2G = {
 888                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 889                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 890                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 891
 892                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 893                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 894                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 895
 896                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 897                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 898                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 899
 900                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 901                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 902                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 903          },
 904         .modalHeader5G = {
 905                 /* 4 idle,t1,t2,b (4 bits per setting) */
 906                 .antCtrlCommon = LE32(0x220),
 907                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 908                 .antCtrlCommon2 = LE32(0x11111),
 909                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 910                 .antCtrlChain = {
 911                         LE16(0x150), LE16(0x150), LE16(0x150),
 912                 },
 913                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 914                 .xatten1DB = {0, 0, 0},
 915
 916                 /*
 917                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 918                  * for merlin (0xa20c/b20c 16:12
 919                  */
 920                 .xatten1Margin = {0, 0, 0},
 921                 .tempSlope = 68,
 922                 .voltSlope = 0,
 923                 /* spurChans spur channels in usual fbin coding format */
 924                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 925                 /* noiseFloorThreshCh Check if the register is per chain */
 926                 .noiseFloorThreshCh = {-1, 0, 0},
 927                 .ob = {3, 3, 3}, /* 3 chain */
 928                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 929                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 930                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 931                 .xpaBiasLvl = 0xf,
 932                 .txFrameToDataStart = 0x0e,
 933                 .txFrameToPaOn = 0x0e,
 934                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 935                 .antennaGain = 0,
 936                 .switchSettling = 0x2d,
 937                 .adcDesiredSize = -30,
 938                 .txEndToXpaOff = 0,
 939                 .txEndToRxOn = 0x2,
 940                 .txFrameToXpaOn = 0xe,
 941                 .thresh62 = 28,
 942                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 943                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 944                 .futureModal = {
 945                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 946                 },
 947          },
 948         .base_ext2 = {
 949                 .tempSlopeLow = 72,
 950                 .tempSlopeHigh = 105,
 951                 .xatten1DBLow = {0, 0, 0},
 952                 .xatten1MarginLow = {0, 0, 0},
 953                 .xatten1DBHigh = {0, 0, 0},
 954                 .xatten1MarginHigh = {0, 0, 0}
 955          },
 956         .calFreqPier5G = {
 957                 FREQ2FBIN(5180, 0),
 958                 FREQ2FBIN(5240, 0),
 959                 FREQ2FBIN(5320, 0),
 960                 FREQ2FBIN(5400, 0),
 961                 FREQ2FBIN(5500, 0),
 962                 FREQ2FBIN(5600, 0),
 963                 FREQ2FBIN(5745, 0),
 964                 FREQ2FBIN(5785, 0)
 965         },
 966         .calPierData5G = {
 967                         {
 968                                 {0, 0, 0, 0, 0, 0},
 969                                 {0, 0, 0, 0, 0, 0},
 970                                 {0, 0, 0, 0, 0, 0},
 971                                 {0, 0, 0, 0, 0, 0},
 972                                 {0, 0, 0, 0, 0, 0},
 973                                 {0, 0, 0, 0, 0, 0},
 974                                 {0, 0, 0, 0, 0, 0},
 975                                 {0, 0, 0, 0, 0, 0},
 976                         },
 977                         {
 978                                 {0, 0, 0, 0, 0, 0},
 979                                 {0, 0, 0, 0, 0, 0},
 980                                 {0, 0, 0, 0, 0, 0},
 981                                 {0, 0, 0, 0, 0, 0},
 982                                 {0, 0, 0, 0, 0, 0},
 983                                 {0, 0, 0, 0, 0, 0},
 984                                 {0, 0, 0, 0, 0, 0},
 985                                 {0, 0, 0, 0, 0, 0},
 986                         },
 987                         {
 988                                 {0, 0, 0, 0, 0, 0},
 989                                 {0, 0, 0, 0, 0, 0},
 990                                 {0, 0, 0, 0, 0, 0},
 991                                 {0, 0, 0, 0, 0, 0},
 992                                 {0, 0, 0, 0, 0, 0},
 993                                 {0, 0, 0, 0, 0, 0},
 994                                 {0, 0, 0, 0, 0, 0},
 995                                 {0, 0, 0, 0, 0, 0},
 996                         },
 997
 998         },
 999         .calTarget_freqbin_5G = {
1000                 FREQ2FBIN(5180, 0),
1001                 FREQ2FBIN(5220, 0),
1002                 FREQ2FBIN(5320, 0),
1003                 FREQ2FBIN(5400, 0),
1004                 FREQ2FBIN(5500, 0),
1005                 FREQ2FBIN(5600, 0),
1006                 FREQ2FBIN(5745, 0),
1007                 FREQ2FBIN(5785, 0)
1008         },
1009         .calTarget_freqbin_5GHT20 = {
1010                 FREQ2FBIN(5180, 0),
1011                 FREQ2FBIN(5240, 0),
1012                 FREQ2FBIN(5320, 0),
1013                 FREQ2FBIN(5400, 0),
1014                 FREQ2FBIN(5500, 0),
1015                 FREQ2FBIN(5700, 0),
1016                 FREQ2FBIN(5745, 0),
1017                 FREQ2FBIN(5825, 0)
1018         },
1019         .calTarget_freqbin_5GHT40 = {
1020                 FREQ2FBIN(5190, 0),
1021                 FREQ2FBIN(5230, 0),
1022                 FREQ2FBIN(5320, 0),
1023                 FREQ2FBIN(5410, 0),
1024                 FREQ2FBIN(5510, 0),
1025                 FREQ2FBIN(5670, 0),
1026                 FREQ2FBIN(5755, 0),
1027                 FREQ2FBIN(5825, 0)
1028          },
1029         .calTargetPower5G = {
1030                 /* 6-24,36,48,54 */
1031                 { {42, 40, 40, 34} },
1032                 { {42, 40, 40, 34} },
1033                 { {42, 40, 40, 34} },
1034                 { {42, 40, 40, 34} },
1035                 { {42, 40, 40, 34} },
1036                 { {42, 40, 40, 34} },
1037                 { {42, 40, 40, 34} },
1038                 { {42, 40, 40, 34} },
1039          },
1040         .calTargetPower5GHT20 = {
1041                 /*
1042                  * 0_8_16,1-3_9-11_17-19,
1043                  * 4,5,6,7,12,13,14,15,20,21,22,23
1044                  */
1045                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1046                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1047                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1048                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1049                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1050                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1051                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1052                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1053          },
1054         .calTargetPower5GHT40 =  {
1055                 /*
1056                  * 0_8_16,1-3_9-11_17-19,
1057                  * 4,5,6,7,12,13,14,15,20,21,22,23
1058                  */
1059                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1060                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1061                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1062                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1063                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1064                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1065                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1066                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1067          },
1068         .ctlIndex_5G =  {
1069                 0x10, 0x16, 0x18, 0x40, 0x46,
1070                 0x48, 0x30, 0x36, 0x38
1071         },
1072         .ctl_freqbin_5G =  {
1073                 {
1074                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1075                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1076                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1077                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1078                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1079                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1080                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1081                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1082                 },
1083                 {
1084                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1085                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1086                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1087                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1088                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1089                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1090                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1091                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1092                 },
1093
1094                 {
1095                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1096                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1097                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1098                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1099                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1100                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1101                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1102                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1103                 },
1104
1105                 {
1106                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1107                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1108                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1109                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1110                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1111                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1112                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1113                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1114                 },
1115
1116                 {
1117                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1118                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1119                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1120                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1121                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1122                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1123                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1124                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1125                 },
1126
1127                 {
1128                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1129                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1130                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1131                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1132                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1133                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1134                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1135                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1136                 },
1137
1138                 {
1139                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1140                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1141                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1142                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1143                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1144                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1145                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1146                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1147                 },
1148
1149                 {
1150                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1151                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1152                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1153                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1154                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1155                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1156                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1157                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1158                 },
1159
1160                 {
1161                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1162                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1163                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1164                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1165                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1166                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1167                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1168                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1169                 }
1170          },
1171         .ctlPowerData_5G = {
1172                 {
1173                         {
1174                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1175                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1176                         }
1177                 },
1178                 {
1179                         {
1180                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1181                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1182                         }
1183                 },
1184                 {
1185                         {
1186                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1187                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1188                         }
1189                 },
1190                 {
1191                         {
1192                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1193                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1194                         }
1195                 },
1196                 {
1197                         {
1198                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1199                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1200                         }
1201                 },
1202                 {
1203                         {
1204                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1205                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1206                         }
1207                 },
1208                 {
1209                         {
1210                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1211                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1212                         }
1213                 },
1214                 {
1215                         {
1216                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1217                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1218                         }
1219                 },
1220                 {
1221                         {
1222                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1223                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1224                         }
1225                 },
1226          }
1227 };
1228
1229
1230 static const struct ar9300_eeprom ar9300_h112 = {
1231         .eepromVersion = 2,
1232         .templateVersion = 3,
1233         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1234         .custData = {"h112-241-f0000"},
1235         .baseEepHeader = {
1236                 .regDmn = { LE16(0), LE16(0x1f) },
1237                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1238                 .opCapFlags = {
1239                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1240                         .eepMisc = 0,
1241                 },
1242                 .rfSilent = 0,
1243                 .blueToothOptions = 0,
1244                 .deviceCap = 0,
1245                 .deviceType = 5, /* takes lower byte in eeprom location */
1246                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1247                 .params_for_tuning_caps = {0, 0},
1248                 .featureEnable = 0x0d,
1249                 /*
1250                  * bit0 - enable tx temp comp - disabled
1251                  * bit1 - enable tx volt comp - disabled
1252                  * bit2 - enable fastClock - enabled
1253                  * bit3 - enable doubling - enabled
1254                  * bit4 - enable internal regulator - disabled
1255                  * bit5 - enable pa predistortion - disabled
1256                  */
1257                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1258                 .eepromWriteEnableGpio = 6,
1259                 .wlanDisableGpio = 0,
1260                 .wlanLedGpio = 8,
1261                 .rxBandSelectGpio = 0xff,
1262                 .txrxgain = 0x10,
1263                 .swreg = 0,
1264         },
1265         .modalHeader2G = {
1266                 /* ar9300_modal_eep_header  2g */
1267                 /* 4 idle,t1,t2,b(4 bits per setting) */
1268                 .antCtrlCommon = LE32(0x110),
1269                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1270                 .antCtrlCommon2 = LE32(0x44444),
1271
1272                 /*
1273                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1274                  * rx1, rx12, b (2 bits each)
1275                  */
1276                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1277
1278                 /*
1279                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1280                  * for ar9280 (0xa20c/b20c 5:0)
1281                  */
1282                 .xatten1DB = {0, 0, 0},
1283
1284                 /*
1285                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1286                  * for ar9280 (0xa20c/b20c 16:12
1287                  */
1288                 .xatten1Margin = {0, 0, 0},
1289                 .tempSlope = 25,
1290                 .voltSlope = 0,
1291
1292                 /*
1293                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1294                  * channels in usual fbin coding format
1295                  */
1296                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1297
1298                 /*
1299                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1300                  * if the register is per chain
1301                  */
1302                 .noiseFloorThreshCh = {-1, 0, 0},
1303                 .ob = {1, 1, 1},/* 3 chain */
1304                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1305                 .db_stage3 = {0, 0, 0},
1306                 .db_stage4 = {0, 0, 0},
1307                 .xpaBiasLvl = 0,
1308                 .txFrameToDataStart = 0x0e,
1309                 .txFrameToPaOn = 0x0e,
1310                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1311                 .antennaGain = 0,
1312                 .switchSettling = 0x2c,
1313                 .adcDesiredSize = -30,
1314                 .txEndToXpaOff = 0,
1315                 .txEndToRxOn = 0x2,
1316                 .txFrameToXpaOn = 0xe,
1317                 .thresh62 = 28,
1318                 .papdRateMaskHt20 = LE32(0x80c080),
1319                 .papdRateMaskHt40 = LE32(0x80c080),
1320                 .futureModal = {
1321                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1322                 },
1323         },
1324         .base_ext1 = {
1325                 .ant_div_control = 0,
1326                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1327         },
1328         .calFreqPier2G = {
1329                 FREQ2FBIN(2412, 1),
1330                 FREQ2FBIN(2437, 1),
1331                 FREQ2FBIN(2472, 1),
1332         },
1333         /* ar9300_cal_data_per_freq_op_loop 2g */
1334         .calPierData2G = {
1335                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1336                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1337                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1338         },
1339         .calTarget_freqbin_Cck = {
1340                 FREQ2FBIN(2412, 1),
1341                 FREQ2FBIN(2484, 1),
1342         },
1343         .calTarget_freqbin_2G = {
1344                 FREQ2FBIN(2412, 1),
1345                 FREQ2FBIN(2437, 1),
1346                 FREQ2FBIN(2472, 1)
1347         },
1348         .calTarget_freqbin_2GHT20 = {
1349                 FREQ2FBIN(2412, 1),
1350                 FREQ2FBIN(2437, 1),
1351                 FREQ2FBIN(2472, 1)
1352         },
1353         .calTarget_freqbin_2GHT40 = {
1354                 FREQ2FBIN(2412, 1),
1355                 FREQ2FBIN(2437, 1),
1356                 FREQ2FBIN(2472, 1)
1357         },
1358         .calTargetPowerCck = {
1359                 /* 1L-5L,5S,11L,11S */
1360                 { {34, 34, 34, 34} },
1361                 { {34, 34, 34, 34} },
1362         },
1363         .calTargetPower2G = {
1364                 /* 6-24,36,48,54 */
1365                 { {34, 34, 32, 32} },
1366                 { {34, 34, 32, 32} },
1367                 { {34, 34, 32, 32} },
1368         },
1369         .calTargetPower2GHT20 = {
1370                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1371                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1372                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1373         },
1374         .calTargetPower2GHT40 = {
1375                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1376                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1377                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1378         },
1379         .ctlIndex_2G =  {
1380                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1381                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1382         },
1383         .ctl_freqbin_2G = {
1384                 {
1385                         FREQ2FBIN(2412, 1),
1386                         FREQ2FBIN(2417, 1),
1387                         FREQ2FBIN(2457, 1),
1388                         FREQ2FBIN(2462, 1)
1389                 },
1390                 {
1391                         FREQ2FBIN(2412, 1),
1392                         FREQ2FBIN(2417, 1),
1393                         FREQ2FBIN(2462, 1),
1394                         0xFF,
1395                 },
1396
1397                 {
1398                         FREQ2FBIN(2412, 1),
1399                         FREQ2FBIN(2417, 1),
1400                         FREQ2FBIN(2462, 1),
1401                         0xFF,
1402                 },
1403                 {
1404                         FREQ2FBIN(2422, 1),
1405                         FREQ2FBIN(2427, 1),
1406                         FREQ2FBIN(2447, 1),
1407                         FREQ2FBIN(2452, 1)
1408                 },
1409
1410                 {
1411                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1412                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1413                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1414                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1415                 },
1416
1417                 {
1418                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1419                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1421                         0,
1422                 },
1423
1424                 {
1425                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1426                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1427                         FREQ2FBIN(2472, 1),
1428                         0,
1429                 },
1430
1431                 {
1432                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1433                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1434                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1435                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1436                 },
1437
1438                 {
1439                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1440                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1441                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1442                 },
1443
1444                 {
1445                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1446                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1447                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1448                         0
1449                 },
1450
1451                 {
1452                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1453                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1454                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1455                         0
1456                 },
1457
1458                 {
1459                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1460                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1461                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1462                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1463                 }
1464         },
1465         .ctlPowerData_2G = {
1466                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1467                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1468                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1469
1470                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
1471                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1472                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1473
1474                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1475                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1476                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1477
1478                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1479                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1480                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1481         },
1482         .modalHeader5G = {
1483                 /* 4 idle,t1,t2,b (4 bits per setting) */
1484                 .antCtrlCommon = LE32(0x220),
1485                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1486                 .antCtrlCommon2 = LE32(0x44444),
1487                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1488                 .antCtrlChain = {
1489                         LE16(0x150), LE16(0x150), LE16(0x150),
1490                 },
1491                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1492                 .xatten1DB = {0, 0, 0},
1493
1494                 /*
1495                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1496                  * for merlin (0xa20c/b20c 16:12
1497                  */
1498                 .xatten1Margin = {0, 0, 0},
1499                 .tempSlope = 45,
1500                 .voltSlope = 0,
1501                 /* spurChans spur channels in usual fbin coding format */
1502                 .spurChans = {0, 0, 0, 0, 0},
1503                 /* noiseFloorThreshCh Check if the register is per chain */
1504                 .noiseFloorThreshCh = {-1, 0, 0},
1505                 .ob = {3, 3, 3}, /* 3 chain */
1506                 .db_stage2 = {3, 3, 3}, /* 3 chain */
1507                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1508                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
1509                 .xpaBiasLvl = 0,
1510                 .txFrameToDataStart = 0x0e,
1511                 .txFrameToPaOn = 0x0e,
1512                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1513                 .antennaGain = 0,
1514                 .switchSettling = 0x2d,
1515                 .adcDesiredSize = -30,
1516                 .txEndToXpaOff = 0,
1517                 .txEndToRxOn = 0x2,
1518                 .txFrameToXpaOn = 0xe,
1519                 .thresh62 = 28,
1520                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1521                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1522                 .futureModal = {
1523                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1524                 },
1525         },
1526         .base_ext2 = {
1527                 .tempSlopeLow = 40,
1528                 .tempSlopeHigh = 50,
1529                 .xatten1DBLow = {0, 0, 0},
1530                 .xatten1MarginLow = {0, 0, 0},
1531                 .xatten1DBHigh = {0, 0, 0},
1532                 .xatten1MarginHigh = {0, 0, 0}
1533         },
1534         .calFreqPier5G = {
1535                 FREQ2FBIN(5180, 0),
1536                 FREQ2FBIN(5220, 0),
1537                 FREQ2FBIN(5320, 0),
1538                 FREQ2FBIN(5400, 0),
1539                 FREQ2FBIN(5500, 0),
1540                 FREQ2FBIN(5600, 0),
1541                 FREQ2FBIN(5700, 0),
1542                 FREQ2FBIN(5825, 0)
1543         },
1544         .calPierData5G = {
1545                 {
1546                         {0, 0, 0, 0, 0, 0},
1547                         {0, 0, 0, 0, 0, 0},
1548                         {0, 0, 0, 0, 0, 0},
1549                         {0, 0, 0, 0, 0, 0},
1550                         {0, 0, 0, 0, 0, 0},
1551                         {0, 0, 0, 0, 0, 0},
1552                         {0, 0, 0, 0, 0, 0},
1553                         {0, 0, 0, 0, 0, 0},
1554                 },
1555                 {
1556                         {0, 0, 0, 0, 0, 0},
1557                         {0, 0, 0, 0, 0, 0},
1558                         {0, 0, 0, 0, 0, 0},
1559                         {0, 0, 0, 0, 0, 0},
1560                         {0, 0, 0, 0, 0, 0},
1561                         {0, 0, 0, 0, 0, 0},
1562                         {0, 0, 0, 0, 0, 0},
1563                         {0, 0, 0, 0, 0, 0},
1564                 },
1565                 {
1566                         {0, 0, 0, 0, 0, 0},
1567                         {0, 0, 0, 0, 0, 0},
1568                         {0, 0, 0, 0, 0, 0},
1569                         {0, 0, 0, 0, 0, 0},
1570                         {0, 0, 0, 0, 0, 0},
1571                         {0, 0, 0, 0, 0, 0},
1572                         {0, 0, 0, 0, 0, 0},
1573                         {0, 0, 0, 0, 0, 0},
1574                 },
1575
1576         },
1577         .calTarget_freqbin_5G = {
1578                 FREQ2FBIN(5180, 0),
1579                 FREQ2FBIN(5240, 0),
1580                 FREQ2FBIN(5320, 0),
1581                 FREQ2FBIN(5400, 0),
1582                 FREQ2FBIN(5500, 0),
1583                 FREQ2FBIN(5600, 0),
1584                 FREQ2FBIN(5700, 0),
1585                 FREQ2FBIN(5825, 0)
1586         },
1587         .calTarget_freqbin_5GHT20 = {
1588                 FREQ2FBIN(5180, 0),
1589                 FREQ2FBIN(5240, 0),
1590                 FREQ2FBIN(5320, 0),
1591                 FREQ2FBIN(5400, 0),
1592                 FREQ2FBIN(5500, 0),
1593                 FREQ2FBIN(5700, 0),
1594                 FREQ2FBIN(5745, 0),
1595                 FREQ2FBIN(5825, 0)
1596         },
1597         .calTarget_freqbin_5GHT40 = {
1598                 FREQ2FBIN(5180, 0),
1599                 FREQ2FBIN(5240, 0),
1600                 FREQ2FBIN(5320, 0),
1601                 FREQ2FBIN(5400, 0),
1602                 FREQ2FBIN(5500, 0),
1603                 FREQ2FBIN(5700, 0),
1604                 FREQ2FBIN(5745, 0),
1605                 FREQ2FBIN(5825, 0)
1606         },
1607         .calTargetPower5G = {
1608                 /* 6-24,36,48,54 */
1609                 { {30, 30, 28, 24} },
1610                 { {30, 30, 28, 24} },
1611                 { {30, 30, 28, 24} },
1612                 { {30, 30, 28, 24} },
1613                 { {30, 30, 28, 24} },
1614                 { {30, 30, 28, 24} },
1615                 { {30, 30, 28, 24} },
1616                 { {30, 30, 28, 24} },
1617         },
1618         .calTargetPower5GHT20 = {
1619                 /*
1620                  * 0_8_16,1-3_9-11_17-19,
1621                  * 4,5,6,7,12,13,14,15,20,21,22,23
1622                  */
1623                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1624                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1625                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1626                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1627                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1628                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1629                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1630                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1631         },
1632         .calTargetPower5GHT40 =  {
1633                 /*
1634                  * 0_8_16,1-3_9-11_17-19,
1635                  * 4,5,6,7,12,13,14,15,20,21,22,23
1636                  */
1637                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1638                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1639                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1640                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1641                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1642                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1643                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1644                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1645         },
1646         .ctlIndex_5G =  {
1647                 0x10, 0x16, 0x18, 0x40, 0x46,
1648                 0x48, 0x30, 0x36, 0x38
1649         },
1650         .ctl_freqbin_5G =  {
1651                 {
1652                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1653                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1654                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1655                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1656                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1657                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1658                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1659                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1660                 },
1661                 {
1662                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1663                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1664                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1665                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1666                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1667                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1668                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1669                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1670                 },
1671
1672                 {
1673                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1674                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1675                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1676                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1677                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1678                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1679                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1680                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1681                 },
1682
1683                 {
1684                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1685                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1686                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1687                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1688                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1689                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1690                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1691                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1692                 },
1693
1694                 {
1695                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1696                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1697                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1698                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1699                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1700                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1701                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1702                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1703                 },
1704
1705                 {
1706                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1707                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1708                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1709                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1710                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1711                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1712                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1713                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1714                 },
1715
1716                 {
1717                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1718                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1719                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1720                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1721                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1722                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1723                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1724                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1725                 },
1726
1727                 {
1728                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1729                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1730                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1731                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1732                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1733                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1734                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1735                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1736                 },
1737
1738                 {
1739                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1740                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1741                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1742                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1743                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1744                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1745                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1746                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1747                 }
1748         },
1749         .ctlPowerData_5G = {
1750                 {
1751                         {
1752                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1753                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1754                         }
1755                 },
1756                 {
1757                         {
1758                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1759                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1760                         }
1761                 },
1762                 {
1763                         {
1764                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1765                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1766                         }
1767                 },
1768                 {
1769                         {
1770                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1771                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1772                         }
1773                 },
1774                 {
1775                         {
1776                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1777                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1778                         }
1779                 },
1780                 {
1781                         {
1782                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1783                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1784                         }
1785                 },
1786                 {
1787                         {
1788                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1789                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1790                         }
1791                 },
1792                 {
1793                         {
1794                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1795                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1796                         }
1797                 },
1798                 {
1799                         {
1800                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1801                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1802                         }
1803                 },
1804         }
1805 };
1806
1807
1808 static const struct ar9300_eeprom ar9300_x112 = {
1809         .eepromVersion = 2,
1810         .templateVersion = 5,
1811         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1812         .custData = {"x112-041-f0000"},
1813         .baseEepHeader = {
1814                 .regDmn = { LE16(0), LE16(0x1f) },
1815                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1816                 .opCapFlags = {
1817                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1818                         .eepMisc = 0,
1819                 },
1820                 .rfSilent = 0,
1821                 .blueToothOptions = 0,
1822                 .deviceCap = 0,
1823                 .deviceType = 5, /* takes lower byte in eeprom location */
1824                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1825                 .params_for_tuning_caps = {0, 0},
1826                 .featureEnable = 0x0d,
1827                 /*
1828                  * bit0 - enable tx temp comp - disabled
1829                  * bit1 - enable tx volt comp - disabled
1830                  * bit2 - enable fastclock - enabled
1831                  * bit3 - enable doubling - enabled
1832                  * bit4 - enable internal regulator - disabled
1833                  * bit5 - enable pa predistortion - disabled
1834                  */
1835                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1836                 .eepromWriteEnableGpio = 6,
1837                 .wlanDisableGpio = 0,
1838                 .wlanLedGpio = 8,
1839                 .rxBandSelectGpio = 0xff,
1840                 .txrxgain = 0x0,
1841                 .swreg = 0,
1842         },
1843         .modalHeader2G = {
1844                 /* ar9300_modal_eep_header  2g */
1845                 /* 4 idle,t1,t2,b(4 bits per setting) */
1846                 .antCtrlCommon = LE32(0x110),
1847                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1848                 .antCtrlCommon2 = LE32(0x22222),
1849
1850                 /*
1851                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1852                  * rx1, rx12, b (2 bits each)
1853                  */
1854                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1855
1856                 /*
1857                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1858                  * for ar9280 (0xa20c/b20c 5:0)
1859                  */
1860                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1861
1862                 /*
1863                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1864                  * for ar9280 (0xa20c/b20c 16:12
1865                  */
1866                 .xatten1Margin = {0x15, 0x15, 0x15},
1867                 .tempSlope = 50,
1868                 .voltSlope = 0,
1869
1870                 /*
1871                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1872                  * channels in usual fbin coding format
1873                  */
1874                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1875
1876                 /*
1877                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1878                  * if the register is per chain
1879                  */
1880                 .noiseFloorThreshCh = {-1, 0, 0},
1881                 .ob = {1, 1, 1},/* 3 chain */
1882                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1883                 .db_stage3 = {0, 0, 0},
1884                 .db_stage4 = {0, 0, 0},
1885                 .xpaBiasLvl = 0,
1886                 .txFrameToDataStart = 0x0e,
1887                 .txFrameToPaOn = 0x0e,
1888                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1889                 .antennaGain = 0,
1890                 .switchSettling = 0x2c,
1891                 .adcDesiredSize = -30,
1892                 .txEndToXpaOff = 0,
1893                 .txEndToRxOn = 0x2,
1894                 .txFrameToXpaOn = 0xe,
1895                 .thresh62 = 28,
1896                 .papdRateMaskHt20 = LE32(0x0c80c080),
1897                 .papdRateMaskHt40 = LE32(0x0080c080),
1898                 .futureModal = {
1899                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1900                 },
1901         },
1902         .base_ext1 = {
1903                 .ant_div_control = 0,
1904                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1905         },
1906         .calFreqPier2G = {
1907                 FREQ2FBIN(2412, 1),
1908                 FREQ2FBIN(2437, 1),
1909                 FREQ2FBIN(2472, 1),
1910         },
1911         /* ar9300_cal_data_per_freq_op_loop 2g */
1912         .calPierData2G = {
1913                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1914                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1915                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1916         },
1917         .calTarget_freqbin_Cck = {
1918                 FREQ2FBIN(2412, 1),
1919                 FREQ2FBIN(2472, 1),
1920         },
1921         .calTarget_freqbin_2G = {
1922                 FREQ2FBIN(2412, 1),
1923                 FREQ2FBIN(2437, 1),
1924                 FREQ2FBIN(2472, 1)
1925         },
1926         .calTarget_freqbin_2GHT20 = {
1927                 FREQ2FBIN(2412, 1),
1928                 FREQ2FBIN(2437, 1),
1929                 FREQ2FBIN(2472, 1)
1930         },
1931         .calTarget_freqbin_2GHT40 = {
1932                 FREQ2FBIN(2412, 1),
1933                 FREQ2FBIN(2437, 1),
1934                 FREQ2FBIN(2472, 1)
1935         },
1936         .calTargetPowerCck = {
1937                 /* 1L-5L,5S,11L,11s */
1938                 { {38, 38, 38, 38} },
1939                 { {38, 38, 38, 38} },
1940         },
1941         .calTargetPower2G = {
1942                 /* 6-24,36,48,54 */
1943                 { {38, 38, 36, 34} },
1944                 { {38, 38, 36, 34} },
1945                 { {38, 38, 34, 32} },
1946         },
1947         .calTargetPower2GHT20 = {
1948                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1949                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1950                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1951         },
1952         .calTargetPower2GHT40 = {
1953                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1954                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1955                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1956         },
1957         .ctlIndex_2G =  {
1958                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1959                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1960         },
1961         .ctl_freqbin_2G = {
1962                 {
1963                         FREQ2FBIN(2412, 1),
1964                         FREQ2FBIN(2417, 1),
1965                         FREQ2FBIN(2457, 1),
1966                         FREQ2FBIN(2462, 1)
1967                 },
1968                 {
1969                         FREQ2FBIN(2412, 1),
1970                         FREQ2FBIN(2417, 1),
1971                         FREQ2FBIN(2462, 1),
1972                         0xFF,
1973                 },
1974
1975                 {
1976                         FREQ2FBIN(2412, 1),
1977                         FREQ2FBIN(2417, 1),
1978                         FREQ2FBIN(2462, 1),
1979                         0xFF,
1980                 },
1981                 {
1982                         FREQ2FBIN(2422, 1),
1983                         FREQ2FBIN(2427, 1),
1984                         FREQ2FBIN(2447, 1),
1985                         FREQ2FBIN(2452, 1)
1986                 },
1987
1988                 {
1989                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1990                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1991                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1992                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1993                 },
1994
1995                 {
1996                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1997                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1998                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1999                         0,
2000                 },
2001
2002                 {
2003                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2004                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2005                         FREQ2FBIN(2472, 1),
2006                         0,
2007                 },
2008
2009                 {
2010                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2011                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2012                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2013                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2014                 },
2015
2016                 {
2017                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2018                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2019                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2020                 },
2021
2022                 {
2023                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2024                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2025                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2026                         0
2027                 },
2028
2029                 {
2030                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2031                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2032                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2033                         0
2034                 },
2035
2036                 {
2037                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2038                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2039                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2040                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2041                 }
2042         },
2043         .ctlPowerData_2G = {
2044                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2046                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2047
2048                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2049                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2050                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2051
2052                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2053                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2054                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2055
2056                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2057                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2058                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2059         },
2060         .modalHeader5G = {
2061                 /* 4 idle,t1,t2,b (4 bits per setting) */
2062                 .antCtrlCommon = LE32(0x110),
2063                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2064                 .antCtrlCommon2 = LE32(0x22222),
2065                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2066                 .antCtrlChain = {
2067                         LE16(0x0), LE16(0x0), LE16(0x0),
2068                 },
2069                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2070                 .xatten1DB = {0x13, 0x19, 0x17},
2071
2072                 /*
2073                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2074                  * for merlin (0xa20c/b20c 16:12
2075                  */
2076                 .xatten1Margin = {0x19, 0x19, 0x19},
2077                 .tempSlope = 70,
2078                 .voltSlope = 15,
2079                 /* spurChans spur channels in usual fbin coding format */
2080                 .spurChans = {0, 0, 0, 0, 0},
2081                 /* noiseFloorThreshch check if the register is per chain */
2082                 .noiseFloorThreshCh = {-1, 0, 0},
2083                 .ob = {3, 3, 3}, /* 3 chain */
2084                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2085                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2086                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2087                 .xpaBiasLvl = 0,
2088                 .txFrameToDataStart = 0x0e,
2089                 .txFrameToPaOn = 0x0e,
2090                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2091                 .antennaGain = 0,
2092                 .switchSettling = 0x2d,
2093                 .adcDesiredSize = -30,
2094                 .txEndToXpaOff = 0,
2095                 .txEndToRxOn = 0x2,
2096                 .txFrameToXpaOn = 0xe,
2097                 .thresh62 = 28,
2098                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2099                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2100                 .futureModal = {
2101                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2102                 },
2103         },
2104         .base_ext2 = {
2105                 .tempSlopeLow = 72,
2106                 .tempSlopeHigh = 105,
2107                 .xatten1DBLow = {0x10, 0x14, 0x10},
2108                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2109                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2110                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2111         },
2112         .calFreqPier5G = {
2113                 FREQ2FBIN(5180, 0),
2114                 FREQ2FBIN(5220, 0),
2115                 FREQ2FBIN(5320, 0),
2116                 FREQ2FBIN(5400, 0),
2117                 FREQ2FBIN(5500, 0),
2118                 FREQ2FBIN(5600, 0),
2119                 FREQ2FBIN(5700, 0),
2120                 FREQ2FBIN(5785, 0)
2121         },
2122         .calPierData5G = {
2123                 {
2124                         {0, 0, 0, 0, 0, 0},
2125                         {0, 0, 0, 0, 0, 0},
2126                         {0, 0, 0, 0, 0, 0},
2127                         {0, 0, 0, 0, 0, 0},
2128                         {0, 0, 0, 0, 0, 0},
2129                         {0, 0, 0, 0, 0, 0},
2130                         {0, 0, 0, 0, 0, 0},
2131                         {0, 0, 0, 0, 0, 0},
2132                 },
2133                 {
2134                         {0, 0, 0, 0, 0, 0},
2135                         {0, 0, 0, 0, 0, 0},
2136                         {0, 0, 0, 0, 0, 0},
2137                         {0, 0, 0, 0, 0, 0},
2138                         {0, 0, 0, 0, 0, 0},
2139                         {0, 0, 0, 0, 0, 0},
2140                         {0, 0, 0, 0, 0, 0},
2141                         {0, 0, 0, 0, 0, 0},
2142                 },
2143                 {
2144                         {0, 0, 0, 0, 0, 0},
2145                         {0, 0, 0, 0, 0, 0},
2146                         {0, 0, 0, 0, 0, 0},
2147                         {0, 0, 0, 0, 0, 0},
2148                         {0, 0, 0, 0, 0, 0},
2149                         {0, 0, 0, 0, 0, 0},
2150                         {0, 0, 0, 0, 0, 0},
2151                         {0, 0, 0, 0, 0, 0},
2152                 },
2153
2154         },
2155         .calTarget_freqbin_5G = {
2156                 FREQ2FBIN(5180, 0),
2157                 FREQ2FBIN(5220, 0),
2158                 FREQ2FBIN(5320, 0),
2159                 FREQ2FBIN(5400, 0),
2160                 FREQ2FBIN(5500, 0),
2161                 FREQ2FBIN(5600, 0),
2162                 FREQ2FBIN(5725, 0),
2163                 FREQ2FBIN(5825, 0)
2164         },
2165         .calTarget_freqbin_5GHT20 = {
2166                 FREQ2FBIN(5180, 0),
2167                 FREQ2FBIN(5220, 0),
2168                 FREQ2FBIN(5320, 0),
2169                 FREQ2FBIN(5400, 0),
2170                 FREQ2FBIN(5500, 0),
2171                 FREQ2FBIN(5600, 0),
2172                 FREQ2FBIN(5725, 0),
2173                 FREQ2FBIN(5825, 0)
2174         },
2175         .calTarget_freqbin_5GHT40 = {
2176                 FREQ2FBIN(5180, 0),
2177                 FREQ2FBIN(5220, 0),
2178                 FREQ2FBIN(5320, 0),
2179                 FREQ2FBIN(5400, 0),
2180                 FREQ2FBIN(5500, 0),
2181                 FREQ2FBIN(5600, 0),
2182                 FREQ2FBIN(5725, 0),
2183                 FREQ2FBIN(5825, 0)
2184         },
2185         .calTargetPower5G = {
2186                 /* 6-24,36,48,54 */
2187                 { {32, 32, 28, 26} },
2188                 { {32, 32, 28, 26} },
2189                 { {32, 32, 28, 26} },
2190                 { {32, 32, 26, 24} },
2191                 { {32, 32, 26, 24} },
2192                 { {32, 32, 24, 22} },
2193                 { {30, 30, 24, 22} },
2194                 { {30, 30, 24, 22} },
2195         },
2196         .calTargetPower5GHT20 = {
2197                 /*
2198                  * 0_8_16,1-3_9-11_17-19,
2199                  * 4,5,6,7,12,13,14,15,20,21,22,23
2200                  */
2201                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2202                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2203                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2204                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2205                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2206                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2207                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2208                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2209         },
2210         .calTargetPower5GHT40 =  {
2211                 /*
2212                  * 0_8_16,1-3_9-11_17-19,
2213                  * 4,5,6,7,12,13,14,15,20,21,22,23
2214                  */
2215                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2216                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2217                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2218                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2219                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2220                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2221                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2222                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2223         },
2224         .ctlIndex_5G =  {
2225                 0x10, 0x16, 0x18, 0x40, 0x46,
2226                 0x48, 0x30, 0x36, 0x38
2227         },
2228         .ctl_freqbin_5G =  {
2229                 {
2230                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2231                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2232                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2233                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2234                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2235                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2236                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2237                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2238                 },
2239                 {
2240                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2241                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2242                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2243                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2244                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2245                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2246                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2247                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2248                 },
2249
2250                 {
2251                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2252                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2253                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2254                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2255                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2256                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2257                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2258                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2259                 },
2260
2261                 {
2262                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2263                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2264                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2265                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2266                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2267                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2268                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2269                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2270                 },
2271
2272                 {
2273                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2274                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2275                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2276                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2277                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2278                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2279                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2280                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2281                 },
2282
2283                 {
2284                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2285                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2286                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2287                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2288                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2289                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2290                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2291                         /* Data[5].ctledges[7].bchannel */ 0xFF
2292                 },
2293
2294                 {
2295                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2296                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2297                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2298                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2299                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2300                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2301                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2302                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2303                 },
2304
2305                 {
2306                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2307                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2308                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2309                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2310                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2311                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2312                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2313                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2314                 },
2315
2316                 {
2317                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2318                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2319                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2320                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2321                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2322                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2323                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2324                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2325                 }
2326         },
2327         .ctlPowerData_5G = {
2328                 {
2329                         {
2330                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2331                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2332                         }
2333                 },
2334                 {
2335                         {
2336                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2337                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2338                         }
2339                 },
2340                 {
2341                         {
2342                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2343                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2344                         }
2345                 },
2346                 {
2347                         {
2348                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2349                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2350                         }
2351                 },
2352                 {
2353                         {
2354                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2355                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2356                         }
2357                 },
2358                 {
2359                         {
2360                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2361                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2362                         }
2363                 },
2364                 {
2365                         {
2366                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2367                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2368                         }
2369                 },
2370                 {
2371                         {
2372                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2373                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2374                         }
2375                 },
2376                 {
2377                         {
2378                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2379                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2380                         }
2381                 },
2382         }
2383 };
2384
2385 static const struct ar9300_eeprom ar9300_h116 = {
2386         .eepromVersion = 2,
2387         .templateVersion = 4,
2388         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2389         .custData = {"h116-041-f0000"},
2390         .baseEepHeader = {
2391                 .regDmn = { LE16(0), LE16(0x1f) },
2392                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2393                 .opCapFlags = {
2394                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2395                         .eepMisc = 0,
2396                 },
2397                 .rfSilent = 0,
2398                 .blueToothOptions = 0,
2399                 .deviceCap = 0,
2400                 .deviceType = 5, /* takes lower byte in eeprom location */
2401                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2402                 .params_for_tuning_caps = {0, 0},
2403                 .featureEnable = 0x0d,
2404                  /*
2405                   * bit0 - enable tx temp comp - disabled
2406                   * bit1 - enable tx volt comp - disabled
2407                   * bit2 - enable fastClock - enabled
2408                   * bit3 - enable doubling - enabled
2409                   * bit4 - enable internal regulator - disabled
2410                   * bit5 - enable pa predistortion - disabled
2411                   */
2412                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2413                 .eepromWriteEnableGpio = 6,
2414                 .wlanDisableGpio = 0,
2415                 .wlanLedGpio = 8,
2416                 .rxBandSelectGpio = 0xff,
2417                 .txrxgain = 0x10,
2418                 .swreg = 0,
2419          },
2420         .modalHeader2G = {
2421         /* ar9300_modal_eep_header  2g */
2422                 /* 4 idle,t1,t2,b(4 bits per setting) */
2423                 .antCtrlCommon = LE32(0x110),
2424                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2425                 .antCtrlCommon2 = LE32(0x44444),
2426
2427                 /*
2428                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2429                  * rx1, rx12, b (2 bits each)
2430                  */
2431                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2432
2433                 /*
2434                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2435                  * for ar9280 (0xa20c/b20c 5:0)
2436                  */
2437                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2438
2439                 /*
2440                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2441                  * for ar9280 (0xa20c/b20c 16:12
2442                  */
2443                 .xatten1Margin = {0x12, 0x12, 0x12},
2444                 .tempSlope = 25,
2445                 .voltSlope = 0,
2446
2447                 /*
2448                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2449                  * channels in usual fbin coding format
2450                  */
2451                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2452
2453                 /*
2454                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2455                  * if the register is per chain
2456                  */
2457                 .noiseFloorThreshCh = {-1, 0, 0},
2458                 .ob = {1, 1, 1},/* 3 chain */
2459                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
2460                 .db_stage3 = {0, 0, 0},
2461                 .db_stage4 = {0, 0, 0},
2462                 .xpaBiasLvl = 0,
2463                 .txFrameToDataStart = 0x0e,
2464                 .txFrameToPaOn = 0x0e,
2465                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2466                 .antennaGain = 0,
2467                 .switchSettling = 0x2c,
2468                 .adcDesiredSize = -30,
2469                 .txEndToXpaOff = 0,
2470                 .txEndToRxOn = 0x2,
2471                 .txFrameToXpaOn = 0xe,
2472                 .thresh62 = 28,
2473                 .papdRateMaskHt20 = LE32(0x0c80C080),
2474                 .papdRateMaskHt40 = LE32(0x0080C080),
2475                 .futureModal = {
2476                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2477                 },
2478          },
2479          .base_ext1 = {
2480                 .ant_div_control = 0,
2481                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2482          },
2483         .calFreqPier2G = {
2484                 FREQ2FBIN(2412, 1),
2485                 FREQ2FBIN(2437, 1),
2486                 FREQ2FBIN(2472, 1),
2487          },
2488         /* ar9300_cal_data_per_freq_op_loop 2g */
2489         .calPierData2G = {
2490                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2491                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2492                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2493          },
2494         .calTarget_freqbin_Cck = {
2495                 FREQ2FBIN(2412, 1),
2496                 FREQ2FBIN(2472, 1),
2497          },
2498         .calTarget_freqbin_2G = {
2499                 FREQ2FBIN(2412, 1),
2500                 FREQ2FBIN(2437, 1),
2501                 FREQ2FBIN(2472, 1)
2502          },
2503         .calTarget_freqbin_2GHT20 = {
2504                 FREQ2FBIN(2412, 1),
2505                 FREQ2FBIN(2437, 1),
2506                 FREQ2FBIN(2472, 1)
2507          },
2508         .calTarget_freqbin_2GHT40 = {
2509                 FREQ2FBIN(2412, 1),
2510                 FREQ2FBIN(2437, 1),
2511                 FREQ2FBIN(2472, 1)
2512          },
2513         .calTargetPowerCck = {
2514                  /* 1L-5L,5S,11L,11S */
2515                  { {34, 34, 34, 34} },
2516                  { {34, 34, 34, 34} },
2517         },
2518         .calTargetPower2G = {
2519                  /* 6-24,36,48,54 */
2520                  { {34, 34, 32, 32} },
2521                  { {34, 34, 32, 32} },
2522                  { {34, 34, 32, 32} },
2523         },
2524         .calTargetPower2GHT20 = {
2525                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2526                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2527                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2528         },
2529         .calTargetPower2GHT40 = {
2530                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2531                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2532                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2533         },
2534         .ctlIndex_2G =  {
2535                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2536                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2537         },
2538         .ctl_freqbin_2G = {
2539                 {
2540                         FREQ2FBIN(2412, 1),
2541                         FREQ2FBIN(2417, 1),
2542                         FREQ2FBIN(2457, 1),
2543                         FREQ2FBIN(2462, 1)
2544                 },
2545                 {
2546                         FREQ2FBIN(2412, 1),
2547                         FREQ2FBIN(2417, 1),
2548                         FREQ2FBIN(2462, 1),
2549                         0xFF,
2550                 },
2551
2552                 {
2553                         FREQ2FBIN(2412, 1),
2554                         FREQ2FBIN(2417, 1),
2555                         FREQ2FBIN(2462, 1),
2556                         0xFF,
2557                 },
2558                 {
2559                         FREQ2FBIN(2422, 1),
2560                         FREQ2FBIN(2427, 1),
2561                         FREQ2FBIN(2447, 1),
2562                         FREQ2FBIN(2452, 1)
2563                 },
2564
2565                 {
2566                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2567                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2568                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2569                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2570                 },
2571
2572                 {
2573                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2574                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2575                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2576                         0,
2577                 },
2578
2579                 {
2580                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2581                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2582                         FREQ2FBIN(2472, 1),
2583                         0,
2584                 },
2585
2586                 {
2587                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2588                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2589                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2590                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2591                 },
2592
2593                 {
2594                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2595                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2596                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2597                 },
2598
2599                 {
2600                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2601                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2602                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2603                         0
2604                 },
2605
2606                 {
2607                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2608                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2609                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2610                         0
2611                 },
2612
2613                 {
2614                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2615                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2616                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2617                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2618                 }
2619          },
2620         .ctlPowerData_2G = {
2621                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2622                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2623                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2624
2625                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2626                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2627                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2628
2629                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2630                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2631                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2632
2633                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2634                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2635                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2636          },
2637         .modalHeader5G = {
2638                 /* 4 idle,t1,t2,b (4 bits per setting) */
2639                 .antCtrlCommon = LE32(0x220),
2640                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2641                 .antCtrlCommon2 = LE32(0x44444),
2642                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2643                 .antCtrlChain = {
2644                         LE16(0x150), LE16(0x150), LE16(0x150),
2645                 },
2646                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2647                 .xatten1DB = {0x19, 0x19, 0x19},
2648
2649                 /*
2650                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2651                  * for merlin (0xa20c/b20c 16:12
2652                  */
2653                 .xatten1Margin = {0x14, 0x14, 0x14},
2654                 .tempSlope = 70,
2655                 .voltSlope = 0,
2656                 /* spurChans spur channels in usual fbin coding format */
2657                 .spurChans = {0, 0, 0, 0, 0},
2658                 /* noiseFloorThreshCh Check if the register is per chain */
2659                 .noiseFloorThreshCh = {-1, 0, 0},
2660                 .ob = {3, 3, 3}, /* 3 chain */
2661                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2662                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2663                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2664                 .xpaBiasLvl = 0,
2665                 .txFrameToDataStart = 0x0e,
2666                 .txFrameToPaOn = 0x0e,
2667                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2668                 .antennaGain = 0,
2669                 .switchSettling = 0x2d,
2670                 .adcDesiredSize = -30,
2671                 .txEndToXpaOff = 0,
2672                 .txEndToRxOn = 0x2,
2673                 .txFrameToXpaOn = 0xe,
2674                 .thresh62 = 28,
2675                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2676                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2677                 .futureModal = {
2678                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2679                 },
2680          },
2681         .base_ext2 = {
2682                 .tempSlopeLow = 35,
2683                 .tempSlopeHigh = 50,
2684                 .xatten1DBLow = {0, 0, 0},
2685                 .xatten1MarginLow = {0, 0, 0},
2686                 .xatten1DBHigh = {0, 0, 0},
2687                 .xatten1MarginHigh = {0, 0, 0}
2688          },
2689         .calFreqPier5G = {
2690                 FREQ2FBIN(5180, 0),
2691                 FREQ2FBIN(5220, 0),
2692                 FREQ2FBIN(5320, 0),
2693                 FREQ2FBIN(5400, 0),
2694                 FREQ2FBIN(5500, 0),
2695                 FREQ2FBIN(5600, 0),
2696                 FREQ2FBIN(5700, 0),
2697                 FREQ2FBIN(5785, 0)
2698         },
2699         .calPierData5G = {
2700                         {
2701                                 {0, 0, 0, 0, 0, 0},
2702                                 {0, 0, 0, 0, 0, 0},
2703                                 {0, 0, 0, 0, 0, 0},
2704                                 {0, 0, 0, 0, 0, 0},
2705                                 {0, 0, 0, 0, 0, 0},
2706                                 {0, 0, 0, 0, 0, 0},
2707                                 {0, 0, 0, 0, 0, 0},
2708                                 {0, 0, 0, 0, 0, 0},
2709                         },
2710                         {
2711                                 {0, 0, 0, 0, 0, 0},
2712                                 {0, 0, 0, 0, 0, 0},
2713                                 {0, 0, 0, 0, 0, 0},
2714                                 {0, 0, 0, 0, 0, 0},
2715                                 {0, 0, 0, 0, 0, 0},
2716                                 {0, 0, 0, 0, 0, 0},
2717                                 {0, 0, 0, 0, 0, 0},
2718                                 {0, 0, 0, 0, 0, 0},
2719                         },
2720                         {
2721                                 {0, 0, 0, 0, 0, 0},
2722                                 {0, 0, 0, 0, 0, 0},
2723                                 {0, 0, 0, 0, 0, 0},
2724                                 {0, 0, 0, 0, 0, 0},
2725                                 {0, 0, 0, 0, 0, 0},
2726                                 {0, 0, 0, 0, 0, 0},
2727                                 {0, 0, 0, 0, 0, 0},
2728                                 {0, 0, 0, 0, 0, 0},
2729                         },
2730
2731         },
2732         .calTarget_freqbin_5G = {
2733                 FREQ2FBIN(5180, 0),
2734                 FREQ2FBIN(5240, 0),
2735                 FREQ2FBIN(5320, 0),
2736                 FREQ2FBIN(5400, 0),
2737                 FREQ2FBIN(5500, 0),
2738                 FREQ2FBIN(5600, 0),
2739                 FREQ2FBIN(5700, 0),
2740                 FREQ2FBIN(5825, 0)
2741         },
2742         .calTarget_freqbin_5GHT20 = {
2743                 FREQ2FBIN(5180, 0),
2744                 FREQ2FBIN(5240, 0),
2745                 FREQ2FBIN(5320, 0),
2746                 FREQ2FBIN(5400, 0),
2747                 FREQ2FBIN(5500, 0),
2748                 FREQ2FBIN(5700, 0),
2749                 FREQ2FBIN(5745, 0),
2750                 FREQ2FBIN(5825, 0)
2751         },
2752         .calTarget_freqbin_5GHT40 = {
2753                 FREQ2FBIN(5180, 0),
2754                 FREQ2FBIN(5240, 0),
2755                 FREQ2FBIN(5320, 0),
2756                 FREQ2FBIN(5400, 0),
2757                 FREQ2FBIN(5500, 0),
2758                 FREQ2FBIN(5700, 0),
2759                 FREQ2FBIN(5745, 0),
2760                 FREQ2FBIN(5825, 0)
2761          },
2762         .calTargetPower5G = {
2763                 /* 6-24,36,48,54 */
2764                 { {30, 30, 28, 24} },
2765                 { {30, 30, 28, 24} },
2766                 { {30, 30, 28, 24} },
2767                 { {30, 30, 28, 24} },
2768                 { {30, 30, 28, 24} },
2769                 { {30, 30, 28, 24} },
2770                 { {30, 30, 28, 24} },
2771                 { {30, 30, 28, 24} },
2772          },
2773         .calTargetPower5GHT20 = {
2774                 /*
2775                  * 0_8_16,1-3_9-11_17-19,
2776                  * 4,5,6,7,12,13,14,15,20,21,22,23
2777                  */
2778                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2779                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2780                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2781                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2782                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2783                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2784                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2785                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2786          },
2787         .calTargetPower5GHT40 =  {
2788                 /*
2789                  * 0_8_16,1-3_9-11_17-19,
2790                  * 4,5,6,7,12,13,14,15,20,21,22,23
2791                  */
2792                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2793                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2794                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2795                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2796                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2797                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2798                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2799                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2800          },
2801         .ctlIndex_5G =  {
2802                 0x10, 0x16, 0x18, 0x40, 0x46,
2803                 0x48, 0x30, 0x36, 0x38
2804         },
2805         .ctl_freqbin_5G =  {
2806                 {
2807                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2808                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2809                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2810                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2811                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2812                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2813                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2814                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2815                 },
2816                 {
2817                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2818                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2819                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2820                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2821                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2822                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2823                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2824                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2825                 },
2826
2827                 {
2828                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2829                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2830                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2831                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2832                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2833                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2834                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2835                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2836                 },
2837
2838                 {
2839                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2840                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2841                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2842                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2843                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2844                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2845                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2846                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2847                 },
2848
2849                 {
2850                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2851                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2852                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2853                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2854                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2855                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2856                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2857                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2858                 },
2859
2860                 {
2861                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2862                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2863                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2864                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2865                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2866                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2867                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2868                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2869                 },
2870
2871                 {
2872                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2873                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2874                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2875                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2876                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2877                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2878                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2879                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2880                 },
2881
2882                 {
2883                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2884                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2885                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2886                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2887                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2888                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2889                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2890                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2891                 },
2892
2893                 {
2894                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2895                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2896                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2897                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2898                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2899                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2900                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2901                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2902                 }
2903          },
2904         .ctlPowerData_5G = {
2905                 {
2906                         {
2907                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2908                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2909                         }
2910                 },
2911                 {
2912                         {
2913                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2914                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2915                         }
2916                 },
2917                 {
2918                         {
2919                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2920                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2921                         }
2922                 },
2923                 {
2924                         {
2925                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2926                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2927                         }
2928                 },
2929                 {
2930                         {
2931                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2932                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2933                         }
2934                 },
2935                 {
2936                         {
2937                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2938                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2939                         }
2940                 },
2941                 {
2942                         {
2943                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2944                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2945                         }
2946                 },
2947                 {
2948                         {
2949                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2950                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2951                         }
2952                 },
2953                 {
2954                         {
2955                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2956                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2957                         }
2958                 },
2959          }
2960 };
2961
2962
2963 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2964         &ar9300_default,
2965         &ar9300_x112,
2966         &ar9300_h116,
2967         &ar9300_h112,
2968         &ar9300_x113,
2969 };
2970
2971 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2972 {
2973 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2974         unsigned int it;
2975
2976         for (it = 0; it < N_LOOP; it++)
2977                 if (ar9300_eep_templates[it]->templateVersion == id)
2978                         return ar9300_eep_templates[it];
2979         return NULL;
2980 #undef N_LOOP
2981 }
2982
2983
2984 static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
2985 {
2986         if (fbin == AR5416_BCHAN_UNUSED)
2987                 return fbin;
2988
2989         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2990 }
2991
2992 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
2993 {
2994         return 0;
2995 }
2996
2997 static int interpolate(int x, int xa, int xb, int ya, int yb)
2998 {
2999         int bf, factor, plus;
3000
3001         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
3002         factor = bf / 2;
3003         plus = bf % 2;
3004         return ya + factor + plus;
3005 }
3006
3007 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3008                                       enum eeprom_param param)
3009 {
3010         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3011         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3012
3013         switch (param) {
3014         case EEP_MAC_LSW:
3015                 return eep->macAddr[0] << 8 | eep->macAddr[1];
3016         case EEP_MAC_MID:
3017                 return eep->macAddr[2] << 8 | eep->macAddr[3];
3018         case EEP_MAC_MSW:
3019                 return eep->macAddr[4] << 8 | eep->macAddr[5];
3020         case EEP_REG_0:
3021                 return (uint16_t)(pBase->regDmn[0]);
3022         case EEP_REG_1:
3023                 return (uint16_t)(pBase->regDmn[1]);
3024         case EEP_OP_CAP:
3025                 return pBase->deviceCap;
3026         case EEP_OP_MODE:
3027                 return pBase->opCapFlags.opFlags;
3028         case EEP_RF_SILENT:
3029                 return pBase->rfSilent;
3030         case EEP_TX_MASK:
3031                 return (pBase->txrxMask >> 4) & 0xf;
3032         case EEP_RX_MASK:
3033                 return pBase->txrxMask & 0xf;
3034         case EEP_DRIVE_STRENGTH:
3035 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
3036                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3037         case EEP_INTERNAL_REGULATOR:
3038                 /* Bit 4 is internal regulator flag */
3039                 return (pBase->featureEnable & 0x10) >> 4;
3040         case EEP_SWREG:
3041                 return (uint32_t)(pBase->swreg);
3042         case EEP_PAPRD:
3043                 return !!(pBase->featureEnable & BIT(5));
3044         case EEP_CHAIN_MASK_REDUCE:
3045                 return (pBase->miscConfiguration >> 0x3) & 0x1;
3046         case EEP_ANT_DIV_CTL1:
3047                 return (uint32_t)(eep->base_ext1.ant_div_control);
3048         default:
3049                 return 0;
3050         }
3051 }
3052
3053 static int ar9300_eeprom_read_byte(struct ath_common *common, int address,
3054                                     u8 *buffer)
3055 {
3056         u16 val;
3057
3058         if (!ath9k_hw_nvram_read(common, address / 2, &val))
3059                 return 0;
3060
3061         *buffer = (val >> (8 * (address % 2))) & 0xff;
3062         return 1;
3063 }
3064
3065 static int ar9300_eeprom_read_word(struct ath_common *common, int address,
3066                                     u8 *buffer)
3067 {
3068         u16 val;
3069
3070         if (!ath9k_hw_nvram_read(common, address / 2, &val))
3071                 return 0;
3072
3073         buffer[0] = val >> 8;
3074         buffer[1] = val & 0xff;
3075
3076         return 1;
3077 }
3078
3079 static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3080                                int count)
3081 {
3082         struct ath_common *common = ath9k_hw_common(ah);
3083         int i;
3084
3085         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3086                 DBG("ath9k: "
3087                         "eeprom address not in range\n");
3088                 return 0;
3089         }
3090
3091         /*
3092          * Since we're reading the bytes in reverse order from a little-endian
3093          * word stream, an even address means we only use the lower half of
3094          * the 16-bit word at that address
3095          */
3096         if (address % 2 == 0) {
3097                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3098                         goto error;
3099
3100                 count--;
3101         }
3102
3103         for (i = 0; i < count / 2; i++) {
3104                 if (!ar9300_eeprom_read_word(common, address, buffer))
3105                         goto error;
3106
3107                 address -= 2;
3108                 buffer += 2;
3109         }
3110
3111         if (count % 2)
3112                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3113                         goto error;
3114
3115         return 1;
3116
3117 error:
3118         DBG("ath9k: "
3119                 "unable to read eeprom region at offset %d\n", address);
3120         return 0;
3121 }
3122
3123 static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3124 {
3125         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3126
3127         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3128                            AR9300_OTP_STATUS_VALID, 1000))
3129                 return 0;
3130
3131         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3132         return 1;
3133 }
3134
3135 static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3136                             int count)
3137 {
3138         u32 data;
3139         int i;
3140
3141         for (i = 0; i < count; i++) {
3142                 int offset = 8 * ((address - i) % 4);
3143                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3144                         return 0;
3145
3146                 buffer[i] = (data >> offset) & 0xff;
3147         }
3148
3149         return 1;
3150 }
3151
3152
3153 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3154                                    int *length, int *major, int *minor)
3155 {
3156         unsigned long value[4];
3157
3158         value[0] = best[0];
3159         value[1] = best[1];
3160         value[2] = best[2];
3161         value[3] = best[3];
3162         *code = ((value[0] >> 5) & 0x0007);
3163         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3164         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3165         *major = (value[2] & 0x000f);
3166         *minor = (value[3] & 0x00ff);
3167 }
3168
3169 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3170 {
3171         int it, checksum = 0;
3172
3173         for (it = 0; it < dsize; it++) {
3174                 checksum += data[it];
3175                 checksum &= 0xffff;
3176         }
3177
3178         return checksum;
3179 }
3180
3181 static int ar9300_uncompress_block(struct ath_hw *ah __unused,
3182                                     u8 *mptr,
3183                                     int mdataSize,
3184                                     u8 *block,
3185                                     int size)
3186 {
3187         int it;
3188         int spot;
3189         int offset;
3190         int length;
3191
3192         spot = 0;
3193
3194         for (it = 0; it < size; it += (length+2)) {
3195                 offset = block[it];
3196                 offset &= 0xff;
3197                 spot += offset;
3198                 length = block[it+1];
3199                 length &= 0xff;
3200
3201                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3202                         DBG2("ath9k: "
3203                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3204                                 it, spot, offset, length);
3205                         memcpy(&mptr[spot], &block[it+2], length);
3206                         spot += length;
3207                 } else if (length > 0) {
3208                         DBG("ath9k: "
3209                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3210                                 it, spot, offset, length);
3211                         return 0;
3212                 }
3213         }
3214         return 1;
3215 }
3216
3217 static int ar9300_compress_decision(struct ath_hw *ah,
3218                                     int it,
3219                                     int code,
3220                                     int reference,
3221                                     u8 *mptr,
3222                                     u8 *word, int length, int mdata_size)
3223 {
3224         const struct ar9300_eeprom *eep = NULL;
3225
3226         switch (code) {
3227         case _CompressNone:
3228                 if (length != mdata_size) {
3229                         DBG("ath9k: "
3230                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3231                                 mdata_size, length);
3232                         return -1;
3233                 }
3234                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3235                 DBG2("ath9k: "
3236                         "restored eeprom %d: uncompressed, length %d\n",
3237                         it, length);
3238                 break;
3239         case _CompressBlock:
3240                 if (reference == 0) {
3241                 } else {
3242                         eep = ar9003_eeprom_struct_find_by_id(reference);
3243                         if (eep == NULL) {
3244                                 DBG("ath9k: "
3245                                         "can't find reference eeprom struct %d\n",
3246                                         reference);
3247                                 return -1;
3248                         }
3249                         memcpy(mptr, eep, mdata_size);
3250                 }
3251                 DBG2("ath9k: "
3252                         "restore eeprom %d: block, reference %d, length %d\n",
3253                         it, reference, length);
3254                 ar9300_uncompress_block(ah, mptr, mdata_size,
3255                                         (u8 *) (word + COMP_HDR_LEN), length);
3256                 break;
3257         default:
3258                 DBG("ath9k: "
3259                         "unknown compression code %d\n", code);
3260                 return -1;
3261         }
3262         return 0;
3263 }
3264
3265 typedef int (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3266                                int count);
3267
3268 static int ar9300_check_header(void *data)
3269 {
3270         u32 *word = data;
3271         return !(*word == 0 || *word == (unsigned int)~0);
3272 }
3273
3274 static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3275                                        int base_addr)
3276 {
3277         u8 header[4];
3278
3279         if (!read(ah, base_addr, header, 4))
3280                 return 0;
3281
3282         return ar9300_check_header(header);
3283 }
3284
3285 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3286                                        int mdata_size)
3287 {
3288         struct ath_common *common = ath9k_hw_common(ah);
3289         u16 *data = (u16 *) mptr;
3290         int i;
3291
3292         for (i = 0; i < mdata_size / 2; i++, data++)
3293                 ath9k_hw_nvram_read(common, i, data);
3294
3295         return 0;
3296 }
3297 /*
3298  * Read the configuration data from the eeprom.
3299  * The data can be put in any specified memory buffer.
3300  *
3301  * Returns -1 on error.
3302  * Returns address of next memory location on success.
3303  */
3304 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3305                                           u8 *mptr, int mdata_size)
3306 {
3307 #define MDEFAULT 15
3308 #define MSTATE 100
3309         int cptr;
3310         u8 *word;
3311         int code;
3312         int reference, length, major, minor;
3313         int osize;
3314         int it;
3315         u16 checksum, mchecksum;
3316         eeprom_read_op read;
3317
3318         if (ath9k_hw_use_flash(ah))
3319                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3320
3321         word = zalloc(2048);
3322         if (!word)
3323                 return -1;
3324
3325         memcpy(mptr, &ar9300_default, mdata_size);
3326
3327         read = ar9300_read_eeprom;
3328         if (AR_SREV_9485(ah))
3329                 cptr = AR9300_BASE_ADDR_4K;
3330         else
3331                 cptr = AR9300_BASE_ADDR;
3332         DBG2("ath9k: "
3333                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3334         if (ar9300_check_eeprom_header(ah, read, cptr))
3335                 goto found;
3336
3337         cptr = AR9300_BASE_ADDR_512;
3338         DBG2("ath9k: "
3339                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3340         if (ar9300_check_eeprom_header(ah, read, cptr))
3341                 goto found;
3342
3343         read = ar9300_read_otp;
3344         cptr = AR9300_BASE_ADDR;
3345         DBG2("ath9k: "
3346                 "Trying OTP access at Address 0x%04x\n", cptr);
3347         if (ar9300_check_eeprom_header(ah, read, cptr))
3348                 goto found;
3349
3350         cptr = AR9300_BASE_ADDR_512;
3351         DBG2("ath9k: "
3352                 "Trying OTP access at Address 0x%04x\n", cptr);
3353         if (ar9300_check_eeprom_header(ah, read, cptr))
3354                 goto found;
3355
3356         goto fail;
3357
3358 found:
3359         DBG2("ath9k: Found valid EEPROM data\n");
3360
3361         for (it = 0; it < MSTATE; it++) {
3362                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3363                         goto fail;
3364
3365                 if (!ar9300_check_header(word))
3366                         break;
3367
3368                 ar9300_comp_hdr_unpack(word, &code, &reference,
3369                                        &length, &major, &minor);
3370                 DBG2("ath9k: "
3371                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3372                         cptr, code, reference, length, major, minor);
3373                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3374                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3375                         DBG2("ath9k: "
3376                                 "Skipping bad header\n");
3377                         cptr -= COMP_HDR_LEN;
3378                         continue;
3379                 }
3380
3381                 osize = length;
3382                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3383                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3384                 mchecksum = word[COMP_HDR_LEN + osize] |
3385                     (word[COMP_HDR_LEN + osize + 1] << 8);
3386                 DBG2("ath9k: "
3387                         "checksum %x %x\n", checksum, mchecksum);
3388                 if (checksum == mchecksum) {
3389                         ar9300_compress_decision(ah, it, code, reference, mptr,
3390                                                  word, length, mdata_size);
3391                 } else {
3392                         DBG2("ath9k: "
3393                                 "skipping block with bad checksum\n");
3394                 }
3395                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3396         }
3397
3398         free(word);
3399         return cptr;
3400
3401 fail:
3402         free(word);
3403         return -1;
3404 }
3405
3406 /*
3407  * Restore the configuration structure by reading the eeprom.
3408  * This function destroys any existing in-memory structure
3409  * content.
3410  */
3411 static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3412 {
3413         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3414
3415         if (ar9300_eeprom_restore_internal(ah, mptr,
3416                         sizeof(struct ar9300_eeprom)) < 0)
3417                 return 0;
3418
3419         return 1;
3420 }
3421
3422 /* XXX: review hardware docs */
3423 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3424 {
3425         return ah->eeprom.ar9300_eep.eepromVersion;
3426 }
3427
3428 /* XXX: could be read from the eepromVersion, not sure yet */
3429 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
3430 {
3431         return 0;
3432 }
3433
3434 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
3435 {
3436         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3437
3438         if (is2ghz)
3439                 return eep->modalHeader2G.xpaBiasLvl;
3440         else
3441                 return eep->modalHeader5G.xpaBiasLvl;
3442 }
3443
3444 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
3445 {
3446         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3447
3448         if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3449                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3450         else {
3451                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3452                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3453                                 AR_CH0_THERM_XPABIASLVL_MSB,
3454                                 bias >> 2);
3455                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3456                                 AR_CH0_THERM_XPASHORT2GND, 1);
3457         }
3458 }
3459
3460 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
3461 {
3462         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3463         uint32_t val;
3464
3465         if (is2ghz)
3466                 val = eep->modalHeader2G.antCtrlCommon;
3467         else
3468                 val = eep->modalHeader5G.antCtrlCommon;
3469         return (uint32_t)(val);
3470 }
3471
3472 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
3473 {
3474         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3475         uint32_t val;
3476
3477         if (is2ghz)
3478                 val = eep->modalHeader2G.antCtrlCommon2;
3479         else
3480                 val = eep->modalHeader5G.antCtrlCommon2;
3481         return (uint32_t)(val);
3482 }
3483
3484 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3485                                         int chain,
3486                                         int is2ghz)
3487 {
3488         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3489         uint16_t val = 0;
3490
3491         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3492                 if (is2ghz)
3493                         val = eep->modalHeader2G.antCtrlChain[chain];
3494                 else
3495                         val = eep->modalHeader5G.antCtrlChain[chain];
3496         }
3497
3498         return (uint16_t)(val);
3499 }
3500
3501 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
3502 {
3503         int chain;
3504         u32 regval;
3505         u32 ant_div_ctl1;
3506         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3507                         AR_PHY_SWITCH_CHAIN_0,
3508                         AR_PHY_SWITCH_CHAIN_1,
3509                         AR_PHY_SWITCH_CHAIN_2,
3510         };
3511
3512         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3513
3514         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3515
3516         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3517         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3518
3519         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3520                 if ((ah->rxchainmask & BIT(chain)) ||
3521                     (ah->txchainmask & BIT(chain))) {
3522                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3523                                                              is2ghz);
3524                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3525                                       AR_SWITCH_TABLE_ALL, value);
3526                 }
3527         }
3528
3529         if (AR_SREV_9485(ah)) {
3530                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3531                 /*
3532                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3533                  * are the fields present
3534                  */
3535                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3536                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3537                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3538                 /* enable_lnadiv */
3539                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3540                 regval |= ((value >> 6) & 0x1) <<
3541                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3542                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3543
3544                 /*enable fast_div */
3545                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3546                 regval &= (~AR_FAST_DIV_ENABLE);
3547                 regval |= ((value >> 7) & 0x1) <<
3548                                 AR_FAST_DIV_ENABLE_S;
3549                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3550                 ant_div_ctl1 =
3551                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3552                 /* check whether antenna diversity is enabled */
3553                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3554                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3555                         /*
3556                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3557                          * main_tb, alt_tb
3558                          */
3559                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3560                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3561                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3562                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3563                         /* by default use LNA1 for the main antenna */
3564                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3565                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3566                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3567                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3568                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3569                 }
3570
3571
3572         }
3573
3574 }
3575
3576 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3577 {
3578         int drive_strength;
3579         unsigned long reg;
3580
3581         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3582
3583         if (!drive_strength)
3584                 return;
3585
3586         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3587         reg &= ~0x00ffffc0;
3588         reg |= 0x5 << 21;
3589         reg |= 0x5 << 18;
3590         reg |= 0x5 << 15;
3591         reg |= 0x5 << 12;
3592         reg |= 0x5 << 9;
3593         reg |= 0x5 << 6;
3594         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3595
3596         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3597         reg &= ~0xffffffe0;
3598         reg |= 0x5 << 29;
3599         reg |= 0x5 << 26;
3600         reg |= 0x5 << 23;
3601         reg |= 0x5 << 20;
3602         reg |= 0x5 << 17;
3603         reg |= 0x5 << 14;
3604         reg |= 0x5 << 11;
3605         reg |= 0x5 << 8;
3606         reg |= 0x5 << 5;
3607         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3608
3609         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3610         reg &= ~0xff800000;
3611         reg |= 0x5 << 29;
3612         reg |= 0x5 << 26;
3613         reg |= 0x5 << 23;
3614         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3615 }
3616
3617 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3618                                      struct ath9k_channel *chan)
3619 {
3620         int f[3], t[3];
3621         u16 value;
3622         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3623
3624         if (chain >= 0 && chain < 3) {
3625                 if (IS_CHAN_2GHZ(chan))
3626                         return eep->modalHeader2G.xatten1DB[chain];
3627                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3628                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3629                         f[0] = 5180;
3630                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3631                         f[1] = 5500;
3632                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3633                         f[2] = 5785;
3634                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3635                                                             f, t, 3);
3636                         return value;
3637                 } else
3638                         return eep->modalHeader5G.xatten1DB[chain];
3639         }
3640
3641         return 0;
3642 }
3643
3644
3645 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3646                                             struct ath9k_channel *chan)
3647 {
3648         int f[3], t[3];
3649         u16 value;
3650         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3651
3652         if (chain >= 0 && chain < 3) {
3653                 if (IS_CHAN_2GHZ(chan))
3654                         return eep->modalHeader2G.xatten1Margin[chain];
3655                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3656                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3657                         f[0] = 5180;
3658                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3659                         f[1] = 5500;
3660                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3661                         f[2] = 5785;
3662                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3663                                                             f, t, 3);
3664                         return value;
3665                 } else
3666                         return eep->modalHeader5G.xatten1Margin[chain];
3667         }
3668
3669         return 0;
3670 }
3671
3672 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3673 {
3674         int i;
3675         u16 value;
3676         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3677                                           AR_PHY_EXT_ATTEN_CTL_1,
3678                                           AR_PHY_EXT_ATTEN_CTL_2,
3679                                          };
3680
3681         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3682         for (i = 0; i < 3; i++) {
3683                 if (ah->txchainmask & BIT(i)) {
3684                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3685                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3686                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3687
3688                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3689                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3690                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3691                                       value);
3692                 }
3693         }
3694 }
3695
3696 static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3697 {
3698         int timeout = 100;
3699
3700         while ((unsigned int)pmu_set != REG_READ(ah, pmu_reg)) {
3701                 if (timeout-- == 0)
3702                         return 0;
3703                 REG_WRITE(ah, pmu_reg, pmu_set);
3704                 udelay(10);
3705         }
3706
3707         return 1;
3708 }
3709
3710 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3711 {
3712         int internal_regulator =
3713                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3714
3715         if (internal_regulator) {
3716                 if (AR_SREV_9485(ah)) {
3717                         int reg_pmu_set;
3718
3719                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3720                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3721                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3722                                 return;
3723
3724                         reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3725                                       (2 << 14) | (6 << 17) | (1 << 20) |
3726                                       (3 << 24) | (1 << 28);
3727
3728                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3729                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3730                                 return;
3731
3732                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3733                                         | (4 << 26);
3734                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3735                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3736                                 return;
3737
3738                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3739                                         | (1 << 21);
3740                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3741                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3742                                 return;
3743                 } else {
3744                         /* Internal regulator is ON. Write swreg register. */
3745                         int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3746                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3747                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3748                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3749                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3750                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3751                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3752                                   REG_READ(ah,
3753                                            AR_RTC_REG_CONTROL1) |
3754                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3755                 }
3756         } else {
3757                 if (AR_SREV_9485(ah)) {
3758                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3759                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3760                                               AR_PHY_PMU2_PGM))
3761                                 udelay(10);
3762
3763                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3764                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3765                                                AR_PHY_PMU1_PWD))
3766                                 udelay(10);
3767                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3768                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3769                                               AR_PHY_PMU2_PGM))
3770                                 udelay(10);
3771                 } else
3772                         REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3773                                   (REG_READ(ah,
3774                                    AR_RTC_SLEEP_CLK) |
3775                                    AR_RTC_FORCE_SWREG_PRD));
3776         }
3777
3778 }
3779
3780 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3781 {
3782         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3783         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3784
3785         if (eep->baseEepHeader.featureEnable & 0x40) {
3786                 tuning_caps_param &= 0x7f;
3787                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3788                               tuning_caps_param);
3789                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3790                               tuning_caps_param);
3791         }
3792 }
3793
3794 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3795                                              struct ath9k_channel *chan)
3796 {
3797         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3798         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3799         ar9003_hw_drive_strength_apply(ah);
3800         ar9003_hw_atten_apply(ah, chan);
3801         if (!AR_SREV_9340(ah))
3802                 ar9003_hw_internal_regulator_apply(ah);
3803         if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3804                 ar9003_hw_apply_tuning_caps(ah);
3805 }
3806
3807 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused,
3808                                       struct ath9k_channel *chan __unused)
3809 {
3810 }
3811
3812 /*
3813  * Returns the interpolated y value corresponding to the specified x value
3814  * from the np ordered pairs of data (px,py).
3815  * The pairs do not have to be in any order.
3816  * If the specified x value is less than any of the px,
3817  * the returned y value is equal to the py for the lowest px.
3818  * If the specified x value is greater than any of the px,
3819  * the returned y value is equal to the py for the highest px.
3820  */
3821 static int ar9003_hw_power_interpolate(int32_t x,
3822                                        int32_t *px, int32_t *py, uint16_t np)
3823 {
3824         int ip = 0;
3825         int lx = 0, ly = 0, lhave = 0;
3826         int hx = 0, hy = 0, hhave = 0;
3827         int dx = 0;
3828         int y = 0;
3829
3830         lhave = 0;
3831         hhave = 0;
3832
3833         /* identify best lower and higher x calibration measurement */
3834         for (ip = 0; ip < np; ip++) {
3835                 dx = x - px[ip];
3836
3837                 /* this measurement is higher than our desired x */
3838                 if (dx <= 0) {
3839                         if (!hhave || dx > (x - hx)) {
3840                                 /* new best higher x measurement */
3841                                 hx = px[ip];
3842                                 hy = py[ip];
3843                                 hhave = 1;
3844                         }
3845                 }
3846                 /* this measurement is lower than our desired x */
3847                 if (dx >= 0) {
3848                         if (!lhave || dx < (x - lx)) {
3849                                 /* new best lower x measurement */
3850                                 lx = px[ip];
3851                                 ly = py[ip];
3852                                 lhave = 1;
3853                         }
3854                 }
3855         }
3856
3857         /* the low x is good */
3858         if (lhave) {
3859                 /* so is the high x */
3860                 if (hhave) {
3861                         /* they're the same, so just pick one */
3862                         if (hx == lx)
3863                                 y = ly;
3864                         else    /* interpolate  */
3865                                 y = interpolate(x, lx, hx, ly, hy);
3866                 } else          /* only low is good, use it */
3867                         y = ly;
3868         } else if (hhave)       /* only high is good, use it */
3869                 y = hy;
3870         else /* nothing is good,this should never happen unless np=0, ???? */
3871                 y = -(1 << 30);
3872         return y;
3873 }
3874
3875 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3876                                        u16 rateIndex, u16 freq, int is2GHz)
3877 {
3878         u16 numPiers, i;
3879         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3880         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3881         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3882         struct cal_tgt_pow_legacy *pEepromTargetPwr;
3883         u8 *pFreqBin;
3884
3885         if (is2GHz) {
3886                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3887                 pEepromTargetPwr = eep->calTargetPower2G;
3888                 pFreqBin = eep->calTarget_freqbin_2G;
3889         } else {
3890                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3891                 pEepromTargetPwr = eep->calTargetPower5G;
3892                 pFreqBin = eep->calTarget_freqbin_5G;
3893         }
3894
3895         /*
3896          * create array of channels and targetpower from
3897          * targetpower piers stored on eeprom
3898          */
3899         for (i = 0; i < numPiers; i++) {
3900                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3901                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3902         }
3903
3904         /* interpolate to get target power for given frequency */
3905         return (u8) ar9003_hw_power_interpolate((s32) freq,
3906                                                  freqArray,
3907                                                  targetPowerArray, numPiers);
3908 }
3909
3910 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3911                                             u16 rateIndex,
3912                                             u16 freq, int is2GHz)
3913 {
3914         u16 numPiers, i;
3915         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3916         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3917         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3918         struct cal_tgt_pow_ht *pEepromTargetPwr;
3919         u8 *pFreqBin;
3920
3921         if (is2GHz) {
3922                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3923                 pEepromTargetPwr = eep->calTargetPower2GHT20;
3924                 pFreqBin = eep->calTarget_freqbin_2GHT20;
3925         } else {
3926                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3927                 pEepromTargetPwr = eep->calTargetPower5GHT20;
3928                 pFreqBin = eep->calTarget_freqbin_5GHT20;
3929         }
3930
3931         /*
3932          * create array of channels and targetpower
3933          * from targetpower piers stored on eeprom
3934          */
3935         for (i = 0; i < numPiers; i++) {
3936                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3937                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3938         }
3939
3940         /* interpolate to get target power for given frequency */
3941         return (u8) ar9003_hw_power_interpolate((s32) freq,
3942                                                  freqArray,
3943                                                  targetPowerArray, numPiers);
3944 }
3945
3946 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3947                                             u16 rateIndex,
3948                                             u16 freq, int is2GHz)
3949 {
3950         u16 numPiers, i;
3951         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3952         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3953         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3954         struct cal_tgt_pow_ht *pEepromTargetPwr;
3955         u8 *pFreqBin;
3956
3957         if (is2GHz) {
3958                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3959                 pEepromTargetPwr = eep->calTargetPower2GHT40;
3960                 pFreqBin = eep->calTarget_freqbin_2GHT40;
3961         } else {
3962                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3963                 pEepromTargetPwr = eep->calTargetPower5GHT40;
3964                 pFreqBin = eep->calTarget_freqbin_5GHT40;
3965         }
3966
3967         /*
3968          * create array of channels and targetpower from
3969          * targetpower piers stored on eeprom
3970          */
3971         for (i = 0; i < numPiers; i++) {
3972                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3973                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3974         }
3975
3976         /* interpolate to get target power for given frequency */
3977         return (u8) ar9003_hw_power_interpolate((s32) freq,
3978                                                  freqArray,
3979                                                  targetPowerArray, numPiers);
3980 }
3981
3982 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3983                                            u16 rateIndex, u16 freq)
3984 {
3985         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3986         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3987         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3988         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3989         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3990         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3991
3992         /*
3993          * create array of channels and targetpower from
3994          * targetpower piers stored on eeprom
3995          */
3996         for (i = 0; i < numPiers; i++) {
3997                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3998                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3999         }
4000
4001         /* interpolate to get target power for given frequency */
4002         return (u8) ar9003_hw_power_interpolate((s32) freq,
4003                                                  freqArray,
4004                                                  targetPowerArray, numPiers);
4005 }
4006
4007 /* Set tx power registers to array of values passed in */
4008 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4009 {
4010 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4011         /* make sure forced gain is not set */
4012         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4013
4014         /* Write the OFDM power per rate set */
4015
4016         /* 6 (LSB), 9, 12, 18 (MSB) */
4017         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4018                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4019                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4020                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4021                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4022
4023         /* 24 (LSB), 36, 48, 54 (MSB) */
4024         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4025                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4026                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4027                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4028                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4029
4030         /* Write the CCK power per rate set */
4031
4032         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4033         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4034                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4035                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4036                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4037                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4038
4039         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4040         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4041                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4042                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4043                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4044                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4045             );
4046
4047         /* Write the power for duplicated frames - HT40 */
4048
4049         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4050         REG_WRITE(ah, 0xa3e0,
4051                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4052                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4053                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4054                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4055             );
4056
4057         /* Write the HT20 power per rate set */
4058
4059         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4060         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4061                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4062                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4063                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4064                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4065             );
4066
4067         /* 6 (LSB), 7, 12, 13 (MSB) */
4068         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4069                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4070                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4071                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4072                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4073             );
4074
4075         /* 14 (LSB), 15, 20, 21 */
4076         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4077                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4078                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4079                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4080                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4081             );
4082
4083         /* Mixed HT20 and HT40 rates */
4084
4085         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4086         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4087                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4088                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4089                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4090                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4091             );
4092
4093         /*
4094          * Write the HT40 power per rate set
4095          * correct PAR difference between HT40 and HT20/LEGACY
4096          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4097          */
4098         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4099                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4100                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4101                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4102                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4103             );
4104
4105         /* 6 (LSB), 7, 12, 13 (MSB) */
4106         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4107                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4108                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4109                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4110                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4111             );
4112
4113         /* 14 (LSB), 15, 20, 21 */
4114         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4115                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4116                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4117                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4118                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4119             );
4120
4121         return 0;
4122 #undef POW_SM
4123 }
4124
4125 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4126                                               u8 *targetPowerValT2)
4127 {
4128         /* XXX: hard code for now, need to get from eeprom struct */
4129         u8 ht40PowerIncForPdadc = 0;
4130         int is2GHz = 0;
4131         unsigned int i = 0;
4132
4133         if (freq < 4000)
4134                 is2GHz = 1;
4135
4136         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4137             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4138                                          is2GHz);
4139         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4140             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4141                                          is2GHz);
4142         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4143             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4144                                          is2GHz);
4145         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4146             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4147                                          is2GHz);
4148         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4149             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4150                                              freq);
4151         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4152             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4153         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4154             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4155         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4156             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4157         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4158             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4159                                               is2GHz);
4160         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4161             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4162                                               freq, is2GHz);
4163         targetPowerValT2[ALL_TARGET_HT20_4] =
4164             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4165                                               is2GHz);
4166         targetPowerValT2[ALL_TARGET_HT20_5] =
4167             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4168                                               is2GHz);
4169         targetPowerValT2[ALL_TARGET_HT20_6] =
4170             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4171                                               is2GHz);
4172         targetPowerValT2[ALL_TARGET_HT20_7] =
4173             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4174                                               is2GHz);
4175         targetPowerValT2[ALL_TARGET_HT20_12] =
4176             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4177                                               is2GHz);
4178         targetPowerValT2[ALL_TARGET_HT20_13] =
4179             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4180                                               is2GHz);
4181         targetPowerValT2[ALL_TARGET_HT20_14] =
4182             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4183                                               is2GHz);
4184         targetPowerValT2[ALL_TARGET_HT20_15] =
4185             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4186                                               is2GHz);
4187         targetPowerValT2[ALL_TARGET_HT20_20] =
4188             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4189                                               is2GHz);
4190         targetPowerValT2[ALL_TARGET_HT20_21] =
4191             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4192                                               is2GHz);
4193         targetPowerValT2[ALL_TARGET_HT20_22] =
4194             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4195                                               is2GHz);
4196         targetPowerValT2[ALL_TARGET_HT20_23] =
4197             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4198                                               is2GHz);
4199         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4200             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4201                                               is2GHz) + ht40PowerIncForPdadc;
4202         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4203             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4204                                               freq,
4205                                               is2GHz) + ht40PowerIncForPdadc;
4206         targetPowerValT2[ALL_TARGET_HT40_4] =
4207             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4208                                               is2GHz) + ht40PowerIncForPdadc;
4209         targetPowerValT2[ALL_TARGET_HT40_5] =
4210             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4211                                               is2GHz) + ht40PowerIncForPdadc;
4212         targetPowerValT2[ALL_TARGET_HT40_6] =
4213             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4214                                               is2GHz) + ht40PowerIncForPdadc;
4215         targetPowerValT2[ALL_TARGET_HT40_7] =
4216             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4217                                               is2GHz) + ht40PowerIncForPdadc;
4218         targetPowerValT2[ALL_TARGET_HT40_12] =
4219             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4220                                               is2GHz) + ht40PowerIncForPdadc;
4221         targetPowerValT2[ALL_TARGET_HT40_13] =
4222             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4223                                               is2GHz) + ht40PowerIncForPdadc;
4224         targetPowerValT2[ALL_TARGET_HT40_14] =
4225             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4226                                               is2GHz) + ht40PowerIncForPdadc;
4227         targetPowerValT2[ALL_TARGET_HT40_15] =
4228             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4229                                               is2GHz) + ht40PowerIncForPdadc;
4230         targetPowerValT2[ALL_TARGET_HT40_20] =
4231             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4232                                               is2GHz) + ht40PowerIncForPdadc;
4233         targetPowerValT2[ALL_TARGET_HT40_21] =
4234             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4235                                               is2GHz) + ht40PowerIncForPdadc;
4236         targetPowerValT2[ALL_TARGET_HT40_22] =
4237             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4238                                               is2GHz) + ht40PowerIncForPdadc;
4239         targetPowerValT2[ALL_TARGET_HT40_23] =
4240             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4241                                               is2GHz) + ht40PowerIncForPdadc;
4242
4243         for (i = 0; i < ar9300RateSize; i++) {
4244                 DBG2("ath9k: "
4245                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4246         }
4247 }
4248
4249 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4250                                   int mode,
4251                                   int ipier,
4252                                   int ichain,
4253                                   int *pfrequency,
4254                                   int *pcorrection,
4255                                   int *ptemperature, int *pvoltage)
4256 {
4257         u8 *pCalPier;
4258         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4259         int is2GHz;
4260         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4261
4262         if (ichain >= AR9300_MAX_CHAINS) {
4263                 DBG("ath9k: "
4264                         "Invalid chain index, must be less than %d\n",
4265                         AR9300_MAX_CHAINS);
4266                 return -1;
4267         }
4268
4269         if (mode) {             /* 5GHz */
4270                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4271                         DBG("ath9k: "
4272                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4273                                 AR9300_NUM_5G_CAL_PIERS);
4274                         return -1;
4275                 }
4276                 pCalPier = &(eep->calFreqPier5G[ipier]);
4277                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4278                 is2GHz = 0;
4279         } else {
4280                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4281                         DBG("ath9k: "
4282                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4283                                 AR9300_NUM_2G_CAL_PIERS);
4284                         return -1;
4285                 }
4286
4287                 pCalPier = &(eep->calFreqPier2G[ipier]);
4288                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4289                 is2GHz = 1;
4290         }
4291
4292         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4293         *pcorrection = pCalPierStruct->refPower;
4294         *ptemperature = pCalPierStruct->tempMeas;
4295         *pvoltage = pCalPierStruct->voltMeas;
4296
4297         return 0;
4298 }
4299
4300 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4301                                             int frequency,
4302                                             int *correction,
4303                                             int *voltage __unused, int *temperature)
4304 {
4305         int tempSlope = 0;
4306         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4307         int f[3], t[3];
4308
4309         REG_RMW(ah, AR_PHY_TPC_11_B0,
4310                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4311                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4312         if (ah->caps.tx_chainmask & BIT(1))
4313                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4314                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4315                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4316         if (ah->caps.tx_chainmask & BIT(2))
4317                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4318                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4319                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4320
4321         /* enable open loop power control on chip */
4322         REG_RMW(ah, AR_PHY_TPC_6_B0,
4323                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4324                 AR_PHY_TPC_6_ERROR_EST_MODE);
4325         if (ah->caps.tx_chainmask & BIT(1))
4326                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4327                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4328                         AR_PHY_TPC_6_ERROR_EST_MODE);
4329         if (ah->caps.tx_chainmask & BIT(2))
4330                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4331                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4332                         AR_PHY_TPC_6_ERROR_EST_MODE);
4333
4334         /*
4335          * enable temperature compensation
4336          * Need to use register names
4337          */
4338         if (frequency < 4000)
4339                 tempSlope = eep->modalHeader2G.tempSlope;
4340         else if (eep->base_ext2.tempSlopeLow != 0) {
4341                 t[0] = eep->base_ext2.tempSlopeLow;
4342                 f[0] = 5180;
4343                 t[1] = eep->modalHeader5G.tempSlope;
4344                 f[1] = 5500;
4345                 t[2] = eep->base_ext2.tempSlopeHigh;
4346                 f[2] = 5785;
4347                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4348                                                         f, t, 3);
4349         } else
4350                 tempSlope = eep->modalHeader5G.tempSlope;
4351
4352         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4353         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4354                       temperature[0]);
4355
4356         return 0;
4357 }
4358
4359 /* Apply the recorded correction values. */
4360 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4361 {
4362         int ichain, ipier, npier;
4363         int mode;
4364         int lfrequency[AR9300_MAX_CHAINS],
4365             lcorrection[AR9300_MAX_CHAINS],
4366             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4367         int hfrequency[AR9300_MAX_CHAINS],
4368             hcorrection[AR9300_MAX_CHAINS],
4369             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4370         int fdiff;
4371         int correction[AR9300_MAX_CHAINS],
4372             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4373         int pfrequency, pcorrection, ptemperature, pvoltage;
4374
4375         mode = (frequency >= 4000);
4376         if (mode)
4377                 npier = AR9300_NUM_5G_CAL_PIERS;
4378         else
4379                 npier = AR9300_NUM_2G_CAL_PIERS;
4380
4381         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4382                 lfrequency[ichain] = 0;
4383                 hfrequency[ichain] = 100000;
4384         }
4385         /* identify best lower and higher frequency calibration measurement */
4386         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4387                 for (ipier = 0; ipier < npier; ipier++) {
4388                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4389                                                     &pfrequency, &pcorrection,
4390                                                     &ptemperature, &pvoltage)) {
4391                                 fdiff = frequency - pfrequency;
4392
4393                                 /*
4394                                  * this measurement is higher than
4395                                  * our desired frequency
4396                                  */
4397                                 if (fdiff <= 0) {
4398                                         if (hfrequency[ichain] <= 0 ||
4399                                             hfrequency[ichain] >= 100000 ||
4400                                             fdiff >
4401                                             (frequency - hfrequency[ichain])) {
4402                                                 /*
4403                                                  * new best higher
4404                                                  * frequency measurement
4405                                                  */
4406                                                 hfrequency[ichain] = pfrequency;
4407                                                 hcorrection[ichain] =
4408                                                     pcorrection;
4409                                                 htemperature[ichain] =
4410                                                     ptemperature;
4411                                                 hvoltage[ichain] = pvoltage;
4412                                         }
4413                                 }
4414                                 if (fdiff >= 0) {
4415                                         if (lfrequency[ichain] <= 0
4416                                             || fdiff <
4417                                             (frequency - lfrequency[ichain])) {
4418                                                 /*
4419                                                  * new best lower
4420                                                  * frequency measurement
4421                                                  */
4422                                                 lfrequency[ichain] = pfrequency;
4423                                                 lcorrection[ichain] =
4424                                                     pcorrection;
4425                                                 ltemperature[ichain] =
4426                                                     ptemperature;
4427                                                 lvoltage[ichain] = pvoltage;
4428                                         }
4429                                 }
4430                         }
4431                 }
4432         }
4433
4434         /* interpolate  */
4435         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4436                 DBG2("ath9k: "
4437                         "ch=%d f=%d low=%d %d h=%d %d\n",
4438                         ichain, frequency, lfrequency[ichain],
4439                         lcorrection[ichain], hfrequency[ichain],
4440                         hcorrection[ichain]);
4441                 /* they're the same, so just pick one */
4442                 if (hfrequency[ichain] == lfrequency[ichain]) {
4443                         correction[ichain] = lcorrection[ichain];
4444                         voltage[ichain] = lvoltage[ichain];
4445                         temperature[ichain] = ltemperature[ichain];
4446                 }
4447                 /* the low frequency is good */
4448                 else if (frequency - lfrequency[ichain] < 1000) {
4449                         /* so is the high frequency, interpolate */
4450                         if (hfrequency[ichain] - frequency < 1000) {
4451
4452                                 correction[ichain] = interpolate(frequency,
4453                                                 lfrequency[ichain],
4454                                                 hfrequency[ichain],
4455                                                 lcorrection[ichain],
4456                                                 hcorrection[ichain]);
4457
4458                                 temperature[ichain] = interpolate(frequency,
4459                                                 lfrequency[ichain],
4460                                                 hfrequency[ichain],
4461                                                 ltemperature[ichain],
4462                                                 htemperature[ichain]);
4463
4464                                 voltage[ichain] = interpolate(frequency,
4465                                                 lfrequency[ichain],
4466                                                 hfrequency[ichain],
4467                                                 lvoltage[ichain],
4468                                                 hvoltage[ichain]);
4469                         }
4470                         /* only low is good, use it */
4471                         else {
4472                                 correction[ichain] = lcorrection[ichain];
4473                                 temperature[ichain] = ltemperature[ichain];
4474                                 voltage[ichain] = lvoltage[ichain];
4475                         }
4476                 }
4477                 /* only high is good, use it */
4478                 else if (hfrequency[ichain] - frequency < 1000) {
4479                         correction[ichain] = hcorrection[ichain];
4480                         temperature[ichain] = htemperature[ichain];
4481                         voltage[ichain] = hvoltage[ichain];
4482                 } else {        /* nothing is good, presume 0???? */
4483                         correction[ichain] = 0;
4484                         temperature[ichain] = 0;
4485                         voltage[ichain] = 0;
4486                 }
4487         }
4488
4489         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4490                                          temperature);
4491
4492         DBG2("ath9k: "
4493                 "for frequency=%d, calibration correction = %d %d %d\n",
4494                 frequency, correction[0], correction[1], correction[2]);
4495
4496         return 0;
4497 }
4498
4499 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4500                                            int idx,
4501                                            int edge,
4502                                            int is2GHz)
4503 {
4504         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4505         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4506
4507         if (is2GHz)
4508                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4509         else
4510                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4511 }
4512
4513 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4514                                              int idx,
4515                                              unsigned int edge,
4516                                              u16 freq,
4517                                              int is2GHz)
4518 {
4519         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4520         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4521
4522         u8 *ctl_freqbin = is2GHz ?
4523                 &eep->ctl_freqbin_2G[idx][0] :
4524                 &eep->ctl_freqbin_5G[idx][0];
4525
4526         if (is2GHz) {
4527                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4528                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4529                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4530         } else {
4531                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4532                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4533                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4534         }
4535
4536         return MAX_RATE_POWER;
4537 }
4538
4539 /*
4540  * Find the maximum conformance test limit for the given channel and CTL info
4541  */
4542 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4543                                         u16 freq, int idx, int is2GHz)
4544 {
4545         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4546         u8 *ctl_freqbin = is2GHz ?
4547                 &eep->ctl_freqbin_2G[idx][0] :
4548                 &eep->ctl_freqbin_5G[idx][0];
4549         u16 num_edges = is2GHz ?
4550                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4551         unsigned int edge;
4552
4553         /* Get the edge power */
4554         for (edge = 0;
4555              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4556              edge++) {
4557                 /*
4558                  * If there's an exact channel match or an inband flag set
4559                  * on the lower channel use the given rdEdgePower
4560                  */
4561                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4562                         twiceMaxEdgePower =
4563                                 ar9003_hw_get_direct_edge_power(eep, idx,
4564                                                                 edge, is2GHz);
4565                         break;
4566                 } else if ((edge > 0) &&
4567                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4568                                                       is2GHz))) {
4569                         twiceMaxEdgePower =
4570                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4571                                                                   edge, freq,
4572                                                                   is2GHz);
4573                         /*
4574                          * Leave loop - no more affecting edges possible in
4575                          * this monotonic increasing list
4576                          */
4577                         break;
4578                 }
4579         }
4580         return twiceMaxEdgePower;
4581 }
4582
4583 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4584                                                struct ath9k_channel *chan,
4585                                                u8 *pPwrArray, u16 cfgCtl,
4586                                                u8 twiceAntennaReduction,
4587                                                u8 twiceMaxRegulatoryPower,
4588                                                u16 powerLimit)
4589 {
4590         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4591         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4592         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4593         static const u16 tpScaleReductionTable[5] = {
4594                 0, 3, 6, 9, MAX_RATE_POWER
4595         };
4596         int i;
4597         int16_t  twiceLargestAntenna;
4598         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4599         static const u16 ctlModesFor11a[] = {
4600                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4601         };
4602         static const u16 ctlModesFor11g[] = {
4603                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4604                 CTL_11G_EXT, CTL_2GHT40
4605         };
4606         u16 numCtlModes;
4607         const u16 *pCtlMode;
4608         u16 ctlMode, freq;
4609         struct chan_centers centers;
4610         u8 *ctlIndex;
4611         u8 ctlNum;
4612         u16 twiceMinEdgePower;
4613         int is2ghz = IS_CHAN_2GHZ(chan);
4614
4615         ath9k_hw_get_channel_centers(ah, chan, &centers);
4616
4617         /* Compute TxPower reduction due to Antenna Gain */
4618         if (is2ghz)
4619                 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4620         else
4621                 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4622
4623         twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4624                                 twiceLargestAntenna, 0);
4625
4626         /*
4627          * scaledPower is the minimum of the user input power level
4628          * and the regulatory allowed power level
4629          */
4630         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4631
4632         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4633                 maxRegAllowedPower -=
4634                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4635         }
4636
4637         scaledPower = min(powerLimit, maxRegAllowedPower);
4638
4639         /*
4640          * Reduce scaled Power by number of chains active to get
4641          * to per chain tx power level
4642          */
4643         switch (ar5416_get_ntxchains(ah->txchainmask)) {
4644         case 1:
4645                 break;
4646         case 2:
4647                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4648                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4649                 else
4650                         scaledPower = 0;
4651                 break;
4652         case 3:
4653                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4654                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4655                 else
4656                         scaledPower = 0;
4657                 break;
4658         }
4659
4660         scaledPower = max((u16)0, scaledPower);
4661
4662         /*
4663          * Get target powers from EEPROM - our baseline for TX Power
4664          */
4665         if (is2ghz) {
4666                 /* Setup for CTL modes */
4667                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4668                 numCtlModes =
4669                         ARRAY_SIZE(ctlModesFor11g) -
4670                                    SUB_NUM_CTL_MODES_AT_2G_40;
4671                 pCtlMode = ctlModesFor11g;
4672                 if (IS_CHAN_HT40(chan))
4673                         /* All 2G CTL's */
4674                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4675         } else {
4676                 /* Setup for CTL modes */
4677                 /* CTL_11A, CTL_5GHT20 */
4678                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4679                                          SUB_NUM_CTL_MODES_AT_5G_40;
4680                 pCtlMode = ctlModesFor11a;
4681                 if (IS_CHAN_HT40(chan))
4682                         /* All 5G CTL's */
4683                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4684         }
4685
4686         /*
4687          * For MIMO, need to apply regulatory caps individually across
4688          * dynamically running modes: CCK, OFDM, HT20, HT40
4689          *
4690          * The outer loop walks through each possible applicable runtime mode.
4691          * The inner loop walks through each ctlIndex entry in EEPROM.
4692          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4693          */
4694         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4695                 int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4696                         (pCtlMode[ctlMode] == CTL_2GHT40);
4697                 if (isHt40CtlMode)
4698                         freq = centers.synth_center;
4699                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4700                         freq = centers.ext_center;
4701                 else
4702                         freq = centers.ctl_center;
4703
4704                 DBG2("ath9k: "
4705                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4706                         ctlMode, numCtlModes, isHt40CtlMode,
4707                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4708
4709                 /* walk through each CTL index stored in EEPROM */
4710                 if (is2ghz) {
4711                         ctlIndex = pEepData->ctlIndex_2G;
4712                         ctlNum = AR9300_NUM_CTLS_2G;
4713                 } else {
4714                         ctlIndex = pEepData->ctlIndex_5G;
4715                         ctlNum = AR9300_NUM_CTLS_5G;
4716                 }
4717
4718                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4719                         DBG2("ath9k: "
4720                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4721                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4722                                 chan->channel);
4723
4724                                 /*
4725                                  * compare test group from regulatory
4726                                  * channel list with test mode from pCtlMode
4727                                  * list
4728                                  */
4729                                 if ((((cfgCtl & ~CTL_MODE_M) |
4730                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4731                                         ctlIndex[i]) ||
4732                                     (((cfgCtl & ~CTL_MODE_M) |
4733                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4734                                      ((ctlIndex[i] & CTL_MODE_M) |
4735                                        SD_NO_CTL))) {
4736                                         twiceMinEdgePower =
4737                                           ar9003_hw_get_max_edge_power(pEepData,
4738                                                                        freq, i,
4739                                                                        is2ghz);
4740
4741                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4742                                                 /*
4743                                                  * Find the minimum of all CTL
4744                                                  * edge powers that apply to
4745                                                  * this channel
4746                                                  */
4747                                                 twiceMaxEdgePower =
4748                                                         min(twiceMaxEdgePower,
4749                                                             twiceMinEdgePower);
4750                                                 else {
4751                                                         /* specific */
4752                                                         twiceMaxEdgePower =
4753                                                           twiceMinEdgePower;
4754                                                         break;
4755                                                 }
4756                                 }
4757                         }
4758
4759                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4760
4761                         DBG2("ath9k: "
4762                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4763                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4764                                 scaledPower, minCtlPower);
4765
4766                         /* Apply ctl mode to correct target power set */
4767                         switch (pCtlMode[ctlMode]) {
4768                         case CTL_11B:
4769                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4770                                      i <= ALL_TARGET_LEGACY_11S; i++)
4771                                         pPwrArray[i] =
4772                                           (u8)min((u16)pPwrArray[i],
4773                                                   minCtlPower);
4774                                 break;
4775                         case CTL_11A:
4776                         case CTL_11G:
4777                                 for (i = ALL_TARGET_LEGACY_6_24;
4778                                      i <= ALL_TARGET_LEGACY_54; i++)
4779                                         pPwrArray[i] =
4780                                           (u8)min((u16)pPwrArray[i],
4781                                                   minCtlPower);
4782                                 break;
4783                         case CTL_5GHT20:
4784                         case CTL_2GHT20:
4785                                 for (i = ALL_TARGET_HT20_0_8_16;
4786                                      i <= ALL_TARGET_HT20_21; i++)
4787                                         pPwrArray[i] =
4788                                           (u8)min((u16)pPwrArray[i],
4789                                                   minCtlPower);
4790                                 pPwrArray[ALL_TARGET_HT20_22] =
4791                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4792                                           minCtlPower);
4793                                 pPwrArray[ALL_TARGET_HT20_23] =
4794                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4795                                            minCtlPower);
4796                                 break;
4797                         case CTL_5GHT40:
4798                         case CTL_2GHT40:
4799                                 for (i = ALL_TARGET_HT40_0_8_16;
4800                                      i <= ALL_TARGET_HT40_23; i++)
4801                                         pPwrArray[i] =
4802                                           (u8)min((u16)pPwrArray[i],
4803                                                   minCtlPower);
4804                                 break;
4805                         default:
4806                             break;
4807                         }
4808         } /* end ctl mode checking */
4809 }
4810
4811 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4812 {
4813         u8 mod_idx = mcs_idx % 8;
4814
4815         if (mod_idx <= 3)
4816                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4817         else
4818                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4819 }
4820
4821 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4822                                         struct ath9k_channel *chan, u16 cfgCtl,
4823                                         u8 twiceAntennaReduction,
4824                                         u8 twiceMaxRegulatoryPower,
4825                                         u8 powerLimit, int test)
4826 {
4827         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4828         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4829         struct ar9300_modal_eep_header *modal_hdr;
4830         u8 targetPowerValT2[ar9300RateSize];
4831         u8 target_power_val_t2_eep[ar9300RateSize];
4832         unsigned int i = 0, paprd_scale_factor = 0;
4833         u8 pwr_idx, min_pwridx = 0;
4834
4835         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4836
4837         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4838                 if (IS_CHAN_2GHZ(chan))
4839                         modal_hdr = &eep->modalHeader2G;
4840                 else
4841                         modal_hdr = &eep->modalHeader5G;
4842
4843                 ah->paprd_ratemask =
4844                                 (uint32_t)(modal_hdr->papdRateMaskHt20) &
4845                         AR9300_PAPRD_RATE_MASK;
4846
4847                 ah->paprd_ratemask_ht40 =
4848                                 (uint32_t)(modal_hdr->papdRateMaskHt40) &
4849                         AR9300_PAPRD_RATE_MASK;
4850
4851                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4852                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4853                                                   ALL_TARGET_HT20_0_8_16;
4854
4855                 if (!ah->paprd_table_write_done) {
4856                         memcpy(target_power_val_t2_eep, targetPowerValT2,
4857                                sizeof(targetPowerValT2));
4858                         for (i = 0; i < 24; i++) {
4859                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4860                                 if (ah->paprd_ratemask & (1 << i)) {
4861                                         if (targetPowerValT2[pwr_idx] &&
4862                                             targetPowerValT2[pwr_idx] ==
4863                                             target_power_val_t2_eep[pwr_idx])
4864                                                 targetPowerValT2[pwr_idx] -=
4865                                                         paprd_scale_factor;
4866                                 }
4867                         }
4868                 }
4869                 memcpy(target_power_val_t2_eep, targetPowerValT2,
4870                        sizeof(targetPowerValT2));
4871         }
4872
4873         ar9003_hw_set_power_per_rate_table(ah, chan,
4874                                            targetPowerValT2, cfgCtl,
4875                                            twiceAntennaReduction,
4876                                            twiceMaxRegulatoryPower,
4877                                            powerLimit);
4878
4879         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4880                 for (i = 0; i < ar9300RateSize; i++) {
4881                         if ((ah->paprd_ratemask & (1 << i)) &&
4882                             ((unsigned int)abs(targetPowerValT2[i] -
4883                                 target_power_val_t2_eep[i]) >
4884                             paprd_scale_factor)) {
4885                                 ah->paprd_ratemask &= ~(1 << i);
4886                                 DBG2("ath9k: "
4887                                         "paprd disabled for mcs %d\n", i);
4888                         }
4889                 }
4890         }
4891
4892         regulatory->max_power_level = 0;
4893         for (i = 0; i < ar9300RateSize; i++) {
4894                 if (targetPowerValT2[i] > regulatory->max_power_level)
4895                         regulatory->max_power_level = targetPowerValT2[i];
4896         }
4897
4898         if (test)
4899                 return;
4900
4901         for (i = 0; i < ar9300RateSize; i++) {
4902                 DBG2("ath9k: "
4903                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4904         }
4905
4906         /*
4907          * This is the TX power we send back to driver core,
4908          * and it can use to pass to userspace to display our
4909          * currently configured TX power setting.
4910          *
4911          * Since power is rate dependent, use one of the indices
4912          * from the AR9300_Rates enum to select an entry from
4913          * targetPowerValT2[] to report. Currently returns the
4914          * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4915          * as CCK power is less interesting (?).
4916          */
4917         i = ALL_TARGET_LEGACY_6_24; /* legacy */
4918         if (IS_CHAN_HT40(chan))
4919                 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4920         else if (IS_CHAN_HT20(chan))
4921                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4922
4923         ah->txpower_limit = targetPowerValT2[i];
4924         regulatory->max_power_level = targetPowerValT2[i];
4925
4926         /* Write target power array to registers */
4927         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4928         ar9003_hw_calibration_apply(ah, chan->channel);
4929
4930         if (IS_CHAN_2GHZ(chan)) {
4931                 if (IS_CHAN_HT40(chan))
4932                         i = ALL_TARGET_HT40_0_8_16;
4933                 else
4934                         i = ALL_TARGET_HT20_0_8_16;
4935         } else {
4936                 if (IS_CHAN_HT40(chan))
4937                         i = ALL_TARGET_HT40_7;
4938                 else
4939                         i = ALL_TARGET_HT20_7;
4940         }
4941         ah->paprd_target_power = targetPowerValT2[i];
4942 }
4943
4944 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused,
4945                                             u16 i __unused, int is2GHz __unused)
4946 {
4947         return AR_NO_SPUR;
4948 }
4949
4950 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4951 {
4952         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4953
4954         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4955 }
4956
4957 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4958 {
4959         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4960
4961         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4962 }
4963
4964 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
4965 {
4966         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4967
4968         if (is_2ghz)
4969                 return eep->modalHeader2G.spurChans;
4970         else
4971                 return eep->modalHeader5G.spurChans;
4972 }
4973
4974 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4975                                            struct ath9k_channel *chan)
4976 {
4977         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4978
4979         if (IS_CHAN_2GHZ(chan))
4980                 return MS((uint32_t)(eep->modalHeader2G.papdRateMaskHt20),
4981                           AR9300_PAPRD_SCALE_1);
4982         else {
4983                 if (chan->channel >= 5700)
4984                 return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt20),
4985                           AR9300_PAPRD_SCALE_1);
4986                 else if (chan->channel >= 5400)
4987                         return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4988                                    AR9300_PAPRD_SCALE_2);
4989                 else
4990                         return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4991                                   AR9300_PAPRD_SCALE_1);
4992         }
4993 }
4994
4995 const struct eeprom_ops eep_ar9300_ops = {
4996         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4997         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4998         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4999         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5000         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5001         .set_board_values = ath9k_hw_ar9300_set_board_values,
5002         .set_addac = ath9k_hw_ar9300_set_addac,
5003         .set_txpower = ath9k_hw_ar9300_set_txpower,
5004         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5005 };