2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifndef AR9003_EEPROM_H
21 #define AR9003_EEPROM_H
23 FILE_LICENCE ( BSD2 );
25 #define AR9300_EEP_VER 0xD000
26 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
27 #define AR9300_EEP_MINOR_VER_1 0x1
28 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
30 /* 16-bit offset location start of calibration struct */
31 #define AR9300_EEP_START_LOC 256
32 #define AR9300_NUM_5G_CAL_PIERS 8
33 #define AR9300_NUM_2G_CAL_PIERS 3
34 #define AR9300_NUM_5G_20_TARGET_POWERS 8
35 #define AR9300_NUM_5G_40_TARGET_POWERS 8
36 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
37 #define AR9300_NUM_2G_20_TARGET_POWERS 3
38 #define AR9300_NUM_2G_40_TARGET_POWERS 3
39 /* #define AR9300_NUM_CTLS 21 */
40 #define AR9300_NUM_CTLS_5G 9
41 #define AR9300_NUM_CTLS_2G 12
42 #define AR9300_NUM_BAND_EDGES_5G 8
43 #define AR9300_NUM_BAND_EDGES_2G 4
44 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
45 #define AR9300_EEPMISC_WOW 0x02
46 #define AR9300_CUSTOMER_DATA_SIZE 20
48 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
49 #define AR9300_MAX_CHAINS 3
50 #define AR9300_ANT_16S 25
51 #define AR9300_FUTURE_MODAL_SZ 6
53 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
54 #define AR9300_PAPRD_SCALE_1 0x0e000000
55 #define AR9300_PAPRD_SCALE_1_S 25
56 #define AR9300_PAPRD_SCALE_2 0x70000000
57 #define AR9300_PAPRD_SCALE_2_S 28
59 /* Delta from which to start power to pdadc table */
60 /* This offset is used in both open loop and closed loop power control
61 * schemes. In open loop power control, it is not really needed, but for
62 * the "sake of consistency" it was kept. For certain AP designs, this
63 * value is overwritten by the value in the flag "pwrTableOffset" just
64 * before writing the pdadc vs pwr into the chip registers.
66 #define AR9300_PWR_TABLE_OFFSET 0
68 /* byte addressable */
69 #define AR9300_EEPROM_SIZE (16*1024)
71 #define AR9300_BASE_ADDR_4K 0xfff
72 #define AR9300_BASE_ADDR 0x3ff
73 #define AR9300_BASE_ADDR_512 0x1ff
75 #define AR9300_OTP_BASE 0x14000
76 #define AR9300_OTP_STATUS 0x15f18
77 #define AR9300_OTP_STATUS_TYPE 0x7
78 #define AR9300_OTP_STATUS_VALID 0x4
79 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
80 #define AR9300_OTP_STATUS_SM_BUSY 0x1
81 #define AR9300_OTP_READ_DATA 0x15f1c
83 enum targetPowerHTRates {
84 HT_TARGET_RATE_0_8_16,
85 HT_TARGET_RATE_1_3_9_11_17_19,
100 enum targetPowerLegacyRates {
101 LEGACY_TARGET_RATE_6_24,
102 LEGACY_TARGET_RATE_36,
103 LEGACY_TARGET_RATE_48,
104 LEGACY_TARGET_RATE_54
107 enum targetPowerCckRates {
108 LEGACY_TARGET_RATE_1L_5L,
109 LEGACY_TARGET_RATE_5S,
110 LEGACY_TARGET_RATE_11L,
111 LEGACY_TARGET_RATE_11S
115 ALL_TARGET_LEGACY_6_24,
116 ALL_TARGET_LEGACY_36,
117 ALL_TARGET_LEGACY_48,
118 ALL_TARGET_LEGACY_54,
119 ALL_TARGET_LEGACY_1L_5L,
120 ALL_TARGET_LEGACY_5S,
121 ALL_TARGET_LEGACY_11L,
122 ALL_TARGET_LEGACY_11S,
123 ALL_TARGET_HT20_0_8_16,
124 ALL_TARGET_HT20_1_3_9_11_17_19,
137 ALL_TARGET_HT40_0_8_16,
138 ALL_TARGET_HT40_1_3_9_11_17_19,
158 } __attribute__((packed));
160 enum CompressAlgorithm {
171 struct ar9300_base_eep_hdr {
173 /* 4 bits tx and 4 bits rx */
175 struct eepFlags opCapFlags;
179 /* takes lower byte in eeprom location */
181 /* offset in dB to be added to beginning
182 * of pdadc table in calibration
184 int8_t pwrTableOffset;
185 u8 params_for_tuning_caps[2];
187 * bit0 - enable tx temp comp
188 * bit1 - enable tx volt comp
189 * bit2 - enable fastClock - default to 1
190 * bit3 - enable doubling - default to 1
191 * bit4 - enable internal regulator - default to 1
194 /* misc flags: bit0 - turn down drivestrength */
195 u8 miscConfiguration;
196 u8 eepromWriteEnableGpio;
201 /* SW controlled internal regulator fields */
203 } __attribute__((packed));
205 struct ar9300_modal_eep_header {
206 /* 4 idle, t1, t2, b (4 bits per setting) */
207 uint32_t antCtrlCommon;
208 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
209 uint32_t antCtrlCommon2;
210 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
211 uint16_t antCtrlChain[AR9300_MAX_CHAINS];
212 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
213 u8 xatten1DB[AR9300_MAX_CHAINS];
214 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
215 u8 xatten1Margin[AR9300_MAX_CHAINS];
218 /* spur channels in usual fbin coding format */
219 u8 spurChans[AR_EEPROM_MODAL_SPURS];
220 /* 3 Check if the register is per chain */
221 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
222 u8 ob[AR9300_MAX_CHAINS];
223 u8 db_stage2[AR9300_MAX_CHAINS];
224 u8 db_stage3[AR9300_MAX_CHAINS];
225 u8 db_stage4[AR9300_MAX_CHAINS];
227 u8 txFrameToDataStart;
232 int8_t adcDesiredSize;
237 uint32_t papdRateMaskHt20;
238 uint32_t papdRateMaskHt40;
240 } __attribute__((packed));
242 struct ar9300_cal_data_per_freq_op_loop {
244 /* pdadc voltage at power measurement */
246 /* pcdac used for power measurement */
248 /* range is -60 to -127 create a mapping equation 1db resolution */
249 int8_t rxNoisefloorCal;
250 /*range is same as noisefloor */
251 int8_t rxNoisefloorPower;
252 /* temp measured when noisefloor cal was performed */
254 } __attribute__((packed));
256 struct cal_tgt_pow_legacy {
258 } __attribute__((packed));
260 struct cal_tgt_pow_ht {
262 } __attribute__((packed));
264 struct cal_ctl_data_2g {
265 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
266 } __attribute__((packed));
268 struct cal_ctl_data_5g {
269 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
270 } __attribute__((packed));
272 struct ar9300_BaseExtension_1 {
275 } __attribute__((packed));
277 struct ar9300_BaseExtension_2 {
279 int8_t tempSlopeHigh;
280 u8 xatten1DBLow[AR9300_MAX_CHAINS];
281 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
282 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
283 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
284 } __attribute__((packed));
286 struct ar9300_eeprom {
290 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
292 struct ar9300_base_eep_hdr baseEepHeader;
294 struct ar9300_modal_eep_header modalHeader2G;
295 struct ar9300_BaseExtension_1 base_ext1;
296 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
297 struct ar9300_cal_data_per_freq_op_loop
298 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
299 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
300 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
301 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
302 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
303 struct cal_tgt_pow_legacy
304 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
305 struct cal_tgt_pow_legacy
306 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
307 struct cal_tgt_pow_ht
308 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
309 struct cal_tgt_pow_ht
310 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
311 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
312 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
313 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
314 struct ar9300_modal_eep_header modalHeader5G;
315 struct ar9300_BaseExtension_2 base_ext2;
316 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
317 struct ar9300_cal_data_per_freq_op_loop
318 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
319 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
320 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
321 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
322 struct cal_tgt_pow_legacy
323 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
324 struct cal_tgt_pow_ht
325 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
326 struct cal_tgt_pow_ht
327 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
328 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
329 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
330 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
331 } __attribute__((packed));
333 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
334 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
336 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz);
338 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
339 struct ath9k_channel *chan);