2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
34 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */
36 FILE_LICENCE ( GPL2_ONLY );
38 #define QIB_7322_Revision_offset 0x00000000UL
39 struct QIB_7322_Revision_pb {
40 pseudo_bit_t R_ChipRevMinor[8];
41 pseudo_bit_t R_ChipRevMajor[8];
42 pseudo_bit_t R_Arch[8];
44 pseudo_bit_t BoardID[8];
45 pseudo_bit_t R_Emulation_Revcode[22];
46 pseudo_bit_t R_Emulation[1];
47 pseudo_bit_t R_Simulator[1];
49 struct QIB_7322_Revision {
50 PSEUDO_BIT_STRUCT ( struct QIB_7322_Revision_pb );
52 /* Default value: 0x0000000002010601 */
54 #define QIB_7322_Control_offset 0x00000008UL
55 struct QIB_7322_Control_pb {
56 pseudo_bit_t SyncReset[1];
57 pseudo_bit_t FreezeMode[1];
58 pseudo_bit_t _unused_0[1];
59 pseudo_bit_t PCIERetryBufDiagEn[1];
60 pseudo_bit_t SDmaDescFetchPriorityEn[1];
61 pseudo_bit_t PCIEPostQDiagEn[1];
62 pseudo_bit_t PCIECplQDiagEn[1];
63 pseudo_bit_t _unused_1[57];
65 struct QIB_7322_Control {
66 PSEUDO_BIT_STRUCT ( struct QIB_7322_Control_pb );
68 /* Default value: 0x0000000000000000 */
70 #define QIB_7322_PageAlign_offset 0x00000010UL
71 /* Default value: 0x0000000000001000 */
73 #define QIB_7322_ContextCnt_offset 0x00000018UL
74 /* Default value: 0x0000000000000012 */
76 #define QIB_7322_Scratch_offset 0x00000020UL
77 /* Default value: 0x0000000000000000 */
79 #define QIB_7322_CntrRegBase_offset 0x00000028UL
80 /* Default value: 0x0000000000011000 */
82 #define QIB_7322_SendRegBase_offset 0x00000030UL
83 /* Default value: 0x0000000000003000 */
85 #define QIB_7322_UserRegBase_offset 0x00000038UL
86 /* Default value: 0x0000000000200000 */
88 #define QIB_7322_DebugPortSel_offset 0x00000040UL
89 struct QIB_7322_DebugPortSel_pb {
90 pseudo_bit_t DebugOutMuxSel[2];
91 pseudo_bit_t _unused_0[28];
92 pseudo_bit_t SrcMuxSel0[8];
93 pseudo_bit_t SrcMuxSel1[8];
94 pseudo_bit_t DbgClkPortSel[5];
95 pseudo_bit_t EnDbgPort[1];
96 pseudo_bit_t EnEnhancedDebugMode[1];
97 pseudo_bit_t EnhMode_SrcMuxSelIndex[10];
98 pseudo_bit_t EnhMode_SrcMuxSelWrEn[1];
100 struct QIB_7322_DebugPortSel {
101 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortSel_pb );
103 /* Default value: 0x0000000000000000 */
105 #define QIB_7322_DebugPortNibbleSel_offset 0x00000048UL
106 struct QIB_7322_DebugPortNibbleSel_pb {
107 pseudo_bit_t NibbleSel0[4];
108 pseudo_bit_t NibbleSel1[4];
109 pseudo_bit_t NibbleSel2[4];
110 pseudo_bit_t NibbleSel3[4];
111 pseudo_bit_t NibbleSel4[4];
112 pseudo_bit_t NibbleSel5[4];
113 pseudo_bit_t NibbleSel6[4];
114 pseudo_bit_t NibbleSel7[4];
115 pseudo_bit_t NibbleSel8[4];
116 pseudo_bit_t NibbleSel9[4];
117 pseudo_bit_t NibbleSel10[4];
118 pseudo_bit_t NibbleSel11[4];
119 pseudo_bit_t NibbleSel12[4];
120 pseudo_bit_t NibbleSel13[4];
121 pseudo_bit_t NibbleSel14[4];
122 pseudo_bit_t NibbleSel15[4];
124 struct QIB_7322_DebugPortNibbleSel {
125 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortNibbleSel_pb );
127 /* Default value: 0xFEDCBA9876543210 */
129 #define QIB_7322_DebugSigsIntSel_offset 0x00000050UL
130 struct QIB_7322_DebugSigsIntSel_pb {
131 pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3];
132 pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3];
133 pseudo_bit_t debug_port_sel_pcs_sdout[1];
134 pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4];
135 pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[3];
136 pseudo_bit_t EnableSDma_SelfDrain[1];
137 pseudo_bit_t debug_port_sel_pcie_rx_tx[1];
138 pseudo_bit_t _unused_0[1];
139 pseudo_bit_t debug_port_sel_tx_ibport[1];
140 pseudo_bit_t debug_port_sel_tx_sdma[1];
141 pseudo_bit_t debug_port_sel_rx_ibport[1];
142 pseudo_bit_t _unused_1[12];
143 pseudo_bit_t debug_port_sel_xgxs_0[4];
144 pseudo_bit_t debug_port_sel_credit_a_0[3];
145 pseudo_bit_t debug_port_sel_credit_b_0[3];
146 pseudo_bit_t debug_port_sel_xgxs_1[4];
147 pseudo_bit_t debug_port_sel_credit_a_1[3];
148 pseudo_bit_t debug_port_sel_credit_b_1[3];
149 pseudo_bit_t _unused_2[12];
151 struct QIB_7322_DebugSigsIntSel {
152 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugSigsIntSel_pb );
154 /* Default value: 0x0000000000000000 */
156 #define QIB_7322_DebugPortValueReg_offset 0x00000058UL
158 #define QIB_7322_IntBlocked_offset 0x00000060UL
159 struct QIB_7322_IntBlocked_pb {
160 pseudo_bit_t RcvAvail0IntBlocked[1];
161 pseudo_bit_t RcvAvail1IntBlocked[1];
162 pseudo_bit_t RcvAvail2IntBlocked[1];
163 pseudo_bit_t RcvAvail3IntBlocked[1];
164 pseudo_bit_t RcvAvail4IntBlocked[1];
165 pseudo_bit_t RcvAvail5IntBlocked[1];
166 pseudo_bit_t RcvAvail6IntBlocked[1];
167 pseudo_bit_t RcvAvail7IntBlocked[1];
168 pseudo_bit_t RcvAvail8IntBlocked[1];
169 pseudo_bit_t RcvAvail9IntBlocked[1];
170 pseudo_bit_t RcvAvail10IntBlocked[1];
171 pseudo_bit_t RcvAvail11IntBlocked[1];
172 pseudo_bit_t RcvAvail12IntBlocked[1];
173 pseudo_bit_t RcvAvail13IntBlocked[1];
174 pseudo_bit_t RcvAvail14IntBlocked[1];
175 pseudo_bit_t RcvAvail15IntBlocked[1];
176 pseudo_bit_t RcvAvail16IntBlocked[1];
177 pseudo_bit_t RcvAvail17IntBlocked[1];
178 pseudo_bit_t _unused_0[5];
179 pseudo_bit_t SendBufAvailIntBlocked[1];
180 pseudo_bit_t SendDoneIntBlocked_0[1];
181 pseudo_bit_t SendDoneIntBlocked_1[1];
182 pseudo_bit_t _unused_1[2];
183 pseudo_bit_t AssertGPIOIntBlocked[1];
184 pseudo_bit_t ErrIntBlocked[1];
185 pseudo_bit_t ErrIntBlocked_0[1];
186 pseudo_bit_t ErrIntBlocked_1[1];
187 pseudo_bit_t RcvUrg0IntBlocked[1];
188 pseudo_bit_t RcvUrg1IntBlocked[1];
189 pseudo_bit_t RcvUrg2IntBlocked[1];
190 pseudo_bit_t RcvUrg3IntBlocked[1];
191 pseudo_bit_t RcvUrg4IntBlocked[1];
192 pseudo_bit_t RcvUrg5IntBlocked[1];
193 pseudo_bit_t RcvUrg6IntBlocked[1];
194 pseudo_bit_t RcvUrg7IntBlocked[1];
195 pseudo_bit_t RcvUrg8IntBlocked[1];
196 pseudo_bit_t RcvUrg9IntBlocked[1];
197 pseudo_bit_t RcvUrg10IntBlocked[1];
198 pseudo_bit_t RcvUrg11IntBlocked[1];
199 pseudo_bit_t RcvUrg12IntBlocked[1];
200 pseudo_bit_t RcvUrg13IntBlocked[1];
201 pseudo_bit_t RcvUrg14IntBlocked[1];
202 pseudo_bit_t RcvUrg15IntBlocked[1];
203 pseudo_bit_t RcvUrg16IntBlocked[1];
204 pseudo_bit_t RcvUrg17IntBlocked[1];
205 pseudo_bit_t _unused_2[6];
206 pseudo_bit_t SDmaCleanupDoneBlocked_0[1];
207 pseudo_bit_t SDmaCleanupDoneBlocked_1[1];
208 pseudo_bit_t SDmaIdleIntBlocked_0[1];
209 pseudo_bit_t SDmaIdleIntBlocked_1[1];
210 pseudo_bit_t SDmaProgressIntBlocked_0[1];
211 pseudo_bit_t SDmaProgressIntBlocked_1[1];
212 pseudo_bit_t SDmaIntBlocked_0[1];
213 pseudo_bit_t SDmaIntBlocked_1[1];
215 struct QIB_7322_IntBlocked {
216 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntBlocked_pb );
218 /* Default value: 0x0000000000000000 */
220 #define QIB_7322_IntMask_offset 0x00000068UL
221 struct QIB_7322_IntMask_pb {
222 pseudo_bit_t RcvAvail0IntMask[1];
223 pseudo_bit_t RcvAvail1IntMask[1];
224 pseudo_bit_t RcvAvail2IntMask[1];
225 pseudo_bit_t RcvAvail3IntMask[1];
226 pseudo_bit_t RcvAvail4IntMask[1];
227 pseudo_bit_t RcvAvail5IntMask[1];
228 pseudo_bit_t RcvAvail6IntMask[1];
229 pseudo_bit_t RcvAvail7IntMask[1];
230 pseudo_bit_t RcvAvail8IntMask[1];
231 pseudo_bit_t RcvAvail9IntMask[1];
232 pseudo_bit_t RcvAvail10IntMask[1];
233 pseudo_bit_t RcvAvail11IntMask[1];
234 pseudo_bit_t RcvAvail12IntMask[1];
235 pseudo_bit_t RcvAvail13IntMask[1];
236 pseudo_bit_t RcvAvail14IntMask[1];
237 pseudo_bit_t RcvAvail15IntMask[1];
238 pseudo_bit_t RcvAvail16IntMask[1];
239 pseudo_bit_t RcvAvail17IntMask[1];
240 pseudo_bit_t _unused_0[5];
241 pseudo_bit_t SendBufAvailIntMask[1];
242 pseudo_bit_t SendDoneIntMask_0[1];
243 pseudo_bit_t SendDoneIntMask_1[1];
244 pseudo_bit_t _unused_1[2];
245 pseudo_bit_t AssertGPIOIntMask[1];
246 pseudo_bit_t ErrIntMask[1];
247 pseudo_bit_t ErrIntMask_0[1];
248 pseudo_bit_t ErrIntMask_1[1];
249 pseudo_bit_t RcvUrg0IntMask[1];
250 pseudo_bit_t RcvUrg1IntMask[1];
251 pseudo_bit_t RcvUrg2IntMask[1];
252 pseudo_bit_t RcvUrg3IntMask[1];
253 pseudo_bit_t RcvUrg4IntMask[1];
254 pseudo_bit_t RcvUrg5IntMask[1];
255 pseudo_bit_t RcvUrg6IntMask[1];
256 pseudo_bit_t RcvUrg7IntMask[1];
257 pseudo_bit_t RcvUrg8IntMask[1];
258 pseudo_bit_t RcvUrg9IntMask[1];
259 pseudo_bit_t RcvUrg10IntMask[1];
260 pseudo_bit_t RcvUrg11IntMask[1];
261 pseudo_bit_t RcvUrg12IntMask[1];
262 pseudo_bit_t RcvUrg13IntMask[1];
263 pseudo_bit_t RcvUrg14IntMask[1];
264 pseudo_bit_t RcvUrg15IntMask[1];
265 pseudo_bit_t RcvUrg16IntMask[1];
266 pseudo_bit_t RcvUrg17IntMask[1];
267 pseudo_bit_t _unused_2[6];
268 pseudo_bit_t SDmaCleanupDoneMask_0[1];
269 pseudo_bit_t SDmaCleanupDoneMask_1[1];
270 pseudo_bit_t SDmaIdleIntMask_0[1];
271 pseudo_bit_t SDmaIdleIntMask_1[1];
272 pseudo_bit_t SDmaProgressIntMask_0[1];
273 pseudo_bit_t SDmaProgressIntMask_1[1];
274 pseudo_bit_t SDmaIntMask_0[1];
275 pseudo_bit_t SDmaIntMask_1[1];
277 struct QIB_7322_IntMask {
278 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntMask_pb );
280 /* Default value: 0x0000000000000000 */
282 #define QIB_7322_IntStatus_offset 0x00000070UL
283 struct QIB_7322_IntStatus_pb {
284 pseudo_bit_t RcvAvail0[1];
285 pseudo_bit_t RcvAvail1[1];
286 pseudo_bit_t RcvAvail2[1];
287 pseudo_bit_t RcvAvail3[1];
288 pseudo_bit_t RcvAvail4[1];
289 pseudo_bit_t RcvAvail5[1];
290 pseudo_bit_t RcvAvail6[1];
291 pseudo_bit_t RcvAvail7[1];
292 pseudo_bit_t RcvAvail8[1];
293 pseudo_bit_t RcvAvail9[1];
294 pseudo_bit_t RcvAvail10[1];
295 pseudo_bit_t RcvAvail11[1];
296 pseudo_bit_t RcvAvail12[1];
297 pseudo_bit_t RcvAvail13[1];
298 pseudo_bit_t RcvAvail14[1];
299 pseudo_bit_t RcvAvail15[1];
300 pseudo_bit_t RcvAvail16[1];
301 pseudo_bit_t RcvAvail17[1];
302 pseudo_bit_t _unused_0[5];
303 pseudo_bit_t SendBufAvail[1];
304 pseudo_bit_t SendDone_0[1];
305 pseudo_bit_t SendDone_1[1];
306 pseudo_bit_t _unused_1[2];
307 pseudo_bit_t AssertGPIO[1];
309 pseudo_bit_t Err_0[1];
310 pseudo_bit_t Err_1[1];
311 pseudo_bit_t RcvUrg0[1];
312 pseudo_bit_t RcvUrg1[1];
313 pseudo_bit_t RcvUrg2[1];
314 pseudo_bit_t RcvUrg3[1];
315 pseudo_bit_t RcvUrg4[1];
316 pseudo_bit_t RcvUrg5[1];
317 pseudo_bit_t RcvUrg6[1];
318 pseudo_bit_t RcvUrg7[1];
319 pseudo_bit_t RcvUrg8[1];
320 pseudo_bit_t RcvUrg9[1];
321 pseudo_bit_t RcvUrg10[1];
322 pseudo_bit_t RcvUrg11[1];
323 pseudo_bit_t RcvUrg12[1];
324 pseudo_bit_t RcvUrg13[1];
325 pseudo_bit_t RcvUrg14[1];
326 pseudo_bit_t RcvUrg15[1];
327 pseudo_bit_t RcvUrg16[1];
328 pseudo_bit_t RcvUrg17[1];
329 pseudo_bit_t _unused_2[6];
330 pseudo_bit_t SDmaCleanupDone_0[1];
331 pseudo_bit_t SDmaCleanupDone_1[1];
332 pseudo_bit_t SDmaIdleInt_0[1];
333 pseudo_bit_t SDmaIdleInt_1[1];
334 pseudo_bit_t SDmaProgressInt_0[1];
335 pseudo_bit_t SDmaProgressInt_1[1];
336 pseudo_bit_t SDmaInt_0[1];
337 pseudo_bit_t SDmaInt_1[1];
339 struct QIB_7322_IntStatus {
340 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntStatus_pb );
342 /* Default value: 0x0000000000000000 */
344 #define QIB_7322_IntClear_offset 0x00000078UL
345 struct QIB_7322_IntClear_pb {
346 pseudo_bit_t RcvAvail0IntClear[1];
347 pseudo_bit_t RcvAvail1IntClear[1];
348 pseudo_bit_t RcvAvail2IntClear[1];
349 pseudo_bit_t RcvAvail3IntClear[1];
350 pseudo_bit_t RcvAvail4IntClear[1];
351 pseudo_bit_t RcvAvail5IntClear[1];
352 pseudo_bit_t RcvAvail6IntClear[1];
353 pseudo_bit_t RcvAvail7IntClear[1];
354 pseudo_bit_t RcvAvail8IntClear[1];
355 pseudo_bit_t RcvAvail9IntClear[1];
356 pseudo_bit_t RcvAvail10IntClear[1];
357 pseudo_bit_t RcvAvail11IntClear[1];
358 pseudo_bit_t RcvAvail12IntClear[1];
359 pseudo_bit_t RcvAvail13IntClear[1];
360 pseudo_bit_t RcvAvail14IntClear[1];
361 pseudo_bit_t RcvAvail15IntClear[1];
362 pseudo_bit_t RcvAvail16IntClear[1];
363 pseudo_bit_t RcvAvail17IntClear[1];
364 pseudo_bit_t _unused_0[5];
365 pseudo_bit_t SendBufAvailIntClear[1];
366 pseudo_bit_t SendDoneIntClear_0[1];
367 pseudo_bit_t SendDoneIntClear_1[1];
368 pseudo_bit_t _unused_1[2];
369 pseudo_bit_t AssertGPIOIntClear[1];
370 pseudo_bit_t ErrIntClear[1];
371 pseudo_bit_t ErrIntClear_0[1];
372 pseudo_bit_t ErrIntClear_1[1];
373 pseudo_bit_t RcvUrg0IntClear[1];
374 pseudo_bit_t RcvUrg1IntClear[1];
375 pseudo_bit_t RcvUrg2IntClear[1];
376 pseudo_bit_t RcvUrg3IntClear[1];
377 pseudo_bit_t RcvUrg4IntClear[1];
378 pseudo_bit_t RcvUrg5IntClear[1];
379 pseudo_bit_t RcvUrg6IntClear[1];
380 pseudo_bit_t RcvUrg7IntClear[1];
381 pseudo_bit_t RcvUrg8IntClear[1];
382 pseudo_bit_t RcvUrg9IntClear[1];
383 pseudo_bit_t RcvUrg10IntClear[1];
384 pseudo_bit_t RcvUrg11IntClear[1];
385 pseudo_bit_t RcvUrg12IntClear[1];
386 pseudo_bit_t RcvUrg13IntClear[1];
387 pseudo_bit_t RcvUrg14IntClear[1];
388 pseudo_bit_t RcvUrg15IntClear[1];
389 pseudo_bit_t RcvUrg16IntClear[1];
390 pseudo_bit_t RcvUrg17IntClear[1];
391 pseudo_bit_t _unused_2[6];
392 pseudo_bit_t SDmaCleanupDoneClear_0[1];
393 pseudo_bit_t SDmaCleanupDoneClear_1[1];
394 pseudo_bit_t SDmaIdleIntClear_0[1];
395 pseudo_bit_t SDmaIdleIntClear_1[1];
396 pseudo_bit_t SDmaProgressIntClear_0[1];
397 pseudo_bit_t SDmaProgressIntClear_1[1];
398 pseudo_bit_t SDmaIntClear_0[1];
399 pseudo_bit_t SDmaIntClear_1[1];
401 struct QIB_7322_IntClear {
402 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntClear_pb );
404 /* Default value: 0x0000000000000000 */
406 #define QIB_7322_ErrMask_offset 0x00000080UL
407 struct QIB_7322_ErrMask_pb {
408 pseudo_bit_t _unused_0[12];
409 pseudo_bit_t RcvEgrFullErrMask[1];
410 pseudo_bit_t RcvHdrFullErrMask[1];
411 pseudo_bit_t _unused_1[11];
412 pseudo_bit_t SDmaBufMaskDuplicateErrMask[1];
413 pseudo_bit_t SDmaWrongPortErrMask[1];
414 pseudo_bit_t SendSpecialTriggerErrMask[1];
415 pseudo_bit_t _unused_2[7];
416 pseudo_bit_t SendArmLaunchErrMask[1];
417 pseudo_bit_t SendVLMismatchErrMask[1];
418 pseudo_bit_t _unused_3[15];
419 pseudo_bit_t RcvContextShareErrMask[1];
420 pseudo_bit_t InvalidEEPCmdMask[1];
421 pseudo_bit_t _unused_4[1];
422 pseudo_bit_t SBufVL15MisUseErrMask[1];
423 pseudo_bit_t SDmaVL15ErrMask[1];
424 pseudo_bit_t _unused_5[4];
425 pseudo_bit_t InvalidAddrErrMask[1];
426 pseudo_bit_t HardwareErrMask[1];
427 pseudo_bit_t ResetNegatedMask[1];
429 struct QIB_7322_ErrMask {
430 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_pb );
432 /* Default value: 0x0000000000000000 */
434 #define QIB_7322_ErrStatus_offset 0x00000088UL
435 struct QIB_7322_ErrStatus_pb {
436 pseudo_bit_t _unused_0[12];
437 pseudo_bit_t RcvEgrFullErr[1];
438 pseudo_bit_t RcvHdrFullErr[1];
439 pseudo_bit_t _unused_1[11];
440 pseudo_bit_t SDmaBufMaskDuplicateErr[1];
441 pseudo_bit_t SDmaWrongPortErr[1];
442 pseudo_bit_t SendSpecialTriggerErr[1];
443 pseudo_bit_t _unused_2[7];
444 pseudo_bit_t SendArmLaunchErr[1];
445 pseudo_bit_t SendVLMismatchErr[1];
446 pseudo_bit_t _unused_3[15];
447 pseudo_bit_t RcvContextShareErr[1];
448 pseudo_bit_t InvalidEEPCmdErr[1];
449 pseudo_bit_t _unused_4[1];
450 pseudo_bit_t SBufVL15MisUseErr[1];
451 pseudo_bit_t SDmaVL15Err[1];
452 pseudo_bit_t _unused_5[4];
453 pseudo_bit_t InvalidAddrErr[1];
454 pseudo_bit_t HardwareErr[1];
455 pseudo_bit_t ResetNegated[1];
457 struct QIB_7322_ErrStatus {
458 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_pb );
460 /* Default value: 0x0000000000000000 */
462 #define QIB_7322_ErrClear_offset 0x00000090UL
463 struct QIB_7322_ErrClear_pb {
464 pseudo_bit_t _unused_0[12];
465 pseudo_bit_t RcvEgrFullErrClear[1];
466 pseudo_bit_t RcvHdrFullErrClear[1];
467 pseudo_bit_t _unused_1[11];
468 pseudo_bit_t SDmaBufMaskDuplicateErrClear[1];
469 pseudo_bit_t SDmaWrongPortErrClear[1];
470 pseudo_bit_t SendSpecialTriggerErrClear[1];
471 pseudo_bit_t _unused_2[7];
472 pseudo_bit_t SendArmLaunchErrClear[1];
473 pseudo_bit_t SendVLMismatchErrMask[1];
474 pseudo_bit_t _unused_3[15];
475 pseudo_bit_t RcvContextShareErrClear[1];
476 pseudo_bit_t InvalidEEPCmdErrClear[1];
477 pseudo_bit_t _unused_4[1];
478 pseudo_bit_t SBufVL15MisUseErrClear[1];
479 pseudo_bit_t SDmaVL15ErrClear[1];
480 pseudo_bit_t _unused_5[4];
481 pseudo_bit_t InvalidAddrErrClear[1];
482 pseudo_bit_t HardwareErrClear[1];
483 pseudo_bit_t ResetNegatedClear[1];
485 struct QIB_7322_ErrClear {
486 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_pb );
488 /* Default value: 0x0000000000000000 */
490 #define QIB_7322_HwErrMask_offset 0x00000098UL
491 struct QIB_7322_HwErrMask_pb {
492 pseudo_bit_t _unused_0[11];
493 pseudo_bit_t LATriggeredMask[1];
494 pseudo_bit_t statusValidNoEopMask_0[1];
495 pseudo_bit_t IBCBusFromSPCParityErrMask_0[1];
496 pseudo_bit_t statusValidNoEopMask_1[1];
497 pseudo_bit_t IBCBusFromSPCParityErrMask_1[1];
498 pseudo_bit_t _unused_1[11];
499 pseudo_bit_t SDmaMemReadErrMask_0[1];
500 pseudo_bit_t SDmaMemReadErrMask_1[1];
501 pseudo_bit_t PciePoisonedTLPMask[1];
502 pseudo_bit_t PcieCplTimeoutMask[1];
503 pseudo_bit_t PCIeBusParityErrMask[3];
504 pseudo_bit_t pcie_phy_txParityErr[1];
505 pseudo_bit_t _unused_2[13];
506 pseudo_bit_t MemoryErrMask[1];
507 pseudo_bit_t _unused_3[4];
508 pseudo_bit_t TempsenseTholdReachedMask[1];
509 pseudo_bit_t PowerOnBISTFailedMask[1];
510 pseudo_bit_t PCIESerdesPClkNotDetectMask[1];
511 pseudo_bit_t _unused_4[6];
512 pseudo_bit_t IBSerdesPClkNotDetectMask_0[1];
513 pseudo_bit_t IBSerdesPClkNotDetectMask_1[1];
515 struct QIB_7322_HwErrMask {
516 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrMask_pb );
518 /* Default value: 0x0000000000000000 */
520 #define QIB_7322_HwErrStatus_offset 0x000000a0UL
521 struct QIB_7322_HwErrStatus_pb {
522 pseudo_bit_t _unused_0[11];
523 pseudo_bit_t LATriggered[1];
524 pseudo_bit_t statusValidNoEop_0[1];
525 pseudo_bit_t IBCBusFromSPCParityErr_0[1];
526 pseudo_bit_t statusValidNoEop_1[1];
527 pseudo_bit_t IBCBusFromSPCParityErr_1[1];
528 pseudo_bit_t _unused_1[11];
529 pseudo_bit_t SDmaMemReadErr_0[1];
530 pseudo_bit_t SDmaMemReadErr_1[1];
531 pseudo_bit_t PciePoisonedTLP[1];
532 pseudo_bit_t PcieCplTimeout[1];
533 pseudo_bit_t PCIeBusParity[3];
534 pseudo_bit_t pcie_phy_txParityErr[1];
535 pseudo_bit_t _unused_2[13];
536 pseudo_bit_t MemoryErr[1];
537 pseudo_bit_t _unused_3[4];
538 pseudo_bit_t TempsenseTholdReached[1];
539 pseudo_bit_t PowerOnBISTFailed[1];
540 pseudo_bit_t PCIESerdesPClkNotDetect[1];
541 pseudo_bit_t _unused_4[6];
542 pseudo_bit_t IBSerdesPClkNotDetect_0[1];
543 pseudo_bit_t IBSerdesPClkNotDetect_1[1];
545 struct QIB_7322_HwErrStatus {
546 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrStatus_pb );
548 /* Default value: 0x0000000000000000 */
550 #define QIB_7322_HwErrClear_offset 0x000000a8UL
551 struct QIB_7322_HwErrClear_pb {
552 pseudo_bit_t _unused_0[11];
553 pseudo_bit_t LATriggeredClear[1];
554 pseudo_bit_t IBCBusToSPCparityErrClear_0[1];
555 pseudo_bit_t IBCBusFromSPCParityErrClear_0[1];
556 pseudo_bit_t IBCBusToSPCparityErrClear_1[1];
557 pseudo_bit_t IBCBusFromSPCParityErrClear_1[1];
558 pseudo_bit_t _unused_1[11];
559 pseudo_bit_t SDmaMemReadErrClear_0[1];
560 pseudo_bit_t SDmaMemReadErrClear_1[1];
561 pseudo_bit_t PciePoisonedTLPClear[1];
562 pseudo_bit_t PcieCplTimeoutClear[1];
563 pseudo_bit_t PCIeBusParityClear[3];
564 pseudo_bit_t pcie_phy_txParityErr[1];
565 pseudo_bit_t _unused_2[13];
566 pseudo_bit_t MemoryErrClear[1];
567 pseudo_bit_t _unused_3[4];
568 pseudo_bit_t TempsenseTholdReachedClear[1];
569 pseudo_bit_t PowerOnBISTFailedClear[1];
570 pseudo_bit_t PCIESerdesPClkNotDetectClear[1];
571 pseudo_bit_t _unused_4[6];
572 pseudo_bit_t IBSerdesPClkNotDetectClear_0[1];
573 pseudo_bit_t IBSerdesPClkNotDetectClear_1[1];
575 struct QIB_7322_HwErrClear {
576 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrClear_pb );
578 /* Default value: 0x0000000000000000 */
580 #define QIB_7322_HwDiagCtrl_offset 0x000000b0UL
581 struct QIB_7322_HwDiagCtrl_pb {
582 pseudo_bit_t _unused_0[12];
583 pseudo_bit_t ForcestatusValidNoEop_0[1];
584 pseudo_bit_t ForceIBCBusFromSPCParityErr_0[1];
585 pseudo_bit_t ForcestatusValidNoEop_1[1];
586 pseudo_bit_t ForceIBCBusFromSPCParityErr_1[1];
587 pseudo_bit_t _unused_1[15];
588 pseudo_bit_t forcePCIeBusParity[4];
589 pseudo_bit_t _unused_2[25];
590 pseudo_bit_t CounterDisable[1];
591 pseudo_bit_t CounterWrEnable[1];
592 pseudo_bit_t _unused_3[1];
593 pseudo_bit_t Diagnostic[1];
595 struct QIB_7322_HwDiagCtrl {
596 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwDiagCtrl_pb );
598 /* Default value: 0x0000000000000000 */
600 #define QIB_7322_EXTStatus_offset 0x000000c0UL
601 struct QIB_7322_EXTStatus_pb {
602 pseudo_bit_t _unused_0[14];
603 pseudo_bit_t MemBISTEndTest[1];
604 pseudo_bit_t MemBISTDisabled[1];
605 pseudo_bit_t _unused_1[32];
606 pseudo_bit_t GPIOIn[16];
608 struct QIB_7322_EXTStatus {
609 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTStatus_pb );
611 /* Default value: 0x000000000000X000 */
613 #define QIB_7322_EXTCtrl_offset 0x000000c8UL
614 struct QIB_7322_EXTCtrl_pb {
615 pseudo_bit_t LEDPort0YellowOn[1];
616 pseudo_bit_t LEDPort0GreenOn[1];
617 pseudo_bit_t LEDPort1YellowOn[1];
618 pseudo_bit_t LEDPort1GreenOn[1];
619 pseudo_bit_t _unused_0[28];
620 pseudo_bit_t GPIOInvert[16];
621 pseudo_bit_t GPIOOe[16];
623 struct QIB_7322_EXTCtrl {
624 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTCtrl_pb );
626 /* Default value: 0x0000000000000000 */
628 #define QIB_7322_GPIODebugSelReg_offset 0x000000d8UL
629 struct QIB_7322_GPIODebugSelReg_pb {
630 pseudo_bit_t GPIOSourceSelDebug[16];
631 pseudo_bit_t SelPulse[16];
632 pseudo_bit_t _unused_0[32];
634 struct QIB_7322_GPIODebugSelReg {
635 PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIODebugSelReg_pb );
637 /* Default value: 0x0000000000000000 */
639 #define QIB_7322_GPIOOut_offset 0x000000e0UL
640 /* Default value: 0x0000000000000000 */
642 #define QIB_7322_GPIOMask_offset 0x000000e8UL
643 /* Default value: 0x0000000000000000 */
645 #define QIB_7322_GPIOStatus_offset 0x000000f0UL
646 /* Default value: 0x0000000000000000 */
648 #define QIB_7322_GPIOClear_offset 0x000000f8UL
649 /* Default value: 0x0000000000000000 */
651 #define QIB_7322_RcvCtrl_offset 0x00000100UL
652 struct QIB_7322_RcvCtrl_pb {
653 pseudo_bit_t dontDropRHQFull[18];
654 pseudo_bit_t _unused_0[2];
655 pseudo_bit_t IntrAvail[18];
656 pseudo_bit_t _unused_1[3];
657 pseudo_bit_t ContextCfg[2];
658 pseudo_bit_t TidFlowEnable[1];
659 pseudo_bit_t XrcTypeCode[3];
660 pseudo_bit_t TailUpd[1];
661 pseudo_bit_t TidReDirect[16];
663 struct QIB_7322_RcvCtrl {
664 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_pb );
666 /* Default value: 0x0000000000000000 */
668 #define QIB_7322_RcvHdrSize_offset 0x00000110UL
669 /* Default value: 0x0000000000000000 */
671 #define QIB_7322_RcvHdrCnt_offset 0x00000118UL
672 /* Default value: 0x0000000000000000 */
674 #define QIB_7322_RcvHdrEntSize_offset 0x00000120UL
675 /* Default value: 0x0000000000000000 */
677 #define QIB_7322_RcvTIDBase_offset 0x00000128UL
678 /* Default value: 0x0000000000050000 */
680 #define QIB_7322_RcvTIDCnt_offset 0x00000130UL
681 /* Default value: 0x0000000000000200 */
683 #define QIB_7322_RcvEgrBase_offset 0x00000138UL
684 /* Default value: 0x0000000000014000 */
686 #define QIB_7322_RcvEgrCnt_offset 0x00000140UL
687 /* Default value: 0x0000000000001000 */
689 #define QIB_7322_RcvBufBase_offset 0x00000148UL
690 /* Default value: 0x0000000000080000 */
692 #define QIB_7322_RcvBufSize_offset 0x00000150UL
693 /* Default value: 0x0000000000005000 */
695 #define QIB_7322_RxIntMemBase_offset 0x00000158UL
696 /* Default value: 0x0000000000077000 */
698 #define QIB_7322_RxIntMemSize_offset 0x00000160UL
699 /* Default value: 0x0000000000007000 */
701 #define QIB_7322_encryption_key_low_offset 0x00000180UL
702 /* Default value: 0x0000000000000000 */
704 #define QIB_7322_encryption_key_high_offset 0x00000188UL
705 /* Default value: 0x0000000000000000 */
707 #define QIB_7322_feature_mask_offset 0x00000190UL
708 /* Default value: 0x00000000000000XX */
710 #define QIB_7322_active_feature_mask_offset 0x00000198UL
711 struct QIB_7322_active_feature_mask_pb {
712 pseudo_bit_t Port0_SDR_Enabled[1];
713 pseudo_bit_t Port0_DDR_Enabled[1];
714 pseudo_bit_t Port0_QDR_Enabled[1];
715 pseudo_bit_t Port1_SDR_Enabled[1];
716 pseudo_bit_t Port1_DDR_Enabled[1];
717 pseudo_bit_t Port1_QDR_Enabled[1];
718 pseudo_bit_t _unused_0[58];
720 struct QIB_7322_active_feature_mask {
721 PSEUDO_BIT_STRUCT ( struct QIB_7322_active_feature_mask_pb );
723 /* Default value: 0x00000000000000XX */
725 #define QIB_7322_SendCtrl_offset 0x000001c0UL
726 struct QIB_7322_SendCtrl_pb {
727 pseudo_bit_t _unused_0[1];
728 pseudo_bit_t SendIntBufAvail[1];
729 pseudo_bit_t SendBufAvailUpd[1];
730 pseudo_bit_t _unused_1[1];
731 pseudo_bit_t SpecialTriggerEn[1];
732 pseudo_bit_t _unused_2[11];
733 pseudo_bit_t DisarmSendBuf[8];
734 pseudo_bit_t AvailUpdThld[5];
735 pseudo_bit_t SendBufAvailPad64Byte[1];
736 pseudo_bit_t _unused_3[1];
737 pseudo_bit_t Disarm[1];
738 pseudo_bit_t _unused_4[32];
740 struct QIB_7322_SendCtrl {
741 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_pb );
743 /* Default value: 0x0000000000000000 */
745 #define QIB_7322_SendBufBase_offset 0x000001c8UL
746 struct QIB_7322_SendBufBase_pb {
747 pseudo_bit_t BaseAddr_SmallPIO[21];
748 pseudo_bit_t _unused_0[11];
749 pseudo_bit_t BaseAddr_LargePIO[21];
750 pseudo_bit_t _unused_1[11];
752 struct QIB_7322_SendBufBase {
753 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufBase_pb );
755 /* Default value: 0x0018000000100000 */
757 #define QIB_7322_SendBufSize_offset 0x000001d0UL
758 struct QIB_7322_SendBufSize_pb {
759 pseudo_bit_t Size_SmallPIO[12];
760 pseudo_bit_t _unused_0[20];
761 pseudo_bit_t Size_LargePIO[13];
762 pseudo_bit_t _unused_1[19];
764 struct QIB_7322_SendBufSize {
765 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufSize_pb );
767 /* Default value: 0x0000108000000880 */
769 #define QIB_7322_SendBufCnt_offset 0x000001d8UL
770 struct QIB_7322_SendBufCnt_pb {
771 pseudo_bit_t Num_SmallBuffers[9];
772 pseudo_bit_t _unused_0[23];
773 pseudo_bit_t Num_LargeBuffers[6];
774 pseudo_bit_t _unused_1[26];
776 struct QIB_7322_SendBufCnt {
777 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufCnt_pb );
779 /* Default value: 0x0000002000000080 */
781 #define QIB_7322_SendBufAvailAddr_offset 0x000001e0UL
782 struct QIB_7322_SendBufAvailAddr_pb {
783 pseudo_bit_t _unused_0[6];
784 pseudo_bit_t SendBufAvailAddr[34];
785 pseudo_bit_t _unused_1[24];
787 struct QIB_7322_SendBufAvailAddr {
788 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvailAddr_pb );
790 /* Default value: 0x0000000000000000 */
792 #define QIB_7322_TxIntMemBase_offset 0x000001e8UL
793 /* Default value: 0x0000000000064000 */
795 #define QIB_7322_TxIntMemSize_offset 0x000001f0UL
796 /* Default value: 0x000000000000C000 */
798 #define QIB_7322_SendBufErr0_offset 0x00000240UL
799 struct QIB_7322_SendBufErr0_pb {
800 pseudo_bit_t SendBufErr_63_0[64];
802 struct QIB_7322_SendBufErr0 {
803 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufErr0_pb );
805 /* Default value: 0x0000000000000000 */
807 #define QIB_7322_AvailUpdCount_offset 0x00000268UL
808 struct QIB_7322_AvailUpdCount_pb {
809 pseudo_bit_t AvailUpdCount[5];
810 pseudo_bit_t _unused_0[59];
812 struct QIB_7322_AvailUpdCount {
813 PSEUDO_BIT_STRUCT ( struct QIB_7322_AvailUpdCount_pb );
815 /* Default value: 0x0000000000000000 */
817 #define QIB_7322_RcvHdrAddr0_offset 0x00000280UL
818 struct QIB_7322_RcvHdrAddr0_pb {
819 pseudo_bit_t _unused_0[2];
820 pseudo_bit_t RcvHdrAddr[38];
821 pseudo_bit_t _unused_1[24];
823 struct QIB_7322_RcvHdrAddr0 {
824 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrAddr0_pb );
826 /* Default value: 0x0000000000000000 */
828 #define QIB_7322_RcvHdrTailAddr0_offset 0x00000340UL
829 struct QIB_7322_RcvHdrTailAddr0_pb {
830 pseudo_bit_t _unused_0[2];
831 pseudo_bit_t RcvHdrTailAddr[38];
832 pseudo_bit_t _unused_1[24];
834 struct QIB_7322_RcvHdrTailAddr0 {
835 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrTailAddr0_pb );
837 /* Default value: 0x0000000000000000 */
839 #define QIB_7322_EEPCtlStat_offset 0x000003e8UL
840 struct QIB_7322_EEPCtlStat_pb {
841 pseudo_bit_t EPAccEn[2];
842 pseudo_bit_t EPReset[1];
843 pseudo_bit_t ByteProg[1];
844 pseudo_bit_t PageMode[1];
845 pseudo_bit_t LstDatWr[1];
846 pseudo_bit_t CmdWrErr[1];
847 pseudo_bit_t _unused_0[24];
848 pseudo_bit_t CtlrStat[1];
849 pseudo_bit_t _unused_1[32];
851 struct QIB_7322_EEPCtlStat {
852 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPCtlStat_pb );
854 /* Default value: 0x0000000000000002 */
856 #define QIB_7322_EEPAddrCmd_offset 0x000003f0UL
857 struct QIB_7322_EEPAddrCmd_pb {
858 pseudo_bit_t EPAddr[24];
859 pseudo_bit_t EPCmd[8];
860 pseudo_bit_t _unused_0[32];
862 struct QIB_7322_EEPAddrCmd {
863 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPAddrCmd_pb );
865 /* Default value: 0x0000000000000000 */
867 #define QIB_7322_EEPData_offset 0x000003f8UL
868 /* Default value: 0x0000000000000000 */
870 #define QIB_7322_efuse_control_reg_offset 0x00000410UL
871 struct QIB_7322_efuse_control_reg_pb {
872 pseudo_bit_t address[11];
873 pseudo_bit_t last_program_address[11];
874 pseudo_bit_t operation[2];
875 pseudo_bit_t start_operation[1];
876 pseudo_bit_t _unused_0[4];
877 pseudo_bit_t req_err[1];
878 pseudo_bit_t read_data_valid[1];
880 pseudo_bit_t _unused_1[32];
882 struct QIB_7322_efuse_control_reg {
883 PSEUDO_BIT_STRUCT ( struct QIB_7322_efuse_control_reg_pb );
885 /* Default value: 0x0000000080000000 */
887 #define QIB_7322_efuse_data_reg_offset 0x00000418UL
888 /* Default value: 0x0000000000000000 */
890 #define QIB_7322_voltage_margin_reg_offset 0x00000428UL
891 struct QIB_7322_voltage_margin_reg_pb {
892 pseudo_bit_t voltage_margin_settings_enable[1];
893 pseudo_bit_t voltage_margin_settings[2];
894 pseudo_bit_t _unused_0[61];
896 struct QIB_7322_voltage_margin_reg {
897 PSEUDO_BIT_STRUCT ( struct QIB_7322_voltage_margin_reg_pb );
899 /* Default value: 0x0000000000000000 */
901 #define QIB_7322_VTSense_reg_offset 0x00000430UL
902 struct QIB_7322_VTSense_reg_pb {
903 pseudo_bit_t temp_sense_select[3];
904 pseudo_bit_t adc_mode[1];
905 pseudo_bit_t start_busy[1];
906 pseudo_bit_t power_down[1];
907 pseudo_bit_t threshold[10];
908 pseudo_bit_t sensor_output_data[10];
909 pseudo_bit_t _unused_0[1];
910 pseudo_bit_t threshold_limbit[1];
911 pseudo_bit_t _unused_1[3];
912 pseudo_bit_t output_valid[1];
913 pseudo_bit_t _unused_2[32];
915 struct QIB_7322_VTSense_reg {
916 PSEUDO_BIT_STRUCT ( struct QIB_7322_VTSense_reg_pb );
918 /* Default value: 0x0000000000000020 */
920 #define QIB_7322_procmon_reg_offset 0x00000438UL
921 struct QIB_7322_procmon_reg_pb {
922 pseudo_bit_t ring_osc_select[3];
923 pseudo_bit_t _unused_0[12];
924 pseudo_bit_t start_counter[1];
925 pseudo_bit_t procmon_count[12];
926 pseudo_bit_t _unused_1[3];
927 pseudo_bit_t procmon_count_valid[1];
928 pseudo_bit_t _unused_2[32];
930 struct QIB_7322_procmon_reg {
931 PSEUDO_BIT_STRUCT ( struct QIB_7322_procmon_reg_pb );
933 /* Default value: 0x0000000000000000 */
935 #define QIB_7322_PcieRbufTestReg0_offset 0x00000440UL
936 /* Default value: 0x0000000000000000 */
938 #define QIB_7322_ahb_access_ctrl_offset 0x00000460UL
939 struct QIB_7322_ahb_access_ctrl_pb {
940 pseudo_bit_t sw_ahb_sel[1];
941 pseudo_bit_t sw_sel_ahb_trgt[2];
942 pseudo_bit_t _unused_0[61];
944 struct QIB_7322_ahb_access_ctrl {
945 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_access_ctrl_pb );
947 /* Default value: 0x0000000000000000 */
949 #define QIB_7322_ahb_transaction_reg_offset 0x00000468UL
950 struct QIB_7322_ahb_transaction_reg_pb {
951 pseudo_bit_t _unused_0[16];
952 pseudo_bit_t ahb_address[11];
953 pseudo_bit_t write_not_read[1];
954 pseudo_bit_t _unused_1[2];
955 pseudo_bit_t ahb_req_err[1];
956 pseudo_bit_t ahb_rdy[1];
957 pseudo_bit_t ahb_data[32];
959 struct QIB_7322_ahb_transaction_reg {
960 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_transaction_reg_pb );
962 /* Default value: 0x0000000080000000 */
964 #define QIB_7322_SPC_JTAG_ACCESS_REG_offset 0x00000470UL
965 struct QIB_7322_SPC_JTAG_ACCESS_REG_pb {
969 pseudo_bit_t opcode[2];
970 pseudo_bit_t bist_en[5];
971 pseudo_bit_t SPC_JTAG_ACCESS_EN[1];
972 pseudo_bit_t _unused_0[53];
974 struct QIB_7322_SPC_JTAG_ACCESS_REG {
975 PSEUDO_BIT_STRUCT ( struct QIB_7322_SPC_JTAG_ACCESS_REG_pb );
977 /* Default value: 0x0000000000000001 */
979 #define QIB_7322_LAControlReg_offset 0x00000478UL
980 struct QIB_7322_LAControlReg_pb {
981 pseudo_bit_t Finished[1];
982 pseudo_bit_t Address[9];
983 pseudo_bit_t Mode[2];
984 pseudo_bit_t Delay[20];
985 pseudo_bit_t Finished_sc[1];
986 pseudo_bit_t Address_sc[9];
987 pseudo_bit_t Mode_sc[2];
988 pseudo_bit_t Delay_sc[20];
990 struct QIB_7322_LAControlReg {
991 PSEUDO_BIT_STRUCT ( struct QIB_7322_LAControlReg_pb );
993 /* Default value: 0x0000000100000001 */
995 #define QIB_7322_PcieRhdrTestReg0_offset 0x00000480UL
996 /* Default value: 0x0000000000000000 */
998 #define QIB_7322_SendCheckMask0_offset 0x000004c0UL
999 struct QIB_7322_SendCheckMask0_pb {
1000 pseudo_bit_t SendCheckMask_63_32[64];
1002 struct QIB_7322_SendCheckMask0 {
1003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckMask0_pb );
1005 /* Default value: 0x0000000000000000 */
1007 #define QIB_7322_SendGRHCheckMask0_offset 0x000004e0UL
1008 struct QIB_7322_SendGRHCheckMask0_pb {
1009 pseudo_bit_t SendGRHCheckMask_63_32[64];
1011 struct QIB_7322_SendGRHCheckMask0 {
1012 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendGRHCheckMask0_pb );
1014 /* Default value: 0x0000000000000000 */
1016 #define QIB_7322_SendIBPacketMask0_offset 0x00000500UL
1017 struct QIB_7322_SendIBPacketMask0_pb {
1018 pseudo_bit_t SendIBPacketMask_63_32[64];
1020 struct QIB_7322_SendIBPacketMask0 {
1021 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBPacketMask0_pb );
1023 /* Default value: 0x0000000000000000 */
1025 #define QIB_7322_IntRedirect0_offset 0x00000540UL
1026 struct QIB_7322_IntRedirect0_pb {
1027 pseudo_bit_t vec0[5];
1028 pseudo_bit_t vec1[5];
1029 pseudo_bit_t vec2[5];
1030 pseudo_bit_t vec3[5];
1031 pseudo_bit_t vec4[5];
1032 pseudo_bit_t vec5[5];
1033 pseudo_bit_t vec6[5];
1034 pseudo_bit_t vec7[5];
1035 pseudo_bit_t vec8[5];
1036 pseudo_bit_t vec9[5];
1037 pseudo_bit_t vec10[5];
1038 pseudo_bit_t vec11[5];
1039 pseudo_bit_t _unused_0[4];
1041 struct QIB_7322_IntRedirect0 {
1042 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntRedirect0_pb );
1044 /* Default value: 0x0000000000000000 */
1046 #define QIB_7322_Int_Granted_offset 0x00000570UL
1047 /* Default value: 0x0000000000000000 */
1049 #define QIB_7322_vec_clr_without_int_offset 0x00000578UL
1050 /* Default value: 0x0000000000000000 */
1052 #define QIB_7322_DCACtrlA_offset 0x00000580UL
1053 struct QIB_7322_DCACtrlA_pb {
1054 pseudo_bit_t RcvHdrqDCAEnable[1];
1055 pseudo_bit_t EagerDCAEnable[1];
1056 pseudo_bit_t RcvTailUpdDCAEnable[1];
1057 pseudo_bit_t SendDMAHead0DCAEnable[1];
1058 pseudo_bit_t SendDMAHead1DCAEnable[1];
1059 pseudo_bit_t _unused_0[59];
1061 struct QIB_7322_DCACtrlA {
1062 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlA_pb );
1064 /* Default value: 0x0000000000000000 */
1066 #define QIB_7322_DCACtrlB_offset 0x00000588UL
1067 struct QIB_7322_DCACtrlB_pb {
1068 pseudo_bit_t RcvHdrq0DCAOPH[8];
1069 pseudo_bit_t RcvHdrq0DCAXfrCnt[6];
1070 pseudo_bit_t RcvHdrq1DCAOPH[8];
1071 pseudo_bit_t RcvHdrq1DCAXfrCnt[6];
1072 pseudo_bit_t _unused_0[4];
1073 pseudo_bit_t RcvHdrq2DCAOPH[8];
1074 pseudo_bit_t RcvHdrq2DCAXfrCnt[6];
1075 pseudo_bit_t RcvHdrq3DCAOPH[8];
1076 pseudo_bit_t RcvHdrq3DCAXfrCnt[6];
1077 pseudo_bit_t _unused_1[4];
1079 struct QIB_7322_DCACtrlB {
1080 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlB_pb );
1082 /* Default value: 0x0000000000000000 */
1084 #define QIB_7322_DCACtrlC_offset 0x00000590UL
1085 struct QIB_7322_DCACtrlC_pb {
1086 pseudo_bit_t RcvHdrq4DCAOPH[8];
1087 pseudo_bit_t RcvHdrq4DCAXfrCnt[6];
1088 pseudo_bit_t RcvHdrq5DCAOPH[8];
1089 pseudo_bit_t RcvHdrq5DCAXfrCnt[6];
1090 pseudo_bit_t _unused_0[4];
1091 pseudo_bit_t RcvHdrq6DCAOPH[8];
1092 pseudo_bit_t RcvHdrq6DCAXfrCnt[6];
1093 pseudo_bit_t RcvHdrq7DCAOPH[8];
1094 pseudo_bit_t RcvHdrq7DCAXfrCnt[6];
1095 pseudo_bit_t _unused_1[4];
1097 struct QIB_7322_DCACtrlC {
1098 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlC_pb );
1100 /* Default value: 0x0000000000000000 */
1102 #define QIB_7322_DCACtrlD_offset 0x00000598UL
1103 struct QIB_7322_DCACtrlD_pb {
1104 pseudo_bit_t RcvHdrq8DCAOPH[8];
1105 pseudo_bit_t RcvHdrq8DCAXfrCnt[6];
1106 pseudo_bit_t RcvHdrq9DCAOPH[8];
1107 pseudo_bit_t RcvHdrq9DCAXfrCnt[6];
1108 pseudo_bit_t _unused_0[4];
1109 pseudo_bit_t RcvHdrq10DCAOPH[8];
1110 pseudo_bit_t RcvHdrq10DCAXfrCnt[6];
1111 pseudo_bit_t RcvHdrq11DCAOPH[8];
1112 pseudo_bit_t RcvHdrq11DCAXfrCnt[6];
1113 pseudo_bit_t _unused_1[4];
1115 struct QIB_7322_DCACtrlD {
1116 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlD_pb );
1118 /* Default value: 0x0000000000000000 */
1120 #define QIB_7322_DCACtrlE_offset 0x000005a0UL
1121 struct QIB_7322_DCACtrlE_pb {
1122 pseudo_bit_t RcvHdrq12DCAOPH[8];
1123 pseudo_bit_t RcvHdrq12DCAXfrCnt[6];
1124 pseudo_bit_t RcvHdrq13DCAOPH[8];
1125 pseudo_bit_t RcvHdrq13DCAXfrCnt[6];
1126 pseudo_bit_t _unused_0[4];
1127 pseudo_bit_t RcvHdrq14DCAOPH[8];
1128 pseudo_bit_t RcvHdrq14DCAXfrCnt[6];
1129 pseudo_bit_t RcvHdrq15DCAOPH[8];
1130 pseudo_bit_t RcvHdrq15DCAXfrCnt[6];
1131 pseudo_bit_t _unused_1[4];
1133 struct QIB_7322_DCACtrlE {
1134 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlE_pb );
1136 /* Default value: 0x0000000000000000 */
1138 #define QIB_7322_DCACtrlF_offset 0x000005a8UL
1139 struct QIB_7322_DCACtrlF_pb {
1140 pseudo_bit_t RcvHdrq16DCAOPH[8];
1141 pseudo_bit_t RcvHdrq16DCAXfrCnt[6];
1142 pseudo_bit_t RcvHdrq17DCAOPH[8];
1143 pseudo_bit_t RcvHdrq17DCAXfrCnt[6];
1144 pseudo_bit_t _unused_0[4];
1145 pseudo_bit_t SendDma0DCAOPH[8];
1146 pseudo_bit_t SendDma1DCAOPH[8];
1147 pseudo_bit_t _unused_1[16];
1149 struct QIB_7322_DCACtrlF {
1150 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlF_pb );
1152 /* Default value: 0x0000000000000000 */
1154 #define QIB_7322_MemErrCtrlA_offset 0x00000600UL
1155 struct QIB_7322_MemErrCtrlA_pb {
1156 pseudo_bit_t FSSUncErrRcvBuf_0[1];
1157 pseudo_bit_t FSSUncErrRcvFlags_0[1];
1158 pseudo_bit_t FSSUncErrLookupiqBuf_0[1];
1159 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_0[1];
1160 pseudo_bit_t FSSUncErrRcvDMADataBuf_0[1];
1161 pseudo_bit_t FSSUncErrRcvBuf_1[1];
1162 pseudo_bit_t FSSUncErrRcvFlags_1[1];
1163 pseudo_bit_t FSSUncErrLookupiqBuf_1[1];
1164 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_1[1];
1165 pseudo_bit_t FSSUncErrRcvDMADataBuf_1[1];
1166 pseudo_bit_t FSSUncErrRcvTIDArray[1];
1167 pseudo_bit_t FSSUncErrRcvEgrArray[1];
1168 pseudo_bit_t _unused_0[3];
1169 pseudo_bit_t FSSUncErrSendBufVL15[1];
1170 pseudo_bit_t FSSUncErrSendBufMain[1];
1171 pseudo_bit_t FSSUncErrSendBufExtra[1];
1172 pseudo_bit_t FSSUncErrSendPbcArray[1];
1173 pseudo_bit_t FSSUncErrSendLaFIFO0_0[1];
1174 pseudo_bit_t FSSUncErrSendLaFIFO1_0[1];
1175 pseudo_bit_t FSSUncErrSendLaFIFO2_0[1];
1176 pseudo_bit_t FSSUncErrSendLaFIFO3_0[1];
1177 pseudo_bit_t FSSUncErrSendLaFIFO4_0[1];
1178 pseudo_bit_t FSSUncErrSendLaFIFO5_0[1];
1179 pseudo_bit_t FSSUncErrSendLaFIFO6_0[1];
1180 pseudo_bit_t FSSUncErrSendLaFIFO7_0[1];
1181 pseudo_bit_t FSSUncErrSendLaFIFO0_1[1];
1182 pseudo_bit_t FSSUncErrSendLaFIFO1_1[1];
1183 pseudo_bit_t FSSUncErrSendLaFIFO2_1[1];
1184 pseudo_bit_t FSSUncErrSendLaFIFO3_1[1];
1185 pseudo_bit_t FSSUncErrSendLaFIFO4_1[1];
1186 pseudo_bit_t FSSUncErrSendLaFIFO5_1[1];
1187 pseudo_bit_t FSSUncErrSendLaFIFO6_1[1];
1188 pseudo_bit_t FSSUncErrSendLaFIFO7_1[1];
1189 pseudo_bit_t FSSUncErrSendRmFIFO_0[1];
1190 pseudo_bit_t FSSUncErrSendRmFIFO_1[1];
1191 pseudo_bit_t _unused_1[11];
1192 pseudo_bit_t FSSUncErrPCIeRetryBuf[1];
1193 pseudo_bit_t FSSUncErrPCIePostHdrBuf[1];
1194 pseudo_bit_t FSSUncErrPCIePostDataBuf[1];
1195 pseudo_bit_t FSSUncErrPCIeCompHdrBuf[1];
1196 pseudo_bit_t FSSUncErrPCIeCompDataBuf[1];
1197 pseudo_bit_t FSSUncErrMsixTable0[1];
1198 pseudo_bit_t FSSUncErrMsixTable1[1];
1199 pseudo_bit_t FSSUncErrMsixTable2[1];
1200 pseudo_bit_t _unused_2[4];
1201 pseudo_bit_t SwapEccDataMsixBits[1];
1202 pseudo_bit_t SwapEccDataExtraBits[1];
1203 pseudo_bit_t DisableEccCorrection[1];
1204 pseudo_bit_t SwapEccDataBits[1];
1206 struct QIB_7322_MemErrCtrlA {
1207 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlA_pb );
1209 /* Default value: 0x0000000000000000 */
1211 #define QIB_7322_MemErrCtrlB_offset 0x00000608UL
1212 struct QIB_7322_MemErrCtrlB_pb {
1213 pseudo_bit_t FSSCorErrRcvBuf_0[1];
1214 pseudo_bit_t FSSCorErrRcvFlags_0[1];
1215 pseudo_bit_t FSSCorErrLookupiqBuf_0[1];
1216 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_0[1];
1217 pseudo_bit_t FSSCorErrRcvDMADataBuf_0[1];
1218 pseudo_bit_t FSSCorErrRcvBuf_1[1];
1219 pseudo_bit_t FSSCorErrRcvFlags_1[1];
1220 pseudo_bit_t FSSCorErrLookupiqBuf_1[1];
1221 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_1[1];
1222 pseudo_bit_t FSSCorErrRcvDMADataBuf_1[1];
1223 pseudo_bit_t FSSCorErrRcvTIDArray[1];
1224 pseudo_bit_t FSSCorErrRcvEgrArray[1];
1225 pseudo_bit_t _unused_0[3];
1226 pseudo_bit_t FSSCorErrSendBufVL15[1];
1227 pseudo_bit_t FSSCorErrSendBufMain[1];
1228 pseudo_bit_t FSSCorErrSendBufExtra[1];
1229 pseudo_bit_t FSSCorErrSendPbcArray[1];
1230 pseudo_bit_t FSSCorErrSendLaFIFO0_0[1];
1231 pseudo_bit_t FSSCorErrSendLaFIFO1_0[1];
1232 pseudo_bit_t FSSCorErrSendLaFIFO2_0[1];
1233 pseudo_bit_t FSSCorErrSendLaFIFO3_0[1];
1234 pseudo_bit_t FSSCorErrSendLaFIFO4_0[1];
1235 pseudo_bit_t FSSCorErrSendLaFIFO5_0[1];
1236 pseudo_bit_t FSSCorErrSendLaFIFO6_0[1];
1237 pseudo_bit_t FSSCorErrSendLaFIFO7_0[1];
1238 pseudo_bit_t FSSCorErrSendLaFIFO0_1[1];
1239 pseudo_bit_t FSSCorErrSendLaFIFO1_1[1];
1240 pseudo_bit_t FSSCorErrSendLaFIFO2_1[1];
1241 pseudo_bit_t FSSCorErrSendLaFIFO3_1[1];
1242 pseudo_bit_t FSSCorErrSendLaFIFO4_1[1];
1243 pseudo_bit_t FSSCorErrSendLaFIFO5_1[1];
1244 pseudo_bit_t FSSCorErrSendLaFIFO6_1[1];
1245 pseudo_bit_t FSSCorErrSendLaFIFO7_1[1];
1246 pseudo_bit_t FSSCorErrSendRmFIFO_0[1];
1247 pseudo_bit_t FSSCorErrSendRmFIFO_1[1];
1248 pseudo_bit_t _unused_1[11];
1249 pseudo_bit_t FSSCorErrPCIeRetryBuf[1];
1250 pseudo_bit_t FSSCorErrPCIePostHdrBuf[1];
1251 pseudo_bit_t FSSCorErrPCIePostDataBuf[1];
1252 pseudo_bit_t FSSCorErrPCIeCompHdrBuf[1];
1253 pseudo_bit_t FSSCorErrPCIeCompDataBuf[1];
1254 pseudo_bit_t FSSCorErrMsixTable0[1];
1255 pseudo_bit_t FSSCorErrMsixTable1[1];
1256 pseudo_bit_t FSSCorErrMsixTable2[1];
1257 pseudo_bit_t _unused_2[8];
1259 struct QIB_7322_MemErrCtrlB {
1260 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlB_pb );
1262 /* Default value: 0x0000000000000000 */
1264 #define QIB_7322_MemMultiUnCorErrMask_offset 0x00000610UL
1265 struct QIB_7322_MemMultiUnCorErrMask_pb {
1266 pseudo_bit_t MulUncErrMskRcvBuf_0[1];
1267 pseudo_bit_t MulUncErrMskRcvFlags_0[1];
1268 pseudo_bit_t MulUncErrMskLookupiqBuf_0[1];
1269 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_0[1];
1270 pseudo_bit_t MulUncErrMskRcvDMADataBuf_0[1];
1271 pseudo_bit_t MulUncErrMskRcvBuf_1[1];
1272 pseudo_bit_t MulUncErrMskRcvFlags_1[1];
1273 pseudo_bit_t MulUncErrMskLookupiqBuf_1[1];
1274 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_1[1];
1275 pseudo_bit_t MulUncErrMskRcvDMADataBuf_1[1];
1276 pseudo_bit_t MulUncErrMskRcvTIDArray[1];
1277 pseudo_bit_t MulUncErrMskRcvEgrArray[1];
1278 pseudo_bit_t _unused_0[3];
1279 pseudo_bit_t MulUncErrMskSendBufVL15[1];
1280 pseudo_bit_t MulUncErrMskSendBufMain[1];
1281 pseudo_bit_t MulUncErrMskSendBufExtra[1];
1282 pseudo_bit_t MulUncErrMskSendPbcArray[1];
1283 pseudo_bit_t MulUncErrMskSendLaFIFO0_0[1];
1284 pseudo_bit_t MulUncErrMskSendLaFIFO1_0[1];
1285 pseudo_bit_t MulUncErrMskSendLaFIFO2_0[1];
1286 pseudo_bit_t MulUncErrMskSendLaFIFO3_0[1];
1287 pseudo_bit_t MulUncErrMskSendLaFIFO4_0[1];
1288 pseudo_bit_t MulUncErrMskSendLaFIFO5_0[1];
1289 pseudo_bit_t MulUncErrMskSendLaFIFO6_0[1];
1290 pseudo_bit_t MulUncErrMskSendLaFIFO7_0[1];
1291 pseudo_bit_t MulUncErrMskSendLaFIFO0_1[1];
1292 pseudo_bit_t MulUncErrMskSendLaFIFO1_1[1];
1293 pseudo_bit_t MulUncErrMskSendLaFIFO2_1[1];
1294 pseudo_bit_t MulUncErrMskSendLaFIFO3_1[1];
1295 pseudo_bit_t MulUncErrMskSendLaFIFO4_1[1];
1296 pseudo_bit_t MulUncErrMskSendLaFIFO5_1[1];
1297 pseudo_bit_t MulUncErrMskSendLaFIFO6_1[1];
1298 pseudo_bit_t MulUncErrMskSendLaFIFO7_1[1];
1299 pseudo_bit_t MulUncErrMskSendRmFIFO_0[1];
1300 pseudo_bit_t MulUncErrMskSendRmFIFO_1[1];
1301 pseudo_bit_t _unused_1[11];
1302 pseudo_bit_t MulUncErrMskPCIeRetryBuf[1];
1303 pseudo_bit_t MulUncErrMskPCIePostHdrBuf[1];
1304 pseudo_bit_t MulUncErrMskPCIePostDataBuf[1];
1305 pseudo_bit_t MulUncErrMskPCIeCompHdrBuf[1];
1306 pseudo_bit_t MulUncErrMskPCIeCompDataBuf[1];
1307 pseudo_bit_t MulUncErrMskMsixTable0[1];
1308 pseudo_bit_t MulUncErrMskMsixTable1[1];
1309 pseudo_bit_t MulUncErrMskMsixTable2[1];
1310 pseudo_bit_t _unused_2[8];
1312 struct QIB_7322_MemMultiUnCorErrMask {
1313 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrMask_pb );
1315 /* Default value: 0x0000000000000000 */
1317 #define QIB_7322_MemMultiUnCorErrStatus_offset 0x00000618UL
1318 struct QIB_7322_MemMultiUnCorErrStatus_pb {
1319 pseudo_bit_t MulUncErrStatusRcvBuf_0[1];
1320 pseudo_bit_t MulUncErrStatusRcvFlags_0[1];
1321 pseudo_bit_t MulUncErrStatusLookupiqBuf_0[1];
1322 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_0[1];
1323 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_0[1];
1324 pseudo_bit_t MulUncErrStatusRcvBuf_1[1];
1325 pseudo_bit_t MulUncErrStatusRcvFlags_1[1];
1326 pseudo_bit_t MulUncErrStatusLookupiqBuf_1[1];
1327 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_1[1];
1328 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_1[1];
1329 pseudo_bit_t MulUncErrStatusRcvTIDArray[1];
1330 pseudo_bit_t MulUncErrStatusRcvEgrArray[1];
1331 pseudo_bit_t _unused_0[3];
1332 pseudo_bit_t MulUncErrStatusSendBufVL15[1];
1333 pseudo_bit_t MulUncErrStatusSendBufMain[1];
1334 pseudo_bit_t MulUncErrStatusSendBufExtra[1];
1335 pseudo_bit_t MulUncErrStatusSendPbcArray[1];
1336 pseudo_bit_t MulUncErrStatusSendLaFIFO0_0[1];
1337 pseudo_bit_t MulUncErrStatusSendLaFIFO1_0[1];
1338 pseudo_bit_t MulUncErrStatusSendLaFIFO2_0[1];
1339 pseudo_bit_t MulUncErrStatusSendLaFIFO3_0[1];
1340 pseudo_bit_t MulUncErrStatusSendLaFIFO4_0[1];
1341 pseudo_bit_t MulUncErrStatusSendLaFIFO5_0[1];
1342 pseudo_bit_t MulUncErrStatusSendLaFIFO6_0[1];
1343 pseudo_bit_t MulUncErrStatusSendLaFIFO7_0[1];
1344 pseudo_bit_t MulUncErrStatusSendLaFIFO0_1[1];
1345 pseudo_bit_t MulUncErrStatusSendLaFIFO1_1[1];
1346 pseudo_bit_t MulUncErrStatusSendLaFIFO2_1[1];
1347 pseudo_bit_t MulUncErrStatusSendLaFIFO3_1[1];
1348 pseudo_bit_t MulUncErrStatusSendLaFIFO4_1[1];
1349 pseudo_bit_t MulUncErrStatusSendLaFIFO5_1[1];
1350 pseudo_bit_t MulUncErrStatusSendLaFIFO6_1[1];
1351 pseudo_bit_t MulUncErrStatusSendLaFIFO7_1[1];
1352 pseudo_bit_t MulUncErrStatusSendRmFIFO_0[1];
1353 pseudo_bit_t MulUncErrStatusSendRmFIFO_1[1];
1354 pseudo_bit_t _unused_1[11];
1355 pseudo_bit_t MulUncErrStatusPCIeRetryBuf[1];
1356 pseudo_bit_t MulUncErrStatusPCIePostHdrBuf[1];
1357 pseudo_bit_t MulUncErrStatusPCIePostDataBuf[1];
1358 pseudo_bit_t MulUncErrStatusPCIeCompHdrBuf[1];
1359 pseudo_bit_t MulUncErrStatusPCIeCompDataBuf[1];
1360 pseudo_bit_t MulUncErrStatusMsixTable0[1];
1361 pseudo_bit_t MulUncErrStatusMsixTable1[1];
1362 pseudo_bit_t MulUncErrStatusMsixTable2[1];
1363 pseudo_bit_t _unused_2[8];
1365 struct QIB_7322_MemMultiUnCorErrStatus {
1366 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrStatus_pb );
1368 /* Default value: 0x0000000000000000 */
1370 #define QIB_7322_MemMultiUnCorErrClear_offset 0x00000620UL
1371 struct QIB_7322_MemMultiUnCorErrClear_pb {
1372 pseudo_bit_t MulUncErrClearRcvBuf_0[1];
1373 pseudo_bit_t MulUncErrClearRcvFlags_0[1];
1374 pseudo_bit_t MulUncErrClearLookupiqBuf_0[1];
1375 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_0[1];
1376 pseudo_bit_t MulUncErrClearRcvDMADataBuf_0[1];
1377 pseudo_bit_t MulUncErrClearRcvBuf_1[1];
1378 pseudo_bit_t MulUncErrClearRcvFlags_1[1];
1379 pseudo_bit_t MulUncErrClearLookupiqBuf_1[1];
1380 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_1[1];
1381 pseudo_bit_t MulUncErrClearRcvDMADataBuf_1[1];
1382 pseudo_bit_t MulUncErrClearRcvTIDArray[1];
1383 pseudo_bit_t MulUncErrClearRcvEgrArray[1];
1384 pseudo_bit_t _unused_0[3];
1385 pseudo_bit_t MulUncErrClearSendBufVL15[1];
1386 pseudo_bit_t MulUncErrClearSendBufMain[1];
1387 pseudo_bit_t MulUncErrClearSendBufExtra[1];
1388 pseudo_bit_t MulUncErrClearSendPbcArray[1];
1389 pseudo_bit_t MulUncErrClearSendLaFIFO0_0[1];
1390 pseudo_bit_t MulUncErrClearSendLaFIFO1_0[1];
1391 pseudo_bit_t MulUncErrClearSendLaFIFO2_0[1];
1392 pseudo_bit_t MulUncErrClearSendLaFIFO3_0[1];
1393 pseudo_bit_t MulUncErrClearSendLaFIFO4_0[1];
1394 pseudo_bit_t MulUncErrClearSendLaFIFO5_0[1];
1395 pseudo_bit_t MulUncErrClearSendLaFIFO6_0[1];
1396 pseudo_bit_t MulUncErrClearSendLaFIFO7_0[1];
1397 pseudo_bit_t MulUncErrClearSendLaFIFO0_1[1];
1398 pseudo_bit_t MulUncErrClearSendLaFIFO1_1[1];
1399 pseudo_bit_t MulUncErrClearSendLaFIFO2_1[1];
1400 pseudo_bit_t MulUncErrClearSendLaFIFO3_1[1];
1401 pseudo_bit_t MulUncErrClearSendLaFIFO4_1[1];
1402 pseudo_bit_t MulUncErrClearSendLaFIFO5_1[1];
1403 pseudo_bit_t MulUncErrClearSendLaFIFO6_1[1];
1404 pseudo_bit_t MulUncErrClearSendLaFIFO7_1[1];
1405 pseudo_bit_t MulUncErrClearSendRmFIFO_0[1];
1406 pseudo_bit_t MulUncErrClearSendRmFIFO_1[1];
1407 pseudo_bit_t _unused_1[11];
1408 pseudo_bit_t MulUncErrClearPCIeRetryBuf[1];
1409 pseudo_bit_t MulUncErrClearPCIePostHdrBuf[1];
1410 pseudo_bit_t MulUncErrClearPCIePostDataBuf[1];
1411 pseudo_bit_t MulUncErrClearPCIeCompHdrBuf[1];
1412 pseudo_bit_t MulUncErrClearPCIeCompDataBuf[1];
1413 pseudo_bit_t MulUncErrClearMsixTable0[1];
1414 pseudo_bit_t MulUncErrClearMsixTable1[1];
1415 pseudo_bit_t MulUncErrClearMsixTable2[1];
1416 pseudo_bit_t _unused_2[8];
1418 struct QIB_7322_MemMultiUnCorErrClear {
1419 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrClear_pb );
1421 /* Default value: 0x0000000000000000 */
1423 #define QIB_7322_MemUnCorErrMask_offset 0x00000628UL
1424 struct QIB_7322_MemUnCorErrMask_pb {
1425 pseudo_bit_t UncErrMskRcvBuf_0[1];
1426 pseudo_bit_t UncErrMskRcvFlags_0[1];
1427 pseudo_bit_t UncErrMskLookupiqBuf_0[1];
1428 pseudo_bit_t UncErrMskRcvDMAHdrBuf_0[1];
1429 pseudo_bit_t UncErrMskRcvDMADataBuf_0[1];
1430 pseudo_bit_t UncErrMskRcvBuf_1[1];
1431 pseudo_bit_t UncErrMskRcvFlags_1[1];
1432 pseudo_bit_t UncErrMskLookupiqBuf_1[1];
1433 pseudo_bit_t UncErrMskRcvDMAHdrBuf_1[1];
1434 pseudo_bit_t UncErrMskRcvDMADataBuf_1[1];
1435 pseudo_bit_t UncErrMskRcvTIDArray[1];
1436 pseudo_bit_t UncErrMskRcvEgrArray[1];
1437 pseudo_bit_t _unused_0[3];
1438 pseudo_bit_t UncErrMskSendBufVL15[1];
1439 pseudo_bit_t UncErrMskSendBufMain[1];
1440 pseudo_bit_t UncErrMskSendBufExtra[1];
1441 pseudo_bit_t UncErrMskSendPbcArray[1];
1442 pseudo_bit_t UncErrMskSendLaFIFO0_0[1];
1443 pseudo_bit_t UncErrMskSendLaFIFO1_0[1];
1444 pseudo_bit_t UncErrMskSendLaFIFO2_0[1];
1445 pseudo_bit_t UncErrMskSendLaFIFO3_0[1];
1446 pseudo_bit_t UncErrMskSendLaFIFO4_0[1];
1447 pseudo_bit_t UncErrMskSendLaFIFO5_0[1];
1448 pseudo_bit_t UncErrMskSendLaFIFO6_0[1];
1449 pseudo_bit_t UncErrMskSendLaFIFO7_0[1];
1450 pseudo_bit_t UncErrMskSendLaFIFO0_1[1];
1451 pseudo_bit_t UncErrMskSendLaFIFO1_1[1];
1452 pseudo_bit_t UncErrMskSendLaFIFO2_1[1];
1453 pseudo_bit_t UncErrMskSendLaFIFO3_1[1];
1454 pseudo_bit_t UncErrMskSendLaFIFO4_1[1];
1455 pseudo_bit_t UncErrMskSendLaFIFO5_1[1];
1456 pseudo_bit_t UncErrMskSendLaFIFO6_1[1];
1457 pseudo_bit_t UncErrMskSendLaFIFO7_1[1];
1458 pseudo_bit_t UncErrMskSendRmFIFO_0[1];
1459 pseudo_bit_t UncErrMskSendRmFIFO_1[1];
1460 pseudo_bit_t _unused_1[11];
1461 pseudo_bit_t UncErrMskPCIeRetryBuf[1];
1462 pseudo_bit_t UncErrMskPCIePostHdrBuf[1];
1463 pseudo_bit_t UncErrMskPCIePostDataBuf[1];
1464 pseudo_bit_t UncErrMskPCIeCompHdrBuf[1];
1465 pseudo_bit_t UncErrMskPCIeCompDataBuf[1];
1466 pseudo_bit_t UncErrMskMsixTable0[1];
1467 pseudo_bit_t UncErrMskMsixTable1[1];
1468 pseudo_bit_t UncErrMskMsixTable2[1];
1469 pseudo_bit_t _unused_2[8];
1471 struct QIB_7322_MemUnCorErrMask {
1472 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrMask_pb );
1474 /* Default value: 0x0000000000000000 */
1476 #define QIB_7322_MemUnCorErrStatus_offset 0x00000630UL
1477 struct QIB_7322_MemUnCorErrStatus_pb {
1478 pseudo_bit_t UncErrStatusRcvBuf_0[1];
1479 pseudo_bit_t UncErrStatusRcvFlags_0[1];
1480 pseudo_bit_t UncErrStatusLookupiqBuf_0[1];
1481 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_0[1];
1482 pseudo_bit_t UncErrStatusRcvDMADataBuf_0[1];
1483 pseudo_bit_t UncErrStatusRcvBuf_1[1];
1484 pseudo_bit_t UncErrStatusRcvFlags_1[1];
1485 pseudo_bit_t UncErrStatusLookupiqBuf_1[1];
1486 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_1[1];
1487 pseudo_bit_t UncErrStatusRcvDMADataBuf_1[1];
1488 pseudo_bit_t UncErrStatusRcvTIDArray[1];
1489 pseudo_bit_t UncErrStatusRcvEgrArray[1];
1490 pseudo_bit_t _unused_0[3];
1491 pseudo_bit_t UncErrStatusSendBufVL15[1];
1492 pseudo_bit_t UncErrStatusSendBufMain[1];
1493 pseudo_bit_t UncErrStatusSendBufExtra[1];
1494 pseudo_bit_t UncErrStatusSendPbcArray[1];
1495 pseudo_bit_t UncErrStatusSendLaFIFO0_0[1];
1496 pseudo_bit_t UncErrStatusSendLaFIFO1_0[1];
1497 pseudo_bit_t UncErrStatusSendLaFIFO2_0[1];
1498 pseudo_bit_t UncErrStatusSendLaFIFO3_0[1];
1499 pseudo_bit_t UncErrStatusSendLaFIFO4_0[1];
1500 pseudo_bit_t UncErrStatusSendLaFIFO5_0[1];
1501 pseudo_bit_t UncErrStatusSendLaFIFO6_0[1];
1502 pseudo_bit_t UncErrStatusSendLaFIFO7_0[1];
1503 pseudo_bit_t UncErrStatusSendLaFIFO0_1[1];
1504 pseudo_bit_t UncErrStatusSendLaFIFO1_1[1];
1505 pseudo_bit_t UncErrStatusSendLaFIFO2_1[1];
1506 pseudo_bit_t UncErrStatusSendLaFIFO3_1[1];
1507 pseudo_bit_t UncErrStatusSendLaFIFO4_1[1];
1508 pseudo_bit_t UncErrStatusSendLaFIFO5_1[1];
1509 pseudo_bit_t UncErrStatusSendLaFIFO6_1[1];
1510 pseudo_bit_t UncErrStatusSendLaFIFO7_1[1];
1511 pseudo_bit_t UncErrStatusSendRmFIFO_0[1];
1512 pseudo_bit_t UncErrStatusSendRmFIFO_1[1];
1513 pseudo_bit_t _unused_1[11];
1514 pseudo_bit_t UncErrStatusPCIeRetryBuf[1];
1515 pseudo_bit_t UncErrStatusPCIePostHdrBuf[1];
1516 pseudo_bit_t UncErrStatusPCIePostDataBuf[1];
1517 pseudo_bit_t UncErrStatusPCIeCompHdrBuf[1];
1518 pseudo_bit_t UncErrStatusPCIeCompDataBuf[1];
1519 pseudo_bit_t UncErrStatusMsixTable0[1];
1520 pseudo_bit_t UncErrStatusMsixTable1[1];
1521 pseudo_bit_t UncErrStatusMsixTable2[1];
1522 pseudo_bit_t _unused_2[8];
1524 struct QIB_7322_MemUnCorErrStatus {
1525 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrStatus_pb );
1527 /* Default value: 0x0000000000000000 */
1529 #define QIB_7322_MemUnCorErrClear_offset 0x00000638UL
1530 struct QIB_7322_MemUnCorErrClear_pb {
1531 pseudo_bit_t UncErrClearRcvBuf_0[1];
1532 pseudo_bit_t UncErrClearRcvFlags_0[1];
1533 pseudo_bit_t UncErrClearLookupiqBuf_0[1];
1534 pseudo_bit_t UncErrClearRcvDMAHdrBuf_0[1];
1535 pseudo_bit_t UncErrClearRcvDMADataBuf_0[1];
1536 pseudo_bit_t UncErrClearRcvBuf_1[1];
1537 pseudo_bit_t UncErrClearRcvFlags_1[1];
1538 pseudo_bit_t UncErrClearLookupiqBuf_1[1];
1539 pseudo_bit_t UncErrClearRcvDMAHdrBuf_1[1];
1540 pseudo_bit_t UncErrClearRcvDMADataBuf_1[1];
1541 pseudo_bit_t UncErrClearRcvTIDArray[1];
1542 pseudo_bit_t UncErrClearRcvEgrArray[1];
1543 pseudo_bit_t _unused_0[3];
1544 pseudo_bit_t UncErrClearSendBufVL15[1];
1545 pseudo_bit_t UncErrClearSendBufMain[1];
1546 pseudo_bit_t UncErrClearSendBufExtra[1];
1547 pseudo_bit_t UncErrClearSendPbcArray[1];
1548 pseudo_bit_t UncErrClearSendLaFIFO0_0[1];
1549 pseudo_bit_t UncErrClearSendLaFIFO1_0[1];
1550 pseudo_bit_t UncErrClearSendLaFIFO2_0[1];
1551 pseudo_bit_t UncErrClearSendLaFIFO3_0[1];
1552 pseudo_bit_t UncErrClearSendLaFIFO4_0[1];
1553 pseudo_bit_t UncErrClearSendLaFIFO5_0[1];
1554 pseudo_bit_t UncErrClearSendLaFIFO6_0[1];
1555 pseudo_bit_t UncErrClearSendLaFIFO7_0[1];
1556 pseudo_bit_t UncErrClearSendLaFIFO0_1[1];
1557 pseudo_bit_t UncErrClearSendLaFIFO1_1[1];
1558 pseudo_bit_t UncErrClearSendLaFIFO2_1[1];
1559 pseudo_bit_t UncErrClearSendLaFIFO3_1[1];
1560 pseudo_bit_t UncErrClearSendLaFIFO4_1[1];
1561 pseudo_bit_t UncErrClearSendLaFIFO5_1[1];
1562 pseudo_bit_t UncErrClearSendLaFIFO6_1[1];
1563 pseudo_bit_t UncErrClearSendLaFIFO7_1[1];
1564 pseudo_bit_t UncErrClearSendRmFIFO_0[1];
1565 pseudo_bit_t UncErrClearSendRmFIFO_1[1];
1566 pseudo_bit_t _unused_1[11];
1567 pseudo_bit_t UncErrClearPCIeRetryBuf[1];
1568 pseudo_bit_t UncErrClearPCIePostHdrBuf[1];
1569 pseudo_bit_t UncErrClearPCIePostDataBuf[1];
1570 pseudo_bit_t UncErrClearPCIeCompHdrBuf[1];
1571 pseudo_bit_t UncErrClearPCIeCompDataBuf[1];
1572 pseudo_bit_t UncErrClearMsixTable0[1];
1573 pseudo_bit_t UncErrClearMsixTable1[1];
1574 pseudo_bit_t UncErrClearMsixTable2[1];
1575 pseudo_bit_t _unused_2[8];
1577 struct QIB_7322_MemUnCorErrClear {
1578 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrClear_pb );
1580 /* Default value: 0x0000000000000000 */
1582 #define QIB_7322_MemMultiCorErrMask_offset 0x00000640UL
1583 struct QIB_7322_MemMultiCorErrMask_pb {
1584 pseudo_bit_t MulCorErrMskRcvBuf_0[1];
1585 pseudo_bit_t MulCorErrMskRcvFlags_0[1];
1586 pseudo_bit_t MulCorErrMskLookupiqBuf_0[1];
1587 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_0[1];
1588 pseudo_bit_t MulCorErrMskRcvDMADataBuf_0[1];
1589 pseudo_bit_t MulCorErrMskRcvBuf_1[1];
1590 pseudo_bit_t MulCorErrMskRcvFlags_1[1];
1591 pseudo_bit_t MulCorErrMskLookupiqBuf_1[1];
1592 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_1[1];
1593 pseudo_bit_t MulCorErrMskRcvDMADataBuf_1[1];
1594 pseudo_bit_t MulCorErrMskRcvTIDArray[1];
1595 pseudo_bit_t MulCorErrMskRcvEgrArray[1];
1596 pseudo_bit_t _unused_0[3];
1597 pseudo_bit_t MulCorErrMskSendBufVL15[1];
1598 pseudo_bit_t MulCorErrMskSendBufMain[1];
1599 pseudo_bit_t MulCorErrMskSendBufExtra[1];
1600 pseudo_bit_t MulCorErrMskSendPbcArray[1];
1601 pseudo_bit_t MulCorErrMskSendLaFIFO0_0[1];
1602 pseudo_bit_t MulCorErrMskSendLaFIFO1_0[1];
1603 pseudo_bit_t MulCorErrMskSendLaFIFO2_0[1];
1604 pseudo_bit_t MulCorErrMskSendLaFIFO3_0[1];
1605 pseudo_bit_t MulCorErrMskSendLaFIFO4_0[1];
1606 pseudo_bit_t MulCorErrMskSendLaFIFO5_0[1];
1607 pseudo_bit_t MulCorErrMskSendLaFIFO6_0[1];
1608 pseudo_bit_t MulCorErrMskSendLaFIFO7_0[1];
1609 pseudo_bit_t MulCorErrMskSendLaFIFO0_1[1];
1610 pseudo_bit_t MulCorErrMskSendLaFIFO1_1[1];
1611 pseudo_bit_t MulCorErrMskSendLaFIFO2_1[1];
1612 pseudo_bit_t MulCorErrMskSendLaFIFO3_1[1];
1613 pseudo_bit_t MulCorErrMskSendLaFIFO4_1[1];
1614 pseudo_bit_t MulCorErrMskSendLaFIFO5_1[1];
1615 pseudo_bit_t MulCorErrMskSendLaFIFO6_1[1];
1616 pseudo_bit_t MulCorErrMskSendLaFIFO7_1[1];
1617 pseudo_bit_t MulCorErrMskSendRmFIFO_0[1];
1618 pseudo_bit_t MulCorErrMskSendRmFIFO_1[1];
1619 pseudo_bit_t _unused_1[11];
1620 pseudo_bit_t MulCorErrMskPCIeRetryBuf[1];
1621 pseudo_bit_t MulCorErrMskPCIePostHdrBuf[1];
1622 pseudo_bit_t MulCorErrMskPCIePostDataBuf[1];
1623 pseudo_bit_t MulCorErrMskPCIeCompHdrBuf[1];
1624 pseudo_bit_t MulCorErrMskPCIeCompDataBuf[1];
1625 pseudo_bit_t MulCorErrMskMsixTable0[1];
1626 pseudo_bit_t MulCorErrMskMsixTable1[1];
1627 pseudo_bit_t MulCorErrMskMsixTable2[1];
1628 pseudo_bit_t _unused_2[8];
1630 struct QIB_7322_MemMultiCorErrMask {
1631 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrMask_pb );
1633 /* Default value: 0x0000000000000000 */
1635 #define QIB_7322_MemMultiCorErrStatus_offset 0x00000648UL
1636 struct QIB_7322_MemMultiCorErrStatus_pb {
1637 pseudo_bit_t MulCorErrStatusRcvBuf_0[1];
1638 pseudo_bit_t MulCorErrStatusRcvFlags_0[1];
1639 pseudo_bit_t MulCorErrStatusLookupiqBuf_0[1];
1640 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_0[1];
1641 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_0[1];
1642 pseudo_bit_t MulCorErrStatusRcvBuf_1[1];
1643 pseudo_bit_t MulCorErrStatusRcvFlags_1[1];
1644 pseudo_bit_t MulCorErrStatusLookupiqBuf_1[1];
1645 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_1[1];
1646 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_1[1];
1647 pseudo_bit_t MulCorErrStatusRcvTIDArray[1];
1648 pseudo_bit_t MulCorErrStatusRcvEgrArray[1];
1649 pseudo_bit_t _unused_0[3];
1650 pseudo_bit_t MulCorErrStatusSendBufVL15[1];
1651 pseudo_bit_t MulCorErrStatusSendBufMain[1];
1652 pseudo_bit_t MulCorErrStatusSendBufExtra[1];
1653 pseudo_bit_t MulCorErrStatusSendPbcArray[1];
1654 pseudo_bit_t MulCorErrStatusSendLaFIFO0_0[1];
1655 pseudo_bit_t MulCorErrStatusSendLaFIFO1_0[1];
1656 pseudo_bit_t MulCorErrStatusSendLaFIFO2_0[1];
1657 pseudo_bit_t MulCorErrStatusSendLaFIFO3_0[1];
1658 pseudo_bit_t MulCorErrStatusSendLaFIFO4_0[1];
1659 pseudo_bit_t MulCorErrStatusSendLaFIFO5_0[1];
1660 pseudo_bit_t MulCorErrStatusSendLaFIFO6_0[1];
1661 pseudo_bit_t MulCorErrStatusSendLaFIFO7_0[1];
1662 pseudo_bit_t MulCorErrStatusSendLaFIFO0_1[1];
1663 pseudo_bit_t MulCorErrStatusSendLaFIFO1_1[1];
1664 pseudo_bit_t MulCorErrStatusSendLaFIFO2_1[1];
1665 pseudo_bit_t MulCorErrStatusSendLaFIFO3_1[1];
1666 pseudo_bit_t MulCorErrStatusSendLaFIFO4_1[1];
1667 pseudo_bit_t MulCorErrStatusSendLaFIFO5_1[1];
1668 pseudo_bit_t MulCorErrStatusSendLaFIFO6_1[1];
1669 pseudo_bit_t MulCorErrStatusSendLaFIFO7_1[1];
1670 pseudo_bit_t MulCorErrStatusSendRmFIFO_0[1];
1671 pseudo_bit_t MulCorErrStatusSendRmFIFO_1[1];
1672 pseudo_bit_t _unused_1[11];
1673 pseudo_bit_t MulCorErrStatusPCIeRetryBuf[1];
1674 pseudo_bit_t MulCorErrStatusPCIePostHdrBuf[1];
1675 pseudo_bit_t MulCorErrStatusPCIePostDataBuf[1];
1676 pseudo_bit_t MulCorErrStatusPCIeCompHdrBuf[1];
1677 pseudo_bit_t MulCorErrStatusPCIeCompDataBuf[1];
1678 pseudo_bit_t MulCorErrStatusMsixTable0[1];
1679 pseudo_bit_t MulCorErrStatusMsixTable1[1];
1680 pseudo_bit_t MulCorErrStatusMsixTable2[1];
1681 pseudo_bit_t _unused_2[8];
1683 struct QIB_7322_MemMultiCorErrStatus {
1684 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrStatus_pb );
1686 /* Default value: 0x0000000000000000 */
1688 #define QIB_7322_MemMultiCorErrClear_offset 0x00000650UL
1689 struct QIB_7322_MemMultiCorErrClear_pb {
1690 pseudo_bit_t MulCorErrClearRcvBuf_0[1];
1691 pseudo_bit_t MulCorErrClearRcvFlags_0[1];
1692 pseudo_bit_t MulCorErrClearLookupiqBuf_0[1];
1693 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_0[1];
1694 pseudo_bit_t MulCorErrClearRcvDMADataBuf_0[1];
1695 pseudo_bit_t MulCorErrClearRcvBuf_1[1];
1696 pseudo_bit_t MulCorErrClearRcvFlags_1[1];
1697 pseudo_bit_t MulCorErrClearLookupiqBuf_1[1];
1698 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_1[1];
1699 pseudo_bit_t MulCorErrClearRcvDMADataBuf_1[1];
1700 pseudo_bit_t MulCorErrClearRcvTIDArray[1];
1701 pseudo_bit_t MulCorErrClearRcvEgrArray[1];
1702 pseudo_bit_t _unused_0[3];
1703 pseudo_bit_t MulCorErrClearSendBufVL15[1];
1704 pseudo_bit_t MulCorErrClearSendBufMain[1];
1705 pseudo_bit_t MulCorErrClearSendBufExtra[1];
1706 pseudo_bit_t MulCorErrClearSendPbcArray[1];
1707 pseudo_bit_t MulCorErrClearSendLaFIFO0_0[1];
1708 pseudo_bit_t MulCorErrClearSendLaFIFO1_0[1];
1709 pseudo_bit_t MulCorErrClearSendLaFIFO2_0[1];
1710 pseudo_bit_t MulCorErrClearSendLaFIFO3_0[1];
1711 pseudo_bit_t MulCorErrClearSendLaFIFO4_0[1];
1712 pseudo_bit_t MulCorErrClearSendLaFIFO5_0[1];
1713 pseudo_bit_t MulCorErrClearSendLaFIFO6_0[1];
1714 pseudo_bit_t MulCorErrClearSendLaFIFO7_0[1];
1715 pseudo_bit_t MulCorErrClearSendLaFIFO0_1[1];
1716 pseudo_bit_t MulCorErrClearSendLaFIFO1_1[1];
1717 pseudo_bit_t MulCorErrClearSendLaFIFO2_1[1];
1718 pseudo_bit_t MulCorErrClearSendLaFIFO3_1[1];
1719 pseudo_bit_t MulCorErrClearSendLaFIFO4_1[1];
1720 pseudo_bit_t MulCorErrClearSendLaFIFO5_1[1];
1721 pseudo_bit_t MulCorErrClearSendLaFIFO6_1[1];
1722 pseudo_bit_t MulCorErrClearSendLaFIFO7_1[1];
1723 pseudo_bit_t MulCorErrClearSendRmFIFO_0[1];
1724 pseudo_bit_t MulCorErrClearSendRmFIFO_1[1];
1725 pseudo_bit_t _unused_1[11];
1726 pseudo_bit_t MulCorErrClearPCIeRetryBuf[1];
1727 pseudo_bit_t MulCorErrClearPCIePostHdrBuf[1];
1728 pseudo_bit_t MulCorErrClearPCIePostDataBuf[1];
1729 pseudo_bit_t MulCorErrClearPCIeCompHdrBuf[1];
1730 pseudo_bit_t MulCorErrClearPCIeCompDataBuf[1];
1731 pseudo_bit_t MulCorErrClearMsixTable0[1];
1732 pseudo_bit_t MulCorErrClearMsixTable1[1];
1733 pseudo_bit_t MulCorErrClearMsixTable2[1];
1734 pseudo_bit_t _unused_2[8];
1736 struct QIB_7322_MemMultiCorErrClear {
1737 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrClear_pb );
1739 /* Default value: 0x0000000000000000 */
1741 #define QIB_7322_MemCorErrMask_offset 0x00000658UL
1742 struct QIB_7322_MemCorErrMask_pb {
1743 pseudo_bit_t CorErrMskRcvBuf_0[1];
1744 pseudo_bit_t CorErrMskRcvFlags_0[1];
1745 pseudo_bit_t CorErrMskLookupiqBuf_0[1];
1746 pseudo_bit_t CorErrMskRcvDMAHdrBuf_0[1];
1747 pseudo_bit_t CorErrMskRcvDMADataBuf_0[1];
1748 pseudo_bit_t CorErrMskRcvBuf_1[1];
1749 pseudo_bit_t CorErrMskRcvFlags_1[1];
1750 pseudo_bit_t CorErrMskLookupiqBuf_1[1];
1751 pseudo_bit_t CorErrMskRcvDMAHdrBuf_1[1];
1752 pseudo_bit_t CorErrMskRcvDMADataBuf_1[1];
1753 pseudo_bit_t CorErrMskRcvTIDArray[1];
1754 pseudo_bit_t CorErrMskRcvEgrArray[1];
1755 pseudo_bit_t _unused_0[3];
1756 pseudo_bit_t CorErrMskSendBufVL15[1];
1757 pseudo_bit_t CorErrMskSendBufMain[1];
1758 pseudo_bit_t CorErrMskSendBufExtra[1];
1759 pseudo_bit_t CorErrMskSendPbcArray[1];
1760 pseudo_bit_t CorErrMskSendLaFIFO0_0[1];
1761 pseudo_bit_t CorErrMskSendLaFIFO1_0[1];
1762 pseudo_bit_t CorErrMskSendLaFIFO2_0[1];
1763 pseudo_bit_t CorErrMskSendLaFIFO3_0[1];
1764 pseudo_bit_t CorErrMskSendLaFIFO4_0[1];
1765 pseudo_bit_t CorErrMskSendLaFIFO5_0[1];
1766 pseudo_bit_t CorErrMskSendLaFIFO6_0[1];
1767 pseudo_bit_t CorErrMskSendLaFIFO7_0[1];
1768 pseudo_bit_t CorErrMskSendLaFIFO0_1[1];
1769 pseudo_bit_t CorErrMskSendLaFIFO1_1[1];
1770 pseudo_bit_t CorErrMskSendLaFIFO2_1[1];
1771 pseudo_bit_t CorErrMskSendLaFIFO3_1[1];
1772 pseudo_bit_t CorErrMskSendLaFIFO4_1[1];
1773 pseudo_bit_t CorErrMskSendLaFIFO5_1[1];
1774 pseudo_bit_t CorErrMskSendLaFIFO6_1[1];
1775 pseudo_bit_t CorErrMskSendLaFIFO7_1[1];
1776 pseudo_bit_t CorErrMskSendRmFIFO_0[1];
1777 pseudo_bit_t CorErrMskSendRmFIFO_1[1];
1778 pseudo_bit_t _unused_1[11];
1779 pseudo_bit_t CorErrMskPCIeRetryBuf[1];
1780 pseudo_bit_t CorErrMskPCIePostHdrBuf[1];
1781 pseudo_bit_t CorErrMskPCIePostDataBuf[1];
1782 pseudo_bit_t CorErrMskPCIeCompHdrBuf[1];
1783 pseudo_bit_t CorErrMskPCIeCompDataBuf[1];
1784 pseudo_bit_t CorErrMskMsixTable0[1];
1785 pseudo_bit_t CorErrMskMsixTable1[1];
1786 pseudo_bit_t CorErrMskMsixTable2[1];
1787 pseudo_bit_t _unused_2[8];
1789 struct QIB_7322_MemCorErrMask {
1790 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrMask_pb );
1792 /* Default value: 0x0000000000000000 */
1794 #define QIB_7322_MemCorErrStatus_offset 0x00000660UL
1795 struct QIB_7322_MemCorErrStatus_pb {
1796 pseudo_bit_t CorErrStatusRcvBuf_0[1];
1797 pseudo_bit_t CorErrStatusRcvFlags_0[1];
1798 pseudo_bit_t CorErrStatusLookupiqBuf_0[1];
1799 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_0[1];
1800 pseudo_bit_t CorErrStatusRcvDMADataBuf_0[1];
1801 pseudo_bit_t CorErrStatusRcvBuf_1[1];
1802 pseudo_bit_t CorErrStatusRcvFlags_1[1];
1803 pseudo_bit_t CorErrStatusLookupiqBuf_1[1];
1804 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_1[1];
1805 pseudo_bit_t CorErrStatusRcvDMADataBuf_1[1];
1806 pseudo_bit_t CorErrStatusRcvTIDArray[1];
1807 pseudo_bit_t CorErrStatusRcvEgrArray[1];
1808 pseudo_bit_t _unused_0[3];
1809 pseudo_bit_t CorErrStatusSendBufVL15[1];
1810 pseudo_bit_t CorErrStatusSendBufMain[1];
1811 pseudo_bit_t CorErrStatusSendBufExtra[1];
1812 pseudo_bit_t CorErrStatusSendPbcArray[1];
1813 pseudo_bit_t CorErrStatusSendLaFIFO0_0[1];
1814 pseudo_bit_t CorErrStatusSendLaFIFO1_0[1];
1815 pseudo_bit_t CorErrStatusSendLaFIFO2_0[1];
1816 pseudo_bit_t CorErrStatusSendLaFIFO3_0[1];
1817 pseudo_bit_t CorErrStatusSendLaFIFO4_0[1];
1818 pseudo_bit_t CorErrStatusSendLaFIFO5_0[1];
1819 pseudo_bit_t CorErrStatusSendLaFIFO6_0[1];
1820 pseudo_bit_t CorErrStatusSendLaFIFO7_0[1];
1821 pseudo_bit_t CorErrStatusSendLaFIFO0_1[1];
1822 pseudo_bit_t CorErrStatusSendLaFIFO1_1[1];
1823 pseudo_bit_t CorErrStatusSendLaFIFO2_1[1];
1824 pseudo_bit_t CorErrStatusSendLaFIFO3_1[1];
1825 pseudo_bit_t CorErrStatusSendLaFIFO4_1[1];
1826 pseudo_bit_t CorErrStatusSendLaFIFO5_1[1];
1827 pseudo_bit_t CorErrStatusSendLaFIFO6_1[1];
1828 pseudo_bit_t CorErrStatusSendLaFIFO7_1[1];
1829 pseudo_bit_t CorErrStatusSendRmFIFO_0[1];
1830 pseudo_bit_t CorErrStatusSendRmFIFO_1[1];
1831 pseudo_bit_t _unused_1[11];
1832 pseudo_bit_t CorErrStatusPCIeRetryBuf[1];
1833 pseudo_bit_t CorErrStatusPCIePostHdrBuf[1];
1834 pseudo_bit_t CorErrStatusPCIePostDataBuf[1];
1835 pseudo_bit_t CorErrStatusPCIeCompHdrBuf[1];
1836 pseudo_bit_t CorErrStatusPCIeCompDataBuf[1];
1837 pseudo_bit_t CorErrStatusMsixTable0[1];
1838 pseudo_bit_t CorErrStatusMsixTable1[1];
1839 pseudo_bit_t CorErrStatusMsixTable2[1];
1840 pseudo_bit_t _unused_2[8];
1842 struct QIB_7322_MemCorErrStatus {
1843 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrStatus_pb );
1845 /* Default value: 0x0000000000000000 */
1847 #define QIB_7322_MemCorErrClear_offset 0x00000668UL
1848 struct QIB_7322_MemCorErrClear_pb {
1849 pseudo_bit_t CorErrClearRcvBuf_0[1];
1850 pseudo_bit_t CorErrClearRcvFlags_0[1];
1851 pseudo_bit_t CorErrClearLookupiqBuf_0[1];
1852 pseudo_bit_t CorErrClearRcvDMAHdrBuf_0[1];
1853 pseudo_bit_t CorErrClearRcvDMADataBuf_0[1];
1854 pseudo_bit_t CorErrClearRcvBuf_1[1];
1855 pseudo_bit_t CorErrClearRcvFlags_1[1];
1856 pseudo_bit_t CorErrClearLookupiqBuf_1[1];
1857 pseudo_bit_t CorErrClearRcvDMAHdrBuf_1[1];
1858 pseudo_bit_t CorErrClearRcvDMADataBuf_1[1];
1859 pseudo_bit_t CorErrClearRcvTIDArray[1];
1860 pseudo_bit_t CorErrClearRcvEgrArray[1];
1861 pseudo_bit_t _unused_0[3];
1862 pseudo_bit_t CorErrClearSendBufVL15[1];
1863 pseudo_bit_t CorErrClearSendBufMain[1];
1864 pseudo_bit_t CorErrClearSendBufExtra[1];
1865 pseudo_bit_t CorErrClearSendPbcArray[1];
1866 pseudo_bit_t CorErrClearSendLaFIFO0_0[1];
1867 pseudo_bit_t CorErrClearSendLaFIFO1_0[1];
1868 pseudo_bit_t CorErrClearSendLaFIFO2_0[1];
1869 pseudo_bit_t CorErrClearSendLaFIFO3_0[1];
1870 pseudo_bit_t CorErrClearSendLaFIFO4_0[1];
1871 pseudo_bit_t CorErrClearSendLaFIFO5_0[1];
1872 pseudo_bit_t CorErrClearSendLaFIFO6_0[1];
1873 pseudo_bit_t CorErrClearSendLaFIFO7_0[1];
1874 pseudo_bit_t CorErrClearSendLaFIFO0_1[1];
1875 pseudo_bit_t CorErrClearSendLaFIFO1_1[1];
1876 pseudo_bit_t CorErrClearSendLaFIFO2_1[1];
1877 pseudo_bit_t CorErrClearSendLaFIFO3_1[1];
1878 pseudo_bit_t CorErrClearSendLaFIFO4_1[1];
1879 pseudo_bit_t CorErrClearSendLaFIFO5_1[1];
1880 pseudo_bit_t CorErrClearSendLaFIFO6_1[1];
1881 pseudo_bit_t CorErrClearSendLaFIFO7_1[1];
1882 pseudo_bit_t CorErrClearSendRmFIFO_0[1];
1883 pseudo_bit_t CorErrClearSendRmFIFO_1[1];
1884 pseudo_bit_t _unused_1[11];
1885 pseudo_bit_t CorErrClearPCIeRetryBuf[1];
1886 pseudo_bit_t CorErrClearPCIePostHdrBuf[1];
1887 pseudo_bit_t CorErrClearPCIePostDataBuf[1];
1888 pseudo_bit_t CorErrClearPCIeCompHdrBuf[1];
1889 pseudo_bit_t CorErrClearPCIeCompDataBuf[1];
1890 pseudo_bit_t CorErrClearMsixTable0[1];
1891 pseudo_bit_t CorErrClearMsixTable1[1];
1892 pseudo_bit_t CorErrClearMsixTable2[1];
1893 pseudo_bit_t _unused_2[8];
1895 struct QIB_7322_MemCorErrClear {
1896 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrClear_pb );
1898 /* Default value: 0x0000000000000000 */
1900 #define QIB_7322_MsixTableUnCorErrLogA_offset 0x00000680UL
1901 struct QIB_7322_MsixTableUnCorErrLogA_pb {
1902 pseudo_bit_t MsixTable_1_0_UnCorErrData[64];
1904 struct QIB_7322_MsixTableUnCorErrLogA {
1905 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogA_pb );
1907 /* Default value: 0x0000000000000000 */
1909 #define QIB_7322_MsixTableUnCorErrLogB_offset 0x00000688UL
1910 struct QIB_7322_MsixTableUnCorErrLogB_pb {
1911 pseudo_bit_t MsixTable_2_UnCorErrData[32];
1912 pseudo_bit_t MsixTable_0_UnCorErrCheckBits[7];
1913 pseudo_bit_t MsixTable_1_UnCorErrCheckBits[7];
1914 pseudo_bit_t MsixTable_2_UnCorErrCheckBits[7];
1915 pseudo_bit_t _unused_0[11];
1917 struct QIB_7322_MsixTableUnCorErrLogB {
1918 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogB_pb );
1920 /* Default value: 0x0000000000000000 */
1922 #define QIB_7322_MsixTableUnCorErrLogC_offset 0x00000690UL
1923 struct QIB_7322_MsixTableUnCorErrLogC_pb {
1924 pseudo_bit_t MsixTable_0_UnCorErrAddr[7];
1925 pseudo_bit_t MsixTable_1_UnCorErrAddr[7];
1926 pseudo_bit_t MsixTable_2_UnCorErrAddr[7];
1927 pseudo_bit_t _unused_0[43];
1929 struct QIB_7322_MsixTableUnCorErrLogC {
1930 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogC_pb );
1932 /* Default value: 0x0000000000000000 */
1934 #define QIB_7322_MsixEntryWithUncorErr_offset 0x00000698UL
1935 /* Default value: 0x0000000000000000 */
1937 #define QIB_7322_MsixTableCorErrLogA_offset 0x000006a0UL
1938 struct QIB_7322_MsixTableCorErrLogA_pb {
1939 pseudo_bit_t MsixTable_1_0_CorErrData[64];
1941 struct QIB_7322_MsixTableCorErrLogA {
1942 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogA_pb );
1944 /* Default value: 0x0000000000000000 */
1946 #define QIB_7322_MsixTableCorErrLogB_offset 0x000006a8UL
1947 struct QIB_7322_MsixTableCorErrLogB_pb {
1948 pseudo_bit_t MsixTable_2_CorErrData[32];
1949 pseudo_bit_t MsixTable_0_CorErrCheckBits[7];
1950 pseudo_bit_t MsixTable_1_CorErrCheckBits[7];
1951 pseudo_bit_t MsixTable_2_CorErrCheckBits[7];
1952 pseudo_bit_t _unused_0[11];
1954 struct QIB_7322_MsixTableCorErrLogB {
1955 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogB_pb );
1957 /* Default value: 0x0000000000000000 */
1959 #define QIB_7322_MsixTableCorErrLogC_offset 0x000006b0UL
1960 struct QIB_7322_MsixTableCorErrLogC_pb {
1961 pseudo_bit_t MsixTable_0_CorErrAddr[7];
1962 pseudo_bit_t MsixTable_1_CorErrAddr[7];
1963 pseudo_bit_t MsixTable_2_CorErrAddr[7];
1964 pseudo_bit_t _unused_0[43];
1966 struct QIB_7322_MsixTableCorErrLogC {
1967 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogC_pb );
1969 /* Default value: 0x0000000000000000 */
1971 #define QIB_7322_PcieCplDataBufrUnCorErrLogA_offset 0x00000700UL
1972 struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb {
1973 pseudo_bit_t PcieCplDataBufrUnCorErrData_63_0[64];
1975 struct QIB_7322_PcieCplDataBufrUnCorErrLogA {
1976 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb );
1978 /* Default value: 0x0000000000000000 */
1980 #define QIB_7322_PcieCplDataBufrUnCorErrLogB_offset 0x00000708UL
1981 struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb {
1982 pseudo_bit_t PcieCplDataBufrUnCorErrData_127_64[64];
1984 struct QIB_7322_PcieCplDataBufrUnCorErrLogB {
1985 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb );
1987 /* Default value: 0x0000000000000000 */
1989 #define QIB_7322_PcieCplDataBufrUnCorErrLogC_offset 0x00000710UL
1990 struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb {
1991 pseudo_bit_t PcieCplDataBufrUnCorErrData_136_128[9];
1992 pseudo_bit_t PcieCplDataBufrUnCorErrCheckBit_21_0[22];
1993 pseudo_bit_t PcieCplDataBufrUnCorErrAddr_13_0[14];
1994 pseudo_bit_t _unused_0[19];
1996 struct QIB_7322_PcieCplDataBufrUnCorErrLogC {
1997 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb );
1999 /* Default value: 0x0000000000000000 */
2001 #define QIB_7322_PcieCplHdrBufrUnCorErrLogA_offset 0x00000720UL
2002 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb {
2003 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_63_0[64];
2005 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA {
2006 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb );
2008 /* Default value: 0x0000000000000000 */
2010 #define QIB_7322_PcieCplHdrBufrUnCorErrLogB_offset 0x00000728UL
2011 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb {
2012 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_103_64[40];
2013 pseudo_bit_t _unused_0[24];
2015 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB {
2016 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb );
2018 /* Default value: 0x0000000000000000 */
2020 #define QIB_7322_PcieCplHdrBufrUnCorErrLogC_offset 0x00000730UL
2021 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb {
2022 pseudo_bit_t PcieCplHdrBufrUnCorErrCheckBit_15_0[16];
2023 pseudo_bit_t PcieCplHdrBufrUnCorErrAddr_8_0[9];
2024 pseudo_bit_t _unused_0[39];
2026 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC {
2027 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb );
2029 /* Default value: 0x0000000000000000 */
2031 #define QIB_7322_PciePDataBufrUnCorErrLogA_offset 0x00000740UL
2032 struct QIB_7322_PciePDataBufrUnCorErrLogA_pb {
2033 pseudo_bit_t PciePDataBufrUnCorErrData_63_0[64];
2035 struct QIB_7322_PciePDataBufrUnCorErrLogA {
2036 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogA_pb );
2038 /* Default value: 0x0000000000000000 */
2040 #define QIB_7322_PciePDataBufrUnCorErrLogB_offset 0x00000748UL
2041 struct QIB_7322_PciePDataBufrUnCorErrLogB_pb {
2042 pseudo_bit_t PciePDataBufrUnCorErrData_127_64[64];
2044 struct QIB_7322_PciePDataBufrUnCorErrLogB {
2045 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogB_pb );
2047 /* Default value: 0x0000000000000000 */
2049 #define QIB_7322_PciePDataBufrUnCorErrLogC_offset 0x00000750UL
2050 struct QIB_7322_PciePDataBufrUnCorErrLogC_pb {
2051 pseudo_bit_t PciePDataBufrUnCorErrData_136_128[9];
2052 pseudo_bit_t PciePDataBufrUnCorErrCheckBit_21_0[22];
2053 pseudo_bit_t PciePDataBufrUnCorErrAddr_13_0[14];
2054 pseudo_bit_t _unused_0[19];
2056 struct QIB_7322_PciePDataBufrUnCorErrLogC {
2057 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogC_pb );
2059 /* Default value: 0x0000000000000000 */
2061 #define QIB_7322_PciePHdrBufrUnCorErrLogA_offset 0x00000760UL
2062 struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb {
2063 pseudo_bit_t PciePHdrBufrUnCorErrData_63_0[64];
2065 struct QIB_7322_PciePHdrBufrUnCorErrLogA {
2066 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb );
2068 /* Default value: 0x0000000000000000 */
2070 #define QIB_7322_PciePHdrBufrUnCorErrLogB_offset 0x00000768UL
2071 struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb {
2072 pseudo_bit_t PciePHdrBufrUnCorErrData_107_64[44];
2073 pseudo_bit_t _unused_0[20];
2075 struct QIB_7322_PciePHdrBufrUnCorErrLogB {
2076 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb );
2078 /* Default value: 0x0000000000000000 */
2080 #define QIB_7322_PciePHdrBufrUnCorErrLogC_offset 0x00000770UL
2081 struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb {
2082 pseudo_bit_t PciePHdrBufrUnCorErrCheckBit_15_0[16];
2083 pseudo_bit_t PciePHdrBufrUnCorErrAddr_8_0[9];
2084 pseudo_bit_t _unused_0[39];
2086 struct QIB_7322_PciePHdrBufrUnCorErrLogC {
2087 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb );
2089 /* Default value: 0x0000000000000000 */
2091 #define QIB_7322_PcieRetryBufrUnCorErrLogA_offset 0x00000780UL
2092 struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb {
2093 pseudo_bit_t PcieRetryBufrUnCorErrData_63_0[64];
2095 struct QIB_7322_PcieRetryBufrUnCorErrLogA {
2096 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb );
2098 /* Default value: 0x0000000000000000 */
2100 #define QIB_7322_PcieRetryBufrUnCorErrLogB_offset 0x00000788UL
2101 struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb {
2102 pseudo_bit_t PcieRetryBufrUnCorErrData_127_64[64];
2104 struct QIB_7322_PcieRetryBufrUnCorErrLogB {
2105 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb );
2107 /* Default value: 0x0000000000000000 */
2109 #define QIB_7322_PcieRetryBufrUnCorErrLogC_offset 0x00000790UL
2110 struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb {
2111 pseudo_bit_t PcieRetryBufrUnCorErrData_133_128[6];
2112 pseudo_bit_t PcieRetryBufrUnCorErrCheckBit_20_0[21];
2113 pseudo_bit_t PcieRetryBufrUnCorErrAddr_13_0[14];
2114 pseudo_bit_t _unused_0[23];
2116 struct QIB_7322_PcieRetryBufrUnCorErrLogC {
2117 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb );
2119 /* Default value: 0x0000000000000000 */
2121 #define QIB_7322_RxTIDArrayUnCorErrLogA_offset 0x00000800UL
2122 struct QIB_7322_RxTIDArrayUnCorErrLogA_pb {
2123 pseudo_bit_t RxTIDArrayUnCorErrData_39_0[40];
2124 pseudo_bit_t RxTIDArrayUnCorErrCheckBit_11_0[12];
2125 pseudo_bit_t _unused_0[12];
2127 struct QIB_7322_RxTIDArrayUnCorErrLogA {
2128 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogA_pb );
2130 /* Default value: 0x0000000000000000 */
2132 #define QIB_7322_RxTIDArrayUnCorErrLogB_offset 0x00000808UL
2133 struct QIB_7322_RxTIDArrayUnCorErrLogB_pb {
2134 pseudo_bit_t RxTIDArrayUnCorErrAddr_16_0[17];
2135 pseudo_bit_t _unused_0[47];
2137 struct QIB_7322_RxTIDArrayUnCorErrLogB {
2138 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogB_pb );
2140 /* Default value: 0x0000000000000000 */
2142 #define QIB_7322_RxEagerArrayUnCorErrLogA_offset 0x00000810UL
2143 struct QIB_7322_RxEagerArrayUnCorErrLogA_pb {
2144 pseudo_bit_t RxEagerArrayUnCorErrData_39_0[40];
2145 pseudo_bit_t RxEagerArrayUnCorErrCheckBit_11_0[12];
2146 pseudo_bit_t _unused_0[12];
2148 struct QIB_7322_RxEagerArrayUnCorErrLogA {
2149 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogA_pb );
2151 /* Default value: 0x0000000000000000 */
2153 #define QIB_7322_RxEagerArrayUnCorErrLogB_offset 0x00000818UL
2154 struct QIB_7322_RxEagerArrayUnCorErrLogB_pb {
2155 pseudo_bit_t RxEagerArrayUnCorErrAddr_17_0[18];
2156 pseudo_bit_t _unused_0[46];
2158 struct QIB_7322_RxEagerArrayUnCorErrLogB {
2159 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogB_pb );
2161 /* Default value: 0x0000000000000000 */
2163 #define QIB_7322_SBufMainArrayUnCorErrLogA_offset 0x00000880UL
2164 struct QIB_7322_SBufMainArrayUnCorErrLogA_pb {
2165 pseudo_bit_t SBufMainArrayUnCorErrData_63_0[64];
2167 struct QIB_7322_SBufMainArrayUnCorErrLogA {
2168 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogA_pb );
2170 /* Default value: 0x0000000000000000 */
2172 #define QIB_7322_SBufMainArrayUnCorErrLogB_offset 0x00000888UL
2173 struct QIB_7322_SBufMainArrayUnCorErrLogB_pb {
2174 pseudo_bit_t SBufMainArrayUnCorErrData_127_64[64];
2176 struct QIB_7322_SBufMainArrayUnCorErrLogB {
2177 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogB_pb );
2179 /* Default value: 0x0000000000000000 */
2181 #define QIB_7322_SBufMainArrayUnCorErrLogC_offset 0x00000890UL
2182 struct QIB_7322_SBufMainArrayUnCorErrLogC_pb {
2183 pseudo_bit_t SBufMainArrayUnCorErrCheckBit_27_0[28];
2184 pseudo_bit_t SBufMainArrayUnCorErrAddr_18_0[19];
2185 pseudo_bit_t _unused_0[13];
2186 pseudo_bit_t SBufMainArrayUnCorErrDword_3_0[4];
2188 struct QIB_7322_SBufMainArrayUnCorErrLogC {
2189 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogC_pb );
2191 /* Default value: 0x0000000000000000 */
2193 #define QIB_7322_SBufExtraArrayUnCorErrLogA_offset 0x00000898UL
2194 struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb {
2195 pseudo_bit_t SBufExtraArrayUnCorErrData_63_0[64];
2197 struct QIB_7322_SBufExtraArrayUnCorErrLogA {
2198 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb );
2200 /* Default value: 0x0000000000000000 */
2202 #define QIB_7322_SBufExtraArrayUnCorErrLogB_offset 0x000008a0UL
2203 struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb {
2204 pseudo_bit_t SBufExtraArrayUnCorErrData_127_64[64];
2206 struct QIB_7322_SBufExtraArrayUnCorErrLogB {
2207 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb );
2209 /* Default value: 0x0000000000000000 */
2211 #define QIB_7322_SBufExtraArrayUnCorErrLogC_offset 0x000008a8UL
2212 struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb {
2213 pseudo_bit_t SBufExtraArrayUnCorErrCheckBit_27_0[28];
2214 pseudo_bit_t SBufExtraArrayUnCorErrAddr_14_0[15];
2215 pseudo_bit_t _unused_0[17];
2216 pseudo_bit_t SBufExtraArrayUnCorErrAdd_3_0[4];
2218 struct QIB_7322_SBufExtraArrayUnCorErrLogC {
2219 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb );
2221 /* Default value: 0x0000000000000000 */
2223 #define QIB_7322_SendPbcArrayUnCorErrLog_offset 0x000008b0UL
2224 struct QIB_7322_SendPbcArrayUnCorErrLog_pb {
2225 pseudo_bit_t SendPbcArrayUnCorErrData_21_0[22];
2226 pseudo_bit_t SendPbcArrayUnCorErrCheckBit_6_0[7];
2227 pseudo_bit_t SendPbcArrayUnCorErrAddr_9_0[10];
2228 pseudo_bit_t _unused_0[25];
2230 struct QIB_7322_SendPbcArrayUnCorErrLog {
2231 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayUnCorErrLog_pb );
2233 /* Default value: 0x0000000000000000 */
2235 #define QIB_7322_SBufVL15ArrayUnCorErrLogA_offset 0x000008c0UL
2236 struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb {
2237 pseudo_bit_t SBufVL15ArrayUnCorErrData_63_0[64];
2239 struct QIB_7322_SBufVL15ArrayUnCorErrLogA {
2240 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb );
2242 /* Default value: 0x0000000000000000 */
2244 #define QIB_7322_PcieCplDataBufrCorErrLogA_offset 0x00000900UL
2245 struct QIB_7322_PcieCplDataBufrCorErrLogA_pb {
2246 pseudo_bit_t PcieCplDataBufrCorErrData_63_0[64];
2248 struct QIB_7322_PcieCplDataBufrCorErrLogA {
2249 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogA_pb );
2251 /* Default value: 0x0000000000000000 */
2253 #define QIB_7322_PcieCplDataBufrCorErrLogB_offset 0x00000908UL
2254 struct QIB_7322_PcieCplDataBufrCorErrLogB_pb {
2255 pseudo_bit_t PcieCplDataBufrCorErrData_127_64[64];
2257 struct QIB_7322_PcieCplDataBufrCorErrLogB {
2258 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogB_pb );
2260 /* Default value: 0x0000000000000000 */
2262 #define QIB_7322_PcieCplDataBufrCorErrLogC_offset 0x00000910UL
2263 struct QIB_7322_PcieCplDataBufrCorErrLogC_pb {
2264 pseudo_bit_t PcieCplDataBufrCorErrData_136_128[9];
2265 pseudo_bit_t PcieCplDataBufrCorErrCheckBit_21_0[22];
2266 pseudo_bit_t PcieCplDataBufrCorErrAddr_13_0[14];
2267 pseudo_bit_t _unused_0[19];
2269 struct QIB_7322_PcieCplDataBufrCorErrLogC {
2270 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogC_pb );
2272 /* Default value: 0x0000000000000000 */
2274 #define QIB_7322_PcieCplHdrBufrCorErrLogA_offset 0x00000920UL
2275 struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb {
2276 pseudo_bit_t PcieCplHdrBufrCorErrHdr_63_0[64];
2278 struct QIB_7322_PcieCplHdrBufrCorErrLogA {
2279 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb );
2281 /* Default value: 0x0000000000000000 */
2283 #define QIB_7322_PcieCplHdrBufrCorErrLogB_offset 0x00000928UL
2284 struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb {
2285 pseudo_bit_t PcieCplHdrBufrCorErrHdr_103_64[40];
2286 pseudo_bit_t _unused_0[24];
2288 struct QIB_7322_PcieCplHdrBufrCorErrLogB {
2289 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb );
2291 /* Default value: 0x0000000000000000 */
2293 #define QIB_7322_PcieCplHdrBufrCorErrLogC_offset 0x00000930UL
2294 struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb {
2295 pseudo_bit_t PcieCplHdrBufrCorErrCheckBit_15_0[16];
2296 pseudo_bit_t PcieCplHdrBufrCorErrAddr_8_0[9];
2297 pseudo_bit_t _unused_0[39];
2299 struct QIB_7322_PcieCplHdrBufrCorErrLogC {
2300 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb );
2302 /* Default value: 0x0000000000000000 */
2304 #define QIB_7322_PciePDataBufrCorErrLogA_offset 0x00000940UL
2305 struct QIB_7322_PciePDataBufrCorErrLogA_pb {
2306 pseudo_bit_t PciePDataBufrCorErrData_63_0[64];
2308 struct QIB_7322_PciePDataBufrCorErrLogA {
2309 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogA_pb );
2311 /* Default value: 0x0000000000000000 */
2313 #define QIB_7322_PciePDataBufrCorErrLogB_offset 0x00000948UL
2314 struct QIB_7322_PciePDataBufrCorErrLogB_pb {
2315 pseudo_bit_t PciePDataBufrCorErrData_127_64[64];
2317 struct QIB_7322_PciePDataBufrCorErrLogB {
2318 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogB_pb );
2320 /* Default value: 0x0000000000000000 */
2322 #define QIB_7322_PciePDataBufrCorErrLogC_offset 0x00000950UL
2323 struct QIB_7322_PciePDataBufrCorErrLogC_pb {
2324 pseudo_bit_t PciePDataBufrCorErrData_136_128[9];
2325 pseudo_bit_t PciePDataBufrCorErrCheckBit_21_0[22];
2326 pseudo_bit_t PciePDataBufrCorErrAddr_13_0[14];
2327 pseudo_bit_t _unused_0[19];
2329 struct QIB_7322_PciePDataBufrCorErrLogC {
2330 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogC_pb );
2332 /* Default value: 0x0000000000000000 */
2334 #define QIB_7322_PciePHdrBufrCorErrLogA_offset 0x00000960UL
2335 struct QIB_7322_PciePHdrBufrCorErrLogA_pb {
2336 pseudo_bit_t PciePHdrBufrCorErrData_63_0[64];
2338 struct QIB_7322_PciePHdrBufrCorErrLogA {
2339 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogA_pb );
2341 /* Default value: 0x0000000000000000 */
2343 #define QIB_7322_PciePHdrBufrCorErrLogB_offset 0x00000968UL
2344 struct QIB_7322_PciePHdrBufrCorErrLogB_pb {
2345 pseudo_bit_t PciePHdrBufrCorErrData_107_64[44];
2346 pseudo_bit_t _unused_0[20];
2348 struct QIB_7322_PciePHdrBufrCorErrLogB {
2349 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogB_pb );
2351 /* Default value: 0x0000000000000000 */
2353 #define QIB_7322_PciePHdrBufrCorErrLogC_offset 0x00000970UL
2354 struct QIB_7322_PciePHdrBufrCorErrLogC_pb {
2355 pseudo_bit_t PciePHdrBufrCorErrCheckBit_15_0[16];
2356 pseudo_bit_t PciePHdrBufrCorErrAddr_8_0[9];
2357 pseudo_bit_t _unused_0[39];
2359 struct QIB_7322_PciePHdrBufrCorErrLogC {
2360 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogC_pb );
2362 /* Default value: 0x0000000000000000 */
2364 #define QIB_7322_PcieRetryBufrCorErrLogA_offset 0x00000980UL
2365 struct QIB_7322_PcieRetryBufrCorErrLogA_pb {
2366 pseudo_bit_t PcieRetryBufrCorErrData_63_0[64];
2368 struct QIB_7322_PcieRetryBufrCorErrLogA {
2369 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogA_pb );
2371 /* Default value: 0x0000000000000000 */
2373 #define QIB_7322_PcieRetryBufrCorErrLogB_offset 0x00000988UL
2374 struct QIB_7322_PcieRetryBufrCorErrLogB_pb {
2375 pseudo_bit_t PcieRetryBufrCorErrData_127_64[64];
2377 struct QIB_7322_PcieRetryBufrCorErrLogB {
2378 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogB_pb );
2380 /* Default value: 0x0000000000000000 */
2382 #define QIB_7322_PcieRetryBufrCorErrLogC_offset 0x00000990UL
2383 struct QIB_7322_PcieRetryBufrCorErrLogC_pb {
2384 pseudo_bit_t PcieRetryBufrCorErrData_133_128[6];
2385 pseudo_bit_t PcieRetryBufrCorErrCheckBit_20_0[21];
2386 pseudo_bit_t PcieRetryBufrCorErrAddr_13_0[14];
2387 pseudo_bit_t _unused_0[23];
2389 struct QIB_7322_PcieRetryBufrCorErrLogC {
2390 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogC_pb );
2392 /* Default value: 0x0000000000000000 */
2394 #define QIB_7322_RxTIDArrayCorErrLogA_offset 0x00000a00UL
2395 struct QIB_7322_RxTIDArrayCorErrLogA_pb {
2396 pseudo_bit_t RxTIDArrayCorErrData_39_0[40];
2397 pseudo_bit_t RxTIDArrayCorErrCheckBit_11_0[12];
2398 pseudo_bit_t _unused_0[12];
2400 struct QIB_7322_RxTIDArrayCorErrLogA {
2401 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogA_pb );
2403 /* Default value: 0x0000000000000000 */
2405 #define QIB_7322_RxTIDArrayCorErrLogB_offset 0x00000a08UL
2406 struct QIB_7322_RxTIDArrayCorErrLogB_pb {
2407 pseudo_bit_t RxTIDArrayCorErrAddr_16_0[17];
2408 pseudo_bit_t _unused_0[47];
2410 struct QIB_7322_RxTIDArrayCorErrLogB {
2411 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogB_pb );
2413 /* Default value: 0x0000000000000000 */
2415 #define QIB_7322_RxEagerArrayCorErrLogA_offset 0x00000a10UL
2416 struct QIB_7322_RxEagerArrayCorErrLogA_pb {
2417 pseudo_bit_t RxEagerArrayCorErrData_39_0[40];
2418 pseudo_bit_t RxEagerArrayCorErrCheckBit_11_0[12];
2419 pseudo_bit_t _unused_0[12];
2421 struct QIB_7322_RxEagerArrayCorErrLogA {
2422 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogA_pb );
2424 /* Default value: 0x0000000000000000 */
2426 #define QIB_7322_RxEagerArrayCorErrLogB_offset 0x00000a18UL
2427 struct QIB_7322_RxEagerArrayCorErrLogB_pb {
2428 pseudo_bit_t RxEagerArrayCorErrAddr_17_0[18];
2429 pseudo_bit_t _unused_0[46];
2431 struct QIB_7322_RxEagerArrayCorErrLogB {
2432 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogB_pb );
2434 /* Default value: 0x0000000000000000 */
2436 #define QIB_7322_SBufMainArrayCorErrLogA_offset 0x00000a80UL
2437 struct QIB_7322_SBufMainArrayCorErrLogA_pb {
2438 pseudo_bit_t SBufMainArrayCorErrData_63_0[64];
2440 struct QIB_7322_SBufMainArrayCorErrLogA {
2441 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogA_pb );
2443 /* Default value: 0x0000000000000000 */
2445 #define QIB_7322_SBufMainArrayCorErrLogB_offset 0x00000a88UL
2446 struct QIB_7322_SBufMainArrayCorErrLogB_pb {
2447 pseudo_bit_t SBufMainArrayCorErrData_127_64[64];
2449 struct QIB_7322_SBufMainArrayCorErrLogB {
2450 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogB_pb );
2452 /* Default value: 0x0000000000000000 */
2454 #define QIB_7322_SBufMainArrayCorErrLogC_offset 0x00000a90UL
2455 struct QIB_7322_SBufMainArrayCorErrLogC_pb {
2456 pseudo_bit_t SBufMainArrayCorErrCheckBit_27_0[28];
2457 pseudo_bit_t SBufMainArrayCorErrAddr_18_0[19];
2458 pseudo_bit_t _unused_0[13];
2459 pseudo_bit_t SBufMainArrayCorErrDword_3_0[4];
2461 struct QIB_7322_SBufMainArrayCorErrLogC {
2462 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogC_pb );
2464 /* Default value: 0x0000000000000000 */
2466 #define QIB_7322_SBufExtraArrayCorErrLogA_offset 0x00000a98UL
2467 struct QIB_7322_SBufExtraArrayCorErrLogA_pb {
2468 pseudo_bit_t SBufExtraArrayCorErrData_63_0[64];
2470 struct QIB_7322_SBufExtraArrayCorErrLogA {
2471 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogA_pb );
2473 /* Default value: 0x0000000000000000 */
2475 #define QIB_7322_SBufExtraArrayCorErrLogB_offset 0x00000aa0UL
2476 struct QIB_7322_SBufExtraArrayCorErrLogB_pb {
2477 pseudo_bit_t SBufExtraArrayCorErrData_127_64[64];
2479 struct QIB_7322_SBufExtraArrayCorErrLogB {
2480 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogB_pb );
2482 /* Default value: 0x0000000000000000 */
2484 #define QIB_7322_SBufExtraArrayCorErrLogC_offset 0x00000aa8UL
2485 struct QIB_7322_SBufExtraArrayCorErrLogC_pb {
2486 pseudo_bit_t SBufExtraArrayCorErrCheckBit_27_0[28];
2487 pseudo_bit_t SBufExtraArrayCorErrAddr_14_0[15];
2488 pseudo_bit_t _unused_0[17];
2489 pseudo_bit_t SBufExtraArrayCorErrAdd_3_0[4];
2491 struct QIB_7322_SBufExtraArrayCorErrLogC {
2492 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogC_pb );
2494 /* Default value: 0x0000000000000000 */
2496 #define QIB_7322_SendPbcArrayCorErrLog_offset 0x00000ab0UL
2497 struct QIB_7322_SendPbcArrayCorErrLog_pb {
2498 pseudo_bit_t SendPbcArrayCorErrData_21_0[22];
2499 pseudo_bit_t SendPbcArrayCorErrCheckBit_6_0[7];
2500 pseudo_bit_t SendPbcArrayCorErrAddr_9_0[10];
2501 pseudo_bit_t _unused_0[25];
2503 struct QIB_7322_SendPbcArrayCorErrLog {
2504 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayCorErrLog_pb );
2506 /* Default value: 0x0000000000000000 */
2508 #define QIB_7322_SBufVL15ArrayCorErrLogA_offset 0x00000ac0UL
2509 struct QIB_7322_SBufVL15ArrayCorErrLogA_pb {
2510 pseudo_bit_t SBufVL15ArrayCorErrData_63_0[64];
2512 struct QIB_7322_SBufVL15ArrayCorErrLogA {
2513 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayCorErrLogA_pb );
2515 /* Default value: 0x0000000000000000 */
2517 #define QIB_7322_RcvAvailTimeOut0_offset 0x00000c00UL
2518 struct QIB_7322_RcvAvailTimeOut0_pb {
2519 pseudo_bit_t RcvAvailTOReload[16];
2520 pseudo_bit_t RcvAvailTOCount[16];
2521 pseudo_bit_t _unused_0[32];
2523 struct QIB_7322_RcvAvailTimeOut0 {
2524 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvAvailTimeOut0_pb );
2526 /* Default value: 0x0000000000000000 */
2528 #define QIB_7322_CntrRegBase_0_offset 0x00001028UL
2529 /* Default value: 0x0000000000012000 */
2531 #define QIB_7322_ErrMask_0_offset 0x00001080UL
2532 struct QIB_7322_ErrMask_0_pb {
2533 pseudo_bit_t RcvFormatErrMask[1];
2534 pseudo_bit_t RcvVCRCErrMask[1];
2535 pseudo_bit_t RcvICRCErrMask[1];
2536 pseudo_bit_t RcvMinPktLenErrMask[1];
2537 pseudo_bit_t RcvMaxPktLenErrMask[1];
2538 pseudo_bit_t RcvLongPktLenErrMask[1];
2539 pseudo_bit_t RcvShortPktLenErrMask[1];
2540 pseudo_bit_t RcvUnexpectedCharErrMask[1];
2541 pseudo_bit_t RcvUnsupportedVLErrMask[1];
2542 pseudo_bit_t RcvEBPErrMask[1];
2543 pseudo_bit_t RcvIBFlowErrMask[1];
2544 pseudo_bit_t RcvBadVersionErrMask[1];
2545 pseudo_bit_t _unused_0[2];
2546 pseudo_bit_t RcvBadTidErrMask[1];
2547 pseudo_bit_t RcvHdrLenErrMask[1];
2548 pseudo_bit_t RcvHdrErrMask[1];
2549 pseudo_bit_t RcvIBLostLinkErrMask[1];
2550 pseudo_bit_t _unused_1[11];
2551 pseudo_bit_t SendMinPktLenErrMask[1];
2552 pseudo_bit_t SendMaxPktLenErrMask[1];
2553 pseudo_bit_t SendUnderRunErrMask[1];
2554 pseudo_bit_t SendPktLenErrMask[1];
2555 pseudo_bit_t SendDroppedSmpPktErrMask[1];
2556 pseudo_bit_t SendDroppedDataPktErrMask[1];
2557 pseudo_bit_t _unused_2[1];
2558 pseudo_bit_t SendUnexpectedPktNumErrMask[1];
2559 pseudo_bit_t SendUnsupportedVLErrMask[1];
2560 pseudo_bit_t SendBufMisuseErrMask[1];
2561 pseudo_bit_t SDmaGenMismatchErrMask[1];
2562 pseudo_bit_t SDmaOutOfBoundErrMask[1];
2563 pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
2564 pseudo_bit_t SDmaBaseErrMask[1];
2565 pseudo_bit_t SDma1stDescErrMask[1];
2566 pseudo_bit_t SDmaRpyTagErrMask[1];
2567 pseudo_bit_t SDmaDwEnErrMask[1];
2568 pseudo_bit_t SDmaMissingDwErrMask[1];
2569 pseudo_bit_t SDmaUnexpDataErrMask[1];
2570 pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
2571 pseudo_bit_t SDmaHaltErrMask[1];
2572 pseudo_bit_t _unused_3[4];
2573 pseudo_bit_t VL15BufMisuseErrMask[1];
2574 pseudo_bit_t _unused_4[2];
2575 pseudo_bit_t SHeadersErrMask[1];
2576 pseudo_bit_t IBStatusChangedMask[1];
2577 pseudo_bit_t _unused_5[5];
2579 struct QIB_7322_ErrMask_0 {
2580 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_0_pb );
2582 /* Default value: 0x0000000000000000 */
2584 #define QIB_7322_ErrStatus_0_offset 0x00001088UL
2585 struct QIB_7322_ErrStatus_0_pb {
2586 pseudo_bit_t RcvFormatErr[1];
2587 pseudo_bit_t RcvVCRCErr[1];
2588 pseudo_bit_t RcvICRCErr[1];
2589 pseudo_bit_t RcvMinPktLenErr[1];
2590 pseudo_bit_t RcvMaxPktLenErr[1];
2591 pseudo_bit_t RcvLongPktLenErr[1];
2592 pseudo_bit_t RcvShortPktLenErr[1];
2593 pseudo_bit_t RcvUnexpectedCharErr[1];
2594 pseudo_bit_t RcvUnsupportedVLErr[1];
2595 pseudo_bit_t RcvEBPErr[1];
2596 pseudo_bit_t RcvIBFlowErr[1];
2597 pseudo_bit_t RcvBadVersionErr[1];
2598 pseudo_bit_t _unused_0[2];
2599 pseudo_bit_t RcvBadTidErr[1];
2600 pseudo_bit_t RcvHdrLenErr[1];
2601 pseudo_bit_t RcvHdrErr[1];
2602 pseudo_bit_t RcvIBLostLinkErr[1];
2603 pseudo_bit_t _unused_1[11];
2604 pseudo_bit_t SendMinPktLenErr[1];
2605 pseudo_bit_t SendMaxPktLenErr[1];
2606 pseudo_bit_t SendUnderRunErr[1];
2607 pseudo_bit_t SendPktLenErr[1];
2608 pseudo_bit_t SendDroppedSmpPktErr[1];
2609 pseudo_bit_t SendDroppedDataPktErr[1];
2610 pseudo_bit_t _unused_2[1];
2611 pseudo_bit_t SendUnexpectedPktNumErr[1];
2612 pseudo_bit_t SendUnsupportedVLErr[1];
2613 pseudo_bit_t SendBufMisuseErr[1];
2614 pseudo_bit_t SDmaGenMismatchErr[1];
2615 pseudo_bit_t SDmaOutOfBoundErr[1];
2616 pseudo_bit_t SDmaTailOutOfBoundErr[1];
2617 pseudo_bit_t SDmaBaseErr[1];
2618 pseudo_bit_t SDma1stDescErr[1];
2619 pseudo_bit_t SDmaRpyTagErr[1];
2620 pseudo_bit_t SDmaDwEnErr[1];
2621 pseudo_bit_t SDmaMissingDwErr[1];
2622 pseudo_bit_t SDmaUnexpDataErr[1];
2623 pseudo_bit_t SDmaDescAddrMisalignErr[1];
2624 pseudo_bit_t SDmaHaltErr[1];
2625 pseudo_bit_t _unused_3[4];
2626 pseudo_bit_t VL15BufMisuseErr[1];
2627 pseudo_bit_t _unused_4[2];
2628 pseudo_bit_t SHeadersErr[1];
2629 pseudo_bit_t IBStatusChanged[1];
2630 pseudo_bit_t _unused_5[5];
2632 struct QIB_7322_ErrStatus_0 {
2633 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_0_pb );
2635 /* Default value: 0x0000000000000000 */
2637 #define QIB_7322_ErrClear_0_offset 0x00001090UL
2638 struct QIB_7322_ErrClear_0_pb {
2639 pseudo_bit_t RcvFormatErrClear[1];
2640 pseudo_bit_t RcvVCRCErrClear[1];
2641 pseudo_bit_t RcvICRCErrClear[1];
2642 pseudo_bit_t RcvMinPktLenErrClear[1];
2643 pseudo_bit_t RcvMaxPktLenErrClear[1];
2644 pseudo_bit_t RcvLongPktLenErrClear[1];
2645 pseudo_bit_t RcvShortPktLenErrClear[1];
2646 pseudo_bit_t RcvUnexpectedCharErrClear[1];
2647 pseudo_bit_t RcvUnsupportedVLErrClear[1];
2648 pseudo_bit_t RcvEBPErrClear[1];
2649 pseudo_bit_t RcvIBFlowErrClear[1];
2650 pseudo_bit_t RcvBadVersionErrClear[1];
2651 pseudo_bit_t _unused_0[2];
2652 pseudo_bit_t RcvBadTidErrClear[1];
2653 pseudo_bit_t RcvHdrLenErrClear[1];
2654 pseudo_bit_t RcvHdrErrClear[1];
2655 pseudo_bit_t RcvIBLostLinkErrClear[1];
2656 pseudo_bit_t _unused_1[11];
2657 pseudo_bit_t SendMinPktLenErrClear[1];
2658 pseudo_bit_t SendMaxPktLenErrClear[1];
2659 pseudo_bit_t SendUnderRunErrClear[1];
2660 pseudo_bit_t SendPktLenErrClear[1];
2661 pseudo_bit_t SendDroppedSmpPktErrClear[1];
2662 pseudo_bit_t SendDroppedDataPktErrClear[1];
2663 pseudo_bit_t _unused_2[1];
2664 pseudo_bit_t SendUnexpectedPktNumErrClear[1];
2665 pseudo_bit_t SendUnsupportedVLErrClear[1];
2666 pseudo_bit_t SendBufMisuseErrClear[1];
2667 pseudo_bit_t SDmaGenMismatchErrClear[1];
2668 pseudo_bit_t SDmaOutOfBoundErrClear[1];
2669 pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
2670 pseudo_bit_t SDmaBaseErrClear[1];
2671 pseudo_bit_t SDma1stDescErrClear[1];
2672 pseudo_bit_t SDmaRpyTagErrClear[1];
2673 pseudo_bit_t SDmaDwEnErrClear[1];
2674 pseudo_bit_t SDmaMissingDwErrClear[1];
2675 pseudo_bit_t SDmaUnexpDataErrClear[1];
2676 pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
2677 pseudo_bit_t SDmaHaltErrClear[1];
2678 pseudo_bit_t _unused_3[4];
2679 pseudo_bit_t VL15BufMisuseErrClear[1];
2680 pseudo_bit_t _unused_4[2];
2681 pseudo_bit_t SHeadersErrClear[1];
2682 pseudo_bit_t IBStatusChangedClear[1];
2683 pseudo_bit_t _unused_5[5];
2685 struct QIB_7322_ErrClear_0 {
2686 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_0_pb );
2688 /* Default value: 0x0000000000000000 */
2690 #define QIB_7322_TXEStatus_0_offset 0x000010b8UL
2691 struct QIB_7322_TXEStatus_0_pb {
2692 pseudo_bit_t LaFifoEmpty_VL0[1];
2693 pseudo_bit_t LaFifoEmpty_VL1[1];
2694 pseudo_bit_t LaFifoEmpty_VL2[1];
2695 pseudo_bit_t LaFifoEmpty_VL3[1];
2696 pseudo_bit_t LaFifoEmpty_VL4[1];
2697 pseudo_bit_t LaFifoEmpty_VL5[1];
2698 pseudo_bit_t LaFifoEmpty_VL6[1];
2699 pseudo_bit_t LaFifoEmpty_VL7[1];
2700 pseudo_bit_t _unused_0[7];
2701 pseudo_bit_t LaFifoEmpty_VL15[1];
2702 pseudo_bit_t _unused_1[14];
2703 pseudo_bit_t RmFifoEmpty[1];
2704 pseudo_bit_t TXE_IBC_Idle[1];
2705 pseudo_bit_t _unused_2[32];
2707 struct QIB_7322_TXEStatus_0 {
2708 PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_0_pb );
2710 /* Default value: 0x0000000XC00080FF */
2712 #define QIB_7322_RcvCtrl_0_offset 0x00001100UL
2713 struct QIB_7322_RcvCtrl_0_pb {
2714 pseudo_bit_t ContextEnableKernel[1];
2715 pseudo_bit_t _unused_0[1];
2716 pseudo_bit_t ContextEnableUser[16];
2717 pseudo_bit_t _unused_1[21];
2718 pseudo_bit_t RcvIBPortEnable[1];
2719 pseudo_bit_t RcvQPMapEnable[1];
2720 pseudo_bit_t RcvPartitionKeyDisable[1];
2721 pseudo_bit_t RcvResetCredit[1];
2722 pseudo_bit_t _unused_2[21];
2724 struct QIB_7322_RcvCtrl_0 {
2725 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_0_pb );
2727 /* Default value: 0x0000000000000000 */
2729 #define QIB_7322_RcvBTHQP_0_offset 0x00001108UL
2730 struct QIB_7322_RcvBTHQP_0_pb {
2731 pseudo_bit_t RcvBTHQP[24];
2732 pseudo_bit_t _unused_0[40];
2734 struct QIB_7322_RcvBTHQP_0 {
2735 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_0_pb );
2737 /* Default value: 0x0000000000000000 */
2739 #define QIB_7322_RcvQPMapTableA_0_offset 0x00001110UL
2740 struct QIB_7322_RcvQPMapTableA_0_pb {
2741 pseudo_bit_t RcvQPMapContext0[5];
2742 pseudo_bit_t RcvQPMapContext1[5];
2743 pseudo_bit_t RcvQPMapContext2[5];
2744 pseudo_bit_t RcvQPMapContext3[5];
2745 pseudo_bit_t RcvQPMapContext4[5];
2746 pseudo_bit_t RcvQPMapContext5[5];
2747 pseudo_bit_t _unused_0[34];
2749 struct QIB_7322_RcvQPMapTableA_0 {
2750 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_0_pb );
2752 /* Default value: 0x0000000000000000 */
2754 #define QIB_7322_RcvQPMapTableB_0_offset 0x00001118UL
2755 struct QIB_7322_RcvQPMapTableB_0_pb {
2756 pseudo_bit_t RcvQPMapContext6[5];
2757 pseudo_bit_t RcvQPMapContext7[5];
2758 pseudo_bit_t RcvQPMapContext8[5];
2759 pseudo_bit_t RcvQPMapContext9[5];
2760 pseudo_bit_t RcvQPMapContext10[5];
2761 pseudo_bit_t RcvQPMapContext11[5];
2762 pseudo_bit_t _unused_0[34];
2764 struct QIB_7322_RcvQPMapTableB_0 {
2765 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_0_pb );
2767 /* Default value: 0x0000000000000000 */
2769 #define QIB_7322_RcvQPMapTableC_0_offset 0x00001120UL
2770 struct QIB_7322_RcvQPMapTableC_0_pb {
2771 pseudo_bit_t RcvQPMapContext12[5];
2772 pseudo_bit_t RcvQPMapContext13[5];
2773 pseudo_bit_t RcvQPMapContext14[5];
2774 pseudo_bit_t RcvQPMapContext15[5];
2775 pseudo_bit_t RcvQPMapContext16[5];
2776 pseudo_bit_t RcvQPMapContext17[5];
2777 pseudo_bit_t _unused_0[34];
2779 struct QIB_7322_RcvQPMapTableC_0 {
2780 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_0_pb );
2782 /* Default value: 0x0000000000000000 */
2784 #define QIB_7322_RcvQPMapTableD_0_offset 0x00001128UL
2785 struct QIB_7322_RcvQPMapTableD_0_pb {
2786 pseudo_bit_t RcvQPMapContext18[5];
2787 pseudo_bit_t RcvQPMapContext19[5];
2788 pseudo_bit_t RcvQPMapContext20[5];
2789 pseudo_bit_t RcvQPMapContext21[5];
2790 pseudo_bit_t RcvQPMapContext22[5];
2791 pseudo_bit_t RcvQPMapContext23[5];
2792 pseudo_bit_t _unused_0[34];
2794 struct QIB_7322_RcvQPMapTableD_0 {
2795 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_0_pb );
2797 /* Default value: 0x0000000000000000 */
2799 #define QIB_7322_RcvQPMapTableE_0_offset 0x00001130UL
2800 struct QIB_7322_RcvQPMapTableE_0_pb {
2801 pseudo_bit_t RcvQPMapContext24[5];
2802 pseudo_bit_t RcvQPMapContext25[5];
2803 pseudo_bit_t RcvQPMapContext26[5];
2804 pseudo_bit_t RcvQPMapContext27[5];
2805 pseudo_bit_t RcvQPMapContext28[5];
2806 pseudo_bit_t RcvQPMapContext29[5];
2807 pseudo_bit_t _unused_0[34];
2809 struct QIB_7322_RcvQPMapTableE_0 {
2810 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_0_pb );
2812 /* Default value: 0x0000000000000000 */
2814 #define QIB_7322_RcvQPMapTableF_0_offset 0x00001138UL
2815 struct QIB_7322_RcvQPMapTableF_0_pb {
2816 pseudo_bit_t RcvQPMapContext30[5];
2817 pseudo_bit_t RcvQPMapContext31[5];
2818 pseudo_bit_t _unused_0[54];
2820 struct QIB_7322_RcvQPMapTableF_0 {
2821 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_0_pb );
2823 /* Default value: 0x0000000000000000 */
2825 #define QIB_7322_PSStat_0_offset 0x00001140UL
2826 /* Default value: 0x0000000000000000 */
2828 #define QIB_7322_PSStart_0_offset 0x00001148UL
2829 /* Default value: 0x0000000000000000 */
2831 #define QIB_7322_PSInterval_0_offset 0x00001150UL
2832 /* Default value: 0x0000000000000000 */
2834 #define QIB_7322_RcvStatus_0_offset 0x00001160UL
2835 struct QIB_7322_RcvStatus_0_pb {
2836 pseudo_bit_t RxPktInProgress[1];
2837 pseudo_bit_t DmaeqBlockingContext[5];
2838 pseudo_bit_t _unused_0[58];
2840 struct QIB_7322_RcvStatus_0 {
2841 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_0_pb );
2843 /* Default value: 0x0000000000000000 */
2845 #define QIB_7322_RcvPartitionKey_0_offset 0x00001168UL
2846 /* Default value: 0x0000000000000000 */
2848 #define QIB_7322_RcvQPMulticastContext_0_offset 0x00001170UL
2849 struct QIB_7322_RcvQPMulticastContext_0_pb {
2850 pseudo_bit_t RcvQpMcContext[5];
2851 pseudo_bit_t _unused_0[59];
2853 struct QIB_7322_RcvQPMulticastContext_0 {
2854 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_0_pb );
2856 /* Default value: 0x0000000000000000 */
2858 #define QIB_7322_RcvPktLEDCnt_0_offset 0x00001178UL
2859 struct QIB_7322_RcvPktLEDCnt_0_pb {
2860 pseudo_bit_t OFFperiod[32];
2861 pseudo_bit_t ONperiod[32];
2863 struct QIB_7322_RcvPktLEDCnt_0 {
2864 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_0_pb );
2866 /* Default value: 0x0000000000000000 */
2868 #define QIB_7322_SendDmaIdleCnt_0_offset 0x00001180UL
2869 struct QIB_7322_SendDmaIdleCnt_0_pb {
2870 pseudo_bit_t SendDmaIdleCnt[16];
2871 pseudo_bit_t _unused_0[48];
2873 struct QIB_7322_SendDmaIdleCnt_0 {
2874 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_0_pb );
2876 /* Default value: 0x0000000000000000 */
2878 #define QIB_7322_SendDmaReloadCnt_0_offset 0x00001188UL
2879 struct QIB_7322_SendDmaReloadCnt_0_pb {
2880 pseudo_bit_t SendDmaReloadCnt[16];
2881 pseudo_bit_t _unused_0[48];
2883 struct QIB_7322_SendDmaReloadCnt_0 {
2884 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_0_pb );
2886 /* Default value: 0x0000000000000000 */
2888 #define QIB_7322_SendDmaDescCnt_0_offset 0x00001190UL
2889 struct QIB_7322_SendDmaDescCnt_0_pb {
2890 pseudo_bit_t SendDmaDescCnt[16];
2891 pseudo_bit_t _unused_0[48];
2893 struct QIB_7322_SendDmaDescCnt_0 {
2894 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_0_pb );
2896 /* Default value: 0x0000000000000000 */
2898 #define QIB_7322_SendCtrl_0_offset 0x000011c0UL
2899 struct QIB_7322_SendCtrl_0_pb {
2900 pseudo_bit_t TxeAbortIbc[1];
2901 pseudo_bit_t TxeBypassIbc[1];
2902 pseudo_bit_t _unused_0[1];
2903 pseudo_bit_t SendEnable[1];
2904 pseudo_bit_t _unused_1[3];
2905 pseudo_bit_t ForceCreditUpToDate[1];
2906 pseudo_bit_t SDmaCleanup[1];
2907 pseudo_bit_t SDmaIntEnable[1];
2908 pseudo_bit_t SDmaSingleDescriptor[1];
2909 pseudo_bit_t SDmaEnable[1];
2910 pseudo_bit_t SDmaHalt[1];
2911 pseudo_bit_t TxeDrainLaFifo[1];
2912 pseudo_bit_t TxeDrainRmFifo[1];
2913 pseudo_bit_t IBVLArbiterEn[1];
2914 pseudo_bit_t _unused_2[48];
2916 struct QIB_7322_SendCtrl_0 {
2917 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_0_pb );
2919 /* Default value: 0x0000000000000000 */
2921 #define QIB_7322_SendDmaBase_0_offset 0x000011f8UL
2922 struct QIB_7322_SendDmaBase_0_pb {
2923 pseudo_bit_t SendDmaBase[48];
2924 pseudo_bit_t _unused_0[16];
2926 struct QIB_7322_SendDmaBase_0 {
2927 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_0_pb );
2929 /* Default value: 0x0000000000000000 */
2931 #define QIB_7322_SendDmaLenGen_0_offset 0x00001200UL
2932 struct QIB_7322_SendDmaLenGen_0_pb {
2933 pseudo_bit_t Length[16];
2934 pseudo_bit_t Generation[3];
2935 pseudo_bit_t _unused_0[45];
2937 struct QIB_7322_SendDmaLenGen_0 {
2938 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_0_pb );
2940 /* Default value: 0x0000000000000000 */
2942 #define QIB_7322_SendDmaTail_0_offset 0x00001208UL
2943 struct QIB_7322_SendDmaTail_0_pb {
2944 pseudo_bit_t SendDmaTail[16];
2945 pseudo_bit_t _unused_0[48];
2947 struct QIB_7322_SendDmaTail_0 {
2948 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_0_pb );
2950 /* Default value: 0x0000000000000000 */
2952 #define QIB_7322_SendDmaHead_0_offset 0x00001210UL
2953 struct QIB_7322_SendDmaHead_0_pb {
2954 pseudo_bit_t SendDmaHead[16];
2955 pseudo_bit_t _unused_0[16];
2956 pseudo_bit_t InternalSendDmaHead[16];
2957 pseudo_bit_t _unused_1[16];
2959 struct QIB_7322_SendDmaHead_0 {
2960 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_0_pb );
2962 /* Default value: 0x0000000000000000 */
2964 #define QIB_7322_SendDmaHeadAddr_0_offset 0x00001218UL
2965 struct QIB_7322_SendDmaHeadAddr_0_pb {
2966 pseudo_bit_t SendDmaHeadAddr[48];
2967 pseudo_bit_t _unused_0[16];
2969 struct QIB_7322_SendDmaHeadAddr_0 {
2970 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_0_pb );
2972 /* Default value: 0x0000000000000000 */
2974 #define QIB_7322_SendDmaBufMask0_0_offset 0x00001220UL
2975 struct QIB_7322_SendDmaBufMask0_0_pb {
2976 pseudo_bit_t BufMask_63_0[64];
2978 struct QIB_7322_SendDmaBufMask0_0 {
2979 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_0_pb );
2981 /* Default value: 0x0000000000000000 */
2983 #define QIB_7322_SendDmaStatus_0_offset 0x00001238UL
2984 struct QIB_7322_SendDmaStatus_0_pb {
2985 pseudo_bit_t SplFifoDescIndex[16];
2986 pseudo_bit_t SplFifoBufNum[8];
2987 pseudo_bit_t SplFifoFull[1];
2988 pseudo_bit_t SplFifoEmpty[1];
2989 pseudo_bit_t SplFifoDisarmed[1];
2990 pseudo_bit_t SplFifoReadyToGo[1];
2991 pseudo_bit_t ScbFetchDescFlag[1];
2992 pseudo_bit_t ScbEntryValid[1];
2993 pseudo_bit_t ScbEmpty[1];
2994 pseudo_bit_t ScbFull[1];
2995 pseudo_bit_t RpyTag_7_0[8];
2996 pseudo_bit_t RpyLowAddr_6_0[7];
2997 pseudo_bit_t ScbDescIndex_13_0[14];
2998 pseudo_bit_t InternalSDmaHalt[1];
2999 pseudo_bit_t HaltInProg[1];
3000 pseudo_bit_t ScoreBoardDrainInProg[1];
3002 struct QIB_7322_SendDmaStatus_0 {
3003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_0_pb );
3005 /* Default value: 0x0000000042000000 */
3007 #define QIB_7322_SendDmaPriorityThld_0_offset 0x00001258UL
3008 struct QIB_7322_SendDmaPriorityThld_0_pb {
3009 pseudo_bit_t PriorityThreshold[4];
3010 pseudo_bit_t _unused_0[60];
3012 struct QIB_7322_SendDmaPriorityThld_0 {
3013 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_0_pb );
3015 /* Default value: 0x0000000000000000 */
3017 #define QIB_7322_SendHdrErrSymptom_0_offset 0x00001260UL
3018 struct QIB_7322_SendHdrErrSymptom_0_pb {
3019 pseudo_bit_t PacketTooSmall[1];
3020 pseudo_bit_t RawIPV6[1];
3021 pseudo_bit_t SLIDFail[1];
3022 pseudo_bit_t QPFail[1];
3023 pseudo_bit_t PkeyFail[1];
3024 pseudo_bit_t GRHFail[1];
3025 pseudo_bit_t NonKeyPacket[1];
3026 pseudo_bit_t _unused_0[57];
3028 struct QIB_7322_SendHdrErrSymptom_0 {
3029 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_0_pb );
3031 /* Default value: 0x0000000000000000 */
3033 #define QIB_7322_RxCreditVL0_0_offset 0x00001280UL
3034 struct QIB_7322_RxCreditVL0_0_pb {
3035 pseudo_bit_t RxMaxCreditVL[12];
3036 pseudo_bit_t _unused_0[4];
3037 pseudo_bit_t RxBufrConsumedVL[12];
3038 pseudo_bit_t _unused_1[36];
3040 struct QIB_7322_RxCreditVL0_0 {
3041 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_0_pb );
3043 /* Default value: 0x0000000000000000 */
3045 #define QIB_7322_SendDmaBufUsed0_0_offset 0x00001480UL
3046 struct QIB_7322_SendDmaBufUsed0_0_pb {
3047 pseudo_bit_t BufUsed_63_0[64];
3049 struct QIB_7322_SendDmaBufUsed0_0 {
3050 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_0_pb );
3052 /* Default value: 0x0000000000000000 */
3054 #define QIB_7322_SendDmaReqTagUsed_0_offset 0x00001498UL
3055 struct QIB_7322_SendDmaReqTagUsed_0_pb {
3056 pseudo_bit_t ReqTagUsed_7_0[8];
3057 pseudo_bit_t _unused_0[56];
3059 struct QIB_7322_SendDmaReqTagUsed_0 {
3060 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_0_pb );
3062 /* Default value: 0x0000000000000000 */
3064 #define QIB_7322_SendCheckControl_0_offset 0x000014a8UL
3065 struct QIB_7322_SendCheckControl_0_pb {
3066 pseudo_bit_t PacketTooSmall_En[1];
3067 pseudo_bit_t RawIPV6_En[1];
3068 pseudo_bit_t SLID_En[1];
3069 pseudo_bit_t BTHQP_En[1];
3070 pseudo_bit_t PKey_En[1];
3071 pseudo_bit_t _unused_0[59];
3073 struct QIB_7322_SendCheckControl_0 {
3074 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_0_pb );
3076 /* Default value: 0x0000000000000000 */
3078 #define QIB_7322_SendIBSLIDMask_0_offset 0x000014b0UL
3079 struct QIB_7322_SendIBSLIDMask_0_pb {
3080 pseudo_bit_t SendIBSLIDMask_15_0[16];
3081 pseudo_bit_t _unused_0[48];
3083 struct QIB_7322_SendIBSLIDMask_0 {
3084 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_0_pb );
3086 /* Default value: 0x0000000000000000 */
3088 #define QIB_7322_SendIBSLIDAssign_0_offset 0x000014b8UL
3089 struct QIB_7322_SendIBSLIDAssign_0_pb {
3090 pseudo_bit_t SendIBSLIDAssign_15_0[16];
3091 pseudo_bit_t _unused_0[48];
3093 struct QIB_7322_SendIBSLIDAssign_0 {
3094 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_0_pb );
3096 /* Default value: 0x0000000000000000 */
3098 #define QIB_7322_IBCStatusA_0_offset 0x00001540UL
3099 struct QIB_7322_IBCStatusA_0_pb {
3100 pseudo_bit_t LinkTrainingState[5];
3101 pseudo_bit_t LinkState[3];
3102 pseudo_bit_t LinkSpeedActive[1];
3103 pseudo_bit_t LinkWidthActive[1];
3104 pseudo_bit_t DDS_RXEQ_FAIL[1];
3105 pseudo_bit_t _unused_0[1];
3106 pseudo_bit_t IBRxLaneReversed[1];
3107 pseudo_bit_t IBTxLaneReversed[1];
3108 pseudo_bit_t ScrambleEn[1];
3109 pseudo_bit_t ScrambleCapRemote[1];
3110 pseudo_bit_t _unused_1[13];
3111 pseudo_bit_t LinkSpeedQDR[1];
3112 pseudo_bit_t TxReady[1];
3113 pseudo_bit_t _unused_2[1];
3114 pseudo_bit_t TxCreditOk_VL0[1];
3115 pseudo_bit_t TxCreditOk_VL1[1];
3116 pseudo_bit_t TxCreditOk_VL2[1];
3117 pseudo_bit_t TxCreditOk_VL3[1];
3118 pseudo_bit_t TxCreditOk_VL4[1];
3119 pseudo_bit_t TxCreditOk_VL5[1];
3120 pseudo_bit_t TxCreditOk_VL6[1];
3121 pseudo_bit_t TxCreditOk_VL7[1];
3122 pseudo_bit_t _unused_3[24];
3124 struct QIB_7322_IBCStatusA_0 {
3125 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_0_pb );
3127 /* Default value: 0x0000000000000X02 */
3129 #define QIB_7322_IBCStatusB_0_offset 0x00001548UL
3130 struct QIB_7322_IBCStatusB_0_pb {
3131 pseudo_bit_t LinkRoundTripLatency[26];
3132 pseudo_bit_t ReqDDSLocalFromRmt[4];
3133 pseudo_bit_t RxEqLocalDevice[2];
3134 pseudo_bit_t heartbeat_crosstalk[4];
3135 pseudo_bit_t heartbeat_timed_out[1];
3136 pseudo_bit_t ibsd_adaptation_timer_started[1];
3137 pseudo_bit_t ibsd_adaptation_timer_reached_threshold[1];
3138 pseudo_bit_t ibsd_adaptation_timer_debug[1];
3139 pseudo_bit_t _unused_0[24];
3141 struct QIB_7322_IBCStatusB_0 {
3142 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_0_pb );
3144 /* Default value: 0x00000000XXXXXXXX */
3146 #define QIB_7322_IBCCtrlA_0_offset 0x00001560UL
3147 struct QIB_7322_IBCCtrlA_0_pb {
3148 pseudo_bit_t FlowCtrlPeriod[8];
3149 pseudo_bit_t FlowCtrlWaterMark[8];
3150 pseudo_bit_t LinkInitCmd[3];
3151 pseudo_bit_t LinkCmd[2];
3152 pseudo_bit_t MaxPktLen[11];
3153 pseudo_bit_t PhyerrThreshold[4];
3154 pseudo_bit_t OverrunThreshold[4];
3155 pseudo_bit_t _unused_0[8];
3156 pseudo_bit_t NumVLane[3];
3157 pseudo_bit_t _unused_1[9];
3158 pseudo_bit_t IBStatIntReductionEn[1];
3159 pseudo_bit_t IBLinkEn[1];
3160 pseudo_bit_t LinkDownDefaultState[1];
3161 pseudo_bit_t Loopback[1];
3163 struct QIB_7322_IBCCtrlA_0 {
3164 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_0_pb );
3166 /* Default value: 0x0000000000000000 */
3168 #define QIB_7322_IBCCtrlB_0_offset 0x00001568UL
3169 struct QIB_7322_IBCCtrlB_0_pb {
3170 pseudo_bit_t IB_ENHANCED_MODE[1];
3171 pseudo_bit_t SD_SPEED[1];
3172 pseudo_bit_t SD_SPEED_SDR[1];
3173 pseudo_bit_t SD_SPEED_DDR[1];
3174 pseudo_bit_t SD_SPEED_QDR[1];
3175 pseudo_bit_t IB_NUM_CHANNELS[2];
3176 pseudo_bit_t IB_POLARITY_REV_SUPP[1];
3177 pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
3178 pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
3179 pseudo_bit_t SD_ADD_ENB[1];
3180 pseudo_bit_t SD_DDSV[1];
3181 pseudo_bit_t SD_DDS[4];
3182 pseudo_bit_t HRTBT_ENB[1];
3183 pseudo_bit_t HRTBT_AUTO[1];
3184 pseudo_bit_t HRTBT_PORT[8];
3185 pseudo_bit_t HRTBT_REQ[1];
3186 pseudo_bit_t IB_ENABLE_FILT_DPKT[1];
3187 pseudo_bit_t _unused_0[4];
3188 pseudo_bit_t IB_DLID[16];
3189 pseudo_bit_t IB_DLID_MASK[16];
3191 struct QIB_7322_IBCCtrlB_0 {
3192 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_0_pb );
3194 /* Default value: 0x00000000000305FF */
3196 #define QIB_7322_IBCCtrlC_0_offset 0x00001570UL
3197 struct QIB_7322_IBCCtrlC_0_pb {
3198 pseudo_bit_t IB_FRONT_PORCH[5];
3199 pseudo_bit_t IB_BACK_PORCH[5];
3200 pseudo_bit_t _unused_0[54];
3202 struct QIB_7322_IBCCtrlC_0 {
3203 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_0_pb );
3205 /* Default value: 0x0000000000000301 */
3207 #define QIB_7322_HRTBT_GUID_0_offset 0x00001588UL
3208 /* Default value: 0x0000000000000000 */
3210 #define QIB_7322_IB_SDTEST_IF_TX_0_offset 0x00001590UL
3211 struct QIB_7322_IB_SDTEST_IF_TX_0_pb {
3212 pseudo_bit_t TS_T_TX_VALID[1];
3213 pseudo_bit_t TS_3_TX_VALID[1];
3214 pseudo_bit_t VL_CAP[2];
3215 pseudo_bit_t CREDIT_CHANGE[1];
3216 pseudo_bit_t _unused_0[6];
3217 pseudo_bit_t TS_TX_OPCODE[2];
3218 pseudo_bit_t TS_TX_SPEED[3];
3219 pseudo_bit_t _unused_1[16];
3220 pseudo_bit_t TS_TX_TX_CFG[16];
3221 pseudo_bit_t TS_TX_RX_CFG[16];
3223 struct QIB_7322_IB_SDTEST_IF_TX_0 {
3224 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_0_pb );
3226 /* Default value: 0x0000000000000000 */
3228 #define QIB_7322_IB_SDTEST_IF_RX_0_offset 0x00001598UL
3229 struct QIB_7322_IB_SDTEST_IF_RX_0_pb {
3230 pseudo_bit_t TS_T_RX_VALID[1];
3231 pseudo_bit_t TS_3_RX_VALID[1];
3232 pseudo_bit_t _unused_0[14];
3233 pseudo_bit_t TS_RX_A[8];
3234 pseudo_bit_t TS_RX_B[8];
3235 pseudo_bit_t TS_RX_TX_CFG[16];
3236 pseudo_bit_t TS_RX_RX_CFG[16];
3238 struct QIB_7322_IB_SDTEST_IF_RX_0 {
3239 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_RX_0_pb );
3241 /* Default value: 0x0000000000000000 */
3243 #define QIB_7322_IBNCModeCtrl_0_offset 0x000015b8UL
3244 struct QIB_7322_IBNCModeCtrl_0_pb {
3245 pseudo_bit_t TSMEnable_send_TS1[1];
3246 pseudo_bit_t TSMEnable_send_TS2[1];
3247 pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1];
3248 pseudo_bit_t _unused_0[5];
3249 pseudo_bit_t TSMCode_TS1[9];
3250 pseudo_bit_t TSMCode_TS2[9];
3251 pseudo_bit_t _unused_1[6];
3252 pseudo_bit_t ScrambleCapLocal[1];
3253 pseudo_bit_t ScrambleCapRemoteMask[1];
3254 pseudo_bit_t ScrambleCapRemoteForce[1];
3255 pseudo_bit_t _unused_2[29];
3257 struct QIB_7322_IBNCModeCtrl_0 {
3258 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBNCModeCtrl_0_pb );
3260 /* Default value: 0x0000000000000000 */
3262 #define QIB_7322_IBSerdesStatus_0_offset 0x000015d0UL
3263 /* Default value: 0x0000000000000000 */
3265 #define QIB_7322_IBPCSConfig_0_offset 0x000015d8UL
3266 struct QIB_7322_IBPCSConfig_0_pb {
3267 pseudo_bit_t tx_rx_reset[1];
3268 pseudo_bit_t xcv_treset[1];
3269 pseudo_bit_t xcv_rreset[1];
3270 pseudo_bit_t _unused_0[6];
3271 pseudo_bit_t link_sync_mask[10];
3272 pseudo_bit_t _unused_1[45];
3274 struct QIB_7322_IBPCSConfig_0 {
3275 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBPCSConfig_0_pb );
3277 /* Default value: 0x0000000000000007 */
3279 #define QIB_7322_IBSerdesCtrl_0_offset 0x000015e0UL
3280 struct QIB_7322_IBSerdesCtrl_0_pb {
3281 pseudo_bit_t CMODE[7];
3282 pseudo_bit_t _unused_0[1];
3283 pseudo_bit_t TXIDLE[1];
3284 pseudo_bit_t RXPD[1];
3285 pseudo_bit_t TXPD[1];
3286 pseudo_bit_t PLLPD[1];
3287 pseudo_bit_t LPEN[1];
3288 pseudo_bit_t RXLOSEN[1];
3289 pseudo_bit_t _unused_1[1];
3290 pseudo_bit_t IB_LAT_MODE[1];
3291 pseudo_bit_t CGMODE[4];
3292 pseudo_bit_t CHANNEL_RESET_N[4];
3293 pseudo_bit_t DISABLE_RXLATOFF_SDR[1];
3294 pseudo_bit_t DISABLE_RXLATOFF_DDR[1];
3295 pseudo_bit_t DISABLE_RXLATOFF_QDR[1];
3296 pseudo_bit_t _unused_2[37];
3298 struct QIB_7322_IBSerdesCtrl_0 {
3299 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSerdesCtrl_0_pb );
3301 /* Default value: 0x0000000000FFA00F */
3303 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_offset 0x00001600UL
3304 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb {
3305 pseudo_bit_t txcn1_ena[3];
3306 pseudo_bit_t txcn1_xtra_emph0[2];
3307 pseudo_bit_t txcp1_ena[4];
3308 pseudo_bit_t txc0_ena[5];
3309 pseudo_bit_t txampcntl_d2a[4];
3310 pseudo_bit_t _unused_0[12];
3311 pseudo_bit_t reset_tx_deemphasis_override[1];
3312 pseudo_bit_t tx_override_deemphasis_select[1];
3313 pseudo_bit_t _unused_1[32];
3315 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0 {
3316 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb );
3318 /* Default value: 0x0000000000000000 */
3320 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_offset 0x00001640UL
3321 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb {
3322 pseudo_bit_t static_disable_rxenadfe_sdr_ch0[8];
3323 pseudo_bit_t static_disable_rxenadfe_sdr_ch1[8];
3324 pseudo_bit_t static_disable_rxenadfe_sdr_ch2[8];
3325 pseudo_bit_t static_disable_rxenadfe_sdr_ch3[8];
3326 pseudo_bit_t static_disable_rxenale_sdr_ch0[1];
3327 pseudo_bit_t static_disable_rxenale_sdr_ch1[1];
3328 pseudo_bit_t static_disable_rxenale_sdr_ch2[1];
3329 pseudo_bit_t static_disable_rxenale_sdr_ch3[1];
3330 pseudo_bit_t static_disable_rxenagain_sdr_ch0[1];
3331 pseudo_bit_t static_disable_rxenagain_sdr_ch1[1];
3332 pseudo_bit_t static_disable_rxenagain_sdr_ch2[1];
3333 pseudo_bit_t static_disable_rxenagain_sdr_ch3[1];
3334 pseudo_bit_t _unused_0[24];
3336 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0 {
3337 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb );
3339 /* Default value: 0x0000000000000000 */
3341 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_offset 0x00001648UL
3342 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb {
3343 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch0[8];
3344 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch1[8];
3345 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch2[8];
3346 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch3[8];
3347 pseudo_bit_t dyn_disable_rxenale_sdr_ch0[1];
3348 pseudo_bit_t dyn_disable_rxenale_sdr_ch1[1];
3349 pseudo_bit_t dyn_disable_rxenale_sdr_ch2[1];
3350 pseudo_bit_t dyn_disable_rxenale_sdr_ch3[1];
3351 pseudo_bit_t dyn_disable_rxenagain_sdr_ch0[1];
3352 pseudo_bit_t dyn_disable_rxenagain_sdr_ch1[1];
3353 pseudo_bit_t dyn_disable_rxenagain_sdr_ch2[1];
3354 pseudo_bit_t dyn_disable_rxenagain_sdr_ch3[1];
3355 pseudo_bit_t _unused_0[24];
3357 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0 {
3358 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb );
3360 /* Default value: 0x0000000000000000 */
3362 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_offset 0x00001650UL
3363 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb {
3364 pseudo_bit_t static_disable_rxenadfe_ddr_ch0[8];
3365 pseudo_bit_t static_disable_rxenadfe_ddr_ch1[8];
3366 pseudo_bit_t static_disable_rxenadfe_ddr_ch2[8];
3367 pseudo_bit_t static_disable_rxenadfe_ddr_ch3[8];
3368 pseudo_bit_t static_disable_rxenale_ddr_ch0[1];
3369 pseudo_bit_t static_disable_rxenale_ddr_ch1[1];
3370 pseudo_bit_t static_disable_rxenale_ddr_ch2[1];
3371 pseudo_bit_t static_disable_rxenale_ddr_ch3[1];
3372 pseudo_bit_t static_disable_rxenagain_ddr_ch0[1];
3373 pseudo_bit_t static_disable_rxenagain_ddr_ch1[1];
3374 pseudo_bit_t static_disable_rxenagain_ddr_ch2[1];
3375 pseudo_bit_t static_disable_rxenagain_ddr_ch3[1];
3376 pseudo_bit_t _unused_0[24];
3378 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0 {
3379 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb );
3381 /* Default value: 0x0000000000000000 */
3383 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_offset 0x00001658UL
3384 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb {
3385 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch0[8];
3386 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch1[8];
3387 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch2[8];
3388 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch3[8];
3389 pseudo_bit_t dyn_disable_rxenale_ddr_ch0[1];
3390 pseudo_bit_t dyn_disable_rxenale_ddr_ch1[1];
3391 pseudo_bit_t dyn_disable_rxenale_ddr_ch2[1];
3392 pseudo_bit_t dyn_disable_rxenale_ddr_ch3[1];
3393 pseudo_bit_t dyn_disable_rxenagain_ddr_ch0[1];
3394 pseudo_bit_t dyn_disable_rxenagain_ddr_ch1[1];
3395 pseudo_bit_t dyn_disable_rxenagain_ddr_ch2[1];
3396 pseudo_bit_t dyn_disable_rxenagain_ddr_ch3[1];
3397 pseudo_bit_t _unused_0[24];
3399 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0 {
3400 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb );
3402 /* Default value: 0x0000000000000000 */
3404 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_offset 0x00001660UL
3405 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb {
3406 pseudo_bit_t static_disable_rxenadfe_qdr_ch0[8];
3407 pseudo_bit_t static_disable_rxenadfe_qdr_ch1[8];
3408 pseudo_bit_t static_disable_rxenadfe_qdr_ch2[8];
3409 pseudo_bit_t static_disable_rxenadfe_qdr_ch3[8];
3410 pseudo_bit_t static_disable_rxenale_qdr_ch0[1];
3411 pseudo_bit_t static_disable_rxenale_qdr_ch1[1];
3412 pseudo_bit_t static_disable_rxenale_qdr_ch2[1];
3413 pseudo_bit_t static_disable_rxenale_qdr_ch3[1];
3414 pseudo_bit_t static_disable_rxenagain_qdr_ch0[1];
3415 pseudo_bit_t static_disable_rxenagain_qdr_ch1[1];
3416 pseudo_bit_t static_disable_rxenagain_qdr_ch2[1];
3417 pseudo_bit_t static_disable_rxenagain_qdr_ch3[1];
3418 pseudo_bit_t _unused_0[24];
3420 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0 {
3421 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb );
3423 /* Default value: 0x0000000000000000 */
3425 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_offset 0x00001668UL
3426 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb {
3427 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch0[8];
3428 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch1[8];
3429 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch2[8];
3430 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch3[8];
3431 pseudo_bit_t dyn_disable_rxenale_qdr_ch0[1];
3432 pseudo_bit_t dyn_disable_rxenale_qdr_ch1[1];
3433 pseudo_bit_t dyn_disable_rxenale_qdr_ch2[1];
3434 pseudo_bit_t dyn_disable_rxenale_qdr_ch3[1];
3435 pseudo_bit_t dyn_disable_rxenagain_qdr_ch0[1];
3436 pseudo_bit_t dyn_disable_rxenagain_qdr_ch1[1];
3437 pseudo_bit_t dyn_disable_rxenagain_qdr_ch2[1];
3438 pseudo_bit_t dyn_disable_rxenagain_qdr_ch3[1];
3439 pseudo_bit_t _unused_0[24];
3441 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0 {
3442 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb );
3444 /* Default value: 0x0000000000000000 */
3446 #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_offset 0x00001670UL
3447 /* Default value: 0x0000000000000000 */
3449 #define QIB_7322_RxBufrUnCorErrLogA_0_offset 0x00001800UL
3450 struct QIB_7322_RxBufrUnCorErrLogA_0_pb {
3451 pseudo_bit_t RxBufrUnCorErrData_63_0[64];
3453 struct QIB_7322_RxBufrUnCorErrLogA_0 {
3454 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogA_0_pb );
3456 /* Default value: 0x0000000000000000 */
3458 #define QIB_7322_RxBufrUnCorErrLogB_0_offset 0x00001808UL
3459 struct QIB_7322_RxBufrUnCorErrLogB_0_pb {
3460 pseudo_bit_t RxBufrUnCorErrData_127_64[64];
3462 struct QIB_7322_RxBufrUnCorErrLogB_0 {
3463 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogB_0_pb );
3465 /* Default value: 0x0000000000000000 */
3467 #define QIB_7322_RxBufrUnCorErrLogC_0_offset 0x00001810UL
3468 struct QIB_7322_RxBufrUnCorErrLogC_0_pb {
3469 pseudo_bit_t RxBufrUnCorErrData_191_128[64];
3471 struct QIB_7322_RxBufrUnCorErrLogC_0 {
3472 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogC_0_pb );
3474 /* Default value: 0x0000000000000000 */
3476 #define QIB_7322_RxBufrUnCorErrLogD_0_offset 0x00001818UL
3477 struct QIB_7322_RxBufrUnCorErrLogD_0_pb {
3478 pseudo_bit_t RxBufrUnCorErrData_255_192[64];
3480 struct QIB_7322_RxBufrUnCorErrLogD_0 {
3481 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogD_0_pb );
3483 /* Default value: 0x0000000000000000 */
3485 #define QIB_7322_RxBufrUnCorErrLogE_0_offset 0x00001820UL
3486 struct QIB_7322_RxBufrUnCorErrLogE_0_pb {
3487 pseudo_bit_t RxBufrUnCorErrData_258_256[3];
3488 pseudo_bit_t RxBufrUnCorErrCheckBit_36_0[37];
3489 pseudo_bit_t RxBufrUnCorErrAddr_15_0[16];
3490 pseudo_bit_t _unused_0[8];
3492 struct QIB_7322_RxBufrUnCorErrLogE_0 {
3493 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogE_0_pb );
3495 /* Default value: 0x0000000000000000 */
3497 #define QIB_7322_RxFlagUnCorErrLogA_0_offset 0x00001828UL
3498 struct QIB_7322_RxFlagUnCorErrLogA_0_pb {
3499 pseudo_bit_t RxFlagUnCorErrData_63_0[64];
3501 struct QIB_7322_RxFlagUnCorErrLogA_0 {
3502 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogA_0_pb );
3504 /* Default value: 0x0000000000000000 */
3506 #define QIB_7322_RxFlagUnCorErrLogB_0_offset 0x00001830UL
3507 struct QIB_7322_RxFlagUnCorErrLogB_0_pb {
3508 pseudo_bit_t RxFlagUnCorErrCheckBit_7_0[8];
3509 pseudo_bit_t RxFlagUnCorErrAddr_12_0[13];
3510 pseudo_bit_t _unused_0[43];
3512 struct QIB_7322_RxFlagUnCorErrLogB_0 {
3513 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogB_0_pb );
3515 /* Default value: 0x0000000000000000 */
3517 #define QIB_7322_RxLkupiqUnCorErrLogA_0_offset 0x00001840UL
3518 struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb {
3519 pseudo_bit_t RxLkupiqUnCorErrData_45_0[46];
3520 pseudo_bit_t RxLkupiqUnCorErrCheckBit_7_0[8];
3521 pseudo_bit_t _unused_0[10];
3523 struct QIB_7322_RxLkupiqUnCorErrLogA_0 {
3524 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb );
3526 /* Default value: 0x0000000000000000 */
3528 #define QIB_7322_RxLkupiqUnCorErrLogB_0_offset 0x00001848UL
3529 struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb {
3530 pseudo_bit_t RxLkupiqUnCorErrAddr_12_0[13];
3531 pseudo_bit_t _unused_0[51];
3533 struct QIB_7322_RxLkupiqUnCorErrLogB_0 {
3534 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb );
3536 /* Default value: 0x0000000000000000 */
3538 #define QIB_7322_RxHdrFifoUnCorErrLogA_0_offset 0x00001850UL
3539 struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb {
3540 pseudo_bit_t RxHdrFifoUnCorErrData_63_0[64];
3542 struct QIB_7322_RxHdrFifoUnCorErrLogA_0 {
3543 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb );
3545 /* Default value: 0x0000000000000000 */
3547 #define QIB_7322_RxHdrFifoUnCorErrLogB_0_offset 0x00001858UL
3548 struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb {
3549 pseudo_bit_t RxHdrFifoUnCorErrData_127_64[64];
3551 struct QIB_7322_RxHdrFifoUnCorErrLogB_0 {
3552 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb );
3554 /* Default value: 0x0000000000000000 */
3556 #define QIB_7322_RxHdrFifoUnCorErrLogC_0_offset 0x00001860UL
3557 struct QIB_7322_RxHdrFifoUnCorErrLogC_0_pb {
3558 pseudo_bit_t RxHdrFifoUnCorErrCheckBit_15_0[16];
3559 pseudo_bit_t RxHdrFifoUnCorErrAddr_10_0[11];
3560 pseudo_bit_t _unused_0[37];
3562 struct QIB_7322_RxHdrFifoUnCorErrLogC_0 {
3563 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogC_0_pb );
3565 /* Default value: 0x0000000000000000 */
3567 #define QIB_7322_RxDataFifoUnCorErrLogA_0_offset 0x00001868UL
3568 struct QIB_7322_RxDataFifoUnCorErrLogA_0_pb {
3569 pseudo_bit_t RxDataFifoUnCorErrData_63_0[64];
3571 struct QIB_7322_RxDataFifoUnCorErrLogA_0 {
3572 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogA_0_pb );
3574 /* Default value: 0x0000000000000000 */
3576 #define QIB_7322_RxDataFifoUnCorErrLogB_0_offset 0x00001870UL
3577 struct QIB_7322_RxDataFifoUnCorErrLogB_0_pb {
3578 pseudo_bit_t RxDataFifoUnCorErrData_127_64[64];
3580 struct QIB_7322_RxDataFifoUnCorErrLogB_0 {
3581 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogB_0_pb );
3583 /* Default value: 0x0000000000000000 */
3585 #define QIB_7322_RxDataFifoUnCorErrLogC_0_offset 0x00001878UL
3586 struct QIB_7322_RxDataFifoUnCorErrLogC_0_pb {
3587 pseudo_bit_t RxDataFifoUnCorErrCheckBit_15_0[16];
3588 pseudo_bit_t RxDataFifoUnCorErrAddr_10_0[11];
3589 pseudo_bit_t _unused_0[37];
3591 struct QIB_7322_RxDataFifoUnCorErrLogC_0 {
3592 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogC_0_pb );
3594 /* Default value: 0x0000000000000000 */
3596 #define QIB_7322_LaFifoArray0UnCorErrLog_0_offset 0x00001880UL
3597 struct QIB_7322_LaFifoArray0UnCorErrLog_0_pb {
3598 pseudo_bit_t LaFifoArray0UnCorErrData_34_0[35];
3599 pseudo_bit_t LaFifoArray0UnCorErrCheckBit_10_0[11];
3600 pseudo_bit_t LaFifoArray0UnCorErrAddr_10_0[11];
3601 pseudo_bit_t _unused_0[7];
3603 struct QIB_7322_LaFifoArray0UnCorErrLog_0 {
3604 PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0UnCorErrLog_0_pb );
3606 /* Default value: 0x0000000000000000 */
3608 #define QIB_7322_RmFifoArrayUnCorErrLogA_0_offset 0x000018c0UL
3609 struct QIB_7322_RmFifoArrayUnCorErrLogA_0_pb {
3610 pseudo_bit_t RmFifoArrayUnCorErrData_63_0[64];
3612 struct QIB_7322_RmFifoArrayUnCorErrLogA_0 {
3613 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogA_0_pb );
3615 /* Default value: 0x0000000000000000 */
3617 #define QIB_7322_RmFifoArrayUnCorErrLogB_0_offset 0x000018c8UL
3618 struct QIB_7322_RmFifoArrayUnCorErrLogB_0_pb {
3619 pseudo_bit_t RmFifoArrayUnCorErrData_127_64[64];
3621 struct QIB_7322_RmFifoArrayUnCorErrLogB_0 {
3622 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogB_0_pb );
3624 /* Default value: 0x0000000000000000 */
3626 #define QIB_7322_RmFifoArrayUnCorErrLogC_0_offset 0x000018d0UL
3627 struct QIB_7322_RmFifoArrayUnCorErrLogC_0_pb {
3628 pseudo_bit_t RmFifoArrayUnCorErrCheckBit_27_0[28];
3629 pseudo_bit_t RmFifoArrayUnCorErrAddr_13_0[14];
3630 pseudo_bit_t _unused_0[18];
3631 pseudo_bit_t RmFifoArrayUnCorErrDword_3_0[4];
3633 struct QIB_7322_RmFifoArrayUnCorErrLogC_0 {
3634 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogC_0_pb );
3636 /* Default value: 0x0000000000000000 */
3638 #define QIB_7322_RxBufrCorErrLogA_0_offset 0x00001900UL
3639 struct QIB_7322_RxBufrCorErrLogA_0_pb {
3640 pseudo_bit_t RxBufrCorErrData_63_0[64];
3642 struct QIB_7322_RxBufrCorErrLogA_0 {
3643 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogA_0_pb );
3645 /* Default value: 0x0000000000000000 */
3647 #define QIB_7322_RxBufrCorErrLogB_0_offset 0x00001908UL
3648 struct QIB_7322_RxBufrCorErrLogB_0_pb {
3649 pseudo_bit_t RxBufrCorErrData_127_64[64];
3651 struct QIB_7322_RxBufrCorErrLogB_0 {
3652 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogB_0_pb );
3654 /* Default value: 0x0000000000000000 */
3656 #define QIB_7322_RxBufrCorErrLogC_0_offset 0x00001910UL
3657 struct QIB_7322_RxBufrCorErrLogC_0_pb {
3658 pseudo_bit_t RxBufrCorErrData_191_128[64];
3660 struct QIB_7322_RxBufrCorErrLogC_0 {
3661 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogC_0_pb );
3663 /* Default value: 0x0000000000000000 */
3665 #define QIB_7322_RxBufrCorErrLogD_0_offset 0x00001918UL
3666 struct QIB_7322_RxBufrCorErrLogD_0_pb {
3667 pseudo_bit_t RxBufrCorErrData_255_192[64];
3669 struct QIB_7322_RxBufrCorErrLogD_0 {
3670 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogD_0_pb );
3672 /* Default value: 0x0000000000000000 */
3674 #define QIB_7322_RxBufrCorErrLogE_0_offset 0x00001920UL
3675 struct QIB_7322_RxBufrCorErrLogE_0_pb {
3676 pseudo_bit_t RxBufrCorErrData_258_256[3];
3677 pseudo_bit_t RxBufrCorErrCheckBit_36_0[37];
3678 pseudo_bit_t RxBufrCorErrAddr_15_0[16];
3679 pseudo_bit_t _unused_0[8];
3681 struct QIB_7322_RxBufrCorErrLogE_0 {
3682 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogE_0_pb );
3684 /* Default value: 0x0000000000000000 */
3686 #define QIB_7322_RxFlagCorErrLogA_0_offset 0x00001928UL
3687 struct QIB_7322_RxFlagCorErrLogA_0_pb {
3688 pseudo_bit_t RxFlagCorErrData_63_0[64];
3690 struct QIB_7322_RxFlagCorErrLogA_0 {
3691 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogA_0_pb );
3693 /* Default value: 0x0000000000000000 */
3695 #define QIB_7322_RxFlagCorErrLogB_0_offset 0x00001930UL
3696 struct QIB_7322_RxFlagCorErrLogB_0_pb {
3697 pseudo_bit_t RxFlagCorErrCheckBit_7_0[8];
3698 pseudo_bit_t RxFlagCorErrAddr_12_0[13];
3699 pseudo_bit_t _unused_0[43];
3701 struct QIB_7322_RxFlagCorErrLogB_0 {
3702 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogB_0_pb );
3704 /* Default value: 0x0000000000000000 */
3706 #define QIB_7322_RxLkupiqCorErrLogA_0_offset 0x00001940UL
3707 struct QIB_7322_RxLkupiqCorErrLogA_0_pb {
3708 pseudo_bit_t RxLkupiqCorErrData_45_0[46];
3709 pseudo_bit_t RxLkupiqCorErrCheckBit_7_0[8];
3710 pseudo_bit_t _unused_0[10];
3712 struct QIB_7322_RxLkupiqCorErrLogA_0 {
3713 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogA_0_pb );
3715 /* Default value: 0x0000000000000000 */
3717 #define QIB_7322_RxLkupiqCorErrLogB_0_offset 0x00001948UL
3718 struct QIB_7322_RxLkupiqCorErrLogB_0_pb {
3719 pseudo_bit_t RxLkupiqCorErrAddr_12_0[13];
3720 pseudo_bit_t _unused_0[51];
3722 struct QIB_7322_RxLkupiqCorErrLogB_0 {
3723 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogB_0_pb );
3725 /* Default value: 0x0000000000000000 */
3727 #define QIB_7322_RxHdrFifoCorErrLogA_0_offset 0x00001950UL
3728 struct QIB_7322_RxHdrFifoCorErrLogA_0_pb {
3729 pseudo_bit_t RxHdrFifoCorErrData_63_0[64];
3731 struct QIB_7322_RxHdrFifoCorErrLogA_0 {
3732 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogA_0_pb );
3734 /* Default value: 0x0000000000000000 */
3736 #define QIB_7322_RxHdrFifoCorErrLogB_0_offset 0x00001958UL
3737 struct QIB_7322_RxHdrFifoCorErrLogB_0_pb {
3738 pseudo_bit_t RxHdrFifoCorErrData_127_64[64];
3740 struct QIB_7322_RxHdrFifoCorErrLogB_0 {
3741 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogB_0_pb );
3743 /* Default value: 0x0000000000000000 */
3745 #define QIB_7322_RxHdrFifoCorErrLogC_0_offset 0x00001960UL
3746 struct QIB_7322_RxHdrFifoCorErrLogC_0_pb {
3747 pseudo_bit_t RxHdrFifoCorErrCheckBit_15_0[16];
3748 pseudo_bit_t RxHdrFifoCorErrAddr_10_0[11];
3749 pseudo_bit_t _unused_0[37];
3751 struct QIB_7322_RxHdrFifoCorErrLogC_0 {
3752 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogC_0_pb );
3754 /* Default value: 0x0000000000000000 */
3756 #define QIB_7322_RxDataFifoCorErrLogA_0_offset 0x00001968UL
3757 struct QIB_7322_RxDataFifoCorErrLogA_0_pb {
3758 pseudo_bit_t RxDataFifoCorErrData_63_0[64];
3760 struct QIB_7322_RxDataFifoCorErrLogA_0 {
3761 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogA_0_pb );
3763 /* Default value: 0x0000000000000000 */
3765 #define QIB_7322_RxDataFifoCorErrLogB_0_offset 0x00001970UL
3766 struct QIB_7322_RxDataFifoCorErrLogB_0_pb {
3767 pseudo_bit_t RxDataFifoCorErrData_127_64[64];
3769 struct QIB_7322_RxDataFifoCorErrLogB_0 {
3770 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogB_0_pb );
3772 /* Default value: 0x0000000000000000 */
3774 #define QIB_7322_RxDataFifoCorErrLogC_0_offset 0x00001978UL
3775 struct QIB_7322_RxDataFifoCorErrLogC_0_pb {
3776 pseudo_bit_t RxDataFifoCorErrCheckBit_15_0[16];
3777 pseudo_bit_t RxDataFifoCorErrAddr_10_0[11];
3778 pseudo_bit_t _unused_0[37];
3780 struct QIB_7322_RxDataFifoCorErrLogC_0 {
3781 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogC_0_pb );
3783 /* Default value: 0x0000000000000000 */
3785 #define QIB_7322_LaFifoArray0CorErrLog_0_offset 0x00001980UL
3786 struct QIB_7322_LaFifoArray0CorErrLog_0_pb {
3787 pseudo_bit_t LaFifoArray0CorErrData_34_0[35];
3788 pseudo_bit_t LaFifoArray0CorErrCheckBit_10_0[11];
3789 pseudo_bit_t LaFifoArray0CorErrAddr_10_0[11];
3790 pseudo_bit_t _unused_0[7];
3792 struct QIB_7322_LaFifoArray0CorErrLog_0 {
3793 PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0CorErrLog_0_pb );
3795 /* Default value: 0x0000000000000000 */
3797 #define QIB_7322_RmFifoArrayCorErrLogA_0_offset 0x000019c0UL
3798 struct QIB_7322_RmFifoArrayCorErrLogA_0_pb {
3799 pseudo_bit_t RmFifoArrayCorErrData_63_0[64];
3801 struct QIB_7322_RmFifoArrayCorErrLogA_0 {
3802 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogA_0_pb );
3804 /* Default value: 0x0000000000000000 */
3806 #define QIB_7322_RmFifoArrayCorErrLogB_0_offset 0x000019c8UL
3807 struct QIB_7322_RmFifoArrayCorErrLogB_0_pb {
3808 pseudo_bit_t RmFifoArrayCorErrData_127_64[64];
3810 struct QIB_7322_RmFifoArrayCorErrLogB_0 {
3811 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogB_0_pb );
3813 /* Default value: 0x0000000000000000 */
3815 #define QIB_7322_RmFifoArrayCorErrLogC_0_offset 0x000019d0UL
3816 struct QIB_7322_RmFifoArrayCorErrLogC_0_pb {
3817 pseudo_bit_t RmFifoArrayCorErrCheckBit_27_0[28];
3818 pseudo_bit_t RmFifoArrayCorErrAddr_13_0[14];
3819 pseudo_bit_t _unused_0[18];
3820 pseudo_bit_t RmFifoArrayCorErrDword_3_0[4];
3822 struct QIB_7322_RmFifoArrayCorErrLogC_0 {
3823 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogC_0_pb );
3825 /* Default value: 0x0000000000000000 */
3827 #define QIB_7322_HighPriorityLimit_0_offset 0x00001bc0UL
3828 struct QIB_7322_HighPriorityLimit_0_pb {
3829 pseudo_bit_t Limit[8];
3830 pseudo_bit_t _unused_0[56];
3832 struct QIB_7322_HighPriorityLimit_0 {
3833 PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriorityLimit_0_pb );
3835 /* Default value: 0x0000000000000000 */
3837 #define QIB_7322_LowPriority0_0_offset 0x00001c00UL
3838 struct QIB_7322_LowPriority0_0_pb {
3839 pseudo_bit_t Weight[8];
3840 pseudo_bit_t _unused_0[8];
3841 pseudo_bit_t VirtualLane[3];
3842 pseudo_bit_t _unused_1[45];
3844 struct QIB_7322_LowPriority0_0 {
3845 PSEUDO_BIT_STRUCT ( struct QIB_7322_LowPriority0_0_pb );
3847 /* Default value: 0x0000000000000000 */
3849 #define QIB_7322_HighPriority0_0_offset 0x00001e00UL
3850 struct QIB_7322_HighPriority0_0_pb {
3851 pseudo_bit_t Weight[8];
3852 pseudo_bit_t _unused_0[8];
3853 pseudo_bit_t VirtualLane[3];
3854 pseudo_bit_t _unused_1[45];
3856 struct QIB_7322_HighPriority0_0 {
3857 PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriority0_0_pb );
3859 /* Default value: 0x0000000000000000 */
3861 #define QIB_7322_CntrRegBase_1_offset 0x00002028UL
3862 /* Default value: 0x0000000000013000 */
3864 #define QIB_7322_ErrMask_1_offset 0x00002080UL
3865 struct QIB_7322_ErrMask_1_pb {
3866 pseudo_bit_t RcvFormatErrMask[1];
3867 pseudo_bit_t RcvVCRCErrMask[1];
3868 pseudo_bit_t RcvICRCErrMask[1];
3869 pseudo_bit_t RcvMinPktLenErrMask[1];
3870 pseudo_bit_t RcvMaxPktLenErrMask[1];
3871 pseudo_bit_t RcvLongPktLenErrMask[1];
3872 pseudo_bit_t RcvShortPktLenErrMask[1];
3873 pseudo_bit_t RcvUnexpectedCharErrMask[1];
3874 pseudo_bit_t RcvUnsupportedVLErrMask[1];
3875 pseudo_bit_t RcvEBPErrMask[1];
3876 pseudo_bit_t RcvIBFlowErrMask[1];
3877 pseudo_bit_t RcvBadVersionErrMask[1];
3878 pseudo_bit_t _unused_0[2];
3879 pseudo_bit_t RcvBadTidErrMask[1];
3880 pseudo_bit_t RcvHdrLenErrMask[1];
3881 pseudo_bit_t RcvHdrErrMask[1];
3882 pseudo_bit_t RcvIBLostLinkErrMask[1];
3883 pseudo_bit_t _unused_1[11];
3884 pseudo_bit_t SendMinPktLenErrMask[1];
3885 pseudo_bit_t SendMaxPktLenErrMask[1];
3886 pseudo_bit_t SendUnderRunErrMask[1];
3887 pseudo_bit_t SendPktLenErrMask[1];
3888 pseudo_bit_t SendDroppedSmpPktErrMask[1];
3889 pseudo_bit_t SendDroppedDataPktErrMask[1];
3890 pseudo_bit_t _unused_2[1];
3891 pseudo_bit_t SendUnexpectedPktNumErrMask[1];
3892 pseudo_bit_t SendUnsupportedVLErrMask[1];
3893 pseudo_bit_t SendBufMisuseErrMask[1];
3894 pseudo_bit_t SDmaGenMismatchErrMask[1];
3895 pseudo_bit_t SDmaOutOfBoundErrMask[1];
3896 pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
3897 pseudo_bit_t SDmaBaseErrMask[1];
3898 pseudo_bit_t SDma1stDescErrMask[1];
3899 pseudo_bit_t SDmaRpyTagErrMask[1];
3900 pseudo_bit_t SDmaDwEnErrMask[1];
3901 pseudo_bit_t SDmaMissingDwErrMask[1];
3902 pseudo_bit_t SDmaUnexpDataErrMask[1];
3903 pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
3904 pseudo_bit_t SDmaHaltErrMask[1];
3905 pseudo_bit_t _unused_3[4];
3906 pseudo_bit_t VL15BufMisuseErrMask[1];
3907 pseudo_bit_t _unused_4[2];
3908 pseudo_bit_t SHeadersErrMask[1];
3909 pseudo_bit_t IBStatusChangedMask[1];
3910 pseudo_bit_t _unused_5[5];
3912 struct QIB_7322_ErrMask_1 {
3913 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_1_pb );
3915 /* Default value: 0x0000000000000000 */
3917 #define QIB_7322_ErrStatus_1_offset 0x00002088UL
3918 struct QIB_7322_ErrStatus_1_pb {
3919 pseudo_bit_t RcvFormatErr[1];
3920 pseudo_bit_t RcvVCRCErr[1];
3921 pseudo_bit_t RcvICRCErr[1];
3922 pseudo_bit_t RcvMinPktLenErr[1];
3923 pseudo_bit_t RcvMaxPktLenErr[1];
3924 pseudo_bit_t RcvLongPktLenErr[1];
3925 pseudo_bit_t RcvShortPktLenErr[1];
3926 pseudo_bit_t RcvUnexpectedCharErr[1];
3927 pseudo_bit_t RcvUnsupportedVLErr[1];
3928 pseudo_bit_t RcvEBPErr[1];
3929 pseudo_bit_t RcvIBFlowErr[1];
3930 pseudo_bit_t RcvBadVersionErr[1];
3931 pseudo_bit_t _unused_0[2];
3932 pseudo_bit_t RcvBadTidErr[1];
3933 pseudo_bit_t RcvHdrLenErr[1];
3934 pseudo_bit_t RcvHdrErr[1];
3935 pseudo_bit_t RcvIBLostLinkErr[1];
3936 pseudo_bit_t _unused_1[11];
3937 pseudo_bit_t SendMinPktLenErr[1];
3938 pseudo_bit_t SendMaxPktLenErr[1];
3939 pseudo_bit_t SendUnderRunErr[1];
3940 pseudo_bit_t SendPktLenErr[1];
3941 pseudo_bit_t SendDroppedSmpPktErr[1];
3942 pseudo_bit_t SendDroppedDataPktErr[1];
3943 pseudo_bit_t _unused_2[1];
3944 pseudo_bit_t SendUnexpectedPktNumErr[1];
3945 pseudo_bit_t SendUnsupportedVLErr[1];
3946 pseudo_bit_t SendBufMisuseErr[1];
3947 pseudo_bit_t SDmaGenMismatchErr[1];
3948 pseudo_bit_t SDmaOutOfBoundErr[1];
3949 pseudo_bit_t SDmaTailOutOfBoundErr[1];
3950 pseudo_bit_t SDmaBaseErr[1];
3951 pseudo_bit_t SDma1stDescErr[1];
3952 pseudo_bit_t SDmaRpyTagErr[1];
3953 pseudo_bit_t SDmaDwEnErr[1];
3954 pseudo_bit_t SDmaMissingDwErr[1];
3955 pseudo_bit_t SDmaUnexpDataErr[1];
3956 pseudo_bit_t SDmaDescAddrMisalignErr[1];
3957 pseudo_bit_t SDmaHaltErr[1];
3958 pseudo_bit_t _unused_3[4];
3959 pseudo_bit_t VL15BufMisuseErr[1];
3960 pseudo_bit_t _unused_4[2];
3961 pseudo_bit_t SHeadersErr[1];
3962 pseudo_bit_t IBStatusChanged[1];
3963 pseudo_bit_t _unused_5[5];
3965 struct QIB_7322_ErrStatus_1 {
3966 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_1_pb );
3968 /* Default value: 0x0000000000000000 */
3970 #define QIB_7322_ErrClear_1_offset 0x00002090UL
3971 struct QIB_7322_ErrClear_1_pb {
3972 pseudo_bit_t RcvFormatErrClear[1];
3973 pseudo_bit_t RcvVCRCErrClear[1];
3974 pseudo_bit_t RcvICRCErrClear[1];
3975 pseudo_bit_t RcvMinPktLenErrClear[1];
3976 pseudo_bit_t RcvMaxPktLenErrClear[1];
3977 pseudo_bit_t RcvLongPktLenErrClear[1];
3978 pseudo_bit_t RcvShortPktLenErrClear[1];
3979 pseudo_bit_t RcvUnexpectedCharErrClear[1];
3980 pseudo_bit_t RcvUnsupportedVLErrClear[1];
3981 pseudo_bit_t RcvEBPErrClear[1];
3982 pseudo_bit_t RcvIBFlowErrClear[1];
3983 pseudo_bit_t RcvBadVersionErrClear[1];
3984 pseudo_bit_t _unused_0[2];
3985 pseudo_bit_t RcvBadTidErrClear[1];
3986 pseudo_bit_t RcvHdrLenErrClear[1];
3987 pseudo_bit_t RcvHdrErrClear[1];
3988 pseudo_bit_t RcvIBLostLinkErrClear[1];
3989 pseudo_bit_t _unused_1[11];
3990 pseudo_bit_t SendMinPktLenErrClear[1];
3991 pseudo_bit_t SendMaxPktLenErrClear[1];
3992 pseudo_bit_t SendUnderRunErrClear[1];
3993 pseudo_bit_t SendPktLenErrClear[1];
3994 pseudo_bit_t SendDroppedSmpPktErrClear[1];
3995 pseudo_bit_t SendDroppedDataPktErrClear[1];
3996 pseudo_bit_t _unused_2[1];
3997 pseudo_bit_t SendUnexpectedPktNumErrClear[1];
3998 pseudo_bit_t SendUnsupportedVLErrClear[1];
3999 pseudo_bit_t SendBufMisuseErrClear[1];
4000 pseudo_bit_t SDmaGenMismatchErrClear[1];
4001 pseudo_bit_t SDmaOutOfBoundErrClear[1];
4002 pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
4003 pseudo_bit_t SDmaBaseErrClear[1];
4004 pseudo_bit_t SDma1stDescErrClear[1];
4005 pseudo_bit_t SDmaRpyTagErrClear[1];
4006 pseudo_bit_t SDmaDwEnErrClear[1];
4007 pseudo_bit_t SDmaMissingDwErrClear[1];
4008 pseudo_bit_t SDmaUnexpDataErrClear[1];
4009 pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
4010 pseudo_bit_t SDmaHaltErrClear[1];
4011 pseudo_bit_t _unused_3[4];
4012 pseudo_bit_t VL15BufMisuseErrClear[1];
4013 pseudo_bit_t _unused_4[2];
4014 pseudo_bit_t SHeadersErrClear[1];
4015 pseudo_bit_t IBStatusChangedClear[1];
4016 pseudo_bit_t _unused_5[5];
4018 struct QIB_7322_ErrClear_1 {
4019 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_1_pb );
4021 /* Default value: 0x0000000000000000 */
4023 #define QIB_7322_TXEStatus_1_offset 0x000020b8UL
4024 struct QIB_7322_TXEStatus_1_pb {
4025 pseudo_bit_t LaFifoEmpty_VL0[1];
4026 pseudo_bit_t LaFifoEmpty_VL1[1];
4027 pseudo_bit_t LaFifoEmpty_VL2[1];
4028 pseudo_bit_t LaFifoEmpty_VL3[1];
4029 pseudo_bit_t LaFifoEmpty_VL4[1];
4030 pseudo_bit_t LaFifoEmpty_VL5[1];
4031 pseudo_bit_t LaFifoEmpty_VL6[1];
4032 pseudo_bit_t LaFifoEmpty_VL7[1];
4033 pseudo_bit_t _unused_0[7];
4034 pseudo_bit_t LaFifoEmpty_VL15[1];
4035 pseudo_bit_t _unused_1[14];
4036 pseudo_bit_t RmFifoEmpty[1];
4037 pseudo_bit_t TXE_IBC_Idle[1];
4038 pseudo_bit_t _unused_2[32];
4040 struct QIB_7322_TXEStatus_1 {
4041 PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_1_pb );
4043 /* Default value: 0x0000000XC00080FF */
4045 #define QIB_7322_RcvCtrl_1_offset 0x00002100UL
4046 struct QIB_7322_RcvCtrl_1_pb {
4047 pseudo_bit_t _unused_0[1];
4048 pseudo_bit_t ContextEnableKernel[1];
4049 pseudo_bit_t ContextEnableUser[16];
4050 pseudo_bit_t _unused_1[21];
4051 pseudo_bit_t RcvIBPortEnable[1];
4052 pseudo_bit_t RcvQPMapEnable[1];
4053 pseudo_bit_t RcvPartitionKeyDisable[1];
4054 pseudo_bit_t RcvResetCredit[1];
4055 pseudo_bit_t _unused_2[21];
4057 struct QIB_7322_RcvCtrl_1 {
4058 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_1_pb );
4060 /* Default value: 0x0000000000000000 */
4062 #define QIB_7322_RcvBTHQP_1_offset 0x00002108UL
4063 struct QIB_7322_RcvBTHQP_1_pb {
4064 pseudo_bit_t RcvBTHQP[24];
4065 pseudo_bit_t _unused_0[40];
4067 struct QIB_7322_RcvBTHQP_1 {
4068 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_1_pb );
4070 /* Default value: 0x0000000000000000 */
4072 #define QIB_7322_RcvQPMapTableA_1_offset 0x00002110UL
4073 struct QIB_7322_RcvQPMapTableA_1_pb {
4074 pseudo_bit_t RcvQPMapContext0[5];
4075 pseudo_bit_t RcvQPMapContext1[5];
4076 pseudo_bit_t RcvQPMapContext2[5];
4077 pseudo_bit_t RcvQPMapContext3[5];
4078 pseudo_bit_t RcvQPMapContext4[5];
4079 pseudo_bit_t RcvQPMapContext5[5];
4080 pseudo_bit_t _unused_0[34];
4082 struct QIB_7322_RcvQPMapTableA_1 {
4083 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_1_pb );
4085 /* Default value: 0x0000000000000000 */
4087 #define QIB_7322_RcvQPMapTableB_1_offset 0x00002118UL
4088 struct QIB_7322_RcvQPMapTableB_1_pb {
4089 pseudo_bit_t RcvQPMapContext6[5];
4090 pseudo_bit_t RcvQPMapContext7[5];
4091 pseudo_bit_t RcvQPMapContext8[5];
4092 pseudo_bit_t RcvQPMapContext9[5];
4093 pseudo_bit_t RcvQPMapContext10[5];
4094 pseudo_bit_t RcvQPMapContext11[5];
4095 pseudo_bit_t _unused_0[34];
4097 struct QIB_7322_RcvQPMapTableB_1 {
4098 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_1_pb );
4100 /* Default value: 0x0000000000000000 */
4102 #define QIB_7322_RcvQPMapTableC_1_offset 0x00002120UL
4103 struct QIB_7322_RcvQPMapTableC_1_pb {
4104 pseudo_bit_t RcvQPMapContext12[5];
4105 pseudo_bit_t RcvQPMapContext13[5];
4106 pseudo_bit_t RcvQPMapContext14[5];
4107 pseudo_bit_t RcvQPMapContext15[5];
4108 pseudo_bit_t RcvQPMapContext16[5];
4109 pseudo_bit_t RcvQPMapContext17[5];
4110 pseudo_bit_t _unused_0[34];
4112 struct QIB_7322_RcvQPMapTableC_1 {
4113 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_1_pb );
4115 /* Default value: 0x0000000000000000 */
4117 #define QIB_7322_RcvQPMapTableD_1_offset 0x00002128UL
4118 struct QIB_7322_RcvQPMapTableD_1_pb {
4119 pseudo_bit_t RcvQPMapContext18[5];
4120 pseudo_bit_t RcvQPMapContext19[5];
4121 pseudo_bit_t RcvQPMapContext20[5];
4122 pseudo_bit_t RcvQPMapContext21[5];
4123 pseudo_bit_t RcvQPMapContext22[5];
4124 pseudo_bit_t RcvQPMapContext23[5];
4125 pseudo_bit_t _unused_0[34];
4127 struct QIB_7322_RcvQPMapTableD_1 {
4128 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_1_pb );
4130 /* Default value: 0x0000000000000000 */
4132 #define QIB_7322_RcvQPMapTableE_1_offset 0x00002130UL
4133 struct QIB_7322_RcvQPMapTableE_1_pb {
4134 pseudo_bit_t RcvQPMapContext24[5];
4135 pseudo_bit_t RcvQPMapContext25[5];
4136 pseudo_bit_t RcvQPMapContext26[5];
4137 pseudo_bit_t RcvQPMapContext27[5];
4138 pseudo_bit_t RcvQPMapContext28[5];
4139 pseudo_bit_t RcvQPMapContext29[5];
4140 pseudo_bit_t _unused_0[34];
4142 struct QIB_7322_RcvQPMapTableE_1 {
4143 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_1_pb );
4145 /* Default value: 0x0000000000000000 */
4147 #define QIB_7322_RcvQPMapTableF_1_offset 0x00002138UL
4148 struct QIB_7322_RcvQPMapTableF_1_pb {
4149 pseudo_bit_t RcvQPMapContext30[5];
4150 pseudo_bit_t RcvQPMapContext31[5];
4151 pseudo_bit_t _unused_0[54];
4153 struct QIB_7322_RcvQPMapTableF_1 {
4154 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_1_pb );
4156 /* Default value: 0x0000000000000000 */
4158 #define QIB_7322_PSStat_1_offset 0x00002140UL
4159 /* Default value: 0x0000000000000000 */
4161 #define QIB_7322_PSStart_1_offset 0x00002148UL
4162 /* Default value: 0x0000000000000000 */
4164 #define QIB_7322_PSInterval_1_offset 0x00002150UL
4165 /* Default value: 0x0000000000000000 */
4167 #define QIB_7322_RcvStatus_1_offset 0x00002160UL
4168 struct QIB_7322_RcvStatus_1_pb {
4169 pseudo_bit_t RxPktInProgress[1];
4170 pseudo_bit_t DmaeqBlockingContext[5];
4171 pseudo_bit_t _unused_0[58];
4173 struct QIB_7322_RcvStatus_1 {
4174 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_1_pb );
4176 /* Default value: 0x0000000000000000 */
4178 #define QIB_7322_RcvPartitionKey_1_offset 0x00002168UL
4179 /* Default value: 0x0000000000000000 */
4181 #define QIB_7322_RcvQPMulticastContext_1_offset 0x00002170UL
4182 struct QIB_7322_RcvQPMulticastContext_1_pb {
4183 pseudo_bit_t RcvQpMcContext[5];
4184 pseudo_bit_t _unused_0[59];
4186 struct QIB_7322_RcvQPMulticastContext_1 {
4187 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_1_pb );
4189 /* Default value: 0x0000000000000000 */
4191 #define QIB_7322_RcvPktLEDCnt_1_offset 0x00002178UL
4192 struct QIB_7322_RcvPktLEDCnt_1_pb {
4193 pseudo_bit_t OFFperiod[32];
4194 pseudo_bit_t ONperiod[32];
4196 struct QIB_7322_RcvPktLEDCnt_1 {
4197 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_1_pb );
4199 /* Default value: 0x0000000000000000 */
4201 #define QIB_7322_SendDmaIdleCnt_1_offset 0x00002180UL
4202 struct QIB_7322_SendDmaIdleCnt_1_pb {
4203 pseudo_bit_t SendDmaIdleCnt[16];
4204 pseudo_bit_t _unused_0[48];
4206 struct QIB_7322_SendDmaIdleCnt_1 {
4207 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_1_pb );
4209 /* Default value: 0x0000000000000000 */
4211 #define QIB_7322_SendDmaReloadCnt_1_offset 0x00002188UL
4212 struct QIB_7322_SendDmaReloadCnt_1_pb {
4213 pseudo_bit_t SendDmaReloadCnt[16];
4214 pseudo_bit_t _unused_0[48];
4216 struct QIB_7322_SendDmaReloadCnt_1 {
4217 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_1_pb );
4219 /* Default value: 0x0000000000000000 */
4221 #define QIB_7322_SendDmaDescCnt_1_offset 0x00002190UL
4222 struct QIB_7322_SendDmaDescCnt_1_pb {
4223 pseudo_bit_t SendDmaDescCnt[16];
4224 pseudo_bit_t _unused_0[48];
4226 struct QIB_7322_SendDmaDescCnt_1 {
4227 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_1_pb );
4229 /* Default value: 0x0000000000000000 */
4231 #define QIB_7322_SendCtrl_1_offset 0x000021c0UL
4232 struct QIB_7322_SendCtrl_1_pb {
4233 pseudo_bit_t TxeAbortIbc[1];
4234 pseudo_bit_t TxeBypassIbc[1];
4235 pseudo_bit_t _unused_0[1];
4236 pseudo_bit_t SendEnable[1];
4237 pseudo_bit_t _unused_1[3];
4238 pseudo_bit_t ForceCreditUpToDate[1];
4239 pseudo_bit_t SDmaCleanup[1];
4240 pseudo_bit_t SDmaIntEnable[1];
4241 pseudo_bit_t SDmaSingleDescriptor[1];
4242 pseudo_bit_t SDmaEnable[1];
4243 pseudo_bit_t SDmaHalt[1];
4244 pseudo_bit_t TxeDrainLaFifo[1];
4245 pseudo_bit_t TxeDrainRmFifo[1];
4246 pseudo_bit_t IBVLArbiterEn[1];
4247 pseudo_bit_t _unused_2[48];
4249 struct QIB_7322_SendCtrl_1 {
4250 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_1_pb );
4252 /* Default value: 0x0000000000000000 */
4254 #define QIB_7322_SendDmaBase_1_offset 0x000021f8UL
4255 struct QIB_7322_SendDmaBase_1_pb {
4256 pseudo_bit_t SendDmaBase[48];
4257 pseudo_bit_t _unused_0[16];
4259 struct QIB_7322_SendDmaBase_1 {
4260 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_1_pb );
4262 /* Default value: 0x0000000000000000 */
4264 #define QIB_7322_SendDmaLenGen_1_offset 0x00002200UL
4265 struct QIB_7322_SendDmaLenGen_1_pb {
4266 pseudo_bit_t Length[16];
4267 pseudo_bit_t Generation[3];
4268 pseudo_bit_t _unused_0[45];
4270 struct QIB_7322_SendDmaLenGen_1 {
4271 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_1_pb );
4273 /* Default value: 0x0000000000000000 */
4275 #define QIB_7322_SendDmaTail_1_offset 0x00002208UL
4276 struct QIB_7322_SendDmaTail_1_pb {
4277 pseudo_bit_t SendDmaTail[16];
4278 pseudo_bit_t _unused_0[48];
4280 struct QIB_7322_SendDmaTail_1 {
4281 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_1_pb );
4283 /* Default value: 0x0000000000000000 */
4285 #define QIB_7322_SendDmaHead_1_offset 0x00002210UL
4286 struct QIB_7322_SendDmaHead_1_pb {
4287 pseudo_bit_t SendDmaHead[16];
4288 pseudo_bit_t _unused_0[16];
4289 pseudo_bit_t InternalSendDmaHead[16];
4290 pseudo_bit_t _unused_1[16];
4292 struct QIB_7322_SendDmaHead_1 {
4293 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_1_pb );
4295 /* Default value: 0x0000000000000000 */
4297 #define QIB_7322_SendDmaHeadAddr_1_offset 0x00002218UL
4298 struct QIB_7322_SendDmaHeadAddr_1_pb {
4299 pseudo_bit_t SendDmaHeadAddr[48];
4300 pseudo_bit_t _unused_0[16];
4302 struct QIB_7322_SendDmaHeadAddr_1 {
4303 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_1_pb );
4305 /* Default value: 0x0000000000000000 */
4307 #define QIB_7322_SendDmaBufMask0_1_offset 0x00002220UL
4308 struct QIB_7322_SendDmaBufMask0_1_pb {
4309 pseudo_bit_t BufMask_63_0[64];
4311 struct QIB_7322_SendDmaBufMask0_1 {
4312 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_1_pb );
4314 /* Default value: 0x0000000000000000 */
4316 #define QIB_7322_SendDmaStatus_1_offset 0x00002238UL
4317 struct QIB_7322_SendDmaStatus_1_pb {
4318 pseudo_bit_t SplFifoDescIndex[16];
4319 pseudo_bit_t SplFifoBufNum[8];
4320 pseudo_bit_t SplFifoFull[1];
4321 pseudo_bit_t SplFifoEmpty[1];
4322 pseudo_bit_t SplFifoDisarmed[1];
4323 pseudo_bit_t SplFifoReadyToGo[1];
4324 pseudo_bit_t ScbFetchDescFlag[1];
4325 pseudo_bit_t ScbEntryValid[1];
4326 pseudo_bit_t ScbEmpty[1];
4327 pseudo_bit_t ScbFull[1];
4328 pseudo_bit_t RpyTag_7_0[8];
4329 pseudo_bit_t RpyLowAddr_6_0[7];
4330 pseudo_bit_t ScbDescIndex_13_0[14];
4331 pseudo_bit_t InternalSDmaHalt[1];
4332 pseudo_bit_t HaltInProg[1];
4333 pseudo_bit_t ScoreBoardDrainInProg[1];
4335 struct QIB_7322_SendDmaStatus_1 {
4336 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_1_pb );
4338 /* Default value: 0x0000000042000000 */
4340 #define QIB_7322_SendDmaPriorityThld_1_offset 0x00002258UL
4341 struct QIB_7322_SendDmaPriorityThld_1_pb {
4342 pseudo_bit_t PriorityThreshold[4];
4343 pseudo_bit_t _unused_0[60];
4345 struct QIB_7322_SendDmaPriorityThld_1 {
4346 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_1_pb );
4348 /* Default value: 0x0000000000000000 */
4350 #define QIB_7322_SendHdrErrSymptom_1_offset 0x00002260UL
4351 struct QIB_7322_SendHdrErrSymptom_1_pb {
4352 pseudo_bit_t PacketTooSmall[1];
4353 pseudo_bit_t RawIPV6[1];
4354 pseudo_bit_t SLIDFail[1];
4355 pseudo_bit_t QPFail[1];
4356 pseudo_bit_t PkeyFail[1];
4357 pseudo_bit_t GRHFail[1];
4358 pseudo_bit_t NonKeyPacket[1];
4359 pseudo_bit_t _unused_0[57];
4361 struct QIB_7322_SendHdrErrSymptom_1 {
4362 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_1_pb );
4364 /* Default value: 0x0000000000000000 */
4366 #define QIB_7322_RxCreditVL0_1_offset 0x00002280UL
4367 struct QIB_7322_RxCreditVL0_1_pb {
4368 pseudo_bit_t RxMaxCreditVL[12];
4369 pseudo_bit_t _unused_0[4];
4370 pseudo_bit_t RxBufrConsumedVL[12];
4371 pseudo_bit_t _unused_1[36];
4373 struct QIB_7322_RxCreditVL0_1 {
4374 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_1_pb );
4376 /* Default value: 0x0000000000000000 */
4378 #define QIB_7322_SendDmaBufUsed0_1_offset 0x00002480UL
4379 struct QIB_7322_SendDmaBufUsed0_1_pb {
4380 pseudo_bit_t BufUsed_63_0[64];
4382 struct QIB_7322_SendDmaBufUsed0_1 {
4383 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_1_pb );
4385 /* Default value: 0x0000000000000000 */
4387 #define QIB_7322_SendDmaReqTagUsed_1_offset 0x00002498UL
4388 struct QIB_7322_SendDmaReqTagUsed_1_pb {
4389 pseudo_bit_t ReqTagUsed_7_0[8];
4390 pseudo_bit_t _unused_0[56];
4392 struct QIB_7322_SendDmaReqTagUsed_1 {
4393 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_1_pb );
4395 /* Default value: 0x0000000000000000 */
4397 #define QIB_7322_SendCheckControl_1_offset 0x000024a8UL
4398 struct QIB_7322_SendCheckControl_1_pb {
4399 pseudo_bit_t PacketTooSmall_En[1];
4400 pseudo_bit_t RawIPV6_En[1];
4401 pseudo_bit_t SLID_En[1];
4402 pseudo_bit_t BTHQP_En[1];
4403 pseudo_bit_t PKey_En[1];
4404 pseudo_bit_t _unused_0[59];
4406 struct QIB_7322_SendCheckControl_1 {
4407 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_1_pb );
4409 /* Default value: 0x0000000000000000 */
4411 #define QIB_7322_SendIBSLIDMask_1_offset 0x000024b0UL
4412 struct QIB_7322_SendIBSLIDMask_1_pb {
4413 pseudo_bit_t SendIBSLIDMask_15_0[16];
4414 pseudo_bit_t _unused_0[48];
4416 struct QIB_7322_SendIBSLIDMask_1 {
4417 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_1_pb );
4419 /* Default value: 0x0000000000000000 */
4421 #define QIB_7322_SendIBSLIDAssign_1_offset 0x000024b8UL
4422 struct QIB_7322_SendIBSLIDAssign_1_pb {
4423 pseudo_bit_t SendIBSLIDAssign_15_0[16];
4424 pseudo_bit_t _unused_0[48];
4426 struct QIB_7322_SendIBSLIDAssign_1 {
4427 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_1_pb );
4429 /* Default value: 0x0000000000000000 */
4431 #define QIB_7322_IBCStatusA_1_offset 0x00002540UL
4432 struct QIB_7322_IBCStatusA_1_pb {
4433 pseudo_bit_t LinkTrainingState[5];
4434 pseudo_bit_t LinkState[3];
4435 pseudo_bit_t LinkSpeedActive[1];
4436 pseudo_bit_t LinkWidthActive[1];
4437 pseudo_bit_t DDS_RXEQ_FAIL[1];
4438 pseudo_bit_t _unused_0[1];
4439 pseudo_bit_t IBRxLaneReversed[1];
4440 pseudo_bit_t IBTxLaneReversed[1];
4441 pseudo_bit_t ScrambleEn[1];
4442 pseudo_bit_t ScrambleCapRemote[1];
4443 pseudo_bit_t _unused_1[13];
4444 pseudo_bit_t LinkSpeedQDR[1];
4445 pseudo_bit_t TxReady[1];
4446 pseudo_bit_t _unused_2[1];
4447 pseudo_bit_t TxCreditOk_VL0[1];
4448 pseudo_bit_t TxCreditOk_VL1[1];
4449 pseudo_bit_t TxCreditOk_VL2[1];
4450 pseudo_bit_t TxCreditOk_VL3[1];
4451 pseudo_bit_t TxCreditOk_VL4[1];
4452 pseudo_bit_t TxCreditOk_VL5[1];
4453 pseudo_bit_t TxCreditOk_VL6[1];
4454 pseudo_bit_t TxCreditOk_VL7[1];
4455 pseudo_bit_t _unused_3[24];
4457 struct QIB_7322_IBCStatusA_1 {
4458 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_1_pb );
4460 /* Default value: 0x0000000000000X02 */
4462 #define QIB_7322_IBCStatusB_1_offset 0x00002548UL
4463 struct QIB_7322_IBCStatusB_1_pb {
4464 pseudo_bit_t LinkRoundTripLatency[26];
4465 pseudo_bit_t ReqDDSLocalFromRmt[4];
4466 pseudo_bit_t RxEqLocalDevice[2];
4467 pseudo_bit_t heartbeat_crosstalk[4];
4468 pseudo_bit_t heartbeat_timed_out[1];
4469 pseudo_bit_t _unused_0[27];
4471 struct QIB_7322_IBCStatusB_1 {
4472 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_1_pb );
4474 /* Default value: 0x00000000XXXXXXXX */
4476 #define QIB_7322_IBCCtrlA_1_offset 0x00002560UL
4477 struct QIB_7322_IBCCtrlA_1_pb {
4478 pseudo_bit_t FlowCtrlPeriod[8];
4479 pseudo_bit_t FlowCtrlWaterMark[8];
4480 pseudo_bit_t LinkInitCmd[3];
4481 pseudo_bit_t LinkCmd[2];
4482 pseudo_bit_t MaxPktLen[11];
4483 pseudo_bit_t PhyerrThreshold[4];
4484 pseudo_bit_t OverrunThreshold[4];
4485 pseudo_bit_t _unused_0[8];
4486 pseudo_bit_t NumVLane[3];
4487 pseudo_bit_t _unused_1[9];
4488 pseudo_bit_t IBStatIntReductionEn[1];
4489 pseudo_bit_t IBLinkEn[1];
4490 pseudo_bit_t LinkDownDefaultState[1];
4491 pseudo_bit_t Loopback[1];
4493 struct QIB_7322_IBCCtrlA_1 {
4494 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_1_pb );
4496 /* Default value: 0x0000000000000000 */
4498 #define QIB_7322_IBCCtrlB_1_offset 0x00002568UL
4499 struct QIB_7322_IBCCtrlB_1_pb {
4500 pseudo_bit_t IB_ENHANCED_MODE[1];
4501 pseudo_bit_t SD_SPEED[1];
4502 pseudo_bit_t SD_SPEED_SDR[1];
4503 pseudo_bit_t SD_SPEED_DDR[1];
4504 pseudo_bit_t SD_SPEED_QDR[1];
4505 pseudo_bit_t IB_NUM_CHANNELS[2];
4506 pseudo_bit_t IB_POLARITY_REV_SUPP[1];
4507 pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
4508 pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
4509 pseudo_bit_t SD_ADD_ENB[1];
4510 pseudo_bit_t SD_DDSV[1];
4511 pseudo_bit_t SD_DDS[4];
4512 pseudo_bit_t HRTBT_ENB[1];
4513 pseudo_bit_t HRTBT_AUTO[1];
4514 pseudo_bit_t HRTBT_PORT[8];
4515 pseudo_bit_t HRTBT_REQ[1];
4516 pseudo_bit_t IB_ENABLE_FILT_DPKT[1];
4517 pseudo_bit_t _unused_0[4];
4518 pseudo_bit_t IB_DLID[16];
4519 pseudo_bit_t IB_DLID_MASK[16];
4521 struct QIB_7322_IBCCtrlB_1 {
4522 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_1_pb );
4524 /* Default value: 0x00000000000305FF */
4526 #define QIB_7322_IBCCtrlC_1_offset 0x00002570UL
4527 struct QIB_7322_IBCCtrlC_1_pb {
4528 pseudo_bit_t IB_FRONT_PORCH[5];
4529 pseudo_bit_t IB_BACK_PORCH[5];
4530 pseudo_bit_t _unused_0[54];
4532 struct QIB_7322_IBCCtrlC_1 {
4533 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_1_pb );
4535 /* Default value: 0x0000000000000301 */
4537 #define QIB_7322_HRTBT_GUID_1_offset 0x00002588UL
4538 /* Default value: 0x0000000000000000 */
4540 #define QIB_7322_IB_SDTEST_IF_TX_1_offset 0x00002590UL
4541 struct QIB_7322_IB_SDTEST_IF_TX_1_pb {
4542 pseudo_bit_t TS_T_TX_VALID[1];
4543 pseudo_bit_t TS_3_TX_VALID[1];
4544 pseudo_bit_t VL_CAP[2];
4545 pseudo_bit_t CREDIT_CHANGE[1];
4546 pseudo_bit_t _unused_0[6];
4547 pseudo_bit_t TS_TX_OPCODE[2];
4548 pseudo_bit_t TS_TX_SPEED[3];
4549 pseudo_bit_t _unused_1[16];
4550 pseudo_bit_t TS_TX_TX_CFG[16];
4551 pseudo_bit_t TS_TX_RX_CFG[16];
4553 struct QIB_7322_IB_SDTEST_IF_TX_1 {
4554 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_1_pb );
4556 /* Default value: 0x0000000000000000 */
4558 #define QIB_7322_IB_SDTEST_IF_RX_1_offset 0x00002598UL
4559 struct QIB_7322_IB_SDTEST_IF_RX_1_pb {
4560 pseudo_bit_t TS_T_RX_VALID[1];
4561 pseudo_bit_t TS_3_RX_VALID[1];
4562 pseudo_bit_t _unused_0[14];
4563 pseudo_bit_t TS_RX_A[8];
4564 pseudo_bit_t TS_RX_B[8];
4565 pseudo_bit_t TS_RX_TX_CFG[16];
4566 pseudo_bit_t TS_RX_RX_CFG[16];
4568 struct QIB_7322_IB_SDTEST_IF_RX_1 {
4569 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_RX_1_pb );
4571 /* Default value: 0x0000000000000000 */
4573 #define QIB_7322_IBNCModeCtrl_1_offset 0x000025b8UL
4574 struct QIB_7322_IBNCModeCtrl_1_pb {
4575 pseudo_bit_t TSMEnable_send_TS1[1];
4576 pseudo_bit_t TSMEnable_send_TS2[1];
4577 pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1];
4578 pseudo_bit_t _unused_0[5];
4579 pseudo_bit_t TSMCode_TS1[9];
4580 pseudo_bit_t TSMCode_TS2[9];
4581 pseudo_bit_t _unused_1[6];
4582 pseudo_bit_t ScrambleCapLocal[1];
4583 pseudo_bit_t ScrambleCapRemoteMask[1];
4584 pseudo_bit_t ScrambleCapRemoteForce[1];
4585 pseudo_bit_t _unused_2[29];
4587 struct QIB_7322_IBNCModeCtrl_1 {
4588 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBNCModeCtrl_1_pb );
4590 /* Default value: 0x0000000000000000 */
4592 #define QIB_7322_IBSerdesStatus_1_offset 0x000025d0UL
4593 /* Default value: 0x0000000000000000 */
4595 #define QIB_7322_IBPCSConfig_1_offset 0x000025d8UL
4596 struct QIB_7322_IBPCSConfig_1_pb {
4597 pseudo_bit_t tx_rx_reset[1];
4598 pseudo_bit_t xcv_treset[1];
4599 pseudo_bit_t xcv_rreset[1];
4600 pseudo_bit_t _unused_0[6];
4601 pseudo_bit_t link_sync_mask[10];
4602 pseudo_bit_t _unused_1[45];
4604 struct QIB_7322_IBPCSConfig_1 {
4605 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBPCSConfig_1_pb );
4607 /* Default value: 0x0000000000000007 */
4609 #define QIB_7322_IBSerdesCtrl_1_offset 0x000025e0UL
4610 struct QIB_7322_IBSerdesCtrl_1_pb {
4611 pseudo_bit_t CMODE[7];
4612 pseudo_bit_t _unused_0[1];
4613 pseudo_bit_t TXIDLE[1];
4614 pseudo_bit_t RXPD[1];
4615 pseudo_bit_t TXPD[1];
4616 pseudo_bit_t PLLPD[1];
4617 pseudo_bit_t LPEN[1];
4618 pseudo_bit_t RXLOSEN[1];
4619 pseudo_bit_t _unused_1[1];
4620 pseudo_bit_t IB_LAT_MODE[1];
4621 pseudo_bit_t CGMODE[4];
4622 pseudo_bit_t CHANNEL_RESET_N[4];
4623 pseudo_bit_t DISABLE_RXLATOFF_SDR[1];
4624 pseudo_bit_t DISABLE_RXLATOFF_DDR[1];
4625 pseudo_bit_t DISABLE_RXLATOFF_QDR[1];
4626 pseudo_bit_t _unused_2[37];
4628 struct QIB_7322_IBSerdesCtrl_1 {
4629 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSerdesCtrl_1_pb );
4631 /* Default value: 0x0000000000FFA00F */
4633 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_offset 0x00002600UL
4634 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_pb {
4635 pseudo_bit_t txcn1_ena[3];
4636 pseudo_bit_t txcn1_xtra_emph0[2];
4637 pseudo_bit_t txcp1_ena[4];
4638 pseudo_bit_t txc0_ena[5];
4639 pseudo_bit_t txampcntl_d2a[4];
4640 pseudo_bit_t _unused_0[12];
4641 pseudo_bit_t reset_tx_deemphasis_override[1];
4642 pseudo_bit_t tx_override_deemphasis_select[1];
4643 pseudo_bit_t _unused_1[32];
4645 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1 {
4646 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_pb );
4648 /* Default value: 0x0000000000000000 */
4650 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_offset 0x00002640UL
4651 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_pb {
4652 pseudo_bit_t static_disable_rxenadfe_sdr_ch0[8];
4653 pseudo_bit_t static_disable_rxenadfe_sdr_ch1[8];
4654 pseudo_bit_t static_disable_rxenadfe_sdr_ch2[8];
4655 pseudo_bit_t static_disable_rxenadfe_sdr_ch3[8];
4656 pseudo_bit_t static_disable_rxenale_sdr_ch0[1];
4657 pseudo_bit_t static_disable_rxenale_sdr_ch1[1];
4658 pseudo_bit_t static_disable_rxenale_sdr_ch2[1];
4659 pseudo_bit_t static_disable_rxenale_sdr_ch3[1];
4660 pseudo_bit_t static_disable_rxenagain_sdr_ch0[1];
4661 pseudo_bit_t static_disable_rxenagain_sdr_ch1[1];
4662 pseudo_bit_t static_disable_rxenagain_sdr_ch2[1];
4663 pseudo_bit_t static_disable_rxenagain_sdr_ch3[1];
4664 pseudo_bit_t _unused_0[24];
4666 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1 {
4667 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_pb );
4669 /* Default value: 0x0000000000000000 */
4671 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_offset 0x00002648UL
4672 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_pb {
4673 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch0[8];
4674 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch1[8];
4675 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch2[8];
4676 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch3[8];
4677 pseudo_bit_t dyn_disable_rxenale_sdr_ch0[1];
4678 pseudo_bit_t dyn_disable_rxenale_sdr_ch1[1];
4679 pseudo_bit_t dyn_disable_rxenale_sdr_ch2[1];
4680 pseudo_bit_t dyn_disable_rxenale_sdr_ch3[1];
4681 pseudo_bit_t dyn_disable_rxenagain_sdr_ch0[1];
4682 pseudo_bit_t dyn_disable_rxenagain_sdr_ch1[1];
4683 pseudo_bit_t dyn_disable_rxenagain_sdr_ch2[1];
4684 pseudo_bit_t dyn_disable_rxenagain_sdr_ch3[1];
4685 pseudo_bit_t _unused_0[24];
4687 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1 {
4688 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_pb );
4690 /* Default value: 0x0000000000000000 */
4692 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_offset 0x00002650UL
4693 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_pb {
4694 pseudo_bit_t static_disable_rxenadfe_ddr_ch0[8];
4695 pseudo_bit_t static_disable_rxenadfe_ddr_ch1[8];
4696 pseudo_bit_t static_disable_rxenadfe_ddr_ch2[8];
4697 pseudo_bit_t static_disable_rxenadfe_ddr_ch3[8];
4698 pseudo_bit_t static_disable_rxenale_ddr_ch0[1];
4699 pseudo_bit_t static_disable_rxenale_ddr_ch1[1];
4700 pseudo_bit_t static_disable_rxenale_ddr_ch2[1];
4701 pseudo_bit_t static_disable_rxenale_ddr_ch3[1];
4702 pseudo_bit_t static_disable_rxenagain_ddr_ch0[1];
4703 pseudo_bit_t static_disable_rxenagain_ddr_ch1[1];
4704 pseudo_bit_t static_disable_rxenagain_ddr_ch2[1];
4705 pseudo_bit_t static_disable_rxenagain_ddr_ch3[1];
4706 pseudo_bit_t _unused_0[24];
4708 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1 {
4709 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_pb );
4711 /* Default value: 0x0000000000000000 */
4713 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_offset 0x00002658UL
4714 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_pb {
4715 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch0[8];
4716 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch1[8];
4717 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch2[8];
4718 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch3[8];
4719 pseudo_bit_t dyn_disable_rxenale_ddr_ch0[1];
4720 pseudo_bit_t dyn_disable_rxenale_ddr_ch1[1];
4721 pseudo_bit_t dyn_disable_rxenale_ddr_ch2[1];
4722 pseudo_bit_t dyn_disable_rxenale_ddr_ch3[1];
4723 pseudo_bit_t dyn_disable_rxenagain_ddr_ch0[1];
4724 pseudo_bit_t dyn_disable_rxenagain_ddr_ch1[1];
4725 pseudo_bit_t dyn_disable_rxenagain_ddr_ch2[1];
4726 pseudo_bit_t dyn_disable_rxenagain_ddr_ch3[1];
4727 pseudo_bit_t _unused_0[24];
4729 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1 {
4730 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_pb );
4732 /* Default value: 0x0000000000000000 */
4734 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_offset 0x00002660UL
4735 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_pb {
4736 pseudo_bit_t static_disable_rxenadfe_qdr_ch0[8];
4737 pseudo_bit_t static_disable_rxenadfe_qdr_ch1[8];
4738 pseudo_bit_t static_disable_rxenadfe_qdr_ch2[8];
4739 pseudo_bit_t static_disable_rxenadfe_qdr_ch3[8];
4740 pseudo_bit_t static_disable_rxenale_qdr_ch0[1];
4741 pseudo_bit_t static_disable_rxenale_qdr_ch1[1];
4742 pseudo_bit_t static_disable_rxenale_qdr_ch2[1];
4743 pseudo_bit_t static_disable_rxenale_qdr_ch3[1];
4744 pseudo_bit_t static_disable_rxenagain_qdr_ch0[1];
4745 pseudo_bit_t static_disable_rxenagain_qdr_ch1[1];
4746 pseudo_bit_t static_disable_rxenagain_qdr_ch2[1];
4747 pseudo_bit_t static_disable_rxenagain_qdr_ch3[1];
4748 pseudo_bit_t _unused_0[24];
4750 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1 {
4751 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_pb );
4753 /* Default value: 0x0000000000000000 */
4755 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_offset 0x00002668UL
4756 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_pb {
4757 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch0[8];
4758 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch1[8];
4759 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch2[8];
4760 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch3[8];
4761 pseudo_bit_t dyn_disable_rxenale_qdr_ch0[1];
4762 pseudo_bit_t dyn_disable_rxenale_qdr_ch1[1];
4763 pseudo_bit_t dyn_disable_rxenale_qdr_ch2[1];
4764 pseudo_bit_t dyn_disable_rxenale_qdr_ch3[1];
4765 pseudo_bit_t dyn_disable_rxenagain_qdr_ch0[1];
4766 pseudo_bit_t dyn_disable_rxenagain_qdr_ch1[1];
4767 pseudo_bit_t dyn_disable_rxenagain_qdr_ch2[1];
4768 pseudo_bit_t dyn_disable_rxenagain_qdr_ch3[1];
4769 pseudo_bit_t _unused_0[24];
4771 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1 {
4772 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_pb );
4774 /* Default value: 0x0000000000000000 */
4776 #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_1_offset 0x00002670UL
4777 /* Default value: 0x0000000000000000 */
4779 #define QIB_7322_RxBufrUnCorErrLogA_1_offset 0x00002800UL
4780 struct QIB_7322_RxBufrUnCorErrLogA_1_pb {
4781 pseudo_bit_t RxBufrUnCorErrData_63_0[64];
4783 struct QIB_7322_RxBufrUnCorErrLogA_1 {
4784 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogA_1_pb );
4786 /* Default value: 0x0000000000000000 */
4788 #define QIB_7322_RxBufrUnCorErrLogB_1_offset 0x00002808UL
4789 struct QIB_7322_RxBufrUnCorErrLogB_1_pb {
4790 pseudo_bit_t RxBufrUnCorErrData_127_64[64];
4792 struct QIB_7322_RxBufrUnCorErrLogB_1 {
4793 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogB_1_pb );
4795 /* Default value: 0x0000000000000000 */
4797 #define QIB_7322_RxBufrUnCorErrLogC_1_offset 0x00002810UL
4798 struct QIB_7322_RxBufrUnCorErrLogC_1_pb {
4799 pseudo_bit_t RxBufrUnCorErrData_191_128[64];
4801 struct QIB_7322_RxBufrUnCorErrLogC_1 {
4802 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogC_1_pb );
4804 /* Default value: 0x0000000000000000 */
4806 #define QIB_7322_RxBufrUnCorErrLogD_1_offset 0x00002818UL
4807 struct QIB_7322_RxBufrUnCorErrLogD_1_pb {
4808 pseudo_bit_t RxBufrUnCorErrData_255_192[64];
4810 struct QIB_7322_RxBufrUnCorErrLogD_1 {
4811 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogD_1_pb );
4813 /* Default value: 0x0000000000000000 */
4815 #define QIB_7322_RxBufrUnCorErrLogE_1_offset 0x00002820UL
4816 struct QIB_7322_RxBufrUnCorErrLogE_1_pb {
4817 pseudo_bit_t RxBufrUnCorErrData_258_256[3];
4818 pseudo_bit_t RxBufrUnCorErrCheckBit_36_0[37];
4819 pseudo_bit_t RxBufrUnCorErrAddr_15_0[16];
4820 pseudo_bit_t _unused_0[8];
4822 struct QIB_7322_RxBufrUnCorErrLogE_1 {
4823 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogE_1_pb );
4825 /* Default value: 0x0000000000000000 */
4827 #define QIB_7322_RxFlagUnCorErrLogA_1_offset 0x00002828UL
4828 struct QIB_7322_RxFlagUnCorErrLogA_1_pb {
4829 pseudo_bit_t RxFlagUnCorErrData_63_0[64];
4831 struct QIB_7322_RxFlagUnCorErrLogA_1 {
4832 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogA_1_pb );
4834 /* Default value: 0x0000000000000000 */
4836 #define QIB_7322_RxFlagUnCorErrLogB_1_offset 0x00002830UL
4837 struct QIB_7322_RxFlagUnCorErrLogB_1_pb {
4838 pseudo_bit_t RxFlagUnCorErrCheckBit_7_0[8];
4839 pseudo_bit_t RxFlagUnCorErrAddr_12_0[13];
4840 pseudo_bit_t _unused_0[43];
4842 struct QIB_7322_RxFlagUnCorErrLogB_1 {
4843 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogB_1_pb );
4845 /* Default value: 0x0000000000000000 */
4847 #define QIB_7322_RxLkupiqUnCorErrLogA_1_offset 0x00002840UL
4848 struct QIB_7322_RxLkupiqUnCorErrLogA_1_pb {
4849 pseudo_bit_t RxLkupiqUnCorErrData_45_0[46];
4850 pseudo_bit_t RxLkupiqUnCorErrCheckBit_7_0[8];
4851 pseudo_bit_t _unused_0[10];
4853 struct QIB_7322_RxLkupiqUnCorErrLogA_1 {
4854 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogA_1_pb );
4856 /* Default value: 0x0000000000000000 */
4858 #define QIB_7322_RxLkupiqUnCorErrLogB_1_offset 0x00002848UL
4859 struct QIB_7322_RxLkupiqUnCorErrLogB_1_pb {
4860 pseudo_bit_t RxLkupiqUnCorErrAddr_12_0[13];
4861 pseudo_bit_t _unused_0[51];
4863 struct QIB_7322_RxLkupiqUnCorErrLogB_1 {
4864 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogB_1_pb );
4866 /* Default value: 0x0000000000000000 */
4868 #define QIB_7322_RxHdrFifoUnCorErrLogA_1_offset 0x00002850UL
4869 struct QIB_7322_RxHdrFifoUnCorErrLogA_1_pb {
4870 pseudo_bit_t RxHdrFifoUnCorErrData_63_0[64];
4872 struct QIB_7322_RxHdrFifoUnCorErrLogA_1 {
4873 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogA_1_pb );
4875 /* Default value: 0x0000000000000000 */
4877 #define QIB_7322_RxHdrFifoUnCorErrLogB_1_offset 0x00002858UL
4878 struct QIB_7322_RxHdrFifoUnCorErrLogB_1_pb {
4879 pseudo_bit_t RxHdrFifoUnCorErrData_127_64[64];
4881 struct QIB_7322_RxHdrFifoUnCorErrLogB_1 {
4882 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogB_1_pb );
4884 /* Default value: 0x0000000000000000 */
4886 #define QIB_7322_RxHdrFifoUnCorErrLogC_1_offset 0x00002860UL
4887 struct QIB_7322_RxHdrFifoUnCorErrLogC_1_pb {
4888 pseudo_bit_t RxHdrFifoUnCorErrCheckBit_15_0[16];
4889 pseudo_bit_t RxHdrFifoUnCorErrAddr_10_0[11];
4890 pseudo_bit_t _unused_0[37];
4892 struct QIB_7322_RxHdrFifoUnCorErrLogC_1 {
4893 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogC_1_pb );
4895 /* Default value: 0x0000000000000000 */
4897 #define QIB_7322_RxDataFifoUnCorErrLogA_1_offset 0x00002868UL
4898 struct QIB_7322_RxDataFifoUnCorErrLogA_1_pb {
4899 pseudo_bit_t RxDataFifoUnCorErrData_63_0[64];
4901 struct QIB_7322_RxDataFifoUnCorErrLogA_1 {
4902 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogA_1_pb );
4904 /* Default value: 0x0000000000000000 */
4906 #define QIB_7322_RxDataFifoUnCorErrLogB_1_offset 0x00002870UL
4907 struct QIB_7322_RxDataFifoUnCorErrLogB_1_pb {
4908 pseudo_bit_t RxDataFifoUnCorErrData_127_64[64];
4910 struct QIB_7322_RxDataFifoUnCorErrLogB_1 {
4911 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogB_1_pb );
4913 /* Default value: 0x0000000000000000 */
4915 #define QIB_7322_RxDataFifoUnCorErrLogC_1_offset 0x00002878UL
4916 struct QIB_7322_RxDataFifoUnCorErrLogC_1_pb {
4917 pseudo_bit_t RxDataFifoUnCorErrCheckBit_15_0[16];
4918 pseudo_bit_t RxDataFifoUnCorErrAddr_10_0[11];
4919 pseudo_bit_t _unused_0[37];
4921 struct QIB_7322_RxDataFifoUnCorErrLogC_1 {
4922 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogC_1_pb );
4924 /* Default value: 0x0000000000000000 */
4926 #define QIB_7322_LaFifoArray0UnCorErrLog_1_offset 0x00002880UL
4927 struct QIB_7322_LaFifoArray0UnCorErrLog_1_pb {
4928 pseudo_bit_t LaFifoArray0UnCorErrData_34_0[35];
4929 pseudo_bit_t LaFifoArray0UnCorErrCheckBit_10_0[11];
4930 pseudo_bit_t LaFifoArray0UnCorErrAddr_10_0[11];
4931 pseudo_bit_t _unused_0[7];
4933 struct QIB_7322_LaFifoArray0UnCorErrLog_1 {
4934 PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0UnCorErrLog_1_pb );
4936 /* Default value: 0x0000000000000000 */
4938 #define QIB_7322_RmFifoArrayUnCorErrLogA_1_offset 0x000028c0UL
4939 struct QIB_7322_RmFifoArrayUnCorErrLogA_1_pb {
4940 pseudo_bit_t RmFifoArrayUnCorErrData_63_0[64];
4942 struct QIB_7322_RmFifoArrayUnCorErrLogA_1 {
4943 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogA_1_pb );
4945 /* Default value: 0x0000000000000000 */
4947 #define QIB_7322_RmFifoArrayUnCorErrLogB_1_offset 0x000028c8UL
4948 struct QIB_7322_RmFifoArrayUnCorErrLogB_1_pb {
4949 pseudo_bit_t RmFifoArrayUnCorErrData_127_64[64];
4951 struct QIB_7322_RmFifoArrayUnCorErrLogB_1 {
4952 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogB_1_pb );
4954 /* Default value: 0x0000000000000000 */
4956 #define QIB_7322_RmFifoArrayUnCorErrLogC_1_offset 0x000028d0UL
4957 struct QIB_7322_RmFifoArrayUnCorErrLogC_1_pb {
4958 pseudo_bit_t RmFifoArrayUnCorErrCheckBit_27_0[28];
4959 pseudo_bit_t RmFifoArrayUnCorErrAddr_13_0[14];
4960 pseudo_bit_t _unused_0[18];
4961 pseudo_bit_t RmFifoArrayUnCorErrDword_3_0[4];
4963 struct QIB_7322_RmFifoArrayUnCorErrLogC_1 {
4964 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogC_1_pb );
4966 /* Default value: 0x0000000000000000 */
4968 #define QIB_7322_RxBufrCorErrLogA_1_offset 0x00002900UL
4969 struct QIB_7322_RxBufrCorErrLogA_1_pb {
4970 pseudo_bit_t RxBufrCorErrData_63_0[64];
4972 struct QIB_7322_RxBufrCorErrLogA_1 {
4973 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogA_1_pb );
4975 /* Default value: 0x0000000000000000 */
4977 #define QIB_7322_RxBufrCorErrLogB_1_offset 0x00002908UL
4978 struct QIB_7322_RxBufrCorErrLogB_1_pb {
4979 pseudo_bit_t RxBufrCorErrData_127_64[64];
4981 struct QIB_7322_RxBufrCorErrLogB_1 {
4982 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogB_1_pb );
4984 /* Default value: 0x0000000000000000 */
4986 #define QIB_7322_RxBufrCorErrLogC_1_offset 0x00002910UL
4987 struct QIB_7322_RxBufrCorErrLogC_1_pb {
4988 pseudo_bit_t RxBufrCorErrData_191_128[64];
4990 struct QIB_7322_RxBufrCorErrLogC_1 {
4991 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogC_1_pb );
4993 /* Default value: 0x0000000000000000 */
4995 #define QIB_7322_RxBufrCorErrLogD_1_offset 0x00002918UL
4996 struct QIB_7322_RxBufrCorErrLogD_1_pb {
4997 pseudo_bit_t RxBufrCorErrData_255_192[64];
4999 struct QIB_7322_RxBufrCorErrLogD_1 {
5000 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogD_1_pb );
5002 /* Default value: 0x0000000000000000 */
5004 #define QIB_7322_RxBufrCorErrLogE_1_offset 0x00002920UL
5005 struct QIB_7322_RxBufrCorErrLogE_1_pb {
5006 pseudo_bit_t RxBufrCorErrData_258_256[3];
5007 pseudo_bit_t RxBufrCorErrCheckBit_36_0[37];
5008 pseudo_bit_t RxBufrCorErrAddr_15_0[16];
5009 pseudo_bit_t _unused_0[8];
5011 struct QIB_7322_RxBufrCorErrLogE_1 {
5012 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogE_1_pb );
5014 /* Default value: 0x0000000000000000 */
5016 #define QIB_7322_RxFlagCorErrLogA_1_offset 0x00002928UL
5017 struct QIB_7322_RxFlagCorErrLogA_1_pb {
5018 pseudo_bit_t RxFlagCorErrData_63_0[64];
5020 struct QIB_7322_RxFlagCorErrLogA_1 {
5021 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogA_1_pb );
5023 /* Default value: 0x0000000000000000 */
5025 #define QIB_7322_RxFlagCorErrLogB_1_offset 0x00002930UL
5026 struct QIB_7322_RxFlagCorErrLogB_1_pb {
5027 pseudo_bit_t RxFlagCorErrCheckBit_7_0[8];
5028 pseudo_bit_t RxFlagCorErrAddr_12_0[13];
5029 pseudo_bit_t _unused_0[43];
5031 struct QIB_7322_RxFlagCorErrLogB_1 {
5032 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogB_1_pb );
5034 /* Default value: 0x0000000000000000 */
5036 #define QIB_7322_RxLkupiqCorErrLogA_1_offset 0x00002940UL
5037 struct QIB_7322_RxLkupiqCorErrLogA_1_pb {
5038 pseudo_bit_t RxLkupiqCorErrData_45_0[46];
5039 pseudo_bit_t RxLkupiqCorErrCheckBit_7_0[8];
5040 pseudo_bit_t _unused_0[10];
5042 struct QIB_7322_RxLkupiqCorErrLogA_1 {
5043 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogA_1_pb );
5045 /* Default value: 0x0000000000000000 */
5047 #define QIB_7322_RxLkupiqCorErrLogB_1_offset 0x00002948UL
5048 struct QIB_7322_RxLkupiqCorErrLogB_1_pb {
5049 pseudo_bit_t RxLkupiqCorErrAddr_12_0[13];
5050 pseudo_bit_t _unused_0[51];
5052 struct QIB_7322_RxLkupiqCorErrLogB_1 {
5053 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogB_1_pb );
5055 /* Default value: 0x0000000000000000 */
5057 #define QIB_7322_RxHdrFifoCorErrLogA_1_offset 0x00002950UL
5058 struct QIB_7322_RxHdrFifoCorErrLogA_1_pb {
5059 pseudo_bit_t RxHdrFifoCorErrData_63_0[64];
5061 struct QIB_7322_RxHdrFifoCorErrLogA_1 {
5062 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogA_1_pb );
5064 /* Default value: 0x0000000000000000 */
5066 #define QIB_7322_RxHdrFifoCorErrLogB_1_offset 0x00002958UL
5067 struct QIB_7322_RxHdrFifoCorErrLogB_1_pb {
5068 pseudo_bit_t RxHdrFifoCorErrData_127_64[64];
5070 struct QIB_7322_RxHdrFifoCorErrLogB_1 {
5071 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogB_1_pb );
5073 /* Default value: 0x0000000000000000 */
5075 #define QIB_7322_RxHdrFifoCorErrLogC_1_offset 0x00002960UL
5076 struct QIB_7322_RxHdrFifoCorErrLogC_1_pb {
5077 pseudo_bit_t RxHdrFifoCorErrCheckBit_15_0[16];
5078 pseudo_bit_t RxHdrFifoCorErrAddr_10_0[11];
5079 pseudo_bit_t _unused_0[37];
5081 struct QIB_7322_RxHdrFifoCorErrLogC_1 {
5082 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogC_1_pb );
5084 /* Default value: 0x0000000000000000 */
5086 #define QIB_7322_RxDataFifoCorErrLogA_1_offset 0x00002968UL
5087 struct QIB_7322_RxDataFifoCorErrLogA_1_pb {
5088 pseudo_bit_t RxDataFifoCorErrData_63_0[64];
5090 struct QIB_7322_RxDataFifoCorErrLogA_1 {
5091 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogA_1_pb );
5093 /* Default value: 0x0000000000000000 */
5095 #define QIB_7322_RxDataFifoCorErrLogB_1_offset 0x00002970UL
5096 struct QIB_7322_RxDataFifoCorErrLogB_1_pb {
5097 pseudo_bit_t RxDataFifoCorErrData_127_64[64];
5099 struct QIB_7322_RxDataFifoCorErrLogB_1 {
5100 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogB_1_pb );
5102 /* Default value: 0x0000000000000000 */
5104 #define QIB_7322_RxDataFifoCorErrLogC_1_offset 0x00002978UL
5105 struct QIB_7322_RxDataFifoCorErrLogC_1_pb {
5106 pseudo_bit_t RxDataFifoCorErrCheckBit_15_0[16];
5107 pseudo_bit_t RxDataFifoCorErrAddr_10_0[11];
5108 pseudo_bit_t _unused_0[37];
5110 struct QIB_7322_RxDataFifoCorErrLogC_1 {
5111 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogC_1_pb );
5113 /* Default value: 0x0000000000000000 */
5115 #define QIB_7322_LaFifoArray0CorErrLog_1_offset 0x00002980UL
5116 struct QIB_7322_LaFifoArray0CorErrLog_1_pb {
5117 pseudo_bit_t LaFifoArray0CorErrData_34_0[35];
5118 pseudo_bit_t LaFifoArray0CorErrCheckBit_10_0[11];
5119 pseudo_bit_t LaFifoArray0CorErrAddr_10_0[11];
5120 pseudo_bit_t _unused_0[7];
5122 struct QIB_7322_LaFifoArray0CorErrLog_1 {
5123 PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0CorErrLog_1_pb );
5125 /* Default value: 0x0000000000000000 */
5127 #define QIB_7322_RmFifoArrayCorErrLogA_1_offset 0x000029c0UL
5128 struct QIB_7322_RmFifoArrayCorErrLogA_1_pb {
5129 pseudo_bit_t RmFifoArrayCorErrData_63_0[64];
5131 struct QIB_7322_RmFifoArrayCorErrLogA_1 {
5132 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogA_1_pb );
5134 /* Default value: 0x0000000000000000 */
5136 #define QIB_7322_RmFifoArrayCorErrLogB_1_offset 0x000029c8UL
5137 struct QIB_7322_RmFifoArrayCorErrLogB_1_pb {
5138 pseudo_bit_t RmFifoArrayCorErrData_127_64[64];
5140 struct QIB_7322_RmFifoArrayCorErrLogB_1 {
5141 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogB_1_pb );
5143 /* Default value: 0x0000000000000000 */
5145 #define QIB_7322_RmFifoArrayCorErrLogC_1_offset 0x000029d0UL
5146 struct QIB_7322_RmFifoArrayCorErrLogC_1_pb {
5147 pseudo_bit_t RmFifoArrayCorErrCheckBit_27_0[28];
5148 pseudo_bit_t RmFifoArrayCorErrAddr_13_0[14];
5149 pseudo_bit_t _unused_0[18];
5150 pseudo_bit_t RmFifoArrayCorErrDword_3_0[4];
5152 struct QIB_7322_RmFifoArrayCorErrLogC_1 {
5153 PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogC_1_pb );
5155 /* Default value: 0x0000000000000000 */
5157 #define QIB_7322_HighPriorityLimit_1_offset 0x00002bc0UL
5158 struct QIB_7322_HighPriorityLimit_1_pb {
5159 pseudo_bit_t Limit[8];
5160 pseudo_bit_t _unused_0[56];
5162 struct QIB_7322_HighPriorityLimit_1 {
5163 PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriorityLimit_1_pb );
5165 /* Default value: 0x0000000000000000 */
5167 #define QIB_7322_LowPriority0_1_offset 0x00002c00UL
5168 struct QIB_7322_LowPriority0_1_pb {
5169 pseudo_bit_t Weight[8];
5170 pseudo_bit_t _unused_0[8];
5171 pseudo_bit_t VirtualLane[3];
5172 pseudo_bit_t _unused_1[45];
5174 struct QIB_7322_LowPriority0_1 {
5175 PSEUDO_BIT_STRUCT ( struct QIB_7322_LowPriority0_1_pb );
5177 /* Default value: 0x0000000000000000 */
5179 #define QIB_7322_HighPriority0_1_offset 0x00002e00UL
5180 struct QIB_7322_HighPriority0_1_pb {
5181 pseudo_bit_t Weight[8];
5182 pseudo_bit_t _unused_0[8];
5183 pseudo_bit_t VirtualLane[3];
5184 pseudo_bit_t _unused_1[45];
5186 struct QIB_7322_HighPriority0_1 {
5187 PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriority0_1_pb );
5189 /* Default value: 0x0000000000000000 */
5191 #define QIB_7322_SendBufAvail0_offset 0x00003000UL
5192 struct QIB_7322_SendBufAvail0_pb {
5193 pseudo_bit_t SendBuf_31_0[64];
5195 struct QIB_7322_SendBufAvail0 {
5196 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail0_pb );
5198 /* Default value: 0x0000000000000000 */
5200 #define QIB_7322_MsixTable_offset 0x00008000UL
5201 /* Default value: 0x0000000000000000 */
5203 #define QIB_7322_MsixPba_offset 0x00009000UL
5204 /* Default value: 0x0000000000000000 */
5206 #define QIB_7322_LAMemory_offset 0x0000a000UL
5207 /* Default value: 0x0000000000000000 */
5209 #define QIB_7322_LBIntCnt_offset 0x00011000UL
5210 /* Default value: 0x0000000000000000 */
5212 #define QIB_7322_LBFlowStallCnt_offset 0x00011008UL
5213 /* Default value: 0x0000000000000000 */
5215 #define QIB_7322_RxTIDFullErrCnt_offset 0x000110d0UL
5216 /* Default value: 0x0000000000000000 */
5218 #define QIB_7322_RxTIDValidErrCnt_offset 0x000110d8UL
5219 /* Default value: 0x0000000000000000 */
5221 #define QIB_7322_RxP0HdrEgrOvflCnt_offset 0x000110e8UL
5222 /* Default value: 0x0000000000000000 */
5224 #define QIB_7322_PcieRetryBufDiagQwordCnt_offset 0x000111a0UL
5225 /* Default value: 0x0000000000000000 */
5227 #define QIB_7322_RxTidFlowDropCnt_offset 0x000111e0UL
5228 /* Default value: 0x0000000000000000 */
5230 #define QIB_7322_LBIntCnt_0_offset 0x00012000UL
5231 /* Default value: 0x0000000000000000 */
5233 #define QIB_7322_TxCreditUpToDateTimeOut_0_offset 0x00012008UL
5234 /* Default value: 0x0000000000000000 */
5236 #define QIB_7322_TxSDmaDescCnt_0_offset 0x00012010UL
5237 /* Default value: 0x0000000000000000 */
5239 #define QIB_7322_TxUnsupVLErrCnt_0_offset 0x00012018UL
5240 /* Default value: 0x0000000000000000 */
5242 #define QIB_7322_TxDataPktCnt_0_offset 0x00012020UL
5243 /* Default value: 0x0000000000000000 */
5245 #define QIB_7322_TxFlowPktCnt_0_offset 0x00012028UL
5246 /* Default value: 0x0000000000000000 */
5248 #define QIB_7322_TxDwordCnt_0_offset 0x00012030UL
5249 /* Default value: 0x0000000000000000 */
5251 #define QIB_7322_TxLenErrCnt_0_offset 0x00012038UL
5252 /* Default value: 0x0000000000000000 */
5254 #define QIB_7322_TxMaxMinLenErrCnt_0_offset 0x00012040UL
5255 /* Default value: 0x0000000000000000 */
5257 #define QIB_7322_TxUnderrunCnt_0_offset 0x00012048UL
5258 /* Default value: 0x0000000000000000 */
5260 #define QIB_7322_TxFlowStallCnt_0_offset 0x00012050UL
5261 /* Default value: 0x0000000000000000 */
5263 #define QIB_7322_TxDroppedPktCnt_0_offset 0x00012058UL
5264 /* Default value: 0x0000000000000000 */
5266 #define QIB_7322_RxDroppedPktCnt_0_offset 0x00012060UL
5267 /* Default value: 0x0000000000000000 */
5269 #define QIB_7322_RxDataPktCnt_0_offset 0x00012068UL
5270 /* Default value: 0x0000000000000000 */
5272 #define QIB_7322_RxFlowPktCnt_0_offset 0x00012070UL
5273 /* Default value: 0x0000000000000000 */
5275 #define QIB_7322_RxDwordCnt_0_offset 0x00012078UL
5276 /* Default value: 0x0000000000000000 */
5278 #define QIB_7322_RxLenErrCnt_0_offset 0x00012080UL
5279 /* Default value: 0x0000000000000000 */
5281 #define QIB_7322_RxMaxMinLenErrCnt_0_offset 0x00012088UL
5282 /* Default value: 0x0000000000000000 */
5284 #define QIB_7322_RxICRCErrCnt_0_offset 0x00012090UL
5285 /* Default value: 0x0000000000000000 */
5287 #define QIB_7322_RxVCRCErrCnt_0_offset 0x00012098UL
5288 /* Default value: 0x0000000000000000 */
5290 #define QIB_7322_RxFlowCtrlViolCnt_0_offset 0x000120a0UL
5291 /* Default value: 0x0000000000000000 */
5293 #define QIB_7322_RxVersionErrCnt_0_offset 0x000120a8UL
5294 /* Default value: 0x0000000000000000 */
5296 #define QIB_7322_RxLinkMalformCnt_0_offset 0x000120b0UL
5297 /* Default value: 0x0000000000000000 */
5299 #define QIB_7322_RxEBPCnt_0_offset 0x000120b8UL
5300 /* Default value: 0x0000000000000000 */
5302 #define QIB_7322_RxLPCRCErrCnt_0_offset 0x000120c0UL
5303 /* Default value: 0x0000000000000000 */
5305 #define QIB_7322_RxBufOvflCnt_0_offset 0x000120c8UL
5306 /* Default value: 0x0000000000000000 */
5308 #define QIB_7322_RxLenTruncateCnt_0_offset 0x000120d0UL
5309 /* Default value: 0x0000000000000000 */
5311 #define QIB_7322_RxPKeyMismatchCnt_0_offset 0x000120e0UL
5312 /* Default value: 0x0000000000000000 */
5314 #define QIB_7322_IBLinkDownedCnt_0_offset 0x00012180UL
5315 /* Default value: 0x0000000000000000 */
5317 #define QIB_7322_IBSymbolErrCnt_0_offset 0x00012188UL
5318 /* Default value: 0x0000000000000000 */
5320 #define QIB_7322_IBStatusChangeCnt_0_offset 0x00012190UL
5321 /* Default value: 0x0000000000000000 */
5323 #define QIB_7322_IBLinkErrRecoveryCnt_0_offset 0x00012198UL
5324 /* Default value: 0x0000000000000000 */
5326 #define QIB_7322_ExcessBufferOvflCnt_0_offset 0x000121a8UL
5327 /* Default value: 0x0000000000000000 */
5329 #define QIB_7322_LocalLinkIntegrityErrCnt_0_offset 0x000121b0UL
5330 /* Default value: 0x0000000000000000 */
5332 #define QIB_7322_RxVlErrCnt_0_offset 0x000121b8UL
5333 /* Default value: 0x0000000000000000 */
5335 #define QIB_7322_RxDlidFltrCnt_0_offset 0x000121c0UL
5336 /* Default value: 0x0000000000000000 */
5338 #define QIB_7322_RxVL15DroppedPktCnt_0_offset 0x000121c8UL
5339 /* Default value: 0x0000000000000000 */
5341 #define QIB_7322_RxOtherLocalPhyErrCnt_0_offset 0x000121d0UL
5342 /* Default value: 0x0000000000000000 */
5344 #define QIB_7322_RxQPInvalidContextCnt_0_offset 0x000121d8UL
5345 /* Default value: 0x0000000000000000 */
5347 #define QIB_7322_TxHeadersErrCnt_0_offset 0x000121f8UL
5348 /* Default value: 0x0000000000000000 */
5350 #define QIB_7322_PSRcvDataCount_0_offset 0x00012218UL
5351 /* Default value: 0x0000000000000000 */
5353 #define QIB_7322_PSRcvPktsCount_0_offset 0x00012220UL
5354 /* Default value: 0x0000000000000000 */
5356 #define QIB_7322_PSXmitDataCount_0_offset 0x00012228UL
5357 /* Default value: 0x0000000000000000 */
5359 #define QIB_7322_PSXmitPktsCount_0_offset 0x00012230UL
5360 /* Default value: 0x0000000000000000 */
5362 #define QIB_7322_PSXmitWaitCount_0_offset 0x00012238UL
5363 /* Default value: 0x0000000000000000 */
5365 #define QIB_7322_LBIntCnt_1_offset 0x00013000UL
5366 /* Default value: 0x0000000000000000 */
5368 #define QIB_7322_TxCreditUpToDateTimeOut_1_offset 0x00013008UL
5369 /* Default value: 0x0000000000000000 */
5371 #define QIB_7322_TxSDmaDescCnt_1_offset 0x00013010UL
5372 /* Default value: 0x0000000000000000 */
5374 #define QIB_7322_TxUnsupVLErrCnt_1_offset 0x00013018UL
5375 /* Default value: 0x0000000000000000 */
5377 #define QIB_7322_TxDataPktCnt_1_offset 0x00013020UL
5378 /* Default value: 0x0000000000000000 */
5380 #define QIB_7322_TxFlowPktCnt_1_offset 0x00013028UL
5381 /* Default value: 0x0000000000000000 */
5383 #define QIB_7322_TxDwordCnt_1_offset 0x00013030UL
5384 /* Default value: 0x0000000000000000 */
5386 #define QIB_7322_TxLenErrCnt_1_offset 0x00013038UL
5387 /* Default value: 0x0000000000000000 */
5389 #define QIB_7322_TxMaxMinLenErrCnt_1_offset 0x00013040UL
5390 /* Default value: 0x0000000000000000 */
5392 #define QIB_7322_TxUnderrunCnt_1_offset 0x00013048UL
5393 /* Default value: 0x0000000000000000 */
5395 #define QIB_7322_TxFlowStallCnt_1_offset 0x00013050UL
5396 /* Default value: 0x0000000000000000 */
5398 #define QIB_7322_TxDroppedPktCnt_1_offset 0x00013058UL
5399 /* Default value: 0x0000000000000000 */
5401 #define QIB_7322_RxDroppedPktCnt_1_offset 0x00013060UL
5402 /* Default value: 0x0000000000000000 */
5404 #define QIB_7322_RxDataPktCnt_1_offset 0x00013068UL
5405 /* Default value: 0x0000000000000000 */
5407 #define QIB_7322_RxFlowPktCnt_1_offset 0x00013070UL
5408 /* Default value: 0x0000000000000000 */
5410 #define QIB_7322_RxDwordCnt_1_offset 0x00013078UL
5411 /* Default value: 0x0000000000000000 */
5413 #define QIB_7322_RxLenErrCnt_1_offset 0x00013080UL
5414 /* Default value: 0x0000000000000000 */
5416 #define QIB_7322_RxMaxMinLenErrCnt_1_offset 0x00013088UL
5417 /* Default value: 0x0000000000000000 */
5419 #define QIB_7322_RxICRCErrCnt_1_offset 0x00013090UL
5420 /* Default value: 0x0000000000000000 */
5422 #define QIB_7322_RxVCRCErrCnt_1_offset 0x00013098UL
5423 /* Default value: 0x0000000000000000 */
5425 #define QIB_7322_RxFlowCtrlViolCnt_1_offset 0x000130a0UL
5426 /* Default value: 0x0000000000000000 */
5428 #define QIB_7322_RxVersionErrCnt_1_offset 0x000130a8UL
5429 /* Default value: 0x0000000000000000 */
5431 #define QIB_7322_RxLinkMalformCnt_1_offset 0x000130b0UL
5432 /* Default value: 0x0000000000000000 */
5434 #define QIB_7322_RxEBPCnt_1_offset 0x000130b8UL
5435 /* Default value: 0x0000000000000000 */
5437 #define QIB_7322_RxLPCRCErrCnt_1_offset 0x000130c0UL
5438 /* Default value: 0x0000000000000000 */
5440 #define QIB_7322_RxBufOvflCnt_1_offset 0x000130c8UL
5441 /* Default value: 0x0000000000000000 */
5443 #define QIB_7322_RxLenTruncateCnt_1_offset 0x000130d0UL
5444 /* Default value: 0x0000000000000000 */
5446 #define QIB_7322_RxPKeyMismatchCnt_1_offset 0x000130e0UL
5447 /* Default value: 0x0000000000000000 */
5449 #define QIB_7322_IBLinkDownedCnt_1_offset 0x00013180UL
5450 /* Default value: 0x0000000000000000 */
5452 #define QIB_7322_IBSymbolErrCnt_1_offset 0x00013188UL
5453 /* Default value: 0x0000000000000000 */
5455 #define QIB_7322_IBStatusChangeCnt_1_offset 0x00013190UL
5456 /* Default value: 0x0000000000000000 */
5458 #define QIB_7322_IBLinkErrRecoveryCnt_1_offset 0x00013198UL
5459 /* Default value: 0x0000000000000000 */
5461 #define QIB_7322_ExcessBufferOvflCnt_1_offset 0x000131a8UL
5462 /* Default value: 0x0000000000000000 */
5464 #define QIB_7322_LocalLinkIntegrityErrCnt_1_offset 0x000131b0UL
5465 /* Default value: 0x0000000000000000 */
5467 #define QIB_7322_RxVlErrCnt_1_offset 0x000131b8UL
5468 /* Default value: 0x0000000000000000 */
5470 #define QIB_7322_RxDlidFltrCnt_1_offset 0x000131c0UL
5471 /* Default value: 0x0000000000000000 */
5473 #define QIB_7322_RxVL15DroppedPktCnt_1_offset 0x000131c8UL
5474 /* Default value: 0x0000000000000000 */
5476 #define QIB_7322_RxOtherLocalPhyErrCnt_1_offset 0x000131d0UL
5477 /* Default value: 0x0000000000000000 */
5479 #define QIB_7322_RxQPInvalidContextCnt_1_offset 0x000131d8UL
5480 /* Default value: 0x0000000000000000 */
5482 #define QIB_7322_TxHeadersErrCnt_1_offset 0x000131f8UL
5483 /* Default value: 0x0000000000000000 */
5485 #define QIB_7322_PSRcvDataCount_1_offset 0x00013218UL
5486 /* Default value: 0x0000000000000000 */
5488 #define QIB_7322_PSRcvPktsCount_1_offset 0x00013220UL
5489 /* Default value: 0x0000000000000000 */
5491 #define QIB_7322_PSXmitDataCount_1_offset 0x00013228UL
5492 /* Default value: 0x0000000000000000 */
5494 #define QIB_7322_PSXmitPktsCount_1_offset 0x00013230UL
5495 /* Default value: 0x0000000000000000 */
5497 #define QIB_7322_PSXmitWaitCount_1_offset 0x00013238UL
5498 /* Default value: 0x0000000000000000 */
5500 #define QIB_7322_RcvEgrArray_offset 0x00014000UL
5501 struct QIB_7322_RcvEgrArray_pb {
5502 pseudo_bit_t RT_Addr[37];
5503 pseudo_bit_t RT_BufSize[3];
5504 pseudo_bit_t _unused_0[24];
5506 struct QIB_7322_RcvEgrArray {
5507 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgrArray_pb );
5509 /* Default value: 0x0000000000000000 */
5511 #define QIB_7322_RcvTIDArray0_offset 0x00050000UL
5512 struct QIB_7322_RcvTIDArray0_pb {
5513 pseudo_bit_t RT_Addr[37];
5514 pseudo_bit_t RT_BufSize[3];
5515 pseudo_bit_t _unused_0[24];
5517 struct QIB_7322_RcvTIDArray0 {
5518 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDArray0_pb );
5520 /* Default value: 0x0000000000000000 */
5522 #define QIB_7322_SendPbcCache_offset 0x00070000UL
5523 /* Default value: 0x0000000000000000 */
5525 #define QIB_7322_LaunchFIFO_v0p0_offset 0x00072000UL
5526 /* Default value: 0x0000000000000000 */
5528 #define QIB_7322_LaunchElement_v15p0_offset 0x00076000UL
5529 /* Default value: 0x0000000000000000 */
5531 #define QIB_7322_PreLaunchFIFO_0_offset 0x00076100UL
5532 /* Default value: 0x0000000000000000 */
5534 #define QIB_7322_ScoreBoard_0_offset 0x00076200UL
5535 /* Default value: 0x0000000000000000 */
5537 #define QIB_7322_DescriptorFIFO_0_offset 0x00076300UL
5538 /* Default value: 0x0000000000000000 */
5540 #define QIB_7322_LaunchFIFO_v0p1_offset 0x00078000UL
5541 /* Default value: 0x0000000000000000 */
5543 #define QIB_7322_LaunchElement_v15p1_offset 0x0007c000UL
5544 /* Default value: 0x0000000000000000 */
5546 #define QIB_7322_PreLaunchFIFO_1_offset 0x0007c100UL
5547 /* Default value: 0x0000000000000000 */
5549 #define QIB_7322_ScoreBoard_1_offset 0x0007c200UL
5550 /* Default value: 0x0000000000000000 */
5552 #define QIB_7322_DescriptorFIFO_1_offset 0x0007c300UL
5553 /* Default value: 0x0000000000000000 */
5555 #define QIB_7322_RcvBufA_0_offset 0x00080000UL
5556 /* Default value: 0x0000000000000000 */
5558 #define QIB_7322_RcvBufB_0_offset 0x00088000UL
5559 /* Default value: 0x0000000000000000 */
5561 #define QIB_7322_RcvFlags_0_offset 0x0008a000UL
5562 /* Default value: 0x0000000000000000 */
5564 #define QIB_7322_RcvLookupiqBuf_0_offset 0x0008c000UL
5565 /* Default value: 0x0000000000000000 */
5567 #define QIB_7322_RcvDMADatBuf_0_offset 0x0008e000UL
5568 /* Default value: 0x0000000000000000 */
5570 #define QIB_7322_RcvDMAHdrBuf_0_offset 0x0008e800UL
5571 /* Default value: 0x0000000000000000 */
5573 #define QIB_7322_RcvBufA_1_offset 0x00090000UL
5574 /* Default value: 0x0000000000000000 */
5576 #define QIB_7322_RcvBufB_1_offset 0x00098000UL
5577 /* Default value: 0x0000000000000000 */
5579 #define QIB_7322_RcvFlags_1_offset 0x0009a000UL
5580 /* Default value: 0x0000000000000000 */
5582 #define QIB_7322_RcvLookupiqBuf_1_offset 0x0009c000UL
5583 /* Default value: 0x0000000000000000 */
5585 #define QIB_7322_RcvDMADatBuf_1_offset 0x0009e000UL
5586 /* Default value: 0x0000000000000000 */
5588 #define QIB_7322_RcvDMAHdrBuf_1_offset 0x0009e800UL
5589 /* Default value: 0x0000000000000000 */
5591 #define QIB_7322_PCIERcvBuf_offset 0x000a0000UL
5592 /* Default value: 0x0000000000000000 */
5594 #define QIB_7322_PCIERetryBuf_offset 0x000a4000UL
5595 /* Default value: 0x0000000000000000 */
5597 #define QIB_7322_PCIERcvBufRdToWrAddr_offset 0x000a8000UL
5598 /* Default value: 0x0000000000000000 */
5600 #define QIB_7322_PCIERcvHdrRdToWrAddr_offset 0x000b0000UL
5601 /* Default value: 0x0000000000000000 */
5603 #define QIB_7322_PCIECplBuf_offset 0x000b8000UL
5604 /* Default value: 0x0000000000000000 */
5606 #define QIB_7322_PCIECplHdr_offset 0x000bc000UL
5607 /* Default value: 0x0000000000000000 */
5609 #define QIB_7322_PCIERcvHdr_offset 0x000bc200UL
5610 /* Default value: 0x0000000000000000 */
5612 #define QIB_7322_IBSD_DDS_MAP_TABLE_0_offset 0x000d0000UL
5613 /* Default value: 0x0000000000000000 */
5615 #define QIB_7322_SendBufMA_0_offset 0x00100000UL
5616 /* Default value: 0x0000000000000000 */
5618 #define QIB_7322_SendBufEA_0_offset 0x00100800UL
5619 /* Default value: 0x0000000000000000 */
5621 #define QIB_7322_SendBufMA_1_offset 0x00101000UL
5622 /* Default value: 0x0000000000000000 */
5624 #define QIB_7322_SendBufEA_1_offset 0x00101800UL
5625 /* Default value: 0x0000000000000000 */
5627 #define QIB_7322_SendBufMA_2_offset 0x00102000UL
5628 /* Default value: 0x0000000000000000 */
5630 #define QIB_7322_SendBufEA_2_offset 0x00102800UL
5631 /* Default value: 0x0000000000000000 */
5633 #define QIB_7322_SendBufMA_3_offset 0x00103000UL
5634 /* Default value: 0x0000000000000000 */
5636 #define QIB_7322_SendBufEA_3_offset 0x00103800UL
5637 /* Default value: 0x0000000000000000 */
5639 #define QIB_7322_SendBufMA_4_offset 0x00104000UL
5640 /* Default value: 0x0000000000000000 */
5642 #define QIB_7322_SendBufEA_4_offset 0x00104800UL
5643 /* Default value: 0x0000000000000000 */
5645 #define QIB_7322_SendBufMA_5_offset 0x00105000UL
5646 /* Default value: 0x0000000000000000 */
5648 #define QIB_7322_SendBufEA_5_offset 0x00105800UL
5649 /* Default value: 0x0000000000000000 */
5651 #define QIB_7322_SendBufMA_6_offset 0x00106000UL
5652 /* Default value: 0x0000000000000000 */
5654 #define QIB_7322_SendBufEA_6_offset 0x00106800UL
5655 /* Default value: 0x0000000000000000 */
5657 #define QIB_7322_SendBufMA_7_offset 0x00107000UL
5658 /* Default value: 0x0000000000000000 */
5660 #define QIB_7322_SendBufEA_7_offset 0x00107800UL
5661 /* Default value: 0x0000000000000000 */
5663 #define QIB_7322_SendBufMA_8_offset 0x00108000UL
5664 /* Default value: 0x0000000000000000 */
5666 #define QIB_7322_SendBufEA_8_offset 0x00108800UL
5667 /* Default value: 0x0000000000000000 */
5669 #define QIB_7322_SendBufMA_9_offset 0x00109000UL
5670 /* Default value: 0x0000000000000000 */
5672 #define QIB_7322_SendBufEA_9_offset 0x00109800UL
5673 /* Default value: 0x0000000000000000 */
5675 #define QIB_7322_SendBufMA_10_offset 0x0010a000UL
5676 /* Default value: 0x0000000000000000 */
5678 #define QIB_7322_SendBufEA_10_offset 0x0010a800UL
5679 /* Default value: 0x0000000000000000 */
5681 #define QIB_7322_SendBufMA_11_offset 0x0010b000UL
5682 /* Default value: 0x0000000000000000 */
5684 #define QIB_7322_SendBufEA_11_offset 0x0010b800UL
5685 /* Default value: 0x0000000000000000 */
5687 #define QIB_7322_SendBufMA_12_offset 0x0010c000UL
5688 /* Default value: 0x0000000000000000 */
5690 #define QIB_7322_SendBufEA_12_offset 0x0010c800UL
5691 /* Default value: 0x0000000000000000 */
5693 #define QIB_7322_SendBufMA_13_offset 0x0010d000UL
5694 /* Default value: 0x0000000000000000 */
5696 #define QIB_7322_SendBufEA_13_offset 0x0010d800UL
5697 /* Default value: 0x0000000000000000 */
5699 #define QIB_7322_SendBufMA_14_offset 0x0010e000UL
5700 /* Default value: 0x0000000000000000 */
5702 #define QIB_7322_SendBufEA_14_offset 0x0010e800UL
5703 /* Default value: 0x0000000000000000 */
5705 #define QIB_7322_SendBufMA_15_offset 0x0010f000UL
5706 /* Default value: 0x0000000000000000 */
5708 #define QIB_7322_SendBufEA_15_offset 0x0010f800UL
5709 /* Default value: 0x0000000000000000 */
5711 #define QIB_7322_SendBufMA_16_offset 0x00110000UL
5712 /* Default value: 0x0000000000000000 */
5714 #define QIB_7322_SendBufEA_16_offset 0x00110800UL
5715 /* Default value: 0x0000000000000000 */
5717 #define QIB_7322_SendBufMA_17_offset 0x00111000UL
5718 /* Default value: 0x0000000000000000 */
5720 #define QIB_7322_SendBufEA_17_offset 0x00111800UL
5721 /* Default value: 0x0000000000000000 */
5723 #define QIB_7322_SendBufMA_18_offset 0x00112000UL
5724 /* Default value: 0x0000000000000000 */
5726 #define QIB_7322_SendBufEA_18_offset 0x00112800UL
5727 /* Default value: 0x0000000000000000 */
5729 #define QIB_7322_SendBufMA_19_offset 0x00113000UL
5730 /* Default value: 0x0000000000000000 */
5732 #define QIB_7322_SendBufEA_19_offset 0x00113800UL
5733 /* Default value: 0x0000000000000000 */
5735 #define QIB_7322_SendBufMA_20_offset 0x00114000UL
5736 /* Default value: 0x0000000000000000 */
5738 #define QIB_7322_SendBufEA_20_offset 0x00114800UL
5739 /* Default value: 0x0000000000000000 */
5741 #define QIB_7322_SendBufMA_21_offset 0x00115000UL
5742 /* Default value: 0x0000000000000000 */
5744 #define QIB_7322_SendBufEA_21_offset 0x00115800UL
5745 /* Default value: 0x0000000000000000 */
5747 #define QIB_7322_SendBufMA_22_offset 0x00116000UL
5748 /* Default value: 0x0000000000000000 */
5750 #define QIB_7322_SendBufEA_22_offset 0x00116800UL
5751 /* Default value: 0x0000000000000000 */
5753 #define QIB_7322_SendBufMA_23_offset 0x00117000UL
5754 /* Default value: 0x0000000000000000 */
5756 #define QIB_7322_SendBufEA_23_offset 0x00117800UL
5757 /* Default value: 0x0000000000000000 */
5759 #define QIB_7322_SendBufMA_24_offset 0x00118000UL
5760 /* Default value: 0x0000000000000000 */
5762 #define QIB_7322_SendBufEA_24_offset 0x00118800UL
5763 /* Default value: 0x0000000000000000 */
5765 #define QIB_7322_SendBufMA_25_offset 0x00119000UL
5766 /* Default value: 0x0000000000000000 */
5768 #define QIB_7322_SendBufEA_25_offset 0x00119800UL
5769 /* Default value: 0x0000000000000000 */
5771 #define QIB_7322_SendBufMA_26_offset 0x0011a000UL
5772 /* Default value: 0x0000000000000000 */
5774 #define QIB_7322_SendBufEA_26_offset 0x0011a800UL
5775 /* Default value: 0x0000000000000000 */
5777 #define QIB_7322_SendBufMA_27_offset 0x0011b000UL
5778 /* Default value: 0x0000000000000000 */
5780 #define QIB_7322_SendBufEA_27_offset 0x0011b800UL
5781 /* Default value: 0x0000000000000000 */
5783 #define QIB_7322_SendBufMA_28_offset 0x0011c000UL
5784 /* Default value: 0x0000000000000000 */
5786 #define QIB_7322_SendBufEA_28_offset 0x0011c800UL
5787 /* Default value: 0x0000000000000000 */
5789 #define QIB_7322_SendBufMA_29_offset 0x0011d000UL
5790 /* Default value: 0x0000000000000000 */
5792 #define QIB_7322_SendBufEA_29_offset 0x0011d800UL
5793 /* Default value: 0x0000000000000000 */
5795 #define QIB_7322_SendBufMA_30_offset 0x0011e000UL
5796 /* Default value: 0x0000000000000000 */
5798 #define QIB_7322_SendBufEA_30_offset 0x0011e800UL
5799 /* Default value: 0x0000000000000000 */
5801 #define QIB_7322_SendBufMA_31_offset 0x0011f000UL
5802 /* Default value: 0x0000000000000000 */
5804 #define QIB_7322_SendBufEA_31_offset 0x0011f800UL
5805 /* Default value: 0x0000000000000000 */
5807 #define QIB_7322_SendBufMA_32_offset 0x00120000UL
5808 /* Default value: 0x0000000000000000 */
5810 #define QIB_7322_SendBufEA_32_offset 0x00120800UL
5811 /* Default value: 0x0000000000000000 */
5813 #define QIB_7322_SendBufMA_33_offset 0x00121000UL
5814 /* Default value: 0x0000000000000000 */
5816 #define QIB_7322_SendBufEA_33_offset 0x00121800UL
5817 /* Default value: 0x0000000000000000 */
5819 #define QIB_7322_SendBufMA_34_offset 0x00122000UL
5820 /* Default value: 0x0000000000000000 */
5822 #define QIB_7322_SendBufEA_34_offset 0x00122800UL
5823 /* Default value: 0x0000000000000000 */
5825 #define QIB_7322_SendBufMA_35_offset 0x00123000UL
5826 /* Default value: 0x0000000000000000 */
5828 #define QIB_7322_SendBufEA_35_offset 0x00123800UL
5829 /* Default value: 0x0000000000000000 */
5831 #define QIB_7322_SendBufMA_36_offset 0x00124000UL
5832 /* Default value: 0x0000000000000000 */
5834 #define QIB_7322_SendBufEA_36_offset 0x00124800UL
5835 /* Default value: 0x0000000000000000 */
5837 #define QIB_7322_SendBufMA_37_offset 0x00125000UL
5838 /* Default value: 0x0000000000000000 */
5840 #define QIB_7322_SendBufEA_37_offset 0x00125800UL
5841 /* Default value: 0x0000000000000000 */
5843 #define QIB_7322_SendBufMA_38_offset 0x00126000UL
5844 /* Default value: 0x0000000000000000 */
5846 #define QIB_7322_SendBufEA_38_offset 0x00126800UL
5847 /* Default value: 0x0000000000000000 */
5849 #define QIB_7322_SendBufMA_39_offset 0x00127000UL
5850 /* Default value: 0x0000000000000000 */
5852 #define QIB_7322_SendBufEA_39_offset 0x00127800UL
5853 /* Default value: 0x0000000000000000 */
5855 #define QIB_7322_SendBufMA_40_offset 0x00128000UL
5856 /* Default value: 0x0000000000000000 */
5858 #define QIB_7322_SendBufEA_40_offset 0x00128800UL
5859 /* Default value: 0x0000000000000000 */
5861 #define QIB_7322_SendBufMA_41_offset 0x00129000UL
5862 /* Default value: 0x0000000000000000 */
5864 #define QIB_7322_SendBufEA_41_offset 0x00129800UL
5865 /* Default value: 0x0000000000000000 */
5867 #define QIB_7322_SendBufMA_42_offset 0x0012a000UL
5868 /* Default value: 0x0000000000000000 */
5870 #define QIB_7322_SendBufEA_42_offset 0x0012a800UL
5871 /* Default value: 0x0000000000000000 */
5873 #define QIB_7322_SendBufMA_43_offset 0x0012b000UL
5874 /* Default value: 0x0000000000000000 */
5876 #define QIB_7322_SendBufEA_43_offset 0x0012b800UL
5877 /* Default value: 0x0000000000000000 */
5879 #define QIB_7322_SendBufMA_44_offset 0x0012c000UL
5880 /* Default value: 0x0000000000000000 */
5882 #define QIB_7322_SendBufEA_44_offset 0x0012c800UL
5883 /* Default value: 0x0000000000000000 */
5885 #define QIB_7322_SendBufMA_45_offset 0x0012d000UL
5886 /* Default value: 0x0000000000000000 */
5888 #define QIB_7322_SendBufEA_45_offset 0x0012d800UL
5889 /* Default value: 0x0000000000000000 */
5891 #define QIB_7322_SendBufMA_46_offset 0x0012e000UL
5892 /* Default value: 0x0000000000000000 */
5894 #define QIB_7322_SendBufEA_46_offset 0x0012e800UL
5895 /* Default value: 0x0000000000000000 */
5897 #define QIB_7322_SendBufMA_47_offset 0x0012f000UL
5898 /* Default value: 0x0000000000000000 */
5900 #define QIB_7322_SendBufEA_47_offset 0x0012f800UL
5901 /* Default value: 0x0000000000000000 */
5903 #define QIB_7322_SendBufMA_48_offset 0x00130000UL
5904 /* Default value: 0x0000000000000000 */
5906 #define QIB_7322_SendBufEA_48_offset 0x00130800UL
5907 /* Default value: 0x0000000000000000 */
5909 #define QIB_7322_SendBufMA_49_offset 0x00131000UL
5910 /* Default value: 0x0000000000000000 */
5912 #define QIB_7322_SendBufEA_49_offset 0x00131800UL
5913 /* Default value: 0x0000000000000000 */
5915 #define QIB_7322_SendBufMA_50_offset 0x00132000UL
5916 /* Default value: 0x0000000000000000 */
5918 #define QIB_7322_SendBufEA_50_offset 0x00132800UL
5919 /* Default value: 0x0000000000000000 */
5921 #define QIB_7322_SendBufMA_51_offset 0x00133000UL
5922 /* Default value: 0x0000000000000000 */
5924 #define QIB_7322_SendBufEA_51_offset 0x00133800UL
5925 /* Default value: 0x0000000000000000 */
5927 #define QIB_7322_SendBufMA_52_offset 0x00134000UL
5928 /* Default value: 0x0000000000000000 */
5930 #define QIB_7322_SendBufEA_52_offset 0x00134800UL
5931 /* Default value: 0x0000000000000000 */
5933 #define QIB_7322_SendBufMA_53_offset 0x00135000UL
5934 /* Default value: 0x0000000000000000 */
5936 #define QIB_7322_SendBufEA_53_offset 0x00135800UL
5937 /* Default value: 0x0000000000000000 */
5939 #define QIB_7322_SendBufMA_54_offset 0x00136000UL
5940 /* Default value: 0x0000000000000000 */
5942 #define QIB_7322_SendBufEA_54_offset 0x00136800UL
5943 /* Default value: 0x0000000000000000 */
5945 #define QIB_7322_SendBufMA_55_offset 0x00137000UL
5946 /* Default value: 0x0000000000000000 */
5948 #define QIB_7322_SendBufEA_55_offset 0x00137800UL
5949 /* Default value: 0x0000000000000000 */
5951 #define QIB_7322_SendBufMA_56_offset 0x00138000UL
5952 /* Default value: 0x0000000000000000 */
5954 #define QIB_7322_SendBufEA_56_offset 0x00138800UL
5955 /* Default value: 0x0000000000000000 */
5957 #define QIB_7322_SendBufMA_57_offset 0x00139000UL
5958 /* Default value: 0x0000000000000000 */
5960 #define QIB_7322_SendBufEA_57_offset 0x00139800UL
5961 /* Default value: 0x0000000000000000 */
5963 #define QIB_7322_SendBufMA_58_offset 0x0013a000UL
5964 /* Default value: 0x0000000000000000 */
5966 #define QIB_7322_SendBufEA_58_offset 0x0013a800UL
5967 /* Default value: 0x0000000000000000 */
5969 #define QIB_7322_SendBufMA_59_offset 0x0013b000UL
5970 /* Default value: 0x0000000000000000 */
5972 #define QIB_7322_SendBufEA_59_offset 0x0013b800UL
5973 /* Default value: 0x0000000000000000 */
5975 #define QIB_7322_SendBufMA_60_offset 0x0013c000UL
5976 /* Default value: 0x0000000000000000 */
5978 #define QIB_7322_SendBufEA_60_offset 0x0013c800UL
5979 /* Default value: 0x0000000000000000 */
5981 #define QIB_7322_SendBufMA_61_offset 0x0013d000UL
5982 /* Default value: 0x0000000000000000 */
5984 #define QIB_7322_SendBufEA_61_offset 0x0013d800UL
5985 /* Default value: 0x0000000000000000 */
5987 #define QIB_7322_SendBufMA_62_offset 0x0013e000UL
5988 /* Default value: 0x0000000000000000 */
5990 #define QIB_7322_SendBufEA_62_offset 0x0013e800UL
5991 /* Default value: 0x0000000000000000 */
5993 #define QIB_7322_SendBufMA_63_offset 0x0013f000UL
5994 /* Default value: 0x0000000000000000 */
5996 #define QIB_7322_SendBufEA_63_offset 0x0013f800UL
5997 /* Default value: 0x0000000000000000 */
5999 #define QIB_7322_SendBufMA_64_offset 0x00140000UL
6000 /* Default value: 0x0000000000000000 */
6002 #define QIB_7322_SendBufEA_64_offset 0x00140800UL
6003 /* Default value: 0x0000000000000000 */
6005 #define QIB_7322_SendBufMA_65_offset 0x00141000UL
6006 /* Default value: 0x0000000000000000 */
6008 #define QIB_7322_SendBufEA_65_offset 0x00141800UL
6009 /* Default value: 0x0000000000000000 */
6011 #define QIB_7322_SendBufMA_66_offset 0x00142000UL
6012 /* Default value: 0x0000000000000000 */
6014 #define QIB_7322_SendBufEA_66_offset 0x00142800UL
6015 /* Default value: 0x0000000000000000 */
6017 #define QIB_7322_SendBufMA_67_offset 0x00143000UL
6018 /* Default value: 0x0000000000000000 */
6020 #define QIB_7322_SendBufEA_67_offset 0x00143800UL
6021 /* Default value: 0x0000000000000000 */
6023 #define QIB_7322_SendBufMA_68_offset 0x00144000UL
6024 /* Default value: 0x0000000000000000 */
6026 #define QIB_7322_SendBufEA_68_offset 0x00144800UL
6027 /* Default value: 0x0000000000000000 */
6029 #define QIB_7322_SendBufMA_69_offset 0x00145000UL
6030 /* Default value: 0x0000000000000000 */
6032 #define QIB_7322_SendBufEA_69_offset 0x00145800UL
6033 /* Default value: 0x0000000000000000 */
6035 #define QIB_7322_SendBufMA_70_offset 0x00146000UL
6036 /* Default value: 0x0000000000000000 */
6038 #define QIB_7322_SendBufEA_70_offset 0x00146800UL
6039 /* Default value: 0x0000000000000000 */
6041 #define QIB_7322_SendBufMA_71_offset 0x00147000UL
6042 /* Default value: 0x0000000000000000 */
6044 #define QIB_7322_SendBufEA_71_offset 0x00147800UL
6045 /* Default value: 0x0000000000000000 */
6047 #define QIB_7322_SendBufMA_72_offset 0x00148000UL
6048 /* Default value: 0x0000000000000000 */
6050 #define QIB_7322_SendBufEA_72_offset 0x00148800UL
6051 /* Default value: 0x0000000000000000 */
6053 #define QIB_7322_SendBufMA_73_offset 0x00149000UL
6054 /* Default value: 0x0000000000000000 */
6056 #define QIB_7322_SendBufEA_73_offset 0x00149800UL
6057 /* Default value: 0x0000000000000000 */
6059 #define QIB_7322_SendBufMA_74_offset 0x0014a000UL
6060 /* Default value: 0x0000000000000000 */
6062 #define QIB_7322_SendBufEA_74_offset 0x0014a800UL
6063 /* Default value: 0x0000000000000000 */
6065 #define QIB_7322_SendBufMA_75_offset 0x0014b000UL
6066 /* Default value: 0x0000000000000000 */
6068 #define QIB_7322_SendBufEA_75_offset 0x0014b800UL
6069 /* Default value: 0x0000000000000000 */
6071 #define QIB_7322_SendBufMA_76_offset 0x0014c000UL
6072 /* Default value: 0x0000000000000000 */
6074 #define QIB_7322_SendBufEA_76_offset 0x0014c800UL
6075 /* Default value: 0x0000000000000000 */
6077 #define QIB_7322_SendBufMA_77_offset 0x0014d000UL
6078 /* Default value: 0x0000000000000000 */
6080 #define QIB_7322_SendBufEA_77_offset 0x0014d800UL
6081 /* Default value: 0x0000000000000000 */
6083 #define QIB_7322_SendBufMA_78_offset 0x0014e000UL
6084 /* Default value: 0x0000000000000000 */
6086 #define QIB_7322_SendBufEA_78_offset 0x0014e800UL
6087 /* Default value: 0x0000000000000000 */
6089 #define QIB_7322_SendBufMA_79_offset 0x0014f000UL
6090 /* Default value: 0x0000000000000000 */
6092 #define QIB_7322_SendBufEA_79_offset 0x0014f800UL
6093 /* Default value: 0x0000000000000000 */
6095 #define QIB_7322_SendBufMA_80_offset 0x00150000UL
6096 /* Default value: 0x0000000000000000 */
6098 #define QIB_7322_SendBufEA_80_offset 0x00150800UL
6099 /* Default value: 0x0000000000000000 */
6101 #define QIB_7322_SendBufMA_81_offset 0x00151000UL
6102 /* Default value: 0x0000000000000000 */
6104 #define QIB_7322_SendBufEA_81_offset 0x00151800UL
6105 /* Default value: 0x0000000000000000 */
6107 #define QIB_7322_SendBufMA_82_offset 0x00152000UL
6108 /* Default value: 0x0000000000000000 */
6110 #define QIB_7322_SendBufEA_82_offset 0x00152800UL
6111 /* Default value: 0x0000000000000000 */
6113 #define QIB_7322_SendBufMA_83_offset 0x00153000UL
6114 /* Default value: 0x0000000000000000 */
6116 #define QIB_7322_SendBufEA_83_offset 0x00153800UL
6117 /* Default value: 0x0000000000000000 */
6119 #define QIB_7322_SendBufMA_84_offset 0x00154000UL
6120 /* Default value: 0x0000000000000000 */
6122 #define QIB_7322_SendBufEA_84_offset 0x00154800UL
6123 /* Default value: 0x0000000000000000 */
6125 #define QIB_7322_SendBufMA_85_offset 0x00155000UL
6126 /* Default value: 0x0000000000000000 */
6128 #define QIB_7322_SendBufEA_85_offset 0x00155800UL
6129 /* Default value: 0x0000000000000000 */
6131 #define QIB_7322_SendBufMA_86_offset 0x00156000UL
6132 /* Default value: 0x0000000000000000 */
6134 #define QIB_7322_SendBufEA_86_offset 0x00156800UL
6135 /* Default value: 0x0000000000000000 */
6137 #define QIB_7322_SendBufMA_87_offset 0x00157000UL
6138 /* Default value: 0x0000000000000000 */
6140 #define QIB_7322_SendBufEA_87_offset 0x00157800UL
6141 /* Default value: 0x0000000000000000 */
6143 #define QIB_7322_SendBufMA_88_offset 0x00158000UL
6144 /* Default value: 0x0000000000000000 */
6146 #define QIB_7322_SendBufEA_88_offset 0x00158800UL
6147 /* Default value: 0x0000000000000000 */
6149 #define QIB_7322_SendBufMA_89_offset 0x00159000UL
6150 /* Default value: 0x0000000000000000 */
6152 #define QIB_7322_SendBufEA_89_offset 0x00159800UL
6153 /* Default value: 0x0000000000000000 */
6155 #define QIB_7322_SendBufMA_90_offset 0x0015a000UL
6156 /* Default value: 0x0000000000000000 */
6158 #define QIB_7322_SendBufEA_90_offset 0x0015a800UL
6159 /* Default value: 0x0000000000000000 */
6161 #define QIB_7322_SendBufMA_91_offset 0x0015b000UL
6162 /* Default value: 0x0000000000000000 */
6164 #define QIB_7322_SendBufEA_91_offset 0x0015b800UL
6165 /* Default value: 0x0000000000000000 */
6167 #define QIB_7322_SendBufMA_92_offset 0x0015c000UL
6168 /* Default value: 0x0000000000000000 */
6170 #define QIB_7322_SendBufEA_92_offset 0x0015c800UL
6171 /* Default value: 0x0000000000000000 */
6173 #define QIB_7322_SendBufMA_93_offset 0x0015d000UL
6174 /* Default value: 0x0000000000000000 */
6176 #define QIB_7322_SendBufEA_93_offset 0x0015d800UL
6177 /* Default value: 0x0000000000000000 */
6179 #define QIB_7322_SendBufMA_94_offset 0x0015e000UL
6180 /* Default value: 0x0000000000000000 */
6182 #define QIB_7322_SendBufEA_94_offset 0x0015e800UL
6183 /* Default value: 0x0000000000000000 */
6185 #define QIB_7322_SendBufMA_95_offset 0x0015f000UL
6186 /* Default value: 0x0000000000000000 */
6188 #define QIB_7322_SendBufEA_95_offset 0x0015f800UL
6189 /* Default value: 0x0000000000000000 */
6191 #define QIB_7322_SendBufMA_96_offset 0x00160000UL
6192 /* Default value: 0x0000000000000000 */
6194 #define QIB_7322_SendBufEA_96_offset 0x00160800UL
6195 /* Default value: 0x0000000000000000 */
6197 #define QIB_7322_SendBufMA_97_offset 0x00161000UL
6198 /* Default value: 0x0000000000000000 */
6200 #define QIB_7322_SendBufEA_97_offset 0x00161800UL
6201 /* Default value: 0x0000000000000000 */
6203 #define QIB_7322_SendBufMA_98_offset 0x00162000UL
6204 /* Default value: 0x0000000000000000 */
6206 #define QIB_7322_SendBufEA_98_offset 0x00162800UL
6207 /* Default value: 0x0000000000000000 */
6209 #define QIB_7322_SendBufMA_99_offset 0x00163000UL
6210 /* Default value: 0x0000000000000000 */
6212 #define QIB_7322_SendBufEA_99_offset 0x00163800UL
6213 /* Default value: 0x0000000000000000 */
6215 #define QIB_7322_SendBufMA_100_offset 0x00164000UL
6216 /* Default value: 0x0000000000000000 */
6218 #define QIB_7322_SendBufEA_100_offset 0x00164800UL
6219 /* Default value: 0x0000000000000000 */
6221 #define QIB_7322_SendBufMA_101_offset 0x00165000UL
6222 /* Default value: 0x0000000000000000 */
6224 #define QIB_7322_SendBufEA_101_offset 0x00165800UL
6225 /* Default value: 0x0000000000000000 */
6227 #define QIB_7322_SendBufMA_102_offset 0x00166000UL
6228 /* Default value: 0x0000000000000000 */
6230 #define QIB_7322_SendBufEA_102_offset 0x00166800UL
6231 /* Default value: 0x0000000000000000 */
6233 #define QIB_7322_SendBufMA_103_offset 0x00167000UL
6234 /* Default value: 0x0000000000000000 */
6236 #define QIB_7322_SendBufEA_103_offset 0x00167800UL
6237 /* Default value: 0x0000000000000000 */
6239 #define QIB_7322_SendBufMA_104_offset 0x00168000UL
6240 /* Default value: 0x0000000000000000 */
6242 #define QIB_7322_SendBufEA_104_offset 0x00168800UL
6243 /* Default value: 0x0000000000000000 */
6245 #define QIB_7322_SendBufMA_105_offset 0x00169000UL
6246 /* Default value: 0x0000000000000000 */
6248 #define QIB_7322_SendBufEA_105_offset 0x00169800UL
6249 /* Default value: 0x0000000000000000 */
6251 #define QIB_7322_SendBufMA_106_offset 0x0016a000UL
6252 /* Default value: 0x0000000000000000 */
6254 #define QIB_7322_SendBufEA_106_offset 0x0016a800UL
6255 /* Default value: 0x0000000000000000 */
6257 #define QIB_7322_SendBufMA_107_offset 0x0016b000UL
6258 /* Default value: 0x0000000000000000 */
6260 #define QIB_7322_SendBufEA_107_offset 0x0016b800UL
6261 /* Default value: 0x0000000000000000 */
6263 #define QIB_7322_SendBufMA_108_offset 0x0016c000UL
6264 /* Default value: 0x0000000000000000 */
6266 #define QIB_7322_SendBufEA_108_offset 0x0016c800UL
6267 /* Default value: 0x0000000000000000 */
6269 #define QIB_7322_SendBufMA_109_offset 0x0016d000UL
6270 /* Default value: 0x0000000000000000 */
6272 #define QIB_7322_SendBufEA_109_offset 0x0016d800UL
6273 /* Default value: 0x0000000000000000 */
6275 #define QIB_7322_SendBufMA_110_offset 0x0016e000UL
6276 /* Default value: 0x0000000000000000 */
6278 #define QIB_7322_SendBufEA_110_offset 0x0016e800UL
6279 /* Default value: 0x0000000000000000 */
6281 #define QIB_7322_SendBufMA_111_offset 0x0016f000UL
6282 /* Default value: 0x0000000000000000 */
6284 #define QIB_7322_SendBufEA_111_offset 0x0016f800UL
6285 /* Default value: 0x0000000000000000 */
6287 #define QIB_7322_SendBufMA_112_offset 0x00170000UL
6288 /* Default value: 0x0000000000000000 */
6290 #define QIB_7322_SendBufEA_112_offset 0x00170800UL
6291 /* Default value: 0x0000000000000000 */
6293 #define QIB_7322_SendBufMA_113_offset 0x00171000UL
6294 /* Default value: 0x0000000000000000 */
6296 #define QIB_7322_SendBufEA_113_offset 0x00171800UL
6297 /* Default value: 0x0000000000000000 */
6299 #define QIB_7322_SendBufMA_114_offset 0x00172000UL
6300 /* Default value: 0x0000000000000000 */
6302 #define QIB_7322_SendBufEA_114_offset 0x00172800UL
6303 /* Default value: 0x0000000000000000 */
6305 #define QIB_7322_SendBufMA_115_offset 0x00173000UL
6306 /* Default value: 0x0000000000000000 */
6308 #define QIB_7322_SendBufEA_115_offset 0x00173800UL
6309 /* Default value: 0x0000000000000000 */
6311 #define QIB_7322_SendBufMA_116_offset 0x00174000UL
6312 /* Default value: 0x0000000000000000 */
6314 #define QIB_7322_SendBufEA_116_offset 0x00174800UL
6315 /* Default value: 0x0000000000000000 */
6317 #define QIB_7322_SendBufMA_117_offset 0x00175000UL
6318 /* Default value: 0x0000000000000000 */
6320 #define QIB_7322_SendBufEA_117_offset 0x00175800UL
6321 /* Default value: 0x0000000000000000 */
6323 #define QIB_7322_SendBufMA_118_offset 0x00176000UL
6324 /* Default value: 0x0000000000000000 */
6326 #define QIB_7322_SendBufEA_118_offset 0x00176800UL
6327 /* Default value: 0x0000000000000000 */
6329 #define QIB_7322_SendBufMA_119_offset 0x00177000UL
6330 /* Default value: 0x0000000000000000 */
6332 #define QIB_7322_SendBufEA_119_offset 0x00177800UL
6333 /* Default value: 0x0000000000000000 */
6335 #define QIB_7322_SendBufMA_120_offset 0x00178000UL
6336 /* Default value: 0x0000000000000000 */
6338 #define QIB_7322_SendBufEA_120_offset 0x00178800UL
6339 /* Default value: 0x0000000000000000 */
6341 #define QIB_7322_SendBufMA_121_offset 0x00179000UL
6342 /* Default value: 0x0000000000000000 */
6344 #define QIB_7322_SendBufEA_121_offset 0x00179800UL
6345 /* Default value: 0x0000000000000000 */
6347 #define QIB_7322_SendBufMA_122_offset 0x0017a000UL
6348 /* Default value: 0x0000000000000000 */
6350 #define QIB_7322_SendBufEA_122_offset 0x0017a800UL
6351 /* Default value: 0x0000000000000000 */
6353 #define QIB_7322_SendBufMA_123_offset 0x0017b000UL
6354 /* Default value: 0x0000000000000000 */
6356 #define QIB_7322_SendBufEA_123_offset 0x0017b800UL
6357 /* Default value: 0x0000000000000000 */
6359 #define QIB_7322_SendBufMA_124_offset 0x0017c000UL
6360 /* Default value: 0x0000000000000000 */
6362 #define QIB_7322_SendBufEA_124_offset 0x0017c800UL
6363 /* Default value: 0x0000000000000000 */
6365 #define QIB_7322_SendBufMA_125_offset 0x0017d000UL
6366 /* Default value: 0x0000000000000000 */
6368 #define QIB_7322_SendBufEA_125_offset 0x0017d800UL
6369 /* Default value: 0x0000000000000000 */
6371 #define QIB_7322_SendBufMA_126_offset 0x0017e000UL
6372 /* Default value: 0x0000000000000000 */
6374 #define QIB_7322_SendBufEA_126_offset 0x0017e800UL
6375 /* Default value: 0x0000000000000000 */
6377 #define QIB_7322_SendBufMA_127_offset 0x0017f000UL
6378 /* Default value: 0x0000000000000000 */
6380 #define QIB_7322_SendBufEA_127_offset 0x0017f800UL
6381 /* Default value: 0x0000000000000000 */
6383 #define QIB_7322_SendBufMA_128_offset 0x00180000UL
6384 /* Default value: 0x0000000000000000 */
6386 #define QIB_7322_SendBufEA_128_offset 0x00181000UL
6387 /* Default value: 0x0000000000000000 */
6389 #define QIB_7322_SendBufMA_129_offset 0x00182000UL
6390 /* Default value: 0x0000000000000000 */
6392 #define QIB_7322_SendBufEA_129_offset 0x00183000UL
6393 /* Default value: 0x0000000000000000 */
6395 #define QIB_7322_SendBufMA_130_offset 0x00184000UL
6396 /* Default value: 0x0000000000000000 */
6398 #define QIB_7322_SendBufEA_130_offset 0x00185000UL
6399 /* Default value: 0x0000000000000000 */
6401 #define QIB_7322_SendBufMA_131_offset 0x00186000UL
6402 /* Default value: 0x0000000000000000 */
6404 #define QIB_7322_SendBufEA_131_offset 0x00187000UL
6405 /* Default value: 0x0000000000000000 */
6407 #define QIB_7322_SendBufMA_132_offset 0x00188000UL
6408 /* Default value: 0x0000000000000000 */
6410 #define QIB_7322_SendBufEA_132_offset 0x00189000UL
6411 /* Default value: 0x0000000000000000 */
6413 #define QIB_7322_SendBufMA_133_offset 0x0018a000UL
6414 /* Default value: 0x0000000000000000 */
6416 #define QIB_7322_SendBufEA_133_offset 0x0018b000UL
6417 /* Default value: 0x0000000000000000 */
6419 #define QIB_7322_SendBufMA_134_offset 0x0018c000UL
6420 /* Default value: 0x0000000000000000 */
6422 #define QIB_7322_SendBufEA_134_offset 0x0018d000UL
6423 /* Default value: 0x0000000000000000 */
6425 #define QIB_7322_SendBufMA_135_offset 0x0018e000UL
6426 /* Default value: 0x0000000000000000 */
6428 #define QIB_7322_SendBufEA_135_offset 0x0018f000UL
6429 /* Default value: 0x0000000000000000 */
6431 #define QIB_7322_SendBufMA_136_offset 0x00190000UL
6432 /* Default value: 0x0000000000000000 */
6434 #define QIB_7322_SendBufEA_136_offset 0x00191000UL
6435 /* Default value: 0x0000000000000000 */
6437 #define QIB_7322_SendBufMA_137_offset 0x00192000UL
6438 /* Default value: 0x0000000000000000 */
6440 #define QIB_7322_SendBufEA_137_offset 0x00193000UL
6441 /* Default value: 0x0000000000000000 */
6443 #define QIB_7322_SendBufMA_138_offset 0x00194000UL
6444 /* Default value: 0x0000000000000000 */
6446 #define QIB_7322_SendBufEA_138_offset 0x00195000UL
6447 /* Default value: 0x0000000000000000 */
6449 #define QIB_7322_SendBufMA_139_offset 0x00196000UL
6450 /* Default value: 0x0000000000000000 */
6452 #define QIB_7322_SendBufEA_139_offset 0x00197000UL
6453 /* Default value: 0x0000000000000000 */
6455 #define QIB_7322_SendBufMA_140_offset 0x00198000UL
6456 /* Default value: 0x0000000000000000 */
6458 #define QIB_7322_SendBufEA_140_offset 0x00199000UL
6459 /* Default value: 0x0000000000000000 */
6461 #define QIB_7322_SendBufMA_141_offset 0x0019a000UL
6462 /* Default value: 0x0000000000000000 */
6464 #define QIB_7322_SendBufEA_141_offset 0x0019b000UL
6465 /* Default value: 0x0000000000000000 */
6467 #define QIB_7322_SendBufMA_142_offset 0x0019c000UL
6468 /* Default value: 0x0000000000000000 */
6470 #define QIB_7322_SendBufEA_142_offset 0x0019d000UL
6471 /* Default value: 0x0000000000000000 */
6473 #define QIB_7322_SendBufMA_143_offset 0x0019e000UL
6474 /* Default value: 0x0000000000000000 */
6476 #define QIB_7322_SendBufEA_143_offset 0x0019f000UL
6477 /* Default value: 0x0000000000000000 */
6479 #define QIB_7322_SendBufMA_144_offset 0x001a0000UL
6480 /* Default value: 0x0000000000000000 */
6482 #define QIB_7322_SendBufEA_144_offset 0x001a1000UL
6483 /* Default value: 0x0000000000000000 */
6485 #define QIB_7322_SendBufMA_145_offset 0x001a2000UL
6486 /* Default value: 0x0000000000000000 */
6488 #define QIB_7322_SendBufEA_145_offset 0x001a3000UL
6489 /* Default value: 0x0000000000000000 */
6491 #define QIB_7322_SendBufMA_146_offset 0x001a4000UL
6492 /* Default value: 0x0000000000000000 */
6494 #define QIB_7322_SendBufEA_146_offset 0x001a5000UL
6495 /* Default value: 0x0000000000000000 */
6497 #define QIB_7322_SendBufMA_147_offset 0x001a6000UL
6498 /* Default value: 0x0000000000000000 */
6500 #define QIB_7322_SendBufEA_147_offset 0x001a7000UL
6501 /* Default value: 0x0000000000000000 */
6503 #define QIB_7322_SendBufMA_148_offset 0x001a8000UL
6504 /* Default value: 0x0000000000000000 */
6506 #define QIB_7322_SendBufEA_148_offset 0x001a9000UL
6507 /* Default value: 0x0000000000000000 */
6509 #define QIB_7322_SendBufMA_149_offset 0x001aa000UL
6510 /* Default value: 0x0000000000000000 */
6512 #define QIB_7322_SendBufEA_149_offset 0x001ab000UL
6513 /* Default value: 0x0000000000000000 */
6515 #define QIB_7322_SendBufMA_150_offset 0x001ac000UL
6516 /* Default value: 0x0000000000000000 */
6518 #define QIB_7322_SendBufEA_150_offset 0x001ad000UL
6519 /* Default value: 0x0000000000000000 */
6521 #define QIB_7322_SendBufMA_151_offset 0x001ae000UL
6522 /* Default value: 0x0000000000000000 */
6524 #define QIB_7322_SendBufEA_151_offset 0x001af000UL
6525 /* Default value: 0x0000000000000000 */
6527 #define QIB_7322_SendBufMA_152_offset 0x001b0000UL
6528 /* Default value: 0x0000000000000000 */
6530 #define QIB_7322_SendBufEA_152_offset 0x001b1000UL
6531 /* Default value: 0x0000000000000000 */
6533 #define QIB_7322_SendBufMA_153_offset 0x001b2000UL
6534 /* Default value: 0x0000000000000000 */
6536 #define QIB_7322_SendBufEA_153_offset 0x001b3000UL
6537 /* Default value: 0x0000000000000000 */
6539 #define QIB_7322_SendBufMA_154_offset 0x001b4000UL
6540 /* Default value: 0x0000000000000000 */
6542 #define QIB_7322_SendBufEA_154_offset 0x001b5000UL
6543 /* Default value: 0x0000000000000000 */
6545 #define QIB_7322_SendBufMA_155_offset 0x001b6000UL
6546 /* Default value: 0x0000000000000000 */
6548 #define QIB_7322_SendBufEA_155_offset 0x001b7000UL
6549 /* Default value: 0x0000000000000000 */
6551 #define QIB_7322_SendBufMA_156_offset 0x001b8000UL
6552 /* Default value: 0x0000000000000000 */
6554 #define QIB_7322_SendBufEA_156_offset 0x001b9000UL
6555 /* Default value: 0x0000000000000000 */
6557 #define QIB_7322_SendBufMA_157_offset 0x001ba000UL
6558 /* Default value: 0x0000000000000000 */
6560 #define QIB_7322_SendBufEA_157_offset 0x001bb000UL
6561 /* Default value: 0x0000000000000000 */
6563 #define QIB_7322_SendBufMA_158_offset 0x001bc000UL
6564 /* Default value: 0x0000000000000000 */
6566 #define QIB_7322_SendBufEA_158_offset 0x001bd000UL
6567 /* Default value: 0x0000000000000000 */
6569 #define QIB_7322_SendBufMA_159_offset 0x001be000UL
6570 /* Default value: 0x0000000000000000 */
6572 #define QIB_7322_SendBufEA_159_offset 0x001bf000UL
6573 /* Default value: 0x0000000000000000 */
6575 #define QIB_7322_SendBufVL15_0_offset 0x001c0000UL
6576 /* Default value: 0x0000000000000000 */
6578 #define QIB_7322_RcvHdrTail0_offset 0x00200000UL
6579 /* Default value: 0x0000000000000000 */
6581 #define QIB_7322_RcvHdrHead0_offset 0x00200008UL
6582 struct QIB_7322_RcvHdrHead0_pb {
6583 pseudo_bit_t RcvHeadPointer[32];
6584 pseudo_bit_t counter[16];
6585 pseudo_bit_t _unused_0[16];
6587 struct QIB_7322_RcvHdrHead0 {
6588 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead0_pb );
6590 /* Default value: 0x0000000000000000 */
6592 #define QIB_7322_RcvEgrIndexTail0_offset 0x00200010UL
6593 /* Default value: 0x0000000000000000 */
6595 #define QIB_7322_RcvEgrIndexHead0_offset 0x00200018UL
6596 /* Default value: 0x0000000000000000 */
6598 #define QIB_7322_RcvTIDFlowTable0_offset 0x00201000UL
6599 struct QIB_7322_RcvTIDFlowTable0_pb {
6600 pseudo_bit_t SeqNum[11];
6601 pseudo_bit_t GenVal[8];
6602 pseudo_bit_t FlowValid[1];
6603 pseudo_bit_t HdrSuppEnabled[1];
6604 pseudo_bit_t KeepAfterSeqErr[1];
6605 pseudo_bit_t KeepOnGenErr[1];
6606 pseudo_bit_t _unused_0[4];
6607 pseudo_bit_t SeqMismatch[1];
6608 pseudo_bit_t GenMismatch[1];
6609 pseudo_bit_t _unused_1[35];
6611 struct QIB_7322_RcvTIDFlowTable0 {
6612 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable0_pb );
6614 /* Default value: 0x0000000000000000 */
6616 #define QIB_7322_RcvHdrTail1_offset 0x00210000UL
6617 /* Default value: 0x0000000000000000 */
6619 #define QIB_7322_RcvHdrHead1_offset 0x00210008UL
6620 struct QIB_7322_RcvHdrHead1_pb {
6621 pseudo_bit_t RcvHeadPointer[32];
6622 pseudo_bit_t counter[16];
6623 pseudo_bit_t _unused_0[16];
6625 struct QIB_7322_RcvHdrHead1 {
6626 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead1_pb );
6628 /* Default value: 0x0000000000000000 */
6630 #define QIB_7322_RcvEgrIndexTail1_offset 0x00210010UL
6631 /* Default value: 0x0000000000000000 */
6633 #define QIB_7322_RcvEgrIndexHead1_offset 0x00210018UL
6634 /* Default value: 0x0000000000000000 */
6636 #define QIB_7322_RcvTIDFlowTable1_offset 0x00211000UL
6637 struct QIB_7322_RcvTIDFlowTable1_pb {
6638 pseudo_bit_t SeqNum[11];
6639 pseudo_bit_t GenVal[8];
6640 pseudo_bit_t FlowValid[1];
6641 pseudo_bit_t HdrSuppEnabled[1];
6642 pseudo_bit_t KeepAfterSeqErr[1];
6643 pseudo_bit_t KeepOnGenErr[1];
6644 pseudo_bit_t _unused_0[4];
6645 pseudo_bit_t SeqMismatch[1];
6646 pseudo_bit_t GenMismatch[1];
6647 pseudo_bit_t _unused_1[35];
6649 struct QIB_7322_RcvTIDFlowTable1 {
6650 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable1_pb );
6652 /* Default value: 0x0000000000000000 */
6654 #define QIB_7322_RcvHdrTail2_offset 0x00220000UL
6655 /* Default value: 0x0000000000000000 */
6657 #define QIB_7322_RcvHdrHead2_offset 0x00220008UL
6658 struct QIB_7322_RcvHdrHead2_pb {
6659 pseudo_bit_t RcvHeadPointer[32];
6660 pseudo_bit_t counter[16];
6661 pseudo_bit_t _unused_0[16];
6663 struct QIB_7322_RcvHdrHead2 {
6664 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead2_pb );
6666 /* Default value: 0x0000000000000000 */
6668 #define QIB_7322_RcvEgrIndexTail2_offset 0x00220010UL
6669 /* Default value: 0x0000000000000000 */
6671 #define QIB_7322_RcvEgrIndexHead2_offset 0x00220018UL
6672 /* Default value: 0x0000000000000000 */
6674 #define QIB_7322_RcvTIDFlowTable2_offset 0x00221000UL
6675 struct QIB_7322_RcvTIDFlowTable2_pb {
6676 pseudo_bit_t SeqNum[11];
6677 pseudo_bit_t GenVal[8];
6678 pseudo_bit_t FlowValid[1];
6679 pseudo_bit_t HdrSuppEnabled[1];
6680 pseudo_bit_t KeepAfterSeqErr[1];
6681 pseudo_bit_t KeepOnGenErr[1];
6682 pseudo_bit_t _unused_0[4];
6683 pseudo_bit_t SeqMismatch[1];
6684 pseudo_bit_t GenMismatch[1];
6685 pseudo_bit_t _unused_1[35];
6687 struct QIB_7322_RcvTIDFlowTable2 {
6688 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable2_pb );
6690 /* Default value: 0x0000000000000000 */
6692 #define QIB_7322_RcvHdrTail3_offset 0x00230000UL
6693 /* Default value: 0x0000000000000000 */
6695 #define QIB_7322_RcvHdrHead3_offset 0x00230008UL
6696 struct QIB_7322_RcvHdrHead3_pb {
6697 pseudo_bit_t RcvHeadPointer[32];
6698 pseudo_bit_t counter[16];
6699 pseudo_bit_t _unused_0[16];
6701 struct QIB_7322_RcvHdrHead3 {
6702 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead3_pb );
6704 /* Default value: 0x0000000000000000 */
6706 #define QIB_7322_RcvEgrIndexTail3_offset 0x00230010UL
6707 /* Default value: 0x0000000000000000 */
6709 #define QIB_7322_RcvEgrIndexHead3_offset 0x00230018UL
6710 /* Default value: 0x0000000000000000 */
6712 #define QIB_7322_RcvTIDFlowTable3_offset 0x00231000UL
6713 struct QIB_7322_RcvTIDFlowTable3_pb {
6714 pseudo_bit_t SeqNum[11];
6715 pseudo_bit_t GenVal[8];
6716 pseudo_bit_t FlowValid[1];
6717 pseudo_bit_t HdrSuppEnabled[1];
6718 pseudo_bit_t KeepAfterSeqErr[1];
6719 pseudo_bit_t KeepOnGenErr[1];
6720 pseudo_bit_t _unused_0[4];
6721 pseudo_bit_t SeqMismatch[1];
6722 pseudo_bit_t GenMismatch[1];
6723 pseudo_bit_t _unused_1[35];
6725 struct QIB_7322_RcvTIDFlowTable3 {
6726 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable3_pb );
6728 /* Default value: 0x0000000000000000 */
6730 #define QIB_7322_RcvHdrTail4_offset 0x00240000UL
6731 /* Default value: 0x0000000000000000 */
6733 #define QIB_7322_RcvHdrHead4_offset 0x00240008UL
6734 struct QIB_7322_RcvHdrHead4_pb {
6735 pseudo_bit_t RcvHeadPointer[32];
6736 pseudo_bit_t counter[16];
6737 pseudo_bit_t _unused_0[16];
6739 struct QIB_7322_RcvHdrHead4 {
6740 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead4_pb );
6742 /* Default value: 0x0000000000000000 */
6744 #define QIB_7322_RcvEgrIndexTail4_offset 0x00240010UL
6745 /* Default value: 0x0000000000000000 */
6747 #define QIB_7322_RcvEgrIndexHead4_offset 0x00240018UL
6748 /* Default value: 0x0000000000000000 */
6750 #define QIB_7322_RcvTIDFlowTable4_offset 0x00241000UL
6751 struct QIB_7322_RcvTIDFlowTable4_pb {
6752 pseudo_bit_t SeqNum[11];
6753 pseudo_bit_t GenVal[8];
6754 pseudo_bit_t FlowValid[1];
6755 pseudo_bit_t HdrSuppEnabled[1];
6756 pseudo_bit_t KeepAfterSeqErr[1];
6757 pseudo_bit_t KeepOnGenErr[1];
6758 pseudo_bit_t _unused_0[4];
6759 pseudo_bit_t SeqMismatch[1];
6760 pseudo_bit_t GenMismatch[1];
6761 pseudo_bit_t _unused_1[35];
6763 struct QIB_7322_RcvTIDFlowTable4 {
6764 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable4_pb );
6766 /* Default value: 0x0000000000000000 */
6768 #define QIB_7322_RcvHdrTail5_offset 0x00250000UL
6769 /* Default value: 0x0000000000000000 */
6771 #define QIB_7322_RcvHdrHead5_offset 0x00250008UL
6772 struct QIB_7322_RcvHdrHead5_pb {
6773 pseudo_bit_t RcvHeadPointer[32];
6774 pseudo_bit_t counter[16];
6775 pseudo_bit_t _unused_0[16];
6777 struct QIB_7322_RcvHdrHead5 {
6778 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead5_pb );
6780 /* Default value: 0x0000000000000000 */
6782 #define QIB_7322_RcvEgrIndexTail5_offset 0x00250010UL
6783 /* Default value: 0x0000000000000000 */
6785 #define QIB_7322_RcvEgrIndexHead5_offset 0x00250018UL
6786 /* Default value: 0x0000000000000000 */
6788 #define QIB_7322_RcvTIDFlowTable5_offset 0x00251000UL
6789 struct QIB_7322_RcvTIDFlowTable5_pb {
6790 pseudo_bit_t SeqNum[11];
6791 pseudo_bit_t GenVal[8];
6792 pseudo_bit_t FlowValid[1];
6793 pseudo_bit_t HdrSuppEnabled[1];
6794 pseudo_bit_t KeepAfterSeqErr[1];
6795 pseudo_bit_t KeepOnGenErr[1];
6796 pseudo_bit_t _unused_0[4];
6797 pseudo_bit_t SeqMismatch[1];
6798 pseudo_bit_t GenMismatch[1];
6799 pseudo_bit_t _unused_1[35];
6801 struct QIB_7322_RcvTIDFlowTable5 {
6802 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable5_pb );
6804 /* Default value: 0x0000000000000000 */
6806 #define QIB_7322_RcvHdrTail6_offset 0x00260000UL
6807 /* Default value: 0x0000000000000000 */
6809 #define QIB_7322_RcvHdrHead6_offset 0x00260008UL
6810 struct QIB_7322_RcvHdrHead6_pb {
6811 pseudo_bit_t RcvHeadPointer[32];
6812 pseudo_bit_t counter[16];
6813 pseudo_bit_t _unused_0[16];
6815 struct QIB_7322_RcvHdrHead6 {
6816 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead6_pb );
6818 /* Default value: 0x0000000000000000 */
6820 #define QIB_7322_RcvEgrIndexTail6_offset 0x00260010UL
6821 /* Default value: 0x0000000000000000 */
6823 #define QIB_7322_RcvEgrIndexHead6_offset 0x00260018UL
6824 /* Default value: 0x0000000000000000 */
6826 #define QIB_7322_RcvTIDFlowTable6_offset 0x00261000UL
6827 struct QIB_7322_RcvTIDFlowTable6_pb {
6828 pseudo_bit_t SeqNum[11];
6829 pseudo_bit_t GenVal[8];
6830 pseudo_bit_t FlowValid[1];
6831 pseudo_bit_t HdrSuppEnabled[1];
6832 pseudo_bit_t KeepAfterSeqErr[1];
6833 pseudo_bit_t KeepOnGenErr[1];
6834 pseudo_bit_t _unused_0[4];
6835 pseudo_bit_t SeqMismatch[1];
6836 pseudo_bit_t GenMismatch[1];
6837 pseudo_bit_t _unused_1[35];
6839 struct QIB_7322_RcvTIDFlowTable6 {
6840 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable6_pb );
6842 /* Default value: 0x0000000000000000 */
6844 #define QIB_7322_RcvHdrTail7_offset 0x00270000UL
6845 /* Default value: 0x0000000000000000 */
6847 #define QIB_7322_RcvHdrHead7_offset 0x00270008UL
6848 struct QIB_7322_RcvHdrHead7_pb {
6849 pseudo_bit_t RcvHeadPointer[32];
6850 pseudo_bit_t counter[16];
6851 pseudo_bit_t _unused_0[16];
6853 struct QIB_7322_RcvHdrHead7 {
6854 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead7_pb );
6856 /* Default value: 0x0000000000000000 */
6858 #define QIB_7322_RcvEgrIndexTail7_offset 0x00270010UL
6859 /* Default value: 0x0000000000000000 */
6861 #define QIB_7322_RcvEgrIndexHead7_offset 0x00270018UL
6862 /* Default value: 0x0000000000000000 */
6864 #define QIB_7322_RcvTIDFlowTable7_offset 0x00271000UL
6865 struct QIB_7322_RcvTIDFlowTable7_pb {
6866 pseudo_bit_t SeqNum[11];
6867 pseudo_bit_t GenVal[8];
6868 pseudo_bit_t FlowValid[1];
6869 pseudo_bit_t HdrSuppEnabled[1];
6870 pseudo_bit_t KeepAfterSeqErr[1];
6871 pseudo_bit_t KeepOnGenErr[1];
6872 pseudo_bit_t _unused_0[4];
6873 pseudo_bit_t SeqMismatch[1];
6874 pseudo_bit_t GenMismatch[1];
6875 pseudo_bit_t _unused_1[35];
6877 struct QIB_7322_RcvTIDFlowTable7 {
6878 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable7_pb );
6880 /* Default value: 0x0000000000000000 */
6882 #define QIB_7322_RcvHdrTail8_offset 0x00280000UL
6883 /* Default value: 0x0000000000000000 */
6885 #define QIB_7322_RcvHdrHead8_offset 0x00280008UL
6886 struct QIB_7322_RcvHdrHead8_pb {
6887 pseudo_bit_t RcvHeadPointer[32];
6888 pseudo_bit_t counter[16];
6889 pseudo_bit_t _unused_0[16];
6891 struct QIB_7322_RcvHdrHead8 {
6892 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead8_pb );
6894 /* Default value: 0x0000000000000000 */
6896 #define QIB_7322_RcvEgrIndexTail8_offset 0x00280010UL
6897 /* Default value: 0x0000000000000000 */
6899 #define QIB_7322_RcvEgrIndexHead8_offset 0x00280018UL
6900 /* Default value: 0x0000000000000000 */
6902 #define QIB_7322_RcvTIDFlowTable8_offset 0x00281000UL
6903 struct QIB_7322_RcvTIDFlowTable8_pb {
6904 pseudo_bit_t SeqNum[11];
6905 pseudo_bit_t GenVal[8];
6906 pseudo_bit_t FlowValid[1];
6907 pseudo_bit_t HdrSuppEnabled[1];
6908 pseudo_bit_t KeepAfterSeqErr[1];
6909 pseudo_bit_t KeepOnGenErr[1];
6910 pseudo_bit_t _unused_0[4];
6911 pseudo_bit_t SeqMismatch[1];
6912 pseudo_bit_t GenMismatch[1];
6913 pseudo_bit_t _unused_1[35];
6915 struct QIB_7322_RcvTIDFlowTable8 {
6916 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable8_pb );
6918 /* Default value: 0x0000000000000000 */
6920 #define QIB_7322_RcvHdrTail9_offset 0x00290000UL
6921 /* Default value: 0x0000000000000000 */
6923 #define QIB_7322_RcvHdrHead9_offset 0x00290008UL
6924 struct QIB_7322_RcvHdrHead9_pb {
6925 pseudo_bit_t RcvHeadPointer[32];
6926 pseudo_bit_t counter[16];
6927 pseudo_bit_t _unused_0[16];
6929 struct QIB_7322_RcvHdrHead9 {
6930 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead9_pb );
6932 /* Default value: 0x0000000000000000 */
6934 #define QIB_7322_RcvEgrIndexTail9_offset 0x00290010UL
6935 /* Default value: 0x0000000000000000 */
6937 #define QIB_7322_RcvEgrIndexHead9_offset 0x00290018UL
6938 /* Default value: 0x0000000000000000 */
6940 #define QIB_7322_RcvTIDFlowTable9_offset 0x00291000UL
6941 struct QIB_7322_RcvTIDFlowTable9_pb {
6942 pseudo_bit_t SeqNum[11];
6943 pseudo_bit_t GenVal[8];
6944 pseudo_bit_t FlowValid[1];
6945 pseudo_bit_t HdrSuppEnabled[1];
6946 pseudo_bit_t KeepAfterSeqErr[1];
6947 pseudo_bit_t KeepOnGenErr[1];
6948 pseudo_bit_t _unused_0[4];
6949 pseudo_bit_t SeqMismatch[1];
6950 pseudo_bit_t GenMismatch[1];
6951 pseudo_bit_t _unused_1[35];
6953 struct QIB_7322_RcvTIDFlowTable9 {
6954 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable9_pb );
6956 /* Default value: 0x0000000000000000 */
6958 #define QIB_7322_RcvHdrTail10_offset 0x002a0000UL
6959 /* Default value: 0x0000000000000000 */
6961 #define QIB_7322_RcvHdrHead10_offset 0x002a0008UL
6962 struct QIB_7322_RcvHdrHead10_pb {
6963 pseudo_bit_t RcvHeadPointer[32];
6964 pseudo_bit_t counter[16];
6965 pseudo_bit_t _unused_0[16];
6967 struct QIB_7322_RcvHdrHead10 {
6968 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead10_pb );
6970 /* Default value: 0x0000000000000000 */
6972 #define QIB_7322_RcvEgrIndexTail10_offset 0x002a0010UL
6973 /* Default value: 0x0000000000000000 */
6975 #define QIB_7322_RcvEgrIndexHead10_offset 0x002a0018UL
6976 /* Default value: 0x0000000000000000 */
6978 #define QIB_7322_RcvTIDFlowTable10_offset 0x002a1000UL
6979 struct QIB_7322_RcvTIDFlowTable10_pb {
6980 pseudo_bit_t SeqNum[11];
6981 pseudo_bit_t GenVal[8];
6982 pseudo_bit_t FlowValid[1];
6983 pseudo_bit_t HdrSuppEnabled[1];
6984 pseudo_bit_t KeepAfterSeqErr[1];
6985 pseudo_bit_t KeepOnGenErr[1];
6986 pseudo_bit_t _unused_0[4];
6987 pseudo_bit_t SeqMismatch[1];
6988 pseudo_bit_t GenMismatch[1];
6989 pseudo_bit_t _unused_1[35];
6991 struct QIB_7322_RcvTIDFlowTable10 {
6992 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable10_pb );
6994 /* Default value: 0x0000000000000000 */
6996 #define QIB_7322_RcvHdrTail11_offset 0x002b0000UL
6997 /* Default value: 0x0000000000000000 */
6999 #define QIB_7322_RcvHdrHead11_offset 0x002b0008UL
7000 struct QIB_7322_RcvHdrHead11_pb {
7001 pseudo_bit_t RcvHeadPointer[32];
7002 pseudo_bit_t counter[16];
7003 pseudo_bit_t _unused_0[16];
7005 struct QIB_7322_RcvHdrHead11 {
7006 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead11_pb );
7008 /* Default value: 0x0000000000000000 */
7010 #define QIB_7322_RcvEgrIndexTail11_offset 0x002b0010UL
7011 /* Default value: 0x0000000000000000 */
7013 #define QIB_7322_RcvEgrIndexHead11_offset 0x002b0018UL
7014 /* Default value: 0x0000000000000000 */
7016 #define QIB_7322_RcvTIDFlowTable11_offset 0x002b1000UL
7017 struct QIB_7322_RcvTIDFlowTable11_pb {
7018 pseudo_bit_t SeqNum[11];
7019 pseudo_bit_t GenVal[8];
7020 pseudo_bit_t FlowValid[1];
7021 pseudo_bit_t HdrSuppEnabled[1];
7022 pseudo_bit_t KeepAfterSeqErr[1];
7023 pseudo_bit_t KeepOnGenErr[1];
7024 pseudo_bit_t _unused_0[4];
7025 pseudo_bit_t SeqMismatch[1];
7026 pseudo_bit_t GenMismatch[1];
7027 pseudo_bit_t _unused_1[35];
7029 struct QIB_7322_RcvTIDFlowTable11 {
7030 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable11_pb );
7032 /* Default value: 0x0000000000000000 */
7034 #define QIB_7322_RcvHdrTail12_offset 0x002c0000UL
7035 /* Default value: 0x0000000000000000 */
7037 #define QIB_7322_RcvHdrHead12_offset 0x002c0008UL
7038 struct QIB_7322_RcvHdrHead12_pb {
7039 pseudo_bit_t RcvHeadPointer[32];
7040 pseudo_bit_t counter[16];
7041 pseudo_bit_t _unused_0[16];
7043 struct QIB_7322_RcvHdrHead12 {
7044 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead12_pb );
7046 /* Default value: 0x0000000000000000 */
7048 #define QIB_7322_RcvEgrIndexTail12_offset 0x002c0010UL
7049 /* Default value: 0x0000000000000000 */
7051 #define QIB_7322_RcvEgrIndexHead12_offset 0x002c0018UL
7052 /* Default value: 0x0000000000000000 */
7054 #define QIB_7322_RcvTIDFlowTable12_offset 0x002c1000UL
7055 struct QIB_7322_RcvTIDFlowTable12_pb {
7056 pseudo_bit_t SeqNum[11];
7057 pseudo_bit_t GenVal[8];
7058 pseudo_bit_t FlowValid[1];
7059 pseudo_bit_t HdrSuppEnabled[1];
7060 pseudo_bit_t KeepAfterSeqErr[1];
7061 pseudo_bit_t KeepOnGenErr[1];
7062 pseudo_bit_t _unused_0[4];
7063 pseudo_bit_t SeqMismatch[1];
7064 pseudo_bit_t GenMismatch[1];
7065 pseudo_bit_t _unused_1[35];
7067 struct QIB_7322_RcvTIDFlowTable12 {
7068 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable12_pb );
7070 /* Default value: 0x0000000000000000 */
7072 #define QIB_7322_RcvHdrTail13_offset 0x002d0000UL
7073 /* Default value: 0x0000000000000000 */
7075 #define QIB_7322_RcvHdrHead13_offset 0x002d0008UL
7076 struct QIB_7322_RcvHdrHead13_pb {
7077 pseudo_bit_t RcvHeadPointer[32];
7078 pseudo_bit_t counter[16];
7079 pseudo_bit_t _unused_0[16];
7081 struct QIB_7322_RcvHdrHead13 {
7082 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead13_pb );
7084 /* Default value: 0x0000000000000000 */
7086 #define QIB_7322_RcvEgrIndexTail13_offset 0x002d0010UL
7087 /* Default value: 0x0000000000000000 */
7089 #define QIB_7322_RcvEgrIndexHead13_offset 0x002d0018UL
7090 /* Default value: 0x0000000000000000 */
7092 #define QIB_7322_RcvTIDFlowTable13_offset 0x002d1000UL
7093 struct QIB_7322_RcvTIDFlowTable13_pb {
7094 pseudo_bit_t SeqNum[11];
7095 pseudo_bit_t GenVal[8];
7096 pseudo_bit_t FlowValid[1];
7097 pseudo_bit_t HdrSuppEnabled[1];
7098 pseudo_bit_t KeepAfterSeqErr[1];
7099 pseudo_bit_t KeepOnGenErr[1];
7100 pseudo_bit_t _unused_0[4];
7101 pseudo_bit_t SeqMismatch[1];
7102 pseudo_bit_t GenMismatch[1];
7103 pseudo_bit_t _unused_1[35];
7105 struct QIB_7322_RcvTIDFlowTable13 {
7106 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable13_pb );
7108 /* Default value: 0x0000000000000000 */
7110 #define QIB_7322_RcvHdrTail14_offset 0x002e0000UL
7111 /* Default value: 0x0000000000000000 */
7113 #define QIB_7322_RcvHdrHead14_offset 0x002e0008UL
7114 struct QIB_7322_RcvHdrHead14_pb {
7115 pseudo_bit_t RcvHeadPointer[32];
7116 pseudo_bit_t counter[16];
7117 pseudo_bit_t _unused_0[16];
7119 struct QIB_7322_RcvHdrHead14 {
7120 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead14_pb );
7122 /* Default value: 0x0000000000000000 */
7124 #define QIB_7322_RcvEgrIndexTail14_offset 0x002e0010UL
7125 /* Default value: 0x0000000000000000 */
7127 #define QIB_7322_RcvEgrIndexHead14_offset 0x002e0018UL
7128 /* Default value: 0x0000000000000000 */
7130 #define QIB_7322_RcvTIDFlowTable14_offset 0x002e1000UL
7131 struct QIB_7322_RcvTIDFlowTable14_pb {
7132 pseudo_bit_t SeqNum[11];
7133 pseudo_bit_t GenVal[8];
7134 pseudo_bit_t FlowValid[1];
7135 pseudo_bit_t HdrSuppEnabled[1];
7136 pseudo_bit_t KeepAfterSeqErr[1];
7137 pseudo_bit_t KeepOnGenErr[1];
7138 pseudo_bit_t _unused_0[4];
7139 pseudo_bit_t SeqMismatch[1];
7140 pseudo_bit_t GenMismatch[1];
7141 pseudo_bit_t _unused_1[35];
7143 struct QIB_7322_RcvTIDFlowTable14 {
7144 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable14_pb );
7146 /* Default value: 0x0000000000000000 */
7148 #define QIB_7322_RcvHdrTail15_offset 0x002f0000UL
7149 /* Default value: 0x0000000000000000 */
7151 #define QIB_7322_RcvHdrHead15_offset 0x002f0008UL
7152 struct QIB_7322_RcvHdrHead15_pb {
7153 pseudo_bit_t RcvHeadPointer[32];
7154 pseudo_bit_t counter[16];
7155 pseudo_bit_t _unused_0[16];
7157 struct QIB_7322_RcvHdrHead15 {
7158 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead15_pb );
7160 /* Default value: 0x0000000000000000 */
7162 #define QIB_7322_RcvEgrIndexTail15_offset 0x002f0010UL
7163 /* Default value: 0x0000000000000000 */
7165 #define QIB_7322_RcvEgrIndexHead15_offset 0x002f0018UL
7166 /* Default value: 0x0000000000000000 */
7168 #define QIB_7322_RcvTIDFlowTable15_offset 0x002f1000UL
7169 struct QIB_7322_RcvTIDFlowTable15_pb {
7170 pseudo_bit_t SeqNum[11];
7171 pseudo_bit_t GenVal[8];
7172 pseudo_bit_t FlowValid[1];
7173 pseudo_bit_t HdrSuppEnabled[1];
7174 pseudo_bit_t KeepAfterSeqErr[1];
7175 pseudo_bit_t KeepOnGenErr[1];
7176 pseudo_bit_t _unused_0[4];
7177 pseudo_bit_t SeqMismatch[1];
7178 pseudo_bit_t GenMismatch[1];
7179 pseudo_bit_t _unused_1[35];
7181 struct QIB_7322_RcvTIDFlowTable15 {
7182 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable15_pb );
7184 /* Default value: 0x0000000000000000 */
7186 #define QIB_7322_RcvHdrTail16_offset 0x00300000UL
7187 /* Default value: 0x0000000000000000 */
7189 #define QIB_7322_RcvHdrHead16_offset 0x00300008UL
7190 struct QIB_7322_RcvHdrHead16_pb {
7191 pseudo_bit_t RcvHeadPointer[32];
7192 pseudo_bit_t counter[16];
7193 pseudo_bit_t _unused_0[16];
7195 struct QIB_7322_RcvHdrHead16 {
7196 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead16_pb );
7198 /* Default value: 0x0000000000000000 */
7200 #define QIB_7322_RcvEgrIndexTail16_offset 0x00300010UL
7201 /* Default value: 0x0000000000000000 */
7203 #define QIB_7322_RcvEgrIndexHead16_offset 0x00300018UL
7204 /* Default value: 0x0000000000000000 */
7206 #define QIB_7322_RcvTIDFlowTable16_offset 0x00301000UL
7207 struct QIB_7322_RcvTIDFlowTable16_pb {
7208 pseudo_bit_t SeqNum[11];
7209 pseudo_bit_t GenVal[8];
7210 pseudo_bit_t FlowValid[1];
7211 pseudo_bit_t HdrSuppEnabled[1];
7212 pseudo_bit_t KeepAfterSeqErr[1];
7213 pseudo_bit_t KeepOnGenErr[1];
7214 pseudo_bit_t _unused_0[4];
7215 pseudo_bit_t SeqMismatch[1];
7216 pseudo_bit_t GenMismatch[1];
7217 pseudo_bit_t _unused_1[35];
7219 struct QIB_7322_RcvTIDFlowTable16 {
7220 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable16_pb );
7222 /* Default value: 0x0000000000000000 */
7224 #define QIB_7322_RcvHdrTail17_offset 0x00310000UL
7225 /* Default value: 0x0000000000000000 */
7227 #define QIB_7322_RcvHdrHead17_offset 0x00310008UL
7228 struct QIB_7322_RcvHdrHead17_pb {
7229 pseudo_bit_t RcvHeadPointer[32];
7230 pseudo_bit_t counter[16];
7231 pseudo_bit_t _unused_0[16];
7233 struct QIB_7322_RcvHdrHead17 {
7234 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead17_pb );
7236 /* Default value: 0x0000000000000000 */
7238 #define QIB_7322_RcvEgrIndexTail17_offset 0x00310010UL
7239 /* Default value: 0x0000000000000000 */
7241 #define QIB_7322_RcvEgrIndexHead17_offset 0x00310018UL
7242 /* Default value: 0x0000000000000000 */
7244 #define QIB_7322_RcvTIDFlowTable17_offset 0x00311000UL
7245 struct QIB_7322_RcvTIDFlowTable17_pb {
7246 pseudo_bit_t SeqNum[11];
7247 pseudo_bit_t GenVal[8];
7248 pseudo_bit_t FlowValid[1];
7249 pseudo_bit_t HdrSuppEnabled[1];
7250 pseudo_bit_t KeepAfterSeqErr[1];
7251 pseudo_bit_t KeepOnGenErr[1];
7252 pseudo_bit_t _unused_0[4];
7253 pseudo_bit_t SeqMismatch[1];
7254 pseudo_bit_t GenMismatch[1];
7255 pseudo_bit_t _unused_1[35];
7257 struct QIB_7322_RcvTIDFlowTable17 {
7258 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable17_pb );
7260 /* Default value: 0x0000000000000000 */