qemu/roms/ipxe/src/drivers/infiniband/qib_7220_regs.h

   1 /*
   2  * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
   3  *
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  *
  33  */
  34 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
  35
  36 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */
  37
  38 FILE_LICENCE ( GPL2_ONLY );
  39
  40 #define QIB_7220_Revision_offset 0x00000000UL
  41 struct QIB_7220_Revision_pb {
  42         pseudo_bit_t R_ChipRevMinor[8];
  43         pseudo_bit_t R_ChipRevMajor[8];
  44         pseudo_bit_t R_Arch[8];
  45         pseudo_bit_t R_SW[8];
  46         pseudo_bit_t BoardID[8];
  47         pseudo_bit_t R_Emulation_Revcode[22];
  48         pseudo_bit_t R_Emulation[1];
  49         pseudo_bit_t R_Simulator[1];
  50 };
  51 struct QIB_7220_Revision {
  52         PSEUDO_BIT_STRUCT ( struct QIB_7220_Revision_pb );
  53 };
  54
  55 #define QIB_7220_Control_offset 0x00000008UL
  56 struct QIB_7220_Control_pb {
  57         pseudo_bit_t SyncReset[1];
  58         pseudo_bit_t FreezeMode[1];
  59         pseudo_bit_t LinkEn[1];
  60         pseudo_bit_t PCIERetryBufDiagEn[1];
  61         pseudo_bit_t TxLatency[1];
  62         pseudo_bit_t Reserved[1];
  63         pseudo_bit_t PCIECplQDiagEn[1];
  64         pseudo_bit_t SyncResetExceptPcieIRAMRST[1];
  65         pseudo_bit_t _unused_0[56];
  66 };
  67 struct QIB_7220_Control {
  68         PSEUDO_BIT_STRUCT ( struct QIB_7220_Control_pb );
  69 };
  70
  71 #define QIB_7220_PageAlign_offset 0x00000010UL
  72
  73 #define QIB_7220_PortCnt_offset 0x00000018UL
  74
  75 #define QIB_7220_DbgPortSel_offset 0x00000020UL
  76 struct QIB_7220_DbgPortSel_pb {
  77         pseudo_bit_t NibbleSel0[4];
  78         pseudo_bit_t NibbleSel1[4];
  79         pseudo_bit_t NibbleSel2[4];
  80         pseudo_bit_t NibbleSel3[4];
  81         pseudo_bit_t NibbleSel4[4];
  82         pseudo_bit_t NibbleSel5[4];
  83         pseudo_bit_t NibbleSel6[4];
  84         pseudo_bit_t NibbleSel7[4];
  85         pseudo_bit_t SrcMuxSel[14];
  86         pseudo_bit_t DbgClkPortSel[5];
  87         pseudo_bit_t EnDbgPort[1];
  88         pseudo_bit_t EnEnhancedDebugMode[1];
  89         pseudo_bit_t EnhMode_SrcMuxSelIndex[10];
  90         pseudo_bit_t EnhMode_SrcMuxSelWrEn[1];
  91 };
  92 struct QIB_7220_DbgPortSel {
  93         PSEUDO_BIT_STRUCT ( struct QIB_7220_DbgPortSel_pb );
  94 };
  95
  96 #define QIB_7220_DebugSigsIntSel_offset 0x00000028UL
  97 struct QIB_7220_DebugSigsIntSel_pb {
  98         pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3];
  99         pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3];
 100         pseudo_bit_t debug_port_sel_pcs_sdout[1];
 101         pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4];
 102         pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[4];
 103         pseudo_bit_t debug_port_sel_pcie_rx_tx[1];
 104         pseudo_bit_t debug_port_sel_xgxs[4];
 105         pseudo_bit_t debug_port_sel_epb_pcie[1];
 106         pseudo_bit_t _unused_0[43];
 107 };
 108 struct QIB_7220_DebugSigsIntSel {
 109         PSEUDO_BIT_STRUCT ( struct QIB_7220_DebugSigsIntSel_pb );
 110 };
 111
 112 #define QIB_7220_SendRegBase_offset 0x00000030UL
 113
 114 #define QIB_7220_UserRegBase_offset 0x00000038UL
 115
 116 #define QIB_7220_CntrRegBase_offset 0x00000040UL
 117
 118 #define QIB_7220_Scratch_offset 0x00000048UL
 119
 120 #define QIB_7220_REG_000050_offset 0x00000050UL
 121
 122 #define QIB_7220_IntBlocked_offset 0x00000060UL
 123 struct QIB_7220_IntBlocked_pb {
 124         pseudo_bit_t RcvAvail0IntBlocked[1];
 125         pseudo_bit_t RcvAvail1IntBlocked[1];
 126         pseudo_bit_t RcvAvail2IntBlocked[1];
 127         pseudo_bit_t RcvAvail3IntBlocked[1];
 128         pseudo_bit_t RcvAvail4IntBlocked[1];
 129         pseudo_bit_t RcvAvail5IntBlocked[1];
 130         pseudo_bit_t RcvAvail6IntBlocked[1];
 131         pseudo_bit_t RcvAvail7IntBlocked[1];
 132         pseudo_bit_t RcvAvail8IntBlocked[1];
 133         pseudo_bit_t RcvAvail9IntBlocked[1];
 134         pseudo_bit_t RcvAvail10IntBlocked[1];
 135         pseudo_bit_t RcvAvail11IntBlocked[1];
 136         pseudo_bit_t RcvAvail12IntBlocked[1];
 137         pseudo_bit_t RcvAvail13IntBlocked[1];
 138         pseudo_bit_t RcvAvail14IntBlocked[1];
 139         pseudo_bit_t RcvAvail15IntBlocked[1];
 140         pseudo_bit_t RcvAvail16IntBlocked[1];
 141         pseudo_bit_t Reserved1[9];
 142         pseudo_bit_t JIntBlocked[1];
 143         pseudo_bit_t IBSerdesTrimDoneIntBlocked[1];
 144         pseudo_bit_t assertGPIOIntBlocked[1];
 145         pseudo_bit_t PioBufAvailIntBlocked[1];
 146         pseudo_bit_t PioSetIntBlocked[1];
 147         pseudo_bit_t ErrorIntBlocked[1];
 148         pseudo_bit_t RcvUrg0IntBlocked[1];
 149         pseudo_bit_t RcvUrg1IntBlocked[1];
 150         pseudo_bit_t RcvUrg2IntBlocked[1];
 151         pseudo_bit_t RcvUrg3IntBlocked[1];
 152         pseudo_bit_t RcvUrg4IntBlocked[1];
 153         pseudo_bit_t RcvUrg5IntBlocked[1];
 154         pseudo_bit_t RcvUrg6IntBlocked[1];
 155         pseudo_bit_t RcvUrg7IntBlocked[1];
 156         pseudo_bit_t RcvUrg8IntBlocked[1];
 157         pseudo_bit_t RcvUrg9IntBlocked[1];
 158         pseudo_bit_t RcvUrg10IntBlocked[1];
 159         pseudo_bit_t RcvUrg11IntBlocked[1];
 160         pseudo_bit_t RcvUrg12IntBlocked[1];
 161         pseudo_bit_t RcvUrg13IntBlocked[1];
 162         pseudo_bit_t RcvUrg14IntBlocked[1];
 163         pseudo_bit_t RcvUrg15IntBlocked[1];
 164         pseudo_bit_t RcvUrg16IntBlocked[1];
 165         pseudo_bit_t Reserved[13];
 166         pseudo_bit_t SDmaDisabledBlocked[1];
 167         pseudo_bit_t SDmaIntBlocked[1];
 168 };
 169 struct QIB_7220_IntBlocked {
 170         PSEUDO_BIT_STRUCT ( struct QIB_7220_IntBlocked_pb );
 171 };
 172
 173 #define QIB_7220_IntMask_offset 0x00000068UL
 174 struct QIB_7220_IntMask_pb {
 175         pseudo_bit_t RcvAvail0IntMask[1];
 176         pseudo_bit_t RcvAvail1IntMask[1];
 177         pseudo_bit_t RcvAvail2IntMask[1];
 178         pseudo_bit_t RcvAvail3IntMask[1];
 179         pseudo_bit_t RcvAvail4IntMask[1];
 180         pseudo_bit_t RcvAvail5IntMask[1];
 181         pseudo_bit_t RcvAvail6IntMask[1];
 182         pseudo_bit_t RcvAvail7IntMask[1];
 183         pseudo_bit_t RcvAvail8IntMask[1];
 184         pseudo_bit_t RcvAvail9IntMask[1];
 185         pseudo_bit_t RcvAvail10IntMask[1];
 186         pseudo_bit_t RcvAvail11IntMask[1];
 187         pseudo_bit_t RcvAvail12IntMask[1];
 188         pseudo_bit_t RcvAvail13IntMask[1];
 189         pseudo_bit_t RcvAvail14IntMask[1];
 190         pseudo_bit_t RcvAvail15IntMask[1];
 191         pseudo_bit_t RcvAvail16IntMask[1];
 192         pseudo_bit_t Reserved1[9];
 193         pseudo_bit_t JIntMask[1];
 194         pseudo_bit_t IBSerdesTrimDoneIntMask[1];
 195         pseudo_bit_t assertGPIOIntMask[1];
 196         pseudo_bit_t PioBufAvailIntMask[1];
 197         pseudo_bit_t PioSetIntMask[1];
 198         pseudo_bit_t ErrorIntMask[1];
 199         pseudo_bit_t RcvUrg0IntMask[1];
 200         pseudo_bit_t RcvUrg1IntMask[1];
 201         pseudo_bit_t RcvUrg2IntMask[1];
 202         pseudo_bit_t RcvUrg3IntMask[1];
 203         pseudo_bit_t RcvUrg4IntMask[1];
 204         pseudo_bit_t RcvUrg5IntMask[1];
 205         pseudo_bit_t RcvUrg6IntMask[1];
 206         pseudo_bit_t RcvUrg7IntMask[1];
 207         pseudo_bit_t RcvUrg8IntMask[1];
 208         pseudo_bit_t RcvUrg9IntMask[1];
 209         pseudo_bit_t RcvUrg10IntMask[1];
 210         pseudo_bit_t RcvUrg11IntMask[1];
 211         pseudo_bit_t RcvUrg12IntMask[1];
 212         pseudo_bit_t RcvUrg13IntMask[1];
 213         pseudo_bit_t RcvUrg14IntMask[1];
 214         pseudo_bit_t RcvUrg15IntMask[1];
 215         pseudo_bit_t RcvUrg16IntMask[1];
 216         pseudo_bit_t Reserved[13];
 217         pseudo_bit_t SDmaDisabledMasked[1];
 218         pseudo_bit_t SDmaIntMask[1];
 219 };
 220 struct QIB_7220_IntMask {
 221         PSEUDO_BIT_STRUCT ( struct QIB_7220_IntMask_pb );
 222 };
 223
 224 #define QIB_7220_IntStatus_offset 0x00000070UL
 225 struct QIB_7220_IntStatus_pb {
 226         pseudo_bit_t RcvAvail0[1];
 227         pseudo_bit_t RcvAvail1[1];
 228         pseudo_bit_t RcvAvail2[1];
 229         pseudo_bit_t RcvAvail3[1];
 230         pseudo_bit_t RcvAvail4[1];
 231         pseudo_bit_t RcvAvail5[1];
 232         pseudo_bit_t RcvAvail6[1];
 233         pseudo_bit_t RcvAvail7[1];
 234         pseudo_bit_t RcvAvail8[1];
 235         pseudo_bit_t RcvAvail9[1];
 236         pseudo_bit_t RcvAvail10[1];
 237         pseudo_bit_t RcvAvail11[1];
 238         pseudo_bit_t RcvAvail12[1];
 239         pseudo_bit_t RcvAvail13[1];
 240         pseudo_bit_t RcvAvail14[1];
 241         pseudo_bit_t RcvAvail15[1];
 242         pseudo_bit_t RcvAvail16[1];
 243         pseudo_bit_t Reserved1[9];
 244         pseudo_bit_t JInt[1];
 245         pseudo_bit_t IBSerdesTrimDone[1];
 246         pseudo_bit_t assertGPIO[1];
 247         pseudo_bit_t PioBufAvail[1];
 248         pseudo_bit_t PioSent[1];
 249         pseudo_bit_t Error[1];
 250         pseudo_bit_t RcvUrg0[1];
 251         pseudo_bit_t RcvUrg1[1];
 252         pseudo_bit_t RcvUrg2[1];
 253         pseudo_bit_t RcvUrg3[1];
 254         pseudo_bit_t RcvUrg4[1];
 255         pseudo_bit_t RcvUrg5[1];
 256         pseudo_bit_t RcvUrg6[1];
 257         pseudo_bit_t RcvUrg7[1];
 258         pseudo_bit_t RcvUrg8[1];
 259         pseudo_bit_t RcvUrg9[1];
 260         pseudo_bit_t RcvUrg10[1];
 261         pseudo_bit_t RcvUrg11[1];
 262         pseudo_bit_t RcvUrg12[1];
 263         pseudo_bit_t RcvUrg13[1];
 264         pseudo_bit_t RcvUrg14[1];
 265         pseudo_bit_t RcvUrg15[1];
 266         pseudo_bit_t RcvUrg16[1];
 267         pseudo_bit_t Reserved[13];
 268         pseudo_bit_t SDmaDisabled[1];
 269         pseudo_bit_t SDmaInt[1];
 270 };
 271 struct QIB_7220_IntStatus {
 272         PSEUDO_BIT_STRUCT ( struct QIB_7220_IntStatus_pb );
 273 };
 274
 275 #define QIB_7220_IntClear_offset 0x00000078UL
 276 struct QIB_7220_IntClear_pb {
 277         pseudo_bit_t RcvAvail0IntClear[1];
 278         pseudo_bit_t RcvAvail1IntClear[1];
 279         pseudo_bit_t RcvAvail2IntClear[1];
 280         pseudo_bit_t RcvAvail3IntClear[1];
 281         pseudo_bit_t RcvAvail4IntClear[1];
 282         pseudo_bit_t RcvAvail5IntClear[1];
 283         pseudo_bit_t RcvAvail6IntClear[1];
 284         pseudo_bit_t RcvAvail7IntClear[1];
 285         pseudo_bit_t RcvAvail8IntClear[1];
 286         pseudo_bit_t RcvAvail9IntClear[1];
 287         pseudo_bit_t RcvAvail10IntClear[1];
 288         pseudo_bit_t RcvAvail11IntClear[1];
 289         pseudo_bit_t RcvAvail12IntClear[1];
 290         pseudo_bit_t RcvAvail13IntClear[1];
 291         pseudo_bit_t RcvAvail14IntClear[1];
 292         pseudo_bit_t RcvAvail15IntClear[1];
 293         pseudo_bit_t RcvAvail16IntClear[1];
 294         pseudo_bit_t Reserved1[9];
 295         pseudo_bit_t JIntClear[1];
 296         pseudo_bit_t IBSerdesTrimDoneClear[1];
 297         pseudo_bit_t assertGPIOIntClear[1];
 298         pseudo_bit_t PioBufAvailIntClear[1];
 299         pseudo_bit_t PioSetIntClear[1];
 300         pseudo_bit_t ErrorIntClear[1];
 301         pseudo_bit_t RcvUrg0IntClear[1];
 302         pseudo_bit_t RcvUrg1IntClear[1];
 303         pseudo_bit_t RcvUrg2IntClear[1];
 304         pseudo_bit_t RcvUrg3IntClear[1];
 305         pseudo_bit_t RcvUrg4IntClear[1];
 306         pseudo_bit_t RcvUrg5IntClear[1];
 307         pseudo_bit_t RcvUrg6IntClear[1];
 308         pseudo_bit_t RcvUrg7IntClear[1];
 309         pseudo_bit_t RcvUrg8IntClear[1];
 310         pseudo_bit_t RcvUrg9IntClear[1];
 311         pseudo_bit_t RcvUrg10IntClear[1];
 312         pseudo_bit_t RcvUrg11IntClear[1];
 313         pseudo_bit_t RcvUrg12IntClear[1];
 314         pseudo_bit_t RcvUrg13IntClear[1];
 315         pseudo_bit_t RcvUrg14IntClear[1];
 316         pseudo_bit_t RcvUrg15IntClear[1];
 317         pseudo_bit_t RcvUrg16IntClear[1];
 318         pseudo_bit_t Reserved[13];
 319         pseudo_bit_t SDmaDisabledClear[1];
 320         pseudo_bit_t SDmaIntClear[1];
 321 };
 322 struct QIB_7220_IntClear {
 323         PSEUDO_BIT_STRUCT ( struct QIB_7220_IntClear_pb );
 324 };
 325
 326 #define QIB_7220_ErrMask_offset 0x00000080UL
 327 struct QIB_7220_ErrMask_pb {
 328         pseudo_bit_t RcvFormatErrMask[1];
 329         pseudo_bit_t RcvVCRCErrMask[1];
 330         pseudo_bit_t RcvICRCErrMask[1];
 331         pseudo_bit_t RcvMinPktLenErrMask[1];
 332         pseudo_bit_t RcvMaxPktLenErrMask[1];
 333         pseudo_bit_t RcvLongPktLenErrMask[1];
 334         pseudo_bit_t RcvShortPktLenErrMask[1];
 335         pseudo_bit_t RcvUnexpectedCharErrMask[1];
 336         pseudo_bit_t RcvUnsupportedVLErrMask[1];
 337         pseudo_bit_t RcvEBPErrMask[1];
 338         pseudo_bit_t RcvIBFlowErrMask[1];
 339         pseudo_bit_t RcvBadVersionErrMask[1];
 340         pseudo_bit_t RcvEgrFullErrMask[1];
 341         pseudo_bit_t RcvHdrFullErrMask[1];
 342         pseudo_bit_t RcvBadTidErrMask[1];
 343         pseudo_bit_t RcvHdrLenErrMask[1];
 344         pseudo_bit_t RcvHdrErrMask[1];
 345         pseudo_bit_t RcvIBLostLinkErrMask[1];
 346         pseudo_bit_t Reserved1[9];
 347         pseudo_bit_t SendSpecialTriggerErrMask[1];
 348         pseudo_bit_t SDmaDisabledErrMask[1];
 349         pseudo_bit_t SendMinPktLenErrMask[1];
 350         pseudo_bit_t SendMaxPktLenErrMask[1];
 351         pseudo_bit_t SendUnderRunErrMask[1];
 352         pseudo_bit_t SendPktLenErrMask[1];
 353         pseudo_bit_t SendDroppedSmpPktErrMask[1];
 354         pseudo_bit_t SendDroppedDataPktErrMask[1];
 355         pseudo_bit_t SendPioArmLaunchErrMask[1];
 356         pseudo_bit_t SendUnexpectedPktNumErrMask[1];
 357         pseudo_bit_t SendUnsupportedVLErrMask[1];
 358         pseudo_bit_t SendBufMisuseErrMask[1];
 359         pseudo_bit_t SDmaGenMismatchErrMask[1];
 360         pseudo_bit_t SDmaOutOfBoundErrMask[1];
 361         pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
 362         pseudo_bit_t SDmaBaseErrMask[1];
 363         pseudo_bit_t SDma1stDescErrMask[1];
 364         pseudo_bit_t SDmaRpyTagErrMask[1];
 365         pseudo_bit_t SDmaDwEnErrMask[1];
 366         pseudo_bit_t SDmaMissingDwErrMask[1];
 367         pseudo_bit_t SDmaUnexpDataErrMask[1];
 368         pseudo_bit_t IBStatusChangedMask[1];
 369         pseudo_bit_t InvalidAddrErrMask[1];
 370         pseudo_bit_t ResetNegatedMask[1];
 371         pseudo_bit_t HardwareErrMask[1];
 372         pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
 373         pseudo_bit_t InvalidEEPCmdMask[1];
 374         pseudo_bit_t Reserved[10];
 375 };
 376 struct QIB_7220_ErrMask {
 377         PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrMask_pb );
 378 };
 379
 380 #define QIB_7220_ErrStatus_offset 0x00000088UL
 381 struct QIB_7220_ErrStatus_pb {
 382         pseudo_bit_t RcvFormatErr[1];
 383         pseudo_bit_t RcvVCRCErr[1];
 384         pseudo_bit_t RcvICRCErr[1];
 385         pseudo_bit_t RcvMinPktLenErr[1];
 386         pseudo_bit_t RcvMaxPktLenErr[1];
 387         pseudo_bit_t RcvLongPktLenErr[1];
 388         pseudo_bit_t RcvShortPktLenErr[1];
 389         pseudo_bit_t RcvUnexpectedCharErr[1];
 390         pseudo_bit_t RcvUnsupportedVLErr[1];
 391         pseudo_bit_t RcvEBPErr[1];
 392         pseudo_bit_t RcvIBFlowErr[1];
 393         pseudo_bit_t RcvBadVersionErr[1];
 394         pseudo_bit_t RcvEgrFullErr[1];
 395         pseudo_bit_t RcvHdrFullErr[1];
 396         pseudo_bit_t RcvBadTidErr[1];
 397         pseudo_bit_t RcvHdrLenErr[1];
 398         pseudo_bit_t RcvHdrErr[1];
 399         pseudo_bit_t RcvIBLostLinkErr[1];
 400         pseudo_bit_t Reserved1[9];
 401         pseudo_bit_t SendSpecialTriggerErr[1];
 402         pseudo_bit_t SDmaDisabledErr[1];
 403         pseudo_bit_t SendMinPktLenErr[1];
 404         pseudo_bit_t SendMaxPktLenErr[1];
 405         pseudo_bit_t SendUnderRunErr[1];
 406         pseudo_bit_t SendPktLenErr[1];
 407         pseudo_bit_t SendDroppedSmpPktErr[1];
 408         pseudo_bit_t SendDroppedDataPktErr[1];
 409         pseudo_bit_t SendPioArmLaunchErr[1];
 410         pseudo_bit_t SendUnexpectedPktNumErr[1];
 411         pseudo_bit_t SendUnsupportedVLErr[1];
 412         pseudo_bit_t SendBufMisuseErr[1];
 413         pseudo_bit_t SDmaGenMismatchErr[1];
 414         pseudo_bit_t SDmaOutOfBoundErr[1];
 415         pseudo_bit_t SDmaTailOutOfBoundErr[1];
 416         pseudo_bit_t SDmaBaseErr[1];
 417         pseudo_bit_t SDma1stDescErr[1];
 418         pseudo_bit_t SDmaRpyTagErr[1];
 419         pseudo_bit_t SDmaDwEnErr[1];
 420         pseudo_bit_t SDmaMissingDwErr[1];
 421         pseudo_bit_t SDmaUnexpDataErr[1];
 422         pseudo_bit_t IBStatusChanged[1];
 423         pseudo_bit_t InvalidAddrErr[1];
 424         pseudo_bit_t ResetNegated[1];
 425         pseudo_bit_t HardwareErr[1];
 426         pseudo_bit_t SDmaDescAddrMisalignErr[1];
 427         pseudo_bit_t InvalidEEPCmdErr[1];
 428         pseudo_bit_t Reserved[10];
 429 };
 430 struct QIB_7220_ErrStatus {
 431         PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrStatus_pb );
 432 };
 433
 434 #define QIB_7220_ErrClear_offset 0x00000090UL
 435 struct QIB_7220_ErrClear_pb {
 436         pseudo_bit_t RcvFormatErrClear[1];
 437         pseudo_bit_t RcvVCRCErrClear[1];
 438         pseudo_bit_t RcvICRCErrClear[1];
 439         pseudo_bit_t RcvMinPktLenErrClear[1];
 440         pseudo_bit_t RcvMaxPktLenErrClear[1];
 441         pseudo_bit_t RcvLongPktLenErrClear[1];
 442         pseudo_bit_t RcvShortPktLenErrClear[1];
 443         pseudo_bit_t RcvUnexpectedCharErrClear[1];
 444         pseudo_bit_t RcvUnsupportedVLErrClear[1];
 445         pseudo_bit_t RcvEBPErrClear[1];
 446         pseudo_bit_t RcvIBFlowErrClear[1];
 447         pseudo_bit_t RcvBadVersionErrClear[1];
 448         pseudo_bit_t RcvEgrFullErrClear[1];
 449         pseudo_bit_t RcvHdrFullErrClear[1];
 450         pseudo_bit_t RcvBadTidErrClear[1];
 451         pseudo_bit_t RcvHdrLenErrClear[1];
 452         pseudo_bit_t RcvHdrErrClear[1];
 453         pseudo_bit_t RcvIBLostLinkErrClear[1];
 454         pseudo_bit_t Reserved1[9];
 455         pseudo_bit_t SendSpecialTriggerErrClear[1];
 456         pseudo_bit_t SDmaDisabledErrClear[1];
 457         pseudo_bit_t SendMinPktLenErrClear[1];
 458         pseudo_bit_t SendMaxPktLenErrClear[1];
 459         pseudo_bit_t SendUnderRunErrClear[1];
 460         pseudo_bit_t SendPktLenErrClear[1];
 461         pseudo_bit_t SendDroppedSmpPktErrClear[1];
 462         pseudo_bit_t SendDroppedDataPktErrClear[1];
 463         pseudo_bit_t SendPioArmLaunchErrClear[1];
 464         pseudo_bit_t SendUnexpectedPktNumErrClear[1];
 465         pseudo_bit_t SendUnsupportedVLErrClear[1];
 466         pseudo_bit_t SendBufMisuseErrClear[1];
 467         pseudo_bit_t SDmaGenMismatchErrClear[1];
 468         pseudo_bit_t SDmaOutOfBoundErrClear[1];
 469         pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
 470         pseudo_bit_t SDmaBaseErrClear[1];
 471         pseudo_bit_t SDma1stDescErrClear[1];
 472         pseudo_bit_t SDmaRpyTagErrClear[1];
 473         pseudo_bit_t SDmaDwEnErrClear[1];
 474         pseudo_bit_t SDmaMissingDwErrClear[1];
 475         pseudo_bit_t SDmaUnexpDataErrClear[1];
 476         pseudo_bit_t IBStatusChangedClear[1];
 477         pseudo_bit_t InvalidAddrErrClear[1];
 478         pseudo_bit_t ResetNegatedClear[1];
 479         pseudo_bit_t HardwareErrClear[1];
 480         pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
 481         pseudo_bit_t InvalidEEPCmdErrClear[1];
 482         pseudo_bit_t Reserved[10];
 483 };
 484 struct QIB_7220_ErrClear {
 485         PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrClear_pb );
 486 };
 487
 488 #define QIB_7220_HwErrMask_offset 0x00000098UL
 489 struct QIB_7220_HwErrMask_pb {
 490         pseudo_bit_t PCIeMemParityErrMask[8];
 491         pseudo_bit_t Reserved3[20];
 492         pseudo_bit_t SDmaMemReadErrMask[1];
 493         pseudo_bit_t PoisonedTLPMask[1];
 494         pseudo_bit_t PcieCplTimeoutMask[1];
 495         pseudo_bit_t PCIeBusParityErrMask[3];
 496         pseudo_bit_t Reserved2[2];
 497         pseudo_bit_t PCIEOct0_uC_MemoryParityErrMask[1];
 498         pseudo_bit_t PCIEOct1_uC_MemoryParityErrMask[1];
 499         pseudo_bit_t IB_uC_MemoryParityErrMask[1];
 500         pseudo_bit_t DDSRXEQMemoryParityErrMask[1];
 501         pseudo_bit_t TXEMemParityErrMask[4];
 502         pseudo_bit_t RXEMemParityErrMask[7];
 503         pseudo_bit_t Reserved1[3];
 504         pseudo_bit_t PowerOnBISTFailedMask[1];
 505         pseudo_bit_t Reserved[1];
 506         pseudo_bit_t PCIESerdesQ0PClkNotDetectMask[1];
 507         pseudo_bit_t PCIESerdesQ1PClkNotDetectMask[1];
 508         pseudo_bit_t PCIESerdesQ2PClkNotDetectMask[1];
 509         pseudo_bit_t PCIESerdesQ3PClkNotDetectMask[1];
 510         pseudo_bit_t IBSerdesPClkNotDetectMask[1];
 511         pseudo_bit_t Clk_uC_PLLNotLockedMask[1];
 512         pseudo_bit_t IBCBusToSPCParityErrMask[1];
 513         pseudo_bit_t IBCBusFromSPCParityErrMask[1];
 514 };
 515 struct QIB_7220_HwErrMask {
 516         PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrMask_pb );
 517 };
 518
 519 #define QIB_7220_HwErrStatus_offset 0x000000a0UL
 520 struct QIB_7220_HwErrStatus_pb {
 521         pseudo_bit_t PCIeMemParity[8];
 522         pseudo_bit_t Reserved3[20];
 523         pseudo_bit_t SDmaMemReadErr[1];
 524         pseudo_bit_t PoisenedTLP[1];
 525         pseudo_bit_t PcieCplTimeout[1];
 526         pseudo_bit_t PCIeBusParity[3];
 527         pseudo_bit_t Reserved2[2];
 528         pseudo_bit_t PCIE_uC_Oct0MemoryParityErr[1];
 529         pseudo_bit_t PCIE_uC_Oct1MemoryParityErr[1];
 530         pseudo_bit_t IB_uC_MemoryParityErr[1];
 531         pseudo_bit_t DDSRXEQMemoryParityErr[1];
 532         pseudo_bit_t TXEMemParity[4];
 533         pseudo_bit_t RXEMemParity[7];
 534         pseudo_bit_t Reserved1[3];
 535         pseudo_bit_t PowerOnBISTFailed[1];
 536         pseudo_bit_t Reserved[1];
 537         pseudo_bit_t PCIESerdesQ0PClkNotDetect[1];
 538         pseudo_bit_t PCIESerdesQ1PClkNotDetect[1];
 539         pseudo_bit_t PCIESerdesQ2PClkNotDetect[1];
 540         pseudo_bit_t PCIESerdesQ3PClkNotDetect[1];
 541         pseudo_bit_t IBSerdesPClkNotDetect[1];
 542         pseudo_bit_t Clk_uC_PLLNotLocked[1];
 543         pseudo_bit_t IBCBusToSPCParityErr[1];
 544         pseudo_bit_t IBCBusFromSPCParityErr[1];
 545 };
 546 struct QIB_7220_HwErrStatus {
 547         PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrStatus_pb );
 548 };
 549
 550 #define QIB_7220_HwErrClear_offset 0x000000a8UL
 551 struct QIB_7220_HwErrClear_pb {
 552         pseudo_bit_t PCIeMemParityClr[8];
 553         pseudo_bit_t Reserved3[20];
 554         pseudo_bit_t SDmaMemReadErrClear[1];
 555         pseudo_bit_t PoisonedTLPClear[1];
 556         pseudo_bit_t PcieCplTimeoutClear[1];
 557         pseudo_bit_t PCIeBusParityClr[3];
 558         pseudo_bit_t Reserved2[2];
 559         pseudo_bit_t PCIE_uC_Oct0MemoryParityErrClear[1];
 560         pseudo_bit_t PCIE_uC_Oct1MemoryParityErrClear[1];
 561         pseudo_bit_t IB_uC_MemoryParityErrClear[1];
 562         pseudo_bit_t DDSRXEQMemoryParityErrClear[1];
 563         pseudo_bit_t TXEMemParityClear[4];
 564         pseudo_bit_t RXEMemParityClear[7];
 565         pseudo_bit_t Reserved1[3];
 566         pseudo_bit_t PowerOnBISTFailedClear[1];
 567         pseudo_bit_t Reserved[1];
 568         pseudo_bit_t PCIESerdesQ0PClkNotDetectClear[1];
 569         pseudo_bit_t PCIESerdesQ1PClkNotDetectClear[1];
 570         pseudo_bit_t PCIESerdesQ2PClkNotDetectClear[1];
 571         pseudo_bit_t PCIESerdesQ3PClkNotDetectClear[1];
 572         pseudo_bit_t IBSerdesPClkNotDetectClear[1];
 573         pseudo_bit_t Clk_uC_PLLNotLockedClear[1];
 574         pseudo_bit_t IBCBusToSPCparityErrClear[1];
 575         pseudo_bit_t IBCBusFromSPCParityErrClear[1];
 576 };
 577 struct QIB_7220_HwErrClear {
 578         PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrClear_pb );
 579 };
 580
 581 #define QIB_7220_HwDiagCtrl_offset 0x000000b0UL
 582 struct QIB_7220_HwDiagCtrl_pb {
 583         pseudo_bit_t forcePCIeMemParity[8];
 584         pseudo_bit_t Reserved2[23];
 585         pseudo_bit_t forcePCIeBusParity[4];
 586         pseudo_bit_t Reserved1[1];
 587         pseudo_bit_t ForcePCIE_uC_Oct0MemoryParityErr[1];
 588         pseudo_bit_t ForcePCIE_uC_Oct1MemoryParityErr[1];
 589         pseudo_bit_t ForceIB_uC_MemoryParityErr[1];
 590         pseudo_bit_t ForceDDSRXEQMemoryParityErr[1];
 591         pseudo_bit_t ForceTxMemparityErr[4];
 592         pseudo_bit_t ForceRxMemParityErr[7];
 593         pseudo_bit_t Reserved[9];
 594         pseudo_bit_t CounterDisable[1];
 595         pseudo_bit_t CounterWrEnable[1];
 596         pseudo_bit_t ForceIBCBusToSPCParityErr[1];
 597         pseudo_bit_t ForceIBCBusFromSPCParityErr[1];
 598 };
 599 struct QIB_7220_HwDiagCtrl {
 600         PSEUDO_BIT_STRUCT ( struct QIB_7220_HwDiagCtrl_pb );
 601 };
 602
 603 #define QIB_7220_REG_0000B8_offset 0x000000b8UL
 604
 605 #define QIB_7220_IBCStatus_offset 0x000000c0UL
 606 struct QIB_7220_IBCStatus_pb {
 607         pseudo_bit_t LinkTrainingState[5];
 608         pseudo_bit_t LinkState[3];
 609         pseudo_bit_t LinkSpeedActive[1];
 610         pseudo_bit_t LinkWidthActive[1];
 611         pseudo_bit_t DDS_RXEQ_FAIL[1];
 612         pseudo_bit_t IB_SERDES_TRIM_DONE[1];
 613         pseudo_bit_t IBRxLaneReversed[1];
 614         pseudo_bit_t IBTxLaneReversed[1];
 615         pseudo_bit_t Reserved[16];
 616         pseudo_bit_t TxReady[1];
 617         pseudo_bit_t TxCreditOk[1];
 618         pseudo_bit_t _unused_0[32];
 619 };
 620 struct QIB_7220_IBCStatus {
 621         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCStatus_pb );
 622 };
 623
 624 #define QIB_7220_IBCCtrl_offset 0x000000c8UL
 625 struct QIB_7220_IBCCtrl_pb {
 626         pseudo_bit_t FlowCtrlPeriod[8];
 627         pseudo_bit_t FlowCtrlWaterMark[8];
 628         pseudo_bit_t LinkInitCmd[3];
 629         pseudo_bit_t LinkCmd[2];
 630         pseudo_bit_t MaxPktLen[11];
 631         pseudo_bit_t PhyerrThreshold[4];
 632         pseudo_bit_t OverrunThreshold[4];
 633         pseudo_bit_t CreditScale[3];
 634         pseudo_bit_t Reserved[19];
 635         pseudo_bit_t LinkDownDefaultState[1];
 636         pseudo_bit_t Loopback[1];
 637 };
 638 struct QIB_7220_IBCCtrl {
 639         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCCtrl_pb );
 640 };
 641
 642 #define QIB_7220_EXTStatus_offset 0x000000d0UL
 643 struct QIB_7220_EXTStatus_pb {
 644         pseudo_bit_t Reserved2[14];
 645         pseudo_bit_t MemBISTEndTest[1];
 646         pseudo_bit_t MemBISTDisabled[1];
 647         pseudo_bit_t Reserved1[16];
 648         pseudo_bit_t Reserved[16];
 649         pseudo_bit_t GPIOIn[16];
 650 };
 651 struct QIB_7220_EXTStatus {
 652         PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTStatus_pb );
 653 };
 654
 655 #define QIB_7220_EXTCtrl_offset 0x000000d8UL
 656 struct QIB_7220_EXTCtrl_pb {
 657         pseudo_bit_t LEDGblErrRedOff[1];
 658         pseudo_bit_t LEDGblOkGreenOn[1];
 659         pseudo_bit_t LEDPriPortYellowOn[1];
 660         pseudo_bit_t LEDPriPortGreenOn[1];
 661         pseudo_bit_t Reserved[28];
 662         pseudo_bit_t GPIOInvert[16];
 663         pseudo_bit_t GPIOOe[16];
 664 };
 665 struct QIB_7220_EXTCtrl {
 666         PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTCtrl_pb );
 667 };
 668
 669 #define QIB_7220_GPIOOut_offset 0x000000e0UL
 670
 671 #define QIB_7220_GPIOMask_offset 0x000000e8UL
 672
 673 #define QIB_7220_GPIOStatus_offset 0x000000f0UL
 674
 675 #define QIB_7220_GPIOClear_offset 0x000000f8UL
 676
 677 #define QIB_7220_RcvCtrl_offset 0x00000100UL
 678 struct QIB_7220_RcvCtrl_pb {
 679         pseudo_bit_t PortEnable[17];
 680         pseudo_bit_t IntrAvail[17];
 681         pseudo_bit_t RcvPartitionKeyDisable[1];
 682         pseudo_bit_t TailUpd[1];
 683         pseudo_bit_t PortCfg[2];
 684         pseudo_bit_t RcvQPMapEnable[1];
 685         pseudo_bit_t Reserved[25];
 686 };
 687 struct QIB_7220_RcvCtrl {
 688         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvCtrl_pb );
 689 };
 690
 691 #define QIB_7220_RcvBTHQP_offset 0x00000108UL
 692 struct QIB_7220_RcvBTHQP_pb {
 693         pseudo_bit_t RcvBTHQP[24];
 694         pseudo_bit_t Reserved[8];
 695         pseudo_bit_t _unused_0[32];
 696 };
 697 struct QIB_7220_RcvBTHQP {
 698         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvBTHQP_pb );
 699 };
 700
 701 #define QIB_7220_RcvHdrSize_offset 0x00000110UL
 702
 703 #define QIB_7220_RcvHdrCnt_offset 0x00000118UL
 704
 705 #define QIB_7220_RcvHdrEntSize_offset 0x00000120UL
 706
 707 #define QIB_7220_RcvTIDBase_offset 0x00000128UL
 708
 709 #define QIB_7220_RcvTIDCnt_offset 0x00000130UL
 710
 711 #define QIB_7220_RcvEgrBase_offset 0x00000138UL
 712
 713 #define QIB_7220_RcvEgrCnt_offset 0x00000140UL
 714
 715 #define QIB_7220_RcvBufBase_offset 0x00000148UL
 716
 717 #define QIB_7220_RcvBufSize_offset 0x00000150UL
 718
 719 #define QIB_7220_RxIntMemBase_offset 0x00000158UL
 720
 721 #define QIB_7220_RxIntMemSize_offset 0x00000160UL
 722
 723 #define QIB_7220_RcvPartitionKey_offset 0x00000168UL
 724
 725 #define QIB_7220_RcvQPMulticastPort_offset 0x00000170UL
 726 struct QIB_7220_RcvQPMulticastPort_pb {
 727         pseudo_bit_t RcvQpMcPort[5];
 728         pseudo_bit_t Reserved[59];
 729 };
 730 struct QIB_7220_RcvQPMulticastPort {
 731         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvQPMulticastPort_pb );
 732 };
 733
 734 #define QIB_7220_RcvPktLEDCnt_offset 0x00000178UL
 735 struct QIB_7220_RcvPktLEDCnt_pb {
 736         pseudo_bit_t OFFperiod[32];
 737         pseudo_bit_t ONperiod[32];
 738 };
 739 struct QIB_7220_RcvPktLEDCnt {
 740         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvPktLEDCnt_pb );
 741 };
 742
 743 #define QIB_7220_IBCDDRCtrl_offset 0x00000180UL
 744 struct QIB_7220_IBCDDRCtrl_pb {
 745         pseudo_bit_t IB_ENHANCED_MODE[1];
 746         pseudo_bit_t SD_SPEED[1];
 747         pseudo_bit_t SD_SPEED_SDR[1];
 748         pseudo_bit_t SD_SPEED_DDR[1];
 749         pseudo_bit_t SD_SPEED_QDR[1];
 750         pseudo_bit_t IB_NUM_CHANNELS[2];
 751         pseudo_bit_t IB_POLARITY_REV_SUPP[1];
 752         pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
 753         pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
 754         pseudo_bit_t SD_ADD_ENB[1];
 755         pseudo_bit_t SD_DDSV[1];
 756         pseudo_bit_t SD_DDS[4];
 757         pseudo_bit_t HRTBT_ENB[1];
 758         pseudo_bit_t HRTBT_AUTO[1];
 759         pseudo_bit_t HRTBT_PORT[8];
 760         pseudo_bit_t HRTBT_REQ[1];
 761         pseudo_bit_t Reserved[5];
 762         pseudo_bit_t IB_DLID[16];
 763         pseudo_bit_t IB_DLID_MASK[16];
 764 };
 765 struct QIB_7220_IBCDDRCtrl {
 766         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl_pb );
 767 };
 768
 769 #define QIB_7220_HRTBT_GUID_offset 0x00000188UL
 770
 771 #define QIB_7220_IB_SDTEST_IF_TX_offset 0x00000190UL
 772 struct QIB_7220_IB_SDTEST_IF_TX_pb {
 773         pseudo_bit_t TS_T_TX_VALID[1];
 774         pseudo_bit_t TS_3_TX_VALID[1];
 775         pseudo_bit_t Reserved1[9];
 776         pseudo_bit_t TS_TX_OPCODE[2];
 777         pseudo_bit_t TS_TX_SPEED[3];
 778         pseudo_bit_t Reserved[16];
 779         pseudo_bit_t TS_TX_TX_CFG[16];
 780         pseudo_bit_t TS_TX_RX_CFG[16];
 781 };
 782 struct QIB_7220_IB_SDTEST_IF_TX {
 783         PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_TX_pb );
 784 };
 785
 786 #define QIB_7220_IB_SDTEST_IF_RX_offset 0x00000198UL
 787 struct QIB_7220_IB_SDTEST_IF_RX_pb {
 788         pseudo_bit_t TS_T_RX_VALID[1];
 789         pseudo_bit_t TS_3_RX_VALID[1];
 790         pseudo_bit_t Reserved[14];
 791         pseudo_bit_t TS_RX_A[8];
 792         pseudo_bit_t TS_RX_B[8];
 793         pseudo_bit_t TS_RX_TX_CFG[16];
 794         pseudo_bit_t TS_RX_RX_CFG[16];
 795 };
 796 struct QIB_7220_IB_SDTEST_IF_RX {
 797         PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_RX_pb );
 798 };
 799
 800 #define QIB_7220_IBCDDRCtrl2_offset 0x000001a0UL
 801 struct QIB_7220_IBCDDRCtrl2_pb {
 802         pseudo_bit_t IB_FRONT_PORCH[5];
 803         pseudo_bit_t IB_BACK_PORCH[5];
 804         pseudo_bit_t _unused_0[54];
 805 };
 806 struct QIB_7220_IBCDDRCtrl2 {
 807         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl2_pb );
 808 };
 809
 810 #define QIB_7220_IBCDDRStatus_offset 0x000001a8UL
 811 struct QIB_7220_IBCDDRStatus_pb {
 812         pseudo_bit_t LinkRoundTripLatency[26];
 813         pseudo_bit_t ReqDDSLocalFromRmt[4];
 814         pseudo_bit_t RxEqLocalDevice[2];
 815         pseudo_bit_t heartbeat_crosstalk[4];
 816         pseudo_bit_t heartbeat_timed_out[1];
 817         pseudo_bit_t _unused_0[27];
 818 };
 819 struct QIB_7220_IBCDDRStatus {
 820         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRStatus_pb );
 821 };
 822
 823 #define QIB_7220_JIntReload_offset 0x000001b0UL
 824 struct QIB_7220_JIntReload_pb {
 825         pseudo_bit_t J_reload[16];
 826         pseudo_bit_t J_limit_reload[16];
 827         pseudo_bit_t _unused_0[32];
 828 };
 829 struct QIB_7220_JIntReload {
 830         PSEUDO_BIT_STRUCT ( struct QIB_7220_JIntReload_pb );
 831 };
 832
 833 #define QIB_7220_IBNCModeCtrl_offset 0x000001b8UL
 834 struct QIB_7220_IBNCModeCtrl_pb {
 835         pseudo_bit_t TSMEnable_send_TS1[1];
 836         pseudo_bit_t TSMEnable_send_TS2[1];
 837         pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1];
 838         pseudo_bit_t Reserved1[5];
 839         pseudo_bit_t TSMCode_TS1[9];
 840         pseudo_bit_t TSMCode_TS2[9];
 841         pseudo_bit_t Reserved[38];
 842 };
 843 struct QIB_7220_IBNCModeCtrl {
 844         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBNCModeCtrl_pb );
 845 };
 846
 847 #define QIB_7220_SendCtrl_offset 0x000001c0UL
 848 struct QIB_7220_SendCtrl_pb {
 849         pseudo_bit_t Abort[1];
 850         pseudo_bit_t SendIntBufAvail[1];
 851         pseudo_bit_t SendBufAvailUpd[1];
 852         pseudo_bit_t SPioEnable[1];
 853         pseudo_bit_t SSpecialTriggerEn[1];
 854         pseudo_bit_t Reserved2[4];
 855         pseudo_bit_t SDmaIntEnable[1];
 856         pseudo_bit_t SDmaSingleDescriptor[1];
 857         pseudo_bit_t SDmaEnable[1];
 858         pseudo_bit_t SDmaHalt[1];
 859         pseudo_bit_t Reserved1[3];
 860         pseudo_bit_t DisarmPIOBuf[8];
 861         pseudo_bit_t AvailUpdThld[5];
 862         pseudo_bit_t Reserved[2];
 863         pseudo_bit_t Disarm[1];
 864         pseudo_bit_t _unused_0[32];
 865 };
 866 struct QIB_7220_SendCtrl {
 867         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendCtrl_pb );
 868 };
 869
 870 #define QIB_7220_SendBufBase_offset 0x000001c8UL
 871 struct QIB_7220_SendBufBase_pb {
 872         pseudo_bit_t BaseAddr_SmallPIO[21];
 873         pseudo_bit_t Reserved1[11];
 874         pseudo_bit_t BaseAddr_LargePIO[21];
 875         pseudo_bit_t Reserved[11];
 876 };
 877 struct QIB_7220_SendBufBase {
 878         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufBase_pb );
 879 };
 880
 881 #define QIB_7220_SendBufSize_offset 0x000001d0UL
 882 struct QIB_7220_SendBufSize_pb {
 883         pseudo_bit_t Size_SmallPIO[12];
 884         pseudo_bit_t Reserved1[20];
 885         pseudo_bit_t Size_LargePIO[13];
 886         pseudo_bit_t Reserved[19];
 887 };
 888 struct QIB_7220_SendBufSize {
 889         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufSize_pb );
 890 };
 891
 892 #define QIB_7220_SendBufCnt_offset 0x000001d8UL
 893 struct QIB_7220_SendBufCnt_pb {
 894         pseudo_bit_t Num_SmallBuffers[9];
 895         pseudo_bit_t Reserved1[23];
 896         pseudo_bit_t Num_LargeBuffers[4];
 897         pseudo_bit_t Reserved[28];
 898 };
 899 struct QIB_7220_SendBufCnt {
 900         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufCnt_pb );
 901 };
 902
 903 #define QIB_7220_SendBufAvailAddr_offset 0x000001e0UL
 904 struct QIB_7220_SendBufAvailAddr_pb {
 905         pseudo_bit_t Reserved[6];
 906         pseudo_bit_t SendBufAvailAddr[34];
 907         pseudo_bit_t _unused_0[24];
 908 };
 909 struct QIB_7220_SendBufAvailAddr {
 910         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvailAddr_pb );
 911 };
 912
 913 #define QIB_7220_TxIntMemBase_offset 0x000001e8UL
 914
 915 #define QIB_7220_TxIntMemSize_offset 0x000001f0UL
 916
 917 #define QIB_7220_SendDmaBase_offset 0x000001f8UL
 918 struct QIB_7220_SendDmaBase_pb {
 919         pseudo_bit_t SendDmaBase[48];
 920         pseudo_bit_t Reserved[16];
 921 };
 922 struct QIB_7220_SendDmaBase {
 923         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBase_pb );
 924 };
 925
 926 #define QIB_7220_SendDmaLenGen_offset 0x00000200UL
 927 struct QIB_7220_SendDmaLenGen_pb {
 928         pseudo_bit_t Length[16];
 929         pseudo_bit_t Generation[3];
 930         pseudo_bit_t Reserved[45];
 931 };
 932 struct QIB_7220_SendDmaLenGen {
 933         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaLenGen_pb );
 934 };
 935
 936 #define QIB_7220_SendDmaTail_offset 0x00000208UL
 937 struct QIB_7220_SendDmaTail_pb {
 938         pseudo_bit_t SendDmaTail[16];
 939         pseudo_bit_t Reserved[48];
 940 };
 941 struct QIB_7220_SendDmaTail {
 942         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaTail_pb );
 943 };
 944
 945 #define QIB_7220_SendDmaHead_offset 0x00000210UL
 946 struct QIB_7220_SendDmaHead_pb {
 947         pseudo_bit_t SendDmaHead[16];
 948         pseudo_bit_t Reserved1[16];
 949         pseudo_bit_t InternalSendDmaHead[16];
 950         pseudo_bit_t Reserved[16];
 951 };
 952 struct QIB_7220_SendDmaHead {
 953         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHead_pb );
 954 };
 955
 956 #define QIB_7220_SendDmaHeadAddr_offset 0x00000218UL
 957 struct QIB_7220_SendDmaHeadAddr_pb {
 958         pseudo_bit_t SendDmaHeadAddr[48];
 959         pseudo_bit_t Reserved[16];
 960 };
 961 struct QIB_7220_SendDmaHeadAddr {
 962         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHeadAddr_pb );
 963 };
 964
 965 #define QIB_7220_SendDmaBufMask0_offset 0x00000220UL
 966 struct QIB_7220_SendDmaBufMask0_pb {
 967         pseudo_bit_t BufMask_63_0[0];
 968         pseudo_bit_t _unused_0[64];
 969 };
 970 struct QIB_7220_SendDmaBufMask0 {
 971         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufMask0_pb );
 972 };
 973
 974 #define QIB_7220_SendDmaStatus_offset 0x00000238UL
 975 struct QIB_7220_SendDmaStatus_pb {
 976         pseudo_bit_t SplFifoDescIndex[16];
 977         pseudo_bit_t SplFifoBufNum[8];
 978         pseudo_bit_t SplFifoFull[1];
 979         pseudo_bit_t SplFifoEmpty[1];
 980         pseudo_bit_t SplFifoDisarmed[1];
 981         pseudo_bit_t SplFifoReadyToGo[1];
 982         pseudo_bit_t ScbFetchDescFlag[1];
 983         pseudo_bit_t ScbEntryValid[1];
 984         pseudo_bit_t ScbEmpty[1];
 985         pseudo_bit_t ScbFull[1];
 986         pseudo_bit_t RpyTag_7_0[8];
 987         pseudo_bit_t RpyLowAddr_6_0[7];
 988         pseudo_bit_t ScbDescIndex_13_0[14];
 989         pseudo_bit_t InternalSDmaEnable[1];
 990         pseudo_bit_t AbortInProg[1];
 991         pseudo_bit_t ScoreBoardDrainInProg[1];
 992 };
 993 struct QIB_7220_SendDmaStatus {
 994         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaStatus_pb );
 995 };
 996
 997 #define QIB_7220_SendBufErr0_offset 0x00000240UL
 998 struct QIB_7220_SendBufErr0_pb {
 999         pseudo_bit_t SendBufErr_63_0[0];
1000         pseudo_bit_t _unused_0[64];
1001 };
1002 struct QIB_7220_SendBufErr0 {
1003         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufErr0_pb );
1004 };
1005
1006 #define QIB_7220_REG_000258_offset 0x00000258UL
1007
1008 #define QIB_7220_AvailUpdCount_offset 0x00000268UL
1009 struct QIB_7220_AvailUpdCount_pb {
1010         pseudo_bit_t AvailUpdCount[5];
1011         pseudo_bit_t _unused_0[59];
1012 };
1013 struct QIB_7220_AvailUpdCount {
1014         PSEUDO_BIT_STRUCT ( struct QIB_7220_AvailUpdCount_pb );
1015 };
1016
1017 #define QIB_7220_RcvHdrAddr0_offset 0x00000270UL
1018 struct QIB_7220_RcvHdrAddr0_pb {
1019         pseudo_bit_t Reserved[2];
1020         pseudo_bit_t RcvHdrAddr0[38];
1021         pseudo_bit_t _unused_0[24];
1022 };
1023 struct QIB_7220_RcvHdrAddr0 {
1024         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrAddr0_pb );
1025 };
1026
1027 #define QIB_7220_REG_0002F8_offset 0x000002f8UL
1028
1029 #define QIB_7220_RcvHdrTailAddr0_offset 0x00000300UL
1030 struct QIB_7220_RcvHdrTailAddr0_pb {
1031         pseudo_bit_t Reserved[2];
1032         pseudo_bit_t RcvHdrTailAddr0[38];
1033         pseudo_bit_t _unused_0[24];
1034 };
1035 struct QIB_7220_RcvHdrTailAddr0 {
1036         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrTailAddr0_pb );
1037 };
1038
1039 #define QIB_7220_REG_000388_offset 0x00000388UL
1040
1041 #define QIB_7220_ibsd_epb_access_ctrl_offset 0x000003c0UL
1042 struct QIB_7220_ibsd_epb_access_ctrl_pb {
1043         pseudo_bit_t sw_ib_epb_req[1];
1044         pseudo_bit_t Reserved[7];
1045         pseudo_bit_t sw_ib_epb_req_granted[1];
1046         pseudo_bit_t _unused_0[55];
1047 };
1048 struct QIB_7220_ibsd_epb_access_ctrl {
1049         PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_access_ctrl_pb );
1050 };
1051
1052 #define QIB_7220_ibsd_epb_transaction_reg_offset 0x000003c8UL
1053 struct QIB_7220_ibsd_epb_transaction_reg_pb {
1054         pseudo_bit_t ib_epb_data[8];
1055         pseudo_bit_t ib_epb_address[15];
1056         pseudo_bit_t Reserved2[1];
1057         pseudo_bit_t ib_epb_read_write[1];
1058         pseudo_bit_t ib_epb_cs[2];
1059         pseudo_bit_t Reserved1[1];
1060         pseudo_bit_t mem_data_parity[1];
1061         pseudo_bit_t Reserved[1];
1062         pseudo_bit_t ib_epb_req_error[1];
1063         pseudo_bit_t ib_epb_rdy[1];
1064         pseudo_bit_t _unused_0[32];
1065 };
1066 struct QIB_7220_ibsd_epb_transaction_reg {
1067         PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_transaction_reg_pb );
1068 };
1069
1070 #define QIB_7220_REG_0003D0_offset 0x000003d0UL
1071
1072 #define QIB_7220_XGXSCfg_offset 0x000003d8UL
1073 struct QIB_7220_XGXSCfg_pb {
1074         pseudo_bit_t tx_rx_reset[1];
1075         pseudo_bit_t Reserved2[1];
1076         pseudo_bit_t xcv_reset[1];
1077         pseudo_bit_t Reserved1[6];
1078         pseudo_bit_t link_sync_mask[10];
1079         pseudo_bit_t Reserved[44];
1080         pseudo_bit_t sel_link_down_for_fctrl_lane_sync_reset[1];
1081 };
1082 struct QIB_7220_XGXSCfg {
1083         PSEUDO_BIT_STRUCT ( struct QIB_7220_XGXSCfg_pb );
1084 };
1085
1086 #define QIB_7220_IBSerDesCtrl_offset 0x000003e0UL
1087 struct QIB_7220_IBSerDesCtrl_pb {
1088         pseudo_bit_t ResetIB_uC_Core[1];
1089         pseudo_bit_t Reserved2[7];
1090         pseudo_bit_t NumSerDesRegsToWrForDDS[5];
1091         pseudo_bit_t NumSerDesRegsToWrForRXEQ[5];
1092         pseudo_bit_t Reserved1[14];
1093         pseudo_bit_t TXINV[1];
1094         pseudo_bit_t RXINV[1];
1095         pseudo_bit_t RXIDLE[1];
1096         pseudo_bit_t TWC[1];
1097         pseudo_bit_t TXOBPD[1];
1098         pseudo_bit_t PLLM[3];
1099         pseudo_bit_t PLLN[2];
1100         pseudo_bit_t CKSEL_uC[2];
1101         pseudo_bit_t INT_uC[1];
1102         pseudo_bit_t Reserved[19];
1103 };
1104 struct QIB_7220_IBSerDesCtrl {
1105         PSEUDO_BIT_STRUCT ( struct QIB_7220_IBSerDesCtrl_pb );
1106 };
1107
1108 #define QIB_7220_EEPCtlStat_offset 0x000003e8UL
1109 struct QIB_7220_EEPCtlStat_pb {
1110         pseudo_bit_t EPAccEn[2];
1111         pseudo_bit_t EPReset[1];
1112         pseudo_bit_t ByteProg[1];
1113         pseudo_bit_t PageMode[1];
1114         pseudo_bit_t LstDatWr[1];
1115         pseudo_bit_t CmdWrErr[1];
1116         pseudo_bit_t Reserved[24];
1117         pseudo_bit_t CtlrStat[1];
1118         pseudo_bit_t _unused_0[32];
1119 };
1120 struct QIB_7220_EEPCtlStat {
1121         PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPCtlStat_pb );
1122 };
1123
1124 #define QIB_7220_EEPAddrCmd_offset 0x000003f0UL
1125 struct QIB_7220_EEPAddrCmd_pb {
1126         pseudo_bit_t EPAddr[24];
1127         pseudo_bit_t EPCmd[8];
1128         pseudo_bit_t _unused_0[32];
1129 };
1130 struct QIB_7220_EEPAddrCmd {
1131         PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPAddrCmd_pb );
1132 };
1133
1134 #define QIB_7220_EEPData_offset 0x000003f8UL
1135
1136 #define QIB_7220_pciesd_epb_access_ctrl_offset 0x00000400UL
1137 struct QIB_7220_pciesd_epb_access_ctrl_pb {
1138         pseudo_bit_t sw_pcie_epb_req[1];
1139         pseudo_bit_t sw_pcieepb_star_en[2];
1140         pseudo_bit_t Reserved[5];
1141         pseudo_bit_t sw_pcie_epb_req_granted[1];
1142         pseudo_bit_t _unused_0[55];
1143 };
1144 struct QIB_7220_pciesd_epb_access_ctrl {
1145         PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_access_ctrl_pb );
1146 };
1147
1148 #define QIB_7220_pciesd_epb_transaction_reg_offset 0x00000408UL
1149 struct QIB_7220_pciesd_epb_transaction_reg_pb {
1150         pseudo_bit_t pcie_epb_data[8];
1151         pseudo_bit_t pcie_epb_address[15];
1152         pseudo_bit_t Reserved1[1];
1153         pseudo_bit_t pcie_epb_read_write[1];
1154         pseudo_bit_t pcie_epb_cs[3];
1155         pseudo_bit_t mem_data_parity[1];
1156         pseudo_bit_t Reserved[1];
1157         pseudo_bit_t pcie_epb_req_error[1];
1158         pseudo_bit_t pcie_epb_rdy[1];
1159         pseudo_bit_t _unused_0[32];
1160 };
1161 struct QIB_7220_pciesd_epb_transaction_reg {
1162         PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_transaction_reg_pb );
1163 };
1164
1165 #define QIB_7220_efuse_control_reg_offset 0x00000410UL
1166 struct QIB_7220_efuse_control_reg_pb {
1167         pseudo_bit_t start_op[1];
1168         pseudo_bit_t operation[1];
1169         pseudo_bit_t read_valid[1];
1170         pseudo_bit_t req_error[1];
1171         pseudo_bit_t Reserved[27];
1172         pseudo_bit_t rdy[1];
1173         pseudo_bit_t _unused_0[32];
1174 };
1175 struct QIB_7220_efuse_control_reg {
1176         PSEUDO_BIT_STRUCT ( struct QIB_7220_efuse_control_reg_pb );
1177 };
1178
1179 #define QIB_7220_efuse_rddata0_reg_offset 0x00000418UL
1180
1181 #define QIB_7220_procmon_register_offset 0x00000438UL
1182 struct QIB_7220_procmon_register_pb {
1183         pseudo_bit_t interval_time[12];
1184         pseudo_bit_t Reserved1[2];
1185         pseudo_bit_t clear_counter[1];
1186         pseudo_bit_t start_counter[1];
1187         pseudo_bit_t procmon_count[9];
1188         pseudo_bit_t Reserved[6];
1189         pseudo_bit_t procmon_count_valid[1];
1190         pseudo_bit_t _unused_0[32];
1191 };
1192 struct QIB_7220_procmon_register {
1193         PSEUDO_BIT_STRUCT ( struct QIB_7220_procmon_register_pb );
1194 };
1195
1196 #define QIB_7220_PcieRbufTestReg0_offset 0x00000440UL
1197
1198 #define QIB_7220_PcieRBufTestReg1_offset 0x00000448UL
1199
1200 #define QIB_7220_SPC_JTAG_ACCESS_REG_offset 0x00000460UL
1201 struct QIB_7220_SPC_JTAG_ACCESS_REG_pb {
1202         pseudo_bit_t rdy[1];
1203         pseudo_bit_t tdo[1];
1204         pseudo_bit_t tdi[1];
1205         pseudo_bit_t opcode[2];
1206         pseudo_bit_t bist_en[5];
1207         pseudo_bit_t SPC_JTAG_ACCESS_EN[1];
1208         pseudo_bit_t _unused_0[53];
1209 };
1210 struct QIB_7220_SPC_JTAG_ACCESS_REG {
1211         PSEUDO_BIT_STRUCT ( struct QIB_7220_SPC_JTAG_ACCESS_REG_pb );
1212 };
1213
1214 #define QIB_7220_LAControlReg_offset 0x00000468UL
1215 struct QIB_7220_LAControlReg_pb {
1216         pseudo_bit_t Finished[1];
1217         pseudo_bit_t Address[8];
1218         pseudo_bit_t Mode[2];
1219         pseudo_bit_t Delay[20];
1220         pseudo_bit_t Reserved[1];
1221         pseudo_bit_t _unused_0[32];
1222 };
1223 struct QIB_7220_LAControlReg {
1224         PSEUDO_BIT_STRUCT ( struct QIB_7220_LAControlReg_pb );
1225 };
1226
1227 #define QIB_7220_GPIODebugSelReg_offset 0x00000470UL
1228 struct QIB_7220_GPIODebugSelReg_pb {
1229         pseudo_bit_t GPIOSourceSelDebug[16];
1230         pseudo_bit_t SelPulse[16];
1231         pseudo_bit_t _unused_0[32];
1232 };
1233 struct QIB_7220_GPIODebugSelReg {
1234         PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIODebugSelReg_pb );
1235 };
1236
1237 #define QIB_7220_DebugPortValueReg_offset 0x00000478UL
1238
1239 #define QIB_7220_SendDmaBufUsed0_offset 0x00000480UL
1240 struct QIB_7220_SendDmaBufUsed0_pb {
1241         pseudo_bit_t BufUsed_63_0[0];
1242         pseudo_bit_t _unused_0[64];
1243 };
1244 struct QIB_7220_SendDmaBufUsed0 {
1245         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufUsed0_pb );
1246 };
1247
1248 #define QIB_7220_SendDmaReqTagUsed_offset 0x00000498UL
1249 struct QIB_7220_SendDmaReqTagUsed_pb {
1250         pseudo_bit_t ReqTagUsed_7_0[8];
1251         pseudo_bit_t _unused_0[8];
1252         pseudo_bit_t Reserved[48];
1253 };
1254 struct QIB_7220_SendDmaReqTagUsed {
1255         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaReqTagUsed_pb );
1256 };
1257
1258 #define QIB_7220_efuse_pgm_data0_offset 0x000004a0UL
1259
1260 #define QIB_7220_MEM_0004B0_offset 0x000004b0UL
1261
1262 #define QIB_7220_SerDes_DDSRXEQ0_offset 0x00000500UL
1263 struct QIB_7220_SerDes_DDSRXEQ0_pb {
1264         pseudo_bit_t element_num[4];
1265         pseudo_bit_t reg_addr[6];
1266         pseudo_bit_t _unused_0[54];
1267 };
1268 struct QIB_7220_SerDes_DDSRXEQ0 {
1269         PSEUDO_BIT_STRUCT ( struct QIB_7220_SerDes_DDSRXEQ0_pb );
1270 };
1271
1272 #define QIB_7220_MEM_0005F0_offset 0x000005f0UL
1273
1274 #define QIB_7220_LAMemory_offset 0x00000600UL
1275
1276 #define QIB_7220_MEM_0007F0_offset 0x000007f0UL
1277
1278 #define QIB_7220_SendBufAvail0_offset 0x00001000UL
1279 struct QIB_7220_SendBufAvail0_pb {
1280         pseudo_bit_t SendBuf_31_0[0];
1281         pseudo_bit_t _unused_0[64];
1282 };
1283 struct QIB_7220_SendBufAvail0 {
1284         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail0_pb );
1285 };
1286
1287 #define QIB_7220_MEM_001028_offset 0x00001028UL
1288
1289 #define QIB_7220_LBIntCnt_offset 0x00013000UL
1290
1291 #define QIB_7220_LBFlowStallCnt_offset 0x00013008UL
1292
1293 #define QIB_7220_TxSDmaDescCnt_offset 0x00013010UL
1294
1295 #define QIB_7220_TxUnsupVLErrCnt_offset 0x00013018UL
1296
1297 #define QIB_7220_TxDataPktCnt_offset 0x00013020UL
1298
1299 #define QIB_7220_TxFlowPktCnt_offset 0x00013028UL
1300
1301 #define QIB_7220_TxDwordCnt_offset 0x00013030UL
1302
1303 #define QIB_7220_TxLenErrCnt_offset 0x00013038UL
1304
1305 #define QIB_7220_TxMaxMinLenErrCnt_offset 0x00013040UL
1306
1307 #define QIB_7220_TxUnderrunCnt_offset 0x00013048UL
1308
1309 #define QIB_7220_TxFlowStallCnt_offset 0x00013050UL
1310
1311 #define QIB_7220_TxDroppedPktCnt_offset 0x00013058UL
1312
1313 #define QIB_7220_RxDroppedPktCnt_offset 0x00013060UL
1314
1315 #define QIB_7220_RxDataPktCnt_offset 0x00013068UL
1316
1317 #define QIB_7220_RxFlowPktCnt_offset 0x00013070UL
1318
1319 #define QIB_7220_RxDwordCnt_offset 0x00013078UL
1320
1321 #define QIB_7220_RxLenErrCnt_offset 0x00013080UL
1322
1323 #define QIB_7220_RxMaxMinLenErrCnt_offset 0x00013088UL
1324
1325 #define QIB_7220_RxICRCErrCnt_offset 0x00013090UL
1326
1327 #define QIB_7220_RxVCRCErrCnt_offset 0x00013098UL
1328
1329 #define QIB_7220_RxFlowCtrlViolCnt_offset 0x000130a0UL
1330
1331 #define QIB_7220_RxVersionErrCnt_offset 0x000130a8UL
1332
1333 #define QIB_7220_RxLinkMalformCnt_offset 0x000130b0UL
1334
1335 #define QIB_7220_RxEBPCnt_offset 0x000130b8UL
1336
1337 #define QIB_7220_RxLPCRCErrCnt_offset 0x000130c0UL
1338
1339 #define QIB_7220_RxBufOvflCnt_offset 0x000130c8UL
1340
1341 #define QIB_7220_RxTIDFullErrCnt_offset 0x000130d0UL
1342
1343 #define QIB_7220_RxTIDValidErrCnt_offset 0x000130d8UL
1344
1345 #define QIB_7220_RxPKeyMismatchCnt_offset 0x000130e0UL
1346
1347 #define QIB_7220_RxP0HdrEgrOvflCnt_offset 0x000130e8UL
1348
1349 #define QIB_7220_IBStatusChangeCnt_offset 0x00013170UL
1350
1351 #define QIB_7220_IBLinkErrRecoveryCnt_offset 0x00013178UL
1352
1353 #define QIB_7220_IBLinkDownedCnt_offset 0x00013180UL
1354
1355 #define QIB_7220_IBSymbolErrCnt_offset 0x00013188UL
1356
1357 #define QIB_7220_RxVL15DroppedPktCnt_offset 0x00013190UL
1358
1359 #define QIB_7220_RxOtherLocalPhyErrCnt_offset 0x00013198UL
1360
1361 #define QIB_7220_PcieRetryBufDiagQwordCnt_offset 0x000131a0UL
1362
1363 #define QIB_7220_ExcessBufferOvflCnt_offset 0x000131a8UL
1364
1365 #define QIB_7220_LocalLinkIntegrityErrCnt_offset 0x000131b0UL
1366
1367 #define QIB_7220_RxVlErrCnt_offset 0x000131b8UL
1368
1369 #define QIB_7220_RxDlidFltrCnt_offset 0x000131c0UL
1370
1371 #define QIB_7220_CNT_0131C8_offset 0x000131c8UL
1372
1373 #define QIB_7220_PSStat_offset 0x00013200UL
1374
1375 #define QIB_7220_PSStart_offset 0x00013208UL
1376
1377 #define QIB_7220_PSInterval_offset 0x00013210UL
1378
1379 #define QIB_7220_PSRcvDataCount_offset 0x00013218UL
1380
1381 #define QIB_7220_PSRcvPktsCount_offset 0x00013220UL
1382
1383 #define QIB_7220_PSXmitDataCount_offset 0x00013228UL
1384
1385 #define QIB_7220_PSXmitPktsCount_offset 0x00013230UL
1386
1387 #define QIB_7220_PSXmitWaitCount_offset 0x00013238UL
1388
1389 #define QIB_7220_CNT_013240_offset 0x00013240UL
1390
1391 #define QIB_7220_RcvEgrArray_offset 0x00014000UL
1392
1393 #define QIB_7220_MEM_038000_offset 0x00038000UL
1394
1395 #define QIB_7220_RcvTIDArray0_offset 0x00053000UL
1396
1397 #define QIB_7220_PIOLaunchFIFO_offset 0x00064000UL
1398
1399 #define QIB_7220_MEM_064480_offset 0x00064480UL
1400
1401 #define QIB_7220_SendPIOpbcCache_offset 0x00064800UL
1402
1403 #define QIB_7220_MEM_064C80_offset 0x00064c80UL
1404
1405 #define QIB_7220_PreLaunchFIFO_offset 0x00065000UL
1406
1407 #define QIB_7220_MEM_065080_offset 0x00065080UL
1408
1409 #define QIB_7220_ScoreBoard_offset 0x00065400UL
1410
1411 #define QIB_7220_MEM_065440_offset 0x00065440UL
1412
1413 #define QIB_7220_DescriptorFIFO_offset 0x00065800UL
1414
1415 #define QIB_7220_MEM_065880_offset 0x00065880UL
1416
1417 #define QIB_7220_RcvBuf1_offset 0x00072000UL
1418
1419 #define QIB_7220_MEM_074800_offset 0x00074800UL
1420
1421 #define QIB_7220_RcvBuf2_offset 0x00075000UL
1422
1423 #define QIB_7220_MEM_076400_offset 0x00076400UL
1424
1425 #define QIB_7220_RcvFlags_offset 0x00077000UL
1426
1427 #define QIB_7220_MEM_078400_offset 0x00078400UL
1428
1429 #define QIB_7220_RcvLookupBuf1_offset 0x00079000UL
1430
1431 #define QIB_7220_MEM_07A400_offset 0x0007a400UL
1432
1433 #define QIB_7220_RcvDMADatBuf_offset 0x0007b000UL
1434
1435 #define QIB_7220_RcvDMAHdrBuf_offset 0x0007b800UL
1436
1437 #define QIB_7220_MiscRXEIntMem_offset 0x0007c000UL
1438
1439 #define QIB_7220_MEM_07D400_offset 0x0007d400UL
1440
1441 #define QIB_7220_PCIERcvBuf_offset 0x00080000UL
1442
1443 #define QIB_7220_PCIERetryBuf_offset 0x00084000UL
1444
1445 #define QIB_7220_PCIERcvBufRdToWrAddr_offset 0x00088000UL
1446
1447 #define QIB_7220_PCIECplBuf_offset 0x00090000UL
1448
1449 #define QIB_7220_IBSerDesMappTable_offset 0x00094000UL
1450
1451 #define QIB_7220_MEM_095000_offset 0x00095000UL
1452
1453 #define QIB_7220_SendBuf0_MA_offset 0x00100000UL
1454
1455 #define QIB_7220_MEM_1A0000_offset 0x001a0000UL
1456
1457 #define QIB_7220_RcvHdrTail0_offset 0x00200000UL
1458
1459 #define QIB_7220_RcvHdrHead0_offset 0x00200008UL
1460 struct QIB_7220_RcvHdrHead0_pb {
1461         pseudo_bit_t RcvHeadPointer[32];
1462         pseudo_bit_t counter[16];
1463         pseudo_bit_t Reserved[16];
1464 };
1465 struct QIB_7220_RcvHdrHead0 {
1466         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead0_pb );
1467 };
1468
1469 #define QIB_7220_RcvEgrIndexTail0_offset 0x00200010UL
1470
1471 #define QIB_7220_RcvEgrIndexHead0_offset 0x00200018UL
1472
1473 #define QIB_7220_MEM_200020_offset 0x00200020UL
1474
1475 #define QIB_7220_RcvHdrTail1_offset 0x00210000UL
1476
1477 #define QIB_7220_RcvHdrHead1_offset 0x00210008UL
1478 struct QIB_7220_RcvHdrHead1_pb {
1479         pseudo_bit_t RcvHeadPointer[32];
1480         pseudo_bit_t counter[16];
1481         pseudo_bit_t Reserved[16];
1482 };
1483 struct QIB_7220_RcvHdrHead1 {
1484         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead1_pb );
1485 };
1486
1487 #define QIB_7220_RcvEgrIndexTail1_offset 0x00210010UL
1488
1489 #define QIB_7220_RcvEgrIndexHead1_offset 0x00210018UL
1490
1491 #define QIB_7220_MEM_210020_offset 0x00210020UL
1492
1493 #define QIB_7220_RcvHdrTail2_offset 0x00220000UL
1494
1495 #define QIB_7220_RcvHdrHead2_offset 0x00220008UL
1496 struct QIB_7220_RcvHdrHead2_pb {
1497         pseudo_bit_t RcvHeadPointer[32];
1498         pseudo_bit_t counter[16];
1499         pseudo_bit_t Reserved[16];
1500 };
1501 struct QIB_7220_RcvHdrHead2 {
1502         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead2_pb );
1503 };
1504
1505 #define QIB_7220_RcvEgrIndexTail2_offset 0x00220010UL
1506
1507 #define QIB_7220_RcvEgrIndexHead2_offset 0x00220018UL
1508
1509 #define QIB_7220_MEM_220020_offset 0x00220020UL
1510
1511 #define QIB_7220_RcvHdrTail3_offset 0x00230000UL
1512
1513 #define QIB_7220_RcvHdrHead3_offset 0x00230008UL
1514 struct QIB_7220_RcvHdrHead3_pb {
1515         pseudo_bit_t RcvHeadPointer[32];
1516         pseudo_bit_t counter[16];
1517         pseudo_bit_t Reserved[16];
1518 };
1519 struct QIB_7220_RcvHdrHead3 {
1520         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead3_pb );
1521 };
1522
1523 #define QIB_7220_RcvEgrIndexTail3_offset 0x00230010UL
1524
1525 #define QIB_7220_RcvEgrIndexHead3_offset 0x00230018UL
1526
1527 #define QIB_7220_MEM_230020_offset 0x00230020UL
1528
1529 #define QIB_7220_RcvHdrTail4_offset 0x00240000UL
1530
1531 #define QIB_7220_RcvHdrHead4_offset 0x00240008UL
1532 struct QIB_7220_RcvHdrHead4_pb {
1533         pseudo_bit_t RcvHeadPointer[32];
1534         pseudo_bit_t counter[16];
1535         pseudo_bit_t Reserved[16];
1536 };
1537 struct QIB_7220_RcvHdrHead4 {
1538         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead4_pb );
1539 };
1540
1541 #define QIB_7220_RcvEgrIndexTail4_offset 0x00240010UL
1542
1543 #define QIB_7220_RcvEgrIndexHead4_offset 0x00240018UL
1544
1545 #define QIB_7220_MEM_240020_offset 0x00240020UL
1546
1547 #define QIB_7220_RcvHdrTail5_offset 0x00250000UL
1548
1549 #define QIB_7220_RcvHdrHead5_offset 0x00250008UL
1550 struct QIB_7220_RcvHdrHead5_pb {
1551         pseudo_bit_t RcvHeadPointer[32];
1552         pseudo_bit_t counter[16];
1553         pseudo_bit_t Reserved[16];
1554 };
1555 struct QIB_7220_RcvHdrHead5 {
1556         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead5_pb );
1557 };
1558
1559 #define QIB_7220_RcvEgrIndexTail5_offset 0x00250010UL
1560
1561 #define QIB_7220_RcvEgrIndexHead5_offset 0x00250018UL
1562
1563 #define QIB_7220_MEM_250020_offset 0x00250020UL
1564
1565 #define QIB_7220_RcvHdrTail6_offset 0x00260000UL
1566
1567 #define QIB_7220_RcvHdrHead6_offset 0x00260008UL
1568 struct QIB_7220_RcvHdrHead6_pb {
1569         pseudo_bit_t RcvHeadPointer[32];
1570         pseudo_bit_t counter[16];
1571         pseudo_bit_t Reserved[16];
1572 };
1573 struct QIB_7220_RcvHdrHead6 {
1574         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead6_pb );
1575 };
1576
1577 #define QIB_7220_RcvEgrIndexTail6_offset 0x00260010UL
1578
1579 #define QIB_7220_RcvEgrIndexHead6_offset 0x00260018UL
1580
1581 #define QIB_7220_MEM_260020_offset 0x00260020UL
1582
1583 #define QIB_7220_RcvHdrTail7_offset 0x00270000UL
1584
1585 #define QIB_7220_RcvHdrHead7_offset 0x00270008UL
1586 struct QIB_7220_RcvHdrHead7_pb {
1587         pseudo_bit_t RcvHeadPointer[32];
1588         pseudo_bit_t counter[16];
1589         pseudo_bit_t Reserved[16];
1590 };
1591 struct QIB_7220_RcvHdrHead7 {
1592         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead7_pb );
1593 };
1594
1595 #define QIB_7220_RcvEgrIndexTail7_offset 0x00270010UL
1596
1597 #define QIB_7220_RcvEgrIndexHead7_offset 0x00270018UL
1598
1599 #define QIB_7220_MEM_270020_offset 0x00270020UL
1600
1601 #define QIB_7220_RcvHdrTail8_offset 0x00280000UL
1602
1603 #define QIB_7220_RcvHdrHead8_offset 0x00280008UL
1604 struct QIB_7220_RcvHdrHead8_pb {
1605         pseudo_bit_t RcvHeadPointer[32];
1606         pseudo_bit_t counter[16];
1607         pseudo_bit_t Reserved[16];
1608 };
1609 struct QIB_7220_RcvHdrHead8 {
1610         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead8_pb );
1611 };
1612
1613 #define QIB_7220_RcvEgrIndexTail8_offset 0x00280010UL
1614
1615 #define QIB_7220_RcvEgrIndexHead8_offset 0x00280018UL
1616
1617 #define QIB_7220_MEM_280020_offset 0x00280020UL
1618
1619 #define QIB_7220_RcvHdrTail9_offset 0x00290000UL
1620
1621 #define QIB_7220_RcvHdrHead9_offset 0x00290008UL
1622 struct QIB_7220_RcvHdrHead9_pb {
1623         pseudo_bit_t RcvHeadPointer[32];
1624         pseudo_bit_t counter[16];
1625         pseudo_bit_t Reserved[16];
1626 };
1627 struct QIB_7220_RcvHdrHead9 {
1628         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead9_pb );
1629 };
1630
1631 #define QIB_7220_RcvEgrIndexTail9_offset 0x00290010UL
1632
1633 #define QIB_7220_RcvEgrIndexHead9_offset 0x00290018UL
1634
1635 #define QIB_7220_MEM_290020_offset 0x00290020UL
1636
1637 #define QIB_7220_RcvHdrTail10_offset 0x002a0000UL
1638
1639 #define QIB_7220_RcvHdrHead10_offset 0x002a0008UL
1640 struct QIB_7220_RcvHdrHead10_pb {
1641         pseudo_bit_t RcvHeadPointer[32];
1642         pseudo_bit_t counter[16];
1643         pseudo_bit_t Reserved[16];
1644 };
1645 struct QIB_7220_RcvHdrHead10 {
1646         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead10_pb );
1647 };
1648
1649 #define QIB_7220_RcvEgrIndexTail10_offset 0x002a0010UL
1650
1651 #define QIB_7220_RcvEgrIndexHead10_offset 0x002a0018UL
1652
1653 #define QIB_7220_MEM_2A0020_offset 0x002a0020UL
1654
1655 #define QIB_7220_RcvHdrTail11_offset 0x002b0000UL
1656
1657 #define QIB_7220_RcvHdrHead11_offset 0x002b0008UL
1658 struct QIB_7220_RcvHdrHead11_pb {
1659         pseudo_bit_t RcvHeadPointer[32];
1660         pseudo_bit_t counter[16];
1661         pseudo_bit_t Reserved[16];
1662 };
1663 struct QIB_7220_RcvHdrHead11 {
1664         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead11_pb );
1665 };
1666
1667 #define QIB_7220_RcvEgrIndexTail11_offset 0x002b0010UL
1668
1669 #define QIB_7220_RcvEgrIndexHead11_offset 0x002b0018UL
1670
1671 #define QIB_7220_MEM_2B0020_offset 0x002b0020UL
1672
1673 #define QIB_7220_RcvHdrTail12_offset 0x002c0000UL
1674
1675 #define QIB_7220_RcvHdrHead12_offset 0x002c0008UL
1676 struct QIB_7220_RcvHdrHead12_pb {
1677         pseudo_bit_t RcvHeadPointer[32];
1678         pseudo_bit_t counter[16];
1679         pseudo_bit_t Reserved[16];
1680 };
1681 struct QIB_7220_RcvHdrHead12 {
1682         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead12_pb );
1683 };
1684
1685 #define QIB_7220_RcvEgrIndexTail12_offset 0x002c0010UL
1686
1687 #define QIB_7220_RcvEgrIndexHead12_offset 0x002c0018UL
1688
1689 #define QIB_7220_MEM_2C0020_offset 0x002c0020UL
1690
1691 #define QIB_7220_RcvHdrTail13_offset 0x002d0000UL
1692
1693 #define QIB_7220_RcvHdrHead13_offset 0x002d0008UL
1694 struct QIB_7220_RcvHdrHead13_pb {
1695         pseudo_bit_t RcvHeadPointer[32];
1696         pseudo_bit_t counter[16];
1697         pseudo_bit_t Reserved[16];
1698 };
1699 struct QIB_7220_RcvHdrHead13 {
1700         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead13_pb );
1701 };
1702
1703 #define QIB_7220_RcvEgrIndexTail13_offset 0x002d0010UL
1704
1705 #define QIB_7220_RcvEgrIndexHead13_offset 0x002d0018UL
1706
1707 #define QIB_7220_MEM_2D0020_offset 0x002d0020UL
1708
1709 #define QIB_7220_RcvHdrTail14_offset 0x002e0000UL
1710
1711 #define QIB_7220_RcvHdrHead14_offset 0x002e0008UL
1712 struct QIB_7220_RcvHdrHead14_pb {
1713         pseudo_bit_t RcvHeadPointer[32];
1714         pseudo_bit_t counter[16];
1715         pseudo_bit_t Reserved[16];
1716 };
1717 struct QIB_7220_RcvHdrHead14 {
1718         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead14_pb );
1719 };
1720
1721 #define QIB_7220_RcvEgrIndexTail14_offset 0x002e0010UL
1722
1723 #define QIB_7220_RcvEgrIndexHead14_offset 0x002e0018UL
1724
1725 #define QIB_7220_MEM_2E0020_offset 0x002e0020UL
1726
1727 #define QIB_7220_RcvHdrTail15_offset 0x002f0000UL
1728
1729 #define QIB_7220_RcvHdrHead15_offset 0x002f0008UL
1730 struct QIB_7220_RcvHdrHead15_pb {
1731         pseudo_bit_t RcvHeadPointer[32];
1732         pseudo_bit_t counter[16];
1733         pseudo_bit_t Reserved[16];
1734 };
1735 struct QIB_7220_RcvHdrHead15 {
1736         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead15_pb );
1737 };
1738
1739 #define QIB_7220_RcvEgrIndexTail15_offset 0x002f0010UL
1740
1741 #define QIB_7220_RcvEgrIndexHead15_offset 0x002f0018UL
1742
1743 #define QIB_7220_MEM_2F0020_offset 0x002f0020UL
1744
1745 #define QIB_7220_RcvHdrTail16_offset 0x00300000UL
1746
1747 #define QIB_7220_RcvHdrHead16_offset 0x00300008UL
1748 struct QIB_7220_RcvHdrHead16_pb {
1749         pseudo_bit_t RcvHeadPointer[32];
1750         pseudo_bit_t counter[16];
1751         pseudo_bit_t Reserved[16];
1752 };
1753 struct QIB_7220_RcvHdrHead16 {
1754         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead16_pb );
1755 };
1756
1757 #define QIB_7220_RcvEgrIndexTail16_offset 0x00300010UL
1758
1759 #define QIB_7220_RcvEgrIndexHead16_offset 0x00300018UL
1760
1761 #define QIB_7220_MEM_300020_offset 0x00300020UL
1762