5 * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 FILE_LICENCE ( GPL2_OR_LATER );
28 * QLogic QIB7322 Infiniband HCA
32 #define BITOPS_LITTLE_ENDIAN
33 #include <ipxe/bitops.h>
34 #include "qib_7322_regs.h"
36 /** A QIB7322 GPIO register */
37 struct QIB_7322_GPIO_pb {
38 pseudo_bit_t GPIO[16];
39 pseudo_bit_t Reserved[48];
41 struct QIB_7322_GPIO {
42 PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
45 /** A QIB7322 general scalar register */
46 struct QIB_7322_scalar_pb {
47 pseudo_bit_t Value[64];
49 struct QIB_7322_scalar {
50 PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
53 /** QIB7322 feature mask */
54 struct QIB_7322_feature_mask_pb {
55 pseudo_bit_t Port0_Link_Speed_Supported[3];
56 pseudo_bit_t Port1_Link_Speed_Supported[3];
57 pseudo_bit_t _unused_0[58];
59 struct QIB_7322_feature_mask {
60 PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
63 /** QIB7322 send per-buffer control word */
64 struct QIB_7322_SendPbc_pb {
65 pseudo_bit_t LengthP1_toibc[11];
66 pseudo_bit_t Reserved1[4];
67 pseudo_bit_t LengthP1_trigger[11];
68 pseudo_bit_t Reserved2[3];
69 pseudo_bit_t TestEbp[1];
72 pseudo_bit_t StaticRateControlCnt[14];
73 pseudo_bit_t Reserved3[12];
75 pseudo_bit_t VLane[3];
76 pseudo_bit_t Reserved4[1];
79 struct QIB_7322_SendPbc {
80 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
83 /** QIB7322 send buffer availability */
84 struct QIB_7322_SendBufAvail_pb {
85 pseudo_bit_t InUseCheck[162][2];
86 pseudo_bit_t Reserved[60];
88 struct QIB_7322_SendBufAvail {
89 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
92 /** DMA alignment for send buffer availability */
93 #define QIB7322_SENDBUFAVAIL_ALIGN 64
95 /** QIB7322 port-specific receive control */
96 struct QIB_7322_RcvCtrl_P_pb {
97 pseudo_bit_t ContextEnable[18];
98 pseudo_bit_t _unused_1[21];
99 pseudo_bit_t RcvIBPortEnable[1];
100 pseudo_bit_t RcvQPMapEnable[1];
101 pseudo_bit_t RcvPartitionKeyDisable[1];
102 pseudo_bit_t RcvResetCredit[1];
103 pseudo_bit_t _unused_2[21];
105 struct QIB_7322_RcvCtrl_P {
106 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
109 /** A QIB7322 eager receive descriptor */
110 struct QIB_7322_RcvEgr_pb {
111 pseudo_bit_t Addr[37];
112 pseudo_bit_t BufSize[3];
113 pseudo_bit_t Reserved[24];
115 struct QIB_7322_RcvEgr {
116 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
119 /** QIB7322 receive header flags */
120 struct QIB_7322_RcvHdrFlags_pb {
121 pseudo_bit_t PktLen[11];
122 pseudo_bit_t RcvType[3];
123 pseudo_bit_t SoftB[1];
124 pseudo_bit_t SoftA[1];
125 pseudo_bit_t EgrIndex[12];
126 pseudo_bit_t Reserved1[3];
127 pseudo_bit_t UseEgrBfr[1];
128 pseudo_bit_t RcvSeq[4];
129 pseudo_bit_t HdrqOffset[11];
130 pseudo_bit_t Reserved2[8];
131 pseudo_bit_t IBErr[1];
132 pseudo_bit_t MKErr[1];
133 pseudo_bit_t TIDErr[1];
134 pseudo_bit_t KHdrErr[1];
135 pseudo_bit_t MTUErr[1];
136 pseudo_bit_t LenErr[1];
137 pseudo_bit_t ParityErr[1];
138 pseudo_bit_t VCRCErr[1];
139 pseudo_bit_t ICRCErr[1];
141 struct QIB_7322_RcvHdrFlags {
142 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
145 /** QIB7322 DDS tuning parameters */
146 struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
148 pseudo_bit_t PreXtra[2];
149 pseudo_bit_t Post[4];
150 pseudo_bit_t Main[5];
152 pseudo_bit_t _unused_0[46];
154 struct QIB_7322_IBSD_DDS_MAP_TABLE {
155 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
158 /** QIB7322 memory BAR size */
159 #define QIB7322_BAR0_SIZE 0x400000
161 /** QIB7322 base port number */
162 #define QIB7322_PORT_BASE 1
164 /** QIB7322 maximum number of ports */
165 #define QIB7322_MAX_PORTS 2
167 /** QIB7322 maximum width */
168 #define QIB7322_MAX_WIDTH 4
170 /** QIB7322 board identifiers */
171 enum qib7322_board_id {
172 QIB7322_BOARD_QLE7342_EMULATION = 0,
173 QIB7322_BOARD_QLE7340 = 1,
174 QIB7322_BOARD_QLE7342 = 2,
175 QIB7322_BOARD_QMI7342 = 3,
176 QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
177 QIB7322_BOARD_QME7342 = 5,
178 QIB7322_BOARD_QMH7342 = 6,
179 QIB7322_BOARD_QLE7342_TEST = 15,
182 /** QIB7322 I2C SCL line GPIO number */
183 #define QIB7322_GPIO_SCL 0
185 /** QIB7322 I2C SDA line GPIO number */
186 #define QIB7322_GPIO_SDA 1
188 /** GUID offset within EEPROM */
189 #define QIB7322_EEPROM_GUID_OFFSET 3
191 /** GUID size within EEPROM */
192 #define QIB7322_EEPROM_GUID_SIZE 8
194 /** Board serial number offset within EEPROM */
195 #define QIB7322_EEPROM_SERIAL_OFFSET 12
197 /** Board serial number size within EEPROM */
198 #define QIB7322_EEPROM_SERIAL_SIZE 12
200 /** QIB7322 small send buffer size */
201 #define QIB7322_SMALL_SEND_BUF_SIZE 4096
203 /** QIB7322 small send buffer starting index */
204 #define QIB7322_SMALL_SEND_BUF_START 0
206 /** QIB7322 small send buffer count */
207 #define QIB7322_SMALL_SEND_BUF_COUNT 128
209 /** QIB7322 large send buffer size */
210 #define QIB7322_LARGE_SEND_BUF_SIZE 8192
212 /** QIB7322 large send buffer starting index */
213 #define QIB7322_LARGE_SEND_BUF_START 128
215 /** QIB7322 large send buffer count */
216 #define QIB7322_LARGE_SEND_BUF_COUNT 32
218 /** QIB7322 VL15 port 0 send buffer starting index */
219 #define QIB7322_VL15_PORT0_SEND_BUF_START 160
221 /** QIB7322 VL15 port 0 send buffer count */
222 #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
224 /** QIB7322 VL15 port 0 send buffer size */
225 #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
227 /** QIB7322 VL15 port 0 send buffer starting index */
228 #define QIB7322_VL15_PORT1_SEND_BUF_START 161
230 /** QIB7322 VL15 port 0 send buffer count */
231 #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
233 /** QIB7322 VL15 port 0 send buffer size */
234 #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
236 /** Number of small send buffers used
238 * This is a policy decision. Must be less than or equal to the total
239 * number of small send buffers supported by the hardware
240 * (QIB7322_SMALL_SEND_BUF_COUNT).
242 #define QIB7322_SMALL_SEND_BUF_USED 32
244 /** Number of contexts (including kernel context)
246 * This is a policy decision. Must be 6, 10 or 18.
248 #define QIB7322_NUM_CONTEXTS 6
250 /** ContextCfg values for different numbers of contexts */
251 enum qib7322_contextcfg {
252 QIB7322_CONTEXTCFG_6CTX = 0,
253 QIB7322_CONTEXTCFG_10CTX = 1,
254 QIB7322_CONTEXTCFG_18CTX = 2,
257 /** ContextCfg values for different numbers of contexts */
258 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
259 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
260 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
261 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
262 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
263 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
265 /** Eager buffer required alignment */
266 #define QIB7322_EAGER_BUFFER_ALIGN 2048
268 /** Eager buffer size encodings */
269 enum qib7322_eager_buffer_size {
270 QIB7322_EAGER_BUFFER_NONE = 0,
271 QIB7322_EAGER_BUFFER_2K = 1,
272 QIB7322_EAGER_BUFFER_4K = 2,
273 QIB7322_EAGER_BUFFER_8K = 3,
274 QIB7322_EAGER_BUFFER_16K = 4,
275 QIB7322_EAGER_BUFFER_32K = 5,
276 QIB7322_EAGER_BUFFER_64K = 6,
279 /** Number of RX headers per context
281 * This is a policy decision.
283 #define QIB7322_RECV_HEADER_COUNT 8
285 /** Maximum size of each RX header
287 * This is a policy decision. Must be divisible by 4.
289 #define QIB7322_RECV_HEADER_SIZE 96
291 /** Total size of an RX header ring */
292 #define QIB7322_RECV_HEADERS_SIZE \
293 ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
295 /** RX header alignment */
296 #define QIB7322_RECV_HEADERS_ALIGN 64
300 * This is a policy decision. Must be a valid eager buffer size.
302 #define QIB7322_RECV_PAYLOAD_SIZE 2048
304 /** Maximum number of credits per port
306 * 64kB of internal RX buffer space, in units of 64 bytes, split
309 #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
311 /** Number of credits to advertise for VL15
313 * This is a policy decision. Using 9 credits allows for 9*64=576
314 * bytes, which is enough for two MADs.
316 #define QIB7322_MAX_CREDITS_VL15 9
318 /** Number of credits to advertise for VL0
320 * This is a policy decision.
322 #define QIB7322_MAX_CREDITS_VL0 \
323 ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
325 /** QPN used for Infinipath Packets
327 * This is a policy decision. Must have bit 0 clear. Must not be a
328 * QPN that we will use.
330 #define QIB7322_QP_IDETH 0xdead0
332 /** Maximum time for wait for AHB, in us */
333 #define QIB7322_AHB_MAX_WAIT_US 500
335 /** QIB7322 AHB locations */
336 #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
337 #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
338 #define QIB7322_AHB_CHAN_0 0
339 #define QIB7322_AHB_CHAN_1 1
340 #define QIB7322_AHB_PLL 2
341 #define QIB7322_AHB_CHAN_2 3
342 #define QIB7322_AHB_CHAN_3 4
343 #define QIB7322_AHB_SUBSYS 5
344 #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
345 #define QIB7322_AHB_TARGET_0 2
346 #define QIB7322_AHB_TARGET_1 3
347 #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
348 #define QIB7322_AHB_LOCATION( _port, _channel, _register ) \
349 ( ( QIB7322_AHB_TARGET(_port) << 16 ) | \
350 ( QIB7322_AHB_CHAN(_channel) << 7 ) | \
351 ( (_register) << 1 ) )
353 /** QIB7322 link states */
354 enum qib7322_link_state {
355 QIB7322_LINK_STATE_DOWN = 0,
356 QIB7322_LINK_STATE_INIT = 1,
357 QIB7322_LINK_STATE_ARM = 2,
358 QIB7322_LINK_STATE_ACTIVE = 3,
359 QIB7322_LINK_STATE_ACT_DEFER = 4,
362 /** Maximum time to wait for link state changes, in us */
363 #define QIB7322_LINK_STATE_MAX_WAIT_US 20
365 #endif /* _QIB7322_H */