2 * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 FILE_LICENCE ( GPL2_OR_LATER );
29 #include <ipxe/infiniband.h>
31 #include <ipxe/bitbash.h>
32 #include <ipxe/malloc.h>
33 #include <ipxe/iobuf.h>
34 #include <ipxe/pcibackup.h>
40 * QLogic QIB7322 Infiniband HCA
44 /** A QIB7322 send buffer set */
45 struct qib7322_send_buffers {
46 /** Offset within register space of the first send buffer */
48 /** Send buffer size */
50 /** Index of first send buffer */
52 /** Number of send buffers
54 * Must be a power of two.
57 /** Send buffer availability producer counter */
59 /** Send buffer availability consumer counter */
61 /** Send buffer availability */
65 /** A QIB7322 send work queue */
66 struct qib7322_send_work_queue {
67 /** Send buffer set */
68 struct qib7322_send_buffers *send_bufs;
69 /** Send buffer usage */
77 /** A QIB7322 receive work queue */
78 struct qib7322_recv_work_queue {
79 /** Receive header ring */
81 /** Receive header producer offset (written by hardware) */
82 struct QIB_7322_scalar header_prod;
83 /** Receive header consumer offset */
84 unsigned int header_cons;
85 /** Offset within register space of the eager array */
86 unsigned long eager_array;
87 /** Number of entries in eager array */
88 unsigned int eager_entries;
89 /** Eager array producer index */
90 unsigned int eager_prod;
91 /** Eager array consumer index */
92 unsigned int eager_cons;
100 /** In-use contexts */
101 uint8_t used_ctx[QIB7322_NUM_CONTEXTS];
102 /** Send work queues */
103 struct qib7322_send_work_queue send_wq[QIB7322_NUM_CONTEXTS];
104 /** Receive work queues */
105 struct qib7322_recv_work_queue recv_wq[QIB7322_NUM_CONTEXTS];
107 /** Send buffer availability (reported by hardware) */
108 struct QIB_7322_SendBufAvail *sendbufavail;
109 /** Small send buffers */
110 struct qib7322_send_buffers *send_bufs_small;
111 /** VL15 port 0 send buffers */
112 struct qib7322_send_buffers *send_bufs_vl15_port0;
113 /** VL15 port 1 send buffers */
114 struct qib7322_send_buffers *send_bufs_vl15_port1;
116 /** I2C bit-bashing interface */
117 struct i2c_bit_basher i2c;
118 /** I2C serial EEPROM */
119 struct i2c_device eeprom;
123 /** Infiniband devices */
124 struct ib_device *ibdev[QIB7322_MAX_PORTS];
127 /***************************************************************************
129 * QIB7322 register access
131 ***************************************************************************
133 * This card requires atomic 64-bit accesses. Strange things happen
134 * if you try to use 32-bit accesses; sometimes they work, sometimes
135 * they don't, sometimes you get random data.
137 * These accessors use the "movq" MMX instruction, and so won't work
138 * on really old Pentiums (which won't have PCIe anyway, so this is
139 * something of a moot point).
143 * Read QIB7322 qword register
145 * @v qib7322 QIB7322 device
146 * @v dwords Register buffer to read into
147 * @v offset Register offset
149 static void qib7322_readq ( struct qib7322 *qib7322, uint32_t *dwords,
150 unsigned long offset ) {
151 void *addr = ( qib7322->regs + offset );
153 __asm__ __volatile__ ( "movq (%1), %%mm0\n\t"
154 "movq %%mm0, (%0)\n\t"
155 : : "r" ( dwords ), "r" ( addr ) : "memory" );
157 DBGIO ( "[%08lx] => %08x%08x\n",
158 virt_to_phys ( addr ), dwords[1], dwords[0] );
160 #define qib7322_readq( _qib7322, _ptr, _offset ) \
161 qib7322_readq ( (_qib7322), (_ptr)->u.dwords, (_offset) )
162 #define qib7322_readq_array8b( _qib7322, _ptr, _offset, _idx ) \
163 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
164 #define qib7322_readq_array64k( _qib7322, _ptr, _offset, _idx ) \
165 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ) )
166 #define qib7322_readq_port( _qib7322, _ptr, _offset, _port ) \
167 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ) )
170 * Write QIB7322 qword register
172 * @v qib7322 QIB7322 device
173 * @v dwords Register buffer to write
174 * @v offset Register offset
176 static void qib7322_writeq ( struct qib7322 *qib7322, const uint32_t *dwords,
177 unsigned long offset ) {
178 void *addr = ( qib7322->regs + offset );
180 DBGIO ( "[%08lx] <= %08x%08x\n",
181 virt_to_phys ( addr ), dwords[1], dwords[0] );
183 __asm__ __volatile__ ( "movq (%0), %%mm0\n\t"
184 "movq %%mm0, (%1)\n\t"
185 : : "r" ( dwords ), "r" ( addr ) : "memory" );
187 #define qib7322_writeq( _qib7322, _ptr, _offset ) \
188 qib7322_writeq ( (_qib7322), (_ptr)->u.dwords, (_offset) )
189 #define qib7322_writeq_array8b( _qib7322, _ptr, _offset, _idx ) \
190 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
191 #define qib7322_writeq_array64k( _qib7322, _ptr, _offset, _idx ) \
192 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ))
193 #define qib7322_writeq_port( _qib7322, _ptr, _offset, _port ) \
194 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ))
197 * Write QIB7322 dword register
199 * @v qib7322 QIB7322 device
200 * @v dword Value to write
201 * @v offset Register offset
203 static void qib7322_writel ( struct qib7322 *qib7322, uint32_t dword,
204 unsigned long offset ) {
205 writel ( dword, ( qib7322->regs + offset ) );
208 /***************************************************************************
210 * Link state management
212 ***************************************************************************
216 * Textual representation of link state
218 * @v link_state Link state
219 * @ret link_text Link state text
221 static const char * qib7322_link_state_text ( unsigned int link_state ) {
222 switch ( link_state ) {
223 case QIB7322_LINK_STATE_DOWN: return "DOWN";
224 case QIB7322_LINK_STATE_INIT: return "INIT";
225 case QIB7322_LINK_STATE_ARM: return "ARM";
226 case QIB7322_LINK_STATE_ACTIVE: return "ACTIVE";
227 case QIB7322_LINK_STATE_ACT_DEFER: return "ACT_DEFER";
228 default: return "UNKNOWN";
233 * Handle link state change
235 * @v qib7322 QIB7322 device
237 static void qib7322_link_state_changed ( struct ib_device *ibdev ) {
238 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
239 struct QIB_7322_IBCStatusA_0 ibcstatusa;
240 struct QIB_7322_EXTCtrl extctrl;
241 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
242 unsigned int link_training_state;
243 unsigned int link_state;
244 unsigned int link_width;
245 unsigned int link_speed;
246 unsigned int link_speed_qdr;
250 /* Read link state */
251 qib7322_readq_port ( qib7322, &ibcstatusa,
252 QIB_7322_IBCStatusA_0_offset, port );
253 link_training_state = BIT_GET ( &ibcstatusa, LinkTrainingState );
254 link_state = BIT_GET ( &ibcstatusa, LinkState );
255 link_width = BIT_GET ( &ibcstatusa, LinkWidthActive );
256 link_speed = BIT_GET ( &ibcstatusa, LinkSpeedActive );
257 link_speed_qdr = BIT_GET ( &ibcstatusa, LinkSpeedQDR );
258 DBGC ( qib7322, "QIB7322 %p port %d training state %#x link state %s "
259 "(%s %s)\n", qib7322, port, link_training_state,
260 qib7322_link_state_text ( link_state ),
261 ( link_speed_qdr ? "QDR" : ( link_speed ? "DDR" : "SDR" ) ),
262 ( link_width ? "x4" : "x1" ) );
264 /* Set LEDs according to link state */
265 qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
266 green = ( ( link_state >= QIB7322_LINK_STATE_INIT ) ? 1 : 0 );
267 yellow = ( ( link_state >= QIB7322_LINK_STATE_ACTIVE ) ? 1 : 0 );
269 BIT_SET ( &extctrl, LEDPort0GreenOn, green );
270 BIT_SET ( &extctrl, LEDPort0YellowOn, yellow );
272 BIT_SET ( &extctrl, LEDPort1GreenOn, green );
273 BIT_SET ( &extctrl, LEDPort1YellowOn, yellow );
275 qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
277 /* Notify Infiniband core of link state change */
278 ibdev->port_state = ( link_state + 1 );
279 ibdev->link_width_active =
280 ( link_width ? IB_LINK_WIDTH_4X : IB_LINK_WIDTH_1X );
281 ibdev->link_speed_active =
282 ( link_speed ? IB_LINK_SPEED_DDR : IB_LINK_SPEED_SDR );
283 ib_link_state_changed ( ibdev );
287 * Wait for link state change to take effect
289 * @v ibdev Infiniband device
290 * @v new_link_state Expected link state
291 * @ret rc Return status code
293 static int qib7322_link_state_check ( struct ib_device *ibdev,
294 unsigned int new_link_state ) {
295 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
296 struct QIB_7322_IBCStatusA_0 ibcstatusa;
297 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
298 unsigned int link_state;
301 for ( i = 0 ; i < QIB7322_LINK_STATE_MAX_WAIT_US ; i++ ) {
302 qib7322_readq_port ( qib7322, &ibcstatusa,
303 QIB_7322_IBCStatusA_0_offset, port );
304 link_state = BIT_GET ( &ibcstatusa, LinkState );
305 if ( link_state == new_link_state )
310 DBGC ( qib7322, "QIB7322 %p port %d timed out waiting for link state "
311 "%s\n", qib7322, port, qib7322_link_state_text ( link_state ) );
316 * Set port information
318 * @v ibdev Infiniband device
319 * @v mad Set port information MAD
321 static int qib7322_set_port_info ( struct ib_device *ibdev,
322 union ib_mad *mad ) {
323 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
324 struct ib_port_info *port_info = &mad->smp.smp_data.port_info;
325 struct QIB_7322_IBCCtrlA_0 ibcctrla;
326 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
327 unsigned int port_state;
328 unsigned int link_state;
330 /* Set new link state */
331 port_state = ( port_info->link_speed_supported__port_state & 0xf );
333 link_state = ( port_state - 1 );
334 DBGC ( qib7322, "QIB7322 %p set link state to %s (%x)\n",
335 qib7322, qib7322_link_state_text ( link_state ),
337 qib7322_readq_port ( qib7322, &ibcctrla,
338 QIB_7322_IBCCtrlA_0_offset, port );
339 BIT_SET ( &ibcctrla, LinkCmd, link_state );
340 qib7322_writeq_port ( qib7322, &ibcctrla,
341 QIB_7322_IBCCtrlA_0_offset, port );
343 /* Wait for link state change to take effect. Ignore
344 * errors; the current link state will be returned via
345 * the GetResponse MAD.
347 qib7322_link_state_check ( ibdev, link_state );
350 /* Detect and report link state change */
351 qib7322_link_state_changed ( ibdev );
357 * Set partition key table
359 * @v ibdev Infiniband device
360 * @v mad Set partition key table MAD
362 static int qib7322_set_pkey_table ( struct ib_device *ibdev __unused,
363 union ib_mad *mad __unused ) {
368 /***************************************************************************
372 ***************************************************************************
376 * Allocate a context and set queue pair number
378 * @v ibdev Infiniband device
380 * @ret rc Return status code
382 static int qib7322_alloc_ctx ( struct ib_device *ibdev,
383 struct ib_queue_pair *qp ) {
384 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
385 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
388 for ( ctx = port ; ctx < QIB7322_NUM_CONTEXTS ; ctx += 2 ) {
390 if ( ! qib7322->used_ctx[ctx] ) {
391 qib7322->used_ctx[ctx] = 1;
392 qp->qpn = ( ctx & ~0x01 );
393 DBGC2 ( qib7322, "QIB7322 %p port %d QPN %ld is CTX "
394 "%d\n", qib7322, port, qp->qpn, ctx );
399 DBGC ( qib7322, "QIB7322 %p port %d out of available contexts\n",
405 * Get queue pair context number
407 * @v ibdev Infiniband device
409 * @ret ctx Context index
411 static unsigned int qib7322_ctx ( struct ib_device *ibdev,
412 struct ib_queue_pair *qp ) {
413 return ( qp->qpn + ( ibdev->port - QIB7322_PORT_BASE ) );
419 * @v qib7322 QIB7322 device
420 * @v ctx Context index
422 static void qib7322_free_ctx ( struct ib_device *ibdev,
423 struct ib_queue_pair *qp ) {
424 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
425 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
426 unsigned int ctx = qib7322_ctx ( ibdev, qp );
428 qib7322->used_ctx[ctx] = 0;
429 DBGC2 ( qib7322, "QIB7322 %p port %d CTX %d freed\n",
430 qib7322, port, ctx );
433 /***************************************************************************
437 ***************************************************************************
440 /** Send buffer toggle bit
442 * We encode send buffers as 15 bits of send buffer index plus a
443 * single bit which should match the "check" bit in the SendBufAvail
446 #define QIB7322_SEND_BUF_TOGGLE 0x8000
449 * Create send buffer set
451 * @v qib7322 QIB7322 device
452 * @v base Send buffer base offset
453 * @v size Send buffer size
454 * @v start Index of first send buffer
455 * @v count Number of send buffers
456 * @ret send_bufs Send buffer set
458 static struct qib7322_send_buffers *
459 qib7322_create_send_bufs ( struct qib7322 *qib7322, unsigned long base,
460 unsigned int size, unsigned int start,
461 unsigned int count ) {
462 struct qib7322_send_buffers *send_bufs;
465 /* Allocate send buffer set */
466 send_bufs = zalloc ( sizeof ( *send_bufs ) +
467 ( count * sizeof ( send_bufs->avail[0] ) ) );
471 /* Populate send buffer set */
472 send_bufs->base = base;
473 send_bufs->size = size;
474 send_bufs->start = start;
475 send_bufs->count = count;
476 for ( i = 0 ; i < count ; i++ )
477 send_bufs->avail[i] = ( start + i );
479 DBGC2 ( qib7322, "QIB7322 %p send buffer set %p [%d,%d] at %lx\n",
480 qib7322, send_bufs, start, ( start + count - 1 ),
487 * Destroy send buffer set
489 * @v qib7322 QIB7322 device
490 * @v send_bufs Send buffer set
493 qib7322_destroy_send_bufs ( struct qib7322 *qib7322 __unused,
494 struct qib7322_send_buffers *send_bufs ) {
499 * Allocate a send buffer
501 * @v qib7322 QIB7322 device
502 * @v send_bufs Send buffer set
503 * @ret send_buf Send buffer, or negative error
505 static int qib7322_alloc_send_buf ( struct qib7322 *qib7322,
506 struct qib7322_send_buffers *send_bufs ) {
509 unsigned int send_buf;
511 used = ( send_bufs->cons - send_bufs->prod );
512 if ( used >= send_bufs->count ) {
513 DBGC ( qib7322, "QIB7322 %p send buffer set %p out of "
514 "buffers\n", qib7322, send_bufs );
518 mask = ( send_bufs->count - 1 );
519 send_buf = send_bufs->avail[ send_bufs->cons++ & mask ];
520 send_buf ^= QIB7322_SEND_BUF_TOGGLE;
527 * @v qib7322 QIB7322 device
528 * @v send_bufs Send buffer set
529 * @v send_buf Send buffer
531 static void qib7322_free_send_buf ( struct qib7322 *qib7322 __unused,
532 struct qib7322_send_buffers *send_bufs,
533 unsigned int send_buf ) {
536 mask = ( send_bufs->count - 1 );
537 send_bufs->avail[ send_bufs->prod++ & mask ] = send_buf;
541 * Check to see if send buffer is in use
543 * @v qib7322 QIB7322 device
544 * @v send_buf Send buffer
545 * @ret in_use Send buffer is in use
547 static int qib7322_send_buf_in_use ( struct qib7322 *qib7322,
548 unsigned int send_buf ) {
549 unsigned int send_idx;
550 unsigned int send_check;
551 unsigned int inusecheck;
555 send_idx = ( send_buf & ~QIB7322_SEND_BUF_TOGGLE );
556 send_check = ( !! ( send_buf & QIB7322_SEND_BUF_TOGGLE ) );
557 inusecheck = BIT_GET ( qib7322->sendbufavail, InUseCheck[send_idx] );
558 inuse = ( !! ( inusecheck & 0x02 ) );
559 check = ( !! ( inusecheck & 0x01 ) );
560 return ( inuse || ( check != send_check ) );
564 * Calculate starting offset for send buffer
566 * @v qib7322 QIB7322 device
567 * @v send_buf Send buffer
568 * @ret offset Starting offset
571 qib7322_send_buffer_offset ( struct qib7322 *qib7322 __unused,
572 struct qib7322_send_buffers *send_bufs,
573 unsigned int send_buf ) {
576 index = ( ( send_buf & ~QIB7322_SEND_BUF_TOGGLE ) - send_bufs->start );
577 return ( send_bufs->base + ( index * send_bufs->size ) );
581 * Create send work queue
583 * @v ibdev Infiniband device
586 static int qib7322_create_send_wq ( struct ib_device *ibdev,
587 struct ib_queue_pair *qp ) {
588 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
589 struct ib_work_queue *wq = &qp->send;
590 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
591 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
593 /* Select send buffer set */
594 if ( qp->type == IB_QPT_SMI ) {
596 qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port0;
598 qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port1;
601 qib7322_wq->send_bufs = qib7322->send_bufs_small;
604 /* Allocate space for send buffer usage list */
605 qib7322_wq->used = zalloc ( qp->send.num_wqes *
606 sizeof ( qib7322_wq->used[0] ) );
607 if ( ! qib7322_wq->used )
610 /* Reset work queue */
611 qib7322_wq->prod = 0;
612 qib7322_wq->cons = 0;
618 * Destroy send work queue
620 * @v ibdev Infiniband device
623 static void qib7322_destroy_send_wq ( struct ib_device *ibdev __unused,
624 struct ib_queue_pair *qp ) {
625 struct ib_work_queue *wq = &qp->send;
626 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
628 free ( qib7322_wq->used );
632 * Initialise send datapath
634 * @v qib7322 QIB7322 device
635 * @ret rc Return status code
637 static int qib7322_init_send ( struct qib7322 *qib7322 ) {
638 struct QIB_7322_SendBufBase sendbufbase;
639 struct QIB_7322_SendBufAvailAddr sendbufavailaddr;
640 struct QIB_7322_SendCtrl sendctrl;
641 struct QIB_7322_SendCtrl_0 sendctrlp;
642 unsigned long baseaddr_smallpio;
643 unsigned long baseaddr_largepio;
644 unsigned long baseaddr_vl15_port0;
645 unsigned long baseaddr_vl15_port1;
648 /* Create send buffer sets */
649 qib7322_readq ( qib7322, &sendbufbase, QIB_7322_SendBufBase_offset );
650 baseaddr_smallpio = BIT_GET ( &sendbufbase, BaseAddr_SmallPIO );
651 baseaddr_largepio = BIT_GET ( &sendbufbase, BaseAddr_LargePIO );
652 baseaddr_vl15_port0 = ( baseaddr_largepio +
653 ( QIB7322_LARGE_SEND_BUF_SIZE *
654 QIB7322_LARGE_SEND_BUF_COUNT ) );
655 baseaddr_vl15_port1 = ( baseaddr_vl15_port0 +
656 QIB7322_VL15_PORT0_SEND_BUF_SIZE );
657 qib7322->send_bufs_small =
658 qib7322_create_send_bufs ( qib7322, baseaddr_smallpio,
659 QIB7322_SMALL_SEND_BUF_SIZE,
660 QIB7322_SMALL_SEND_BUF_START,
661 QIB7322_SMALL_SEND_BUF_USED );
662 if ( ! qib7322->send_bufs_small ) {
664 goto err_create_send_bufs_small;
666 qib7322->send_bufs_vl15_port0 =
667 qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port0,
668 QIB7322_VL15_PORT0_SEND_BUF_SIZE,
669 QIB7322_VL15_PORT0_SEND_BUF_START,
670 QIB7322_VL15_PORT0_SEND_BUF_COUNT );
671 if ( ! qib7322->send_bufs_vl15_port0 ) {
673 goto err_create_send_bufs_vl15_port0;
675 qib7322->send_bufs_vl15_port1 =
676 qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port1,
677 QIB7322_VL15_PORT1_SEND_BUF_SIZE,
678 QIB7322_VL15_PORT1_SEND_BUF_START,
679 QIB7322_VL15_PORT1_SEND_BUF_COUNT );
680 if ( ! qib7322->send_bufs_vl15_port1 ) {
682 goto err_create_send_bufs_vl15_port1;
685 /* Allocate space for the SendBufAvail array */
686 qib7322->sendbufavail = malloc_dma ( sizeof ( *qib7322->sendbufavail ),
687 QIB7322_SENDBUFAVAIL_ALIGN );
688 if ( ! qib7322->sendbufavail ) {
690 goto err_alloc_sendbufavail;
692 memset ( qib7322->sendbufavail, 0, sizeof ( qib7322->sendbufavail ) );
694 /* Program SendBufAvailAddr into the hardware */
695 memset ( &sendbufavailaddr, 0, sizeof ( sendbufavailaddr ) );
696 BIT_FILL_1 ( &sendbufavailaddr, SendBufAvailAddr,
697 ( virt_to_bus ( qib7322->sendbufavail ) >> 6 ) );
698 qib7322_writeq ( qib7322, &sendbufavailaddr,
699 QIB_7322_SendBufAvailAddr_offset );
702 memset ( &sendctrlp, 0, sizeof ( sendctrlp ) );
703 BIT_FILL_1 ( &sendctrlp, SendEnable, 1 );
704 qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_0_offset );
705 qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_1_offset );
707 /* Enable DMA of SendBufAvail */
708 memset ( &sendctrl, 0, sizeof ( sendctrl ) );
709 BIT_FILL_1 ( &sendctrl, SendBufAvailUpd, 1 );
710 qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
714 free_dma ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
715 err_alloc_sendbufavail:
716 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
717 err_create_send_bufs_vl15_port1:
718 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
719 err_create_send_bufs_vl15_port0:
720 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
721 err_create_send_bufs_small:
726 * Shut down send datapath
728 * @v qib7322 QIB7322 device
730 static void qib7322_fini_send ( struct qib7322 *qib7322 ) {
731 struct QIB_7322_SendCtrl sendctrl;
733 /* Disable sending and DMA of SendBufAvail */
734 memset ( &sendctrl, 0, sizeof ( sendctrl ) );
735 qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
738 /* Ensure hardware has seen this disable */
739 qib7322_readq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
741 free_dma ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
742 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
743 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
744 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
747 /***************************************************************************
751 ***************************************************************************
755 * Create receive work queue
757 * @v ibdev Infiniband device
759 * @ret rc Return status code
761 static int qib7322_create_recv_wq ( struct ib_device *ibdev,
762 struct ib_queue_pair *qp ) {
763 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
764 struct ib_work_queue *wq = &qp->recv;
765 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
766 struct QIB_7322_RcvHdrAddr0 rcvhdraddr;
767 struct QIB_7322_RcvHdrTailAddr0 rcvhdrtailaddr;
768 struct QIB_7322_RcvHdrHead0 rcvhdrhead;
769 struct QIB_7322_scalar rcvegrindexhead;
770 struct QIB_7322_RcvCtrl rcvctrl;
771 struct QIB_7322_RcvCtrl_P rcvctrlp;
772 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
773 unsigned int ctx = qib7322_ctx ( ibdev, qp );
776 /* Reset context information */
777 memset ( &qib7322_wq->header_prod, 0,
778 sizeof ( qib7322_wq->header_prod ) );
779 qib7322_wq->header_cons = 0;
780 qib7322_wq->eager_prod = 0;
781 qib7322_wq->eager_cons = 0;
783 /* Allocate receive header buffer */
784 qib7322_wq->header = malloc_dma ( QIB7322_RECV_HEADERS_SIZE,
785 QIB7322_RECV_HEADERS_ALIGN );
786 if ( ! qib7322_wq->header ) {
788 goto err_alloc_header;
791 /* Enable context in hardware */
792 memset ( &rcvhdraddr, 0, sizeof ( rcvhdraddr ) );
793 BIT_FILL_1 ( &rcvhdraddr, RcvHdrAddr,
794 ( virt_to_bus ( qib7322_wq->header ) >> 2 ) );
795 qib7322_writeq_array8b ( qib7322, &rcvhdraddr,
796 QIB_7322_RcvHdrAddr0_offset, ctx );
797 memset ( &rcvhdrtailaddr, 0, sizeof ( rcvhdrtailaddr ) );
798 BIT_FILL_1 ( &rcvhdrtailaddr, RcvHdrTailAddr,
799 ( virt_to_bus ( &qib7322_wq->header_prod ) >> 2 ) );
800 qib7322_writeq_array8b ( qib7322, &rcvhdrtailaddr,
801 QIB_7322_RcvHdrTailAddr0_offset, ctx );
802 memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
803 BIT_FILL_1 ( &rcvhdrhead, counter, 1 );
804 qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
805 QIB_7322_RcvHdrHead0_offset, ctx );
806 memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
807 BIT_FILL_1 ( &rcvegrindexhead, Value, 1 );
808 qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
809 QIB_7322_RcvEgrIndexHead0_offset, ctx );
810 qib7322_readq_port ( qib7322, &rcvctrlp,
811 QIB_7322_RcvCtrl_0_offset, port );
812 BIT_SET ( &rcvctrlp, ContextEnable[ctx], 1 );
813 qib7322_writeq_port ( qib7322, &rcvctrlp,
814 QIB_7322_RcvCtrl_0_offset, port );
815 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
816 BIT_SET ( &rcvctrl, IntrAvail[ctx], 1 );
817 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
819 DBGC ( qib7322, "QIB7322 %p port %d QPN %ld CTX %d hdrs [%lx,%lx) prod "
820 "%lx\n", qib7322, port, qp->qpn, ctx,
821 virt_to_bus ( qib7322_wq->header ),
822 ( virt_to_bus ( qib7322_wq->header )
823 + QIB7322_RECV_HEADERS_SIZE ),
824 virt_to_bus ( &qib7322_wq->header_prod ) );
827 free_dma ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
833 * Destroy receive work queue
835 * @v ibdev Infiniband device
838 static void qib7322_destroy_recv_wq ( struct ib_device *ibdev,
839 struct ib_queue_pair *qp ) {
840 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
841 struct ib_work_queue *wq = &qp->recv;
842 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
843 struct QIB_7322_RcvCtrl rcvctrl;
844 struct QIB_7322_RcvCtrl_P rcvctrlp;
845 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
846 unsigned int ctx = qib7322_ctx ( ibdev, qp );
848 /* Disable context in hardware */
849 qib7322_readq_port ( qib7322, &rcvctrlp,
850 QIB_7322_RcvCtrl_0_offset, port );
851 BIT_SET ( &rcvctrlp, ContextEnable[ctx], 0 );
852 qib7322_writeq_port ( qib7322, &rcvctrlp,
853 QIB_7322_RcvCtrl_0_offset, port );
854 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
855 BIT_SET ( &rcvctrl, IntrAvail[ctx], 0 );
856 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
858 /* Make sure the hardware has seen that the context is disabled */
859 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
862 /* Free headers ring */
863 free_dma ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
867 * Initialise receive datapath
869 * @v qib7322 QIB7322 device
870 * @ret rc Return status code
872 static int qib7322_init_recv ( struct qib7322 *qib7322 ) {
873 struct QIB_7322_RcvCtrl rcvctrl;
874 struct QIB_7322_RcvCtrl_0 rcvctrlp;
875 struct QIB_7322_RcvQPMapTableA_0 rcvqpmaptablea0;
876 struct QIB_7322_RcvQPMapTableB_0 rcvqpmaptableb0;
877 struct QIB_7322_RcvQPMapTableA_1 rcvqpmaptablea1;
878 struct QIB_7322_RcvQPMapTableB_1 rcvqpmaptableb1;
879 struct QIB_7322_RcvQPMulticastContext_0 rcvqpmcastctx0;
880 struct QIB_7322_RcvQPMulticastContext_1 rcvqpmcastctx1;
881 struct QIB_7322_scalar rcvegrbase;
882 struct QIB_7322_scalar rcvhdrentsize;
883 struct QIB_7322_scalar rcvhdrcnt;
884 struct QIB_7322_RcvBTHQP_0 rcvbthqp;
885 struct QIB_7322_RxCreditVL0_0 rxcreditvl;
886 unsigned int contextcfg;
887 unsigned long egrbase;
888 unsigned int eager_array_size_kernel;
889 unsigned int eager_array_size_user;
892 /* Select configuration based on number of contexts */
893 switch ( QIB7322_NUM_CONTEXTS ) {
895 contextcfg = QIB7322_CONTEXTCFG_6CTX;
896 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL;
897 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_6CTX_USER;
900 contextcfg = QIB7322_CONTEXTCFG_10CTX;
901 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL;
902 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_10CTX_USER;
905 contextcfg = QIB7322_CONTEXTCFG_18CTX;
906 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL;
907 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_18CTX_USER;
910 linker_assert ( 0, invalid_QIB7322_NUM_CONTEXTS );
914 /* Configure number of contexts */
915 memset ( &rcvctrl, 0, sizeof ( rcvctrl ) );
916 BIT_FILL_2 ( &rcvctrl,
918 ContextCfg, contextcfg );
919 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
921 /* Map QPNs to contexts */
922 memset ( &rcvctrlp, 0, sizeof ( rcvctrlp ) );
923 BIT_FILL_3 ( &rcvctrlp,
926 RcvPartitionKeyDisable, 1 );
927 qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_0_offset );
928 qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_1_offset );
929 memset ( &rcvqpmaptablea0, 0, sizeof ( rcvqpmaptablea0 ) );
930 BIT_FILL_6 ( &rcvqpmaptablea0,
936 RcvQPMapContext5, 10 );
937 qib7322_writeq ( qib7322, &rcvqpmaptablea0,
938 QIB_7322_RcvQPMapTableA_0_offset );
939 memset ( &rcvqpmaptableb0, 0, sizeof ( rcvqpmaptableb0 ) );
940 BIT_FILL_3 ( &rcvqpmaptableb0,
941 RcvQPMapContext6, 12,
942 RcvQPMapContext7, 14,
943 RcvQPMapContext8, 16 );
944 qib7322_writeq ( qib7322, &rcvqpmaptableb0,
945 QIB_7322_RcvQPMapTableB_0_offset );
946 memset ( &rcvqpmaptablea1, 0, sizeof ( rcvqpmaptablea1 ) );
947 BIT_FILL_6 ( &rcvqpmaptablea1,
953 RcvQPMapContext5, 11 );
954 qib7322_writeq ( qib7322, &rcvqpmaptablea1,
955 QIB_7322_RcvQPMapTableA_1_offset );
956 memset ( &rcvqpmaptableb1, 0, sizeof ( rcvqpmaptableb1 ) );
957 BIT_FILL_3 ( &rcvqpmaptableb1,
958 RcvQPMapContext6, 13,
959 RcvQPMapContext7, 15,
960 RcvQPMapContext8, 17 );
961 qib7322_writeq ( qib7322, &rcvqpmaptableb1,
962 QIB_7322_RcvQPMapTableB_1_offset );
964 /* Map multicast QPNs to contexts */
965 memset ( &rcvqpmcastctx0, 0, sizeof ( rcvqpmcastctx0 ) );
966 BIT_FILL_1 ( &rcvqpmcastctx0, RcvQpMcContext, 0 );
967 qib7322_writeq ( qib7322, &rcvqpmcastctx0,
968 QIB_7322_RcvQPMulticastContext_0_offset );
969 memset ( &rcvqpmcastctx1, 0, sizeof ( rcvqpmcastctx1 ) );
970 BIT_FILL_1 ( &rcvqpmcastctx1, RcvQpMcContext, 1 );
971 qib7322_writeq ( qib7322, &rcvqpmcastctx1,
972 QIB_7322_RcvQPMulticastContext_1_offset );
974 /* Configure receive header buffer sizes */
975 memset ( &rcvhdrcnt, 0, sizeof ( rcvhdrcnt ) );
976 BIT_FILL_1 ( &rcvhdrcnt, Value, QIB7322_RECV_HEADER_COUNT );
977 qib7322_writeq ( qib7322, &rcvhdrcnt, QIB_7322_RcvHdrCnt_offset );
978 memset ( &rcvhdrentsize, 0, sizeof ( rcvhdrentsize ) );
979 BIT_FILL_1 ( &rcvhdrentsize, Value, ( QIB7322_RECV_HEADER_SIZE >> 2 ) );
980 qib7322_writeq ( qib7322, &rcvhdrentsize,
981 QIB_7322_RcvHdrEntSize_offset );
983 /* Calculate eager array start addresses for each context */
984 qib7322_readq ( qib7322, &rcvegrbase, QIB_7322_RcvEgrBase_offset );
985 egrbase = BIT_GET ( &rcvegrbase, Value );
986 for ( ctx = 0 ; ctx < QIB7322_MAX_PORTS ; ctx++ ) {
987 qib7322->recv_wq[ctx].eager_array = egrbase;
988 qib7322->recv_wq[ctx].eager_entries = eager_array_size_kernel;
989 egrbase += ( eager_array_size_kernel *
990 sizeof ( struct QIB_7322_RcvEgr ) );
992 for ( ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
993 qib7322->recv_wq[ctx].eager_array = egrbase;
994 qib7322->recv_wq[ctx].eager_entries = eager_array_size_user;
995 egrbase += ( eager_array_size_user *
996 sizeof ( struct QIB_7322_RcvEgr ) );
998 for ( ctx = 0 ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
999 DBGC ( qib7322, "QIB7322 %p CTX %d eager array at %lx (%d "
1000 "entries)\n", qib7322, ctx,
1001 qib7322->recv_wq[ctx].eager_array,
1002 qib7322->recv_wq[ctx].eager_entries );
1005 /* Set the BTH QP for Infinipath packets to an unused value */
1006 memset ( &rcvbthqp, 0, sizeof ( rcvbthqp ) );
1007 BIT_FILL_1 ( &rcvbthqp, RcvBTHQP, QIB7322_QP_IDETH );
1008 qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_0_offset );
1009 qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_1_offset );
1011 /* Assign initial credits */
1012 memset ( &rxcreditvl, 0, sizeof ( rxcreditvl ) );
1013 BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL0 );
1014 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1015 QIB_7322_RxCreditVL0_0_offset, 0 );
1016 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1017 QIB_7322_RxCreditVL0_1_offset, 0 );
1018 BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL15 );
1019 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1020 QIB_7322_RxCreditVL0_0_offset, 15 );
1021 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1022 QIB_7322_RxCreditVL0_1_offset, 15 );
1028 * Shut down receive datapath
1030 * @v qib7322 QIB7322 device
1032 static void qib7322_fini_recv ( struct qib7322 *qib7322 __unused ) {
1033 /* Nothing to do; all contexts were already disabled when the
1034 * queue pairs were destroyed
1038 /***************************************************************************
1040 * Completion queue operations
1042 ***************************************************************************
1046 * Create completion queue
1048 * @v ibdev Infiniband device
1049 * @v cq Completion queue
1050 * @ret rc Return status code
1052 static int qib7322_create_cq ( struct ib_device *ibdev,
1053 struct ib_completion_queue *cq ) {
1054 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1057 /* The hardware has no concept of completion queues. We
1058 * simply use the association between CQs and WQs (already
1059 * handled by the IB core) to decide which WQs to poll.
1061 * We do set a CQN, just to avoid confusing debug messages
1065 DBGC ( qib7322, "QIB7322 %p CQN %ld created\n", qib7322, cq->cqn );
1071 * Destroy completion queue
1073 * @v ibdev Infiniband device
1074 * @v cq Completion queue
1076 static void qib7322_destroy_cq ( struct ib_device *ibdev,
1077 struct ib_completion_queue *cq ) {
1078 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1081 DBGC ( qib7322, "QIB7322 %p CQN %ld destroyed\n", qib7322, cq->cqn );
1084 /***************************************************************************
1086 * Queue pair operations
1088 ***************************************************************************
1094 * @v ibdev Infiniband device
1096 * @ret rc Return status code
1098 static int qib7322_create_qp ( struct ib_device *ibdev,
1099 struct ib_queue_pair *qp ) {
1100 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1104 /* Allocate a context and QPN */
1105 if ( ( rc = qib7322_alloc_ctx ( ibdev, qp ) ) != 0 )
1107 ctx = qib7322_ctx ( ibdev, qp );
1109 /* Set work-queue private data pointers */
1110 ib_wq_set_drvdata ( &qp->send, &qib7322->send_wq[ctx] );
1111 ib_wq_set_drvdata ( &qp->recv, &qib7322->recv_wq[ctx] );
1113 /* Create receive work queue */
1114 if ( ( rc = qib7322_create_recv_wq ( ibdev, qp ) ) != 0 )
1115 goto err_create_recv_wq;
1117 /* Create send work queue */
1118 if ( ( rc = qib7322_create_send_wq ( ibdev, qp ) ) != 0 )
1119 goto err_create_send_wq;
1123 qib7322_destroy_send_wq ( ibdev, qp );
1125 qib7322_destroy_recv_wq ( ibdev, qp );
1127 qib7322_free_ctx ( ibdev, qp );
1135 * @v ibdev Infiniband device
1137 * @ret rc Return status code
1139 static int qib7322_modify_qp ( struct ib_device *ibdev,
1140 struct ib_queue_pair *qp ) {
1141 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1143 /* Nothing to do; the hardware doesn't have a notion of queue
1146 DBGC2 ( qib7322, "QIB7322 %p QPN %ld modified\n", qib7322, qp->qpn );
1151 * Destroy queue pair
1153 * @v ibdev Infiniband device
1156 static void qib7322_destroy_qp ( struct ib_device *ibdev,
1157 struct ib_queue_pair *qp ) {
1159 qib7322_destroy_send_wq ( ibdev, qp );
1160 qib7322_destroy_recv_wq ( ibdev, qp );
1161 qib7322_free_ctx ( ibdev, qp );
1164 /***************************************************************************
1166 * Work request operations
1168 ***************************************************************************
1172 * Post send work queue entry
1174 * @v ibdev Infiniband device
1176 * @v dest Destination address vector
1177 * @v iobuf I/O buffer
1178 * @ret rc Return status code
1180 static int qib7322_post_send ( struct ib_device *ibdev,
1181 struct ib_queue_pair *qp,
1182 struct ib_address_vector *dest,
1183 struct io_buffer *iobuf ) {
1184 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1185 struct ib_work_queue *wq = &qp->send;
1186 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1187 struct QIB_7322_SendPbc sendpbc;
1188 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1189 uint8_t header_buf[IB_MAX_HEADER_SIZE];
1190 struct io_buffer headers;
1192 unsigned long start_offset;
1193 unsigned long offset;
1198 /* Allocate send buffer and calculate offset */
1199 send_buf = qib7322_alloc_send_buf ( qib7322, qib7322_wq->send_bufs );
1202 start_offset = offset =
1203 qib7322_send_buffer_offset ( qib7322, qib7322_wq->send_bufs,
1206 /* Store I/O buffer and send buffer index */
1207 assert ( wq->iobufs[qib7322_wq->prod] == NULL );
1208 wq->iobufs[qib7322_wq->prod] = iobuf;
1209 qib7322_wq->used[qib7322_wq->prod] = send_buf;
1211 /* Construct headers */
1212 iob_populate ( &headers, header_buf, 0, sizeof ( header_buf ) );
1213 iob_reserve ( &headers, sizeof ( header_buf ) );
1214 ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), dest );
1216 /* Calculate packet length */
1217 len = ( ( sizeof ( sendpbc ) + iob_len ( &headers ) +
1218 iob_len ( iobuf ) + 3 ) & ~3 );
1220 /* Construct send per-buffer control word */
1221 memset ( &sendpbc, 0, sizeof ( sendpbc ) );
1222 BIT_FILL_3 ( &sendpbc,
1223 LengthP1_toibc, ( ( len >> 2 ) - 1 ),
1225 VL15, ( ( qp->type == IB_QPT_SMI ) ? 1 : 0 ) );
1228 DBG_DISABLE ( DBGLVL_IO );
1229 qib7322_writeq ( qib7322, &sendpbc, offset );
1230 offset += sizeof ( sendpbc );
1233 for ( data = headers.data, frag_len = iob_len ( &headers ) ;
1234 frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1235 qib7322_writel ( qib7322, *data, offset );
1239 for ( data = iobuf->data, frag_len = iob_len ( iobuf ) ;
1240 frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1241 qib7322_writel ( qib7322, *data, offset );
1243 DBG_ENABLE ( DBGLVL_IO );
1245 assert ( ( start_offset + len ) == offset );
1246 DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) posted [%lx,%lx)\n",
1247 qib7322, qp->qpn, send_buf, qib7322_wq->prod,
1248 start_offset, offset );
1250 /* Increment producer counter */
1251 qib7322_wq->prod = ( ( qib7322_wq->prod + 1 ) & ( wq->num_wqes - 1 ) );
1257 * Complete send work queue entry
1259 * @v ibdev Infiniband device
1261 * @v wqe_idx Work queue entry index
1263 static void qib7322_complete_send ( struct ib_device *ibdev,
1264 struct ib_queue_pair *qp,
1265 unsigned int wqe_idx ) {
1266 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1267 struct ib_work_queue *wq = &qp->send;
1268 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1269 struct io_buffer *iobuf;
1270 unsigned int send_buf;
1272 /* Parse completion */
1273 send_buf = qib7322_wq->used[wqe_idx];
1274 DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) complete\n",
1275 qib7322, qp->qpn, send_buf, wqe_idx );
1277 /* Complete work queue entry */
1278 iobuf = wq->iobufs[wqe_idx];
1279 assert ( iobuf != NULL );
1280 ib_complete_send ( ibdev, qp, iobuf, 0 );
1281 wq->iobufs[wqe_idx] = NULL;
1283 /* Free send buffer */
1284 qib7322_free_send_buf ( qib7322, qib7322_wq->send_bufs, send_buf );
1288 * Poll send work queue
1290 * @v ibdev Infiniband device
1293 static void qib7322_poll_send_wq ( struct ib_device *ibdev,
1294 struct ib_queue_pair *qp ) {
1295 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1296 struct ib_work_queue *wq = &qp->send;
1297 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1298 unsigned int send_buf;
1300 /* Look for completions */
1301 while ( wq->fill ) {
1303 /* Check to see if send buffer has completed */
1304 send_buf = qib7322_wq->used[qib7322_wq->cons];
1305 if ( qib7322_send_buf_in_use ( qib7322, send_buf ) )
1308 /* Complete this buffer */
1309 qib7322_complete_send ( ibdev, qp, qib7322_wq->cons );
1311 /* Increment consumer counter */
1312 qib7322_wq->cons = ( ( qib7322_wq->cons + 1 ) &
1313 ( wq->num_wqes - 1 ) );
1318 * Post receive work queue entry
1320 * @v ibdev Infiniband device
1322 * @v iobuf I/O buffer
1323 * @ret rc Return status code
1325 static int qib7322_post_recv ( struct ib_device *ibdev,
1326 struct ib_queue_pair *qp,
1327 struct io_buffer *iobuf ) {
1328 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1329 struct ib_work_queue *wq = &qp->recv;
1330 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1331 struct QIB_7322_RcvEgr rcvegr;
1332 struct QIB_7322_scalar rcvegrindexhead;
1333 unsigned int ctx = qib7322_ctx ( ibdev, qp );
1336 unsigned int wqe_idx;
1337 unsigned int bufsize;
1340 addr = virt_to_bus ( iobuf->data );
1341 len = iob_tailroom ( iobuf );
1342 if ( addr & ( QIB7322_EAGER_BUFFER_ALIGN - 1 ) ) {
1343 DBGC ( qib7322, "QIB7322 %p QPN %ld misaligned RX buffer "
1344 "(%08lx)\n", qib7322, qp->qpn, addr );
1347 if ( len != QIB7322_RECV_PAYLOAD_SIZE ) {
1348 DBGC ( qib7322, "QIB7322 %p QPN %ld wrong RX buffer size "
1349 "(%zd)\n", qib7322, qp->qpn, len );
1353 /* Calculate eager producer index and WQE index */
1354 wqe_idx = ( qib7322_wq->eager_prod & ( wq->num_wqes - 1 ) );
1355 assert ( wq->iobufs[wqe_idx] == NULL );
1357 /* Store I/O buffer */
1358 wq->iobufs[wqe_idx] = iobuf;
1360 /* Calculate buffer size */
1361 switch ( QIB7322_RECV_PAYLOAD_SIZE ) {
1362 case 2048: bufsize = QIB7322_EAGER_BUFFER_2K; break;
1363 case 4096: bufsize = QIB7322_EAGER_BUFFER_4K; break;
1364 case 8192: bufsize = QIB7322_EAGER_BUFFER_8K; break;
1365 case 16384: bufsize = QIB7322_EAGER_BUFFER_16K; break;
1366 case 32768: bufsize = QIB7322_EAGER_BUFFER_32K; break;
1367 case 65536: bufsize = QIB7322_EAGER_BUFFER_64K; break;
1368 default: linker_assert ( 0, invalid_rx_payload_size );
1369 bufsize = QIB7322_EAGER_BUFFER_NONE;
1372 /* Post eager buffer */
1373 memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1374 BIT_FILL_2 ( &rcvegr,
1375 Addr, ( addr >> 11 ),
1377 qib7322_writeq_array8b ( qib7322, &rcvegr, qib7322_wq->eager_array,
1378 qib7322_wq->eager_prod );
1379 DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x(%04x) posted "
1380 "[%lx,%lx)\n", qib7322, qp->qpn, qib7322_wq->eager_prod,
1381 wqe_idx, addr, ( addr + len ) );
1383 /* Increment producer index */
1384 qib7322_wq->eager_prod = ( ( qib7322_wq->eager_prod + 1 ) &
1385 ( qib7322_wq->eager_entries - 1 ) );
1387 /* Update head index */
1388 memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
1389 BIT_FILL_1 ( &rcvegrindexhead,
1390 Value, ( ( qib7322_wq->eager_prod + 1 ) &
1391 ( qib7322_wq->eager_entries - 1 ) ) );
1392 qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
1393 QIB_7322_RcvEgrIndexHead0_offset, ctx );
1399 * Complete receive work queue entry
1401 * @v ibdev Infiniband device
1403 * @v header_offs Header offset
1405 static void qib7322_complete_recv ( struct ib_device *ibdev,
1406 struct ib_queue_pair *qp,
1407 unsigned int header_offs ) {
1408 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1409 struct ib_work_queue *wq = &qp->recv;
1410 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1411 struct QIB_7322_RcvHdrFlags *rcvhdrflags;
1412 struct QIB_7322_RcvEgr rcvegr;
1413 struct io_buffer headers;
1414 struct io_buffer *iobuf;
1415 struct ib_queue_pair *intended_qp;
1416 struct ib_address_vector dest;
1417 struct ib_address_vector source;
1418 unsigned int rcvtype;
1419 unsigned int pktlen;
1420 unsigned int egrindex;
1421 unsigned int useegrbfr;
1422 unsigned int iberr, mkerr, tiderr, khdrerr, mtuerr;
1423 unsigned int lenerr, parityerr, vcrcerr, icrcerr;
1425 unsigned int hdrqoffset;
1426 unsigned int header_len;
1427 unsigned int padded_payload_len;
1428 unsigned int wqe_idx;
1433 /* RcvHdrFlags are at the end of the header entry */
1434 rcvhdrflags = ( qib7322_wq->header + header_offs +
1435 QIB7322_RECV_HEADER_SIZE - sizeof ( *rcvhdrflags ) );
1436 rcvtype = BIT_GET ( rcvhdrflags, RcvType );
1437 pktlen = ( BIT_GET ( rcvhdrflags, PktLen ) << 2 );
1438 egrindex = BIT_GET ( rcvhdrflags, EgrIndex );
1439 useegrbfr = BIT_GET ( rcvhdrflags, UseEgrBfr );
1440 hdrqoffset = ( BIT_GET ( rcvhdrflags, HdrqOffset ) << 2 );
1441 iberr = BIT_GET ( rcvhdrflags, IBErr );
1442 mkerr = BIT_GET ( rcvhdrflags, MKErr );
1443 tiderr = BIT_GET ( rcvhdrflags, TIDErr );
1444 khdrerr = BIT_GET ( rcvhdrflags, KHdrErr );
1445 mtuerr = BIT_GET ( rcvhdrflags, MTUErr );
1446 lenerr = BIT_GET ( rcvhdrflags, LenErr );
1447 parityerr = BIT_GET ( rcvhdrflags, ParityErr );
1448 vcrcerr = BIT_GET ( rcvhdrflags, VCRCErr );
1449 icrcerr = BIT_GET ( rcvhdrflags, ICRCErr );
1450 header_len = ( QIB7322_RECV_HEADER_SIZE - hdrqoffset -
1451 sizeof ( *rcvhdrflags ) );
1452 padded_payload_len = ( pktlen - header_len - 4 /* ICRC */ );
1453 err = ( iberr | mkerr | tiderr | khdrerr | mtuerr |
1454 lenerr | parityerr | vcrcerr | icrcerr );
1455 /* IB header is placed immediately before RcvHdrFlags */
1456 iob_populate ( &headers, ( ( ( void * ) rcvhdrflags ) - header_len ),
1457 header_len, header_len );
1459 /* Dump diagnostic information */
1460 DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x%s hdr %d type %d len "
1461 "%d(%d+%d+4)%s%s%s%s%s%s%s%s%s%s%s\n", qib7322, qp->qpn,
1462 egrindex, ( useegrbfr ? "" : "(unused)" ),
1463 ( header_offs / QIB7322_RECV_HEADER_SIZE ),
1464 rcvtype, pktlen, header_len, padded_payload_len,
1465 ( err ? " [Err" : "" ), ( iberr ? " IB" : "" ),
1466 ( mkerr ? " MK" : "" ), ( tiderr ? " TID" : "" ),
1467 ( khdrerr ? " KHdr" : "" ), ( mtuerr ? " MTU" : "" ),
1468 ( lenerr ? " Len" : "" ), ( parityerr ? " Parity" : ""),
1469 ( vcrcerr ? " VCRC" : "" ), ( icrcerr ? " ICRC" : "" ),
1470 ( err ? "]" : "" ) );
1471 DBGCP_HDA ( qib7322, hdrqoffset, headers.data,
1472 ( header_len + sizeof ( *rcvhdrflags ) ) );
1474 /* Parse header to generate address vector */
1475 qp0 = ( qp->qpn == 0 );
1477 if ( ( rc = ib_pull ( ibdev, &headers, ( qp0 ? &intended_qp : NULL ),
1478 &payload_len, &dest, &source ) ) != 0 ) {
1479 DBGC ( qib7322, "QIB7322 %p could not parse headers: %s\n",
1480 qib7322, strerror ( rc ) );
1483 if ( ! intended_qp )
1486 /* Complete this buffer and any skipped buffers. Note that
1487 * when the hardware runs out of buffers, it will repeatedly
1488 * report the same buffer (the tail) as a TID error, and that
1489 * it also has a habit of sometimes skipping over several
1494 /* If we have caught up to the producer counter, stop.
1495 * This will happen when the hardware first runs out
1496 * of buffers and starts reporting TID errors against
1497 * the eager buffer it wants to use next.
1499 if ( qib7322_wq->eager_cons == qib7322_wq->eager_prod )
1502 /* If we have caught up to where we should be after
1503 * completing this egrindex, stop. We phrase the test
1504 * this way to avoid completing the entire ring when
1505 * we receive the same egrindex twice in a row.
1507 if ( ( qib7322_wq->eager_cons ==
1508 ( ( egrindex + 1 ) & ( qib7322_wq->eager_entries - 1 ))))
1511 /* Identify work queue entry and corresponding I/O
1514 wqe_idx = ( qib7322_wq->eager_cons & ( wq->num_wqes - 1 ) );
1515 iobuf = wq->iobufs[wqe_idx];
1516 assert ( iobuf != NULL );
1517 wq->iobufs[wqe_idx] = NULL;
1519 /* Complete the eager buffer */
1520 if ( qib7322_wq->eager_cons == egrindex ) {
1521 /* Completing the eager buffer described in
1522 * this header entry.
1524 iob_put ( iobuf, payload_len );
1525 rc = ( err ? -EIO : ( useegrbfr ? 0 : -ECANCELED ) );
1526 /* Redirect to target QP if necessary */
1527 if ( qp != intended_qp ) {
1528 DBGC2 ( qib7322, "QIB7322 %p redirecting QPN "
1530 qib7322, qp->qpn, intended_qp->qpn );
1531 /* Compensate for incorrect fill levels */
1533 intended_qp->recv.fill++;
1535 ib_complete_recv ( ibdev, intended_qp, &dest, &source,
1538 /* Completing on a skipped-over eager buffer */
1539 ib_complete_recv ( ibdev, qp, &dest, &source, iobuf,
1543 /* Clear eager buffer */
1544 memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1545 qib7322_writeq_array8b ( qib7322, &rcvegr,
1546 qib7322_wq->eager_array,
1547 qib7322_wq->eager_cons );
1549 /* Increment consumer index */
1550 qib7322_wq->eager_cons = ( ( qib7322_wq->eager_cons + 1 ) &
1551 ( qib7322_wq->eager_entries - 1 ) );
1556 * Poll receive work queue
1558 * @v ibdev Infiniband device
1561 static void qib7322_poll_recv_wq ( struct ib_device *ibdev,
1562 struct ib_queue_pair *qp ) {
1563 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1564 struct ib_work_queue *wq = &qp->recv;
1565 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1566 struct QIB_7322_RcvHdrHead0 rcvhdrhead;
1567 unsigned int ctx = qib7322_ctx ( ibdev, qp );
1568 unsigned int header_prod;
1570 /* Check for received packets */
1571 header_prod = ( BIT_GET ( &qib7322_wq->header_prod, Value ) << 2 );
1572 if ( header_prod == qib7322_wq->header_cons )
1575 /* Process all received packets */
1576 while ( qib7322_wq->header_cons != header_prod ) {
1578 /* Complete the receive */
1579 qib7322_complete_recv ( ibdev, qp, qib7322_wq->header_cons );
1581 /* Increment the consumer offset */
1582 qib7322_wq->header_cons += QIB7322_RECV_HEADER_SIZE;
1583 qib7322_wq->header_cons %= QIB7322_RECV_HEADERS_SIZE;
1585 /* QIB7322 has only one send buffer per port for VL15,
1586 * which almost always leads to send buffer exhaustion
1587 * and dropped MADs. Mitigate this by refusing to
1588 * process more than one VL15 MAD per poll, which will
1589 * enforce interleaved TX/RX polls.
1591 if ( qp->type == IB_QPT_SMI )
1595 /* Update consumer offset */
1596 memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
1597 BIT_FILL_2 ( &rcvhdrhead,
1598 RcvHeadPointer, ( qib7322_wq->header_cons >> 2 ),
1600 qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
1601 QIB_7322_RcvHdrHead0_offset, ctx );
1605 * Poll completion queue
1607 * @v ibdev Infiniband device
1608 * @v cq Completion queue
1610 static void qib7322_poll_cq ( struct ib_device *ibdev,
1611 struct ib_completion_queue *cq ) {
1612 struct ib_work_queue *wq;
1614 /* Poll associated send and receive queues */
1615 list_for_each_entry ( wq, &cq->work_queues, list ) {
1616 if ( wq->is_send ) {
1617 qib7322_poll_send_wq ( ibdev, wq->qp );
1619 qib7322_poll_recv_wq ( ibdev, wq->qp );
1624 /***************************************************************************
1628 ***************************************************************************
1634 * @v ibdev Infiniband device
1636 static void qib7322_poll_eq ( struct ib_device *ibdev ) {
1637 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1638 struct QIB_7322_ErrStatus_0 errstatus;
1639 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1641 /* Check for and clear status bits */
1642 DBG_DISABLE ( DBGLVL_IO );
1643 qib7322_readq_port ( qib7322, &errstatus,
1644 QIB_7322_ErrStatus_0_offset, port );
1645 if ( errstatus.u.qwords[0] ) {
1646 DBGC ( qib7322, "QIB7322 %p port %d status %08x%08x\n", qib7322,
1647 port, errstatus.u.dwords[1], errstatus.u.dwords[0] );
1648 qib7322_writeq_port ( qib7322, &errstatus,
1649 QIB_7322_ErrClear_0_offset, port );
1651 DBG_ENABLE ( DBGLVL_IO );
1653 /* Check for link status changes */
1654 if ( BIT_GET ( &errstatus, IBStatusChanged ) )
1655 qib7322_link_state_changed ( ibdev );
1658 /***************************************************************************
1660 * Infiniband link-layer operations
1662 ***************************************************************************
1666 * Determine supported link speeds
1668 * @v qib7322 QIB7322 device
1669 * @ret supported Supported link speeds
1671 static unsigned int qib7322_link_speed_supported ( struct qib7322 *qib7322,
1672 unsigned int port ) {
1673 struct QIB_7322_feature_mask features;
1674 struct QIB_7322_Revision revision;
1675 unsigned int supported;
1676 unsigned int boardid;
1678 /* Read the active feature mask */
1679 qib7322_readq ( qib7322, &features,
1680 QIB_7322_active_feature_mask_offset );
1683 supported = BIT_GET ( &features, Port0_Link_Speed_Supported );
1686 supported = BIT_GET ( &features, Port1_Link_Speed_Supported );
1689 DBGC ( qib7322, "QIB7322 %p port %d is invalid\n",
1695 /* Apply hacks for specific board IDs */
1696 qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
1697 boardid = BIT_GET ( &revision, BoardID );
1698 switch ( boardid ) {
1699 case QIB7322_BOARD_QMH7342 :
1700 DBGC2 ( qib7322, "QIB7322 %p is a QMH7342; forcing QDR-only\n",
1702 supported = IB_LINK_SPEED_QDR;
1709 DBGC2 ( qib7322, "QIB7322 %p port %d %s%s%s%s\n", qib7322, port,
1710 ( supported ? "supports" : "disabled" ),
1711 ( ( supported & IB_LINK_SPEED_SDR ) ? " SDR" : "" ),
1712 ( ( supported & IB_LINK_SPEED_DDR ) ? " DDR" : "" ),
1713 ( ( supported & IB_LINK_SPEED_QDR ) ? " QDR" : "" ) );
1718 * Initialise Infiniband link
1720 * @v ibdev Infiniband device
1721 * @ret rc Return status code
1723 static int qib7322_open ( struct ib_device *ibdev ) {
1724 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1725 struct QIB_7322_IBCCtrlA_0 ibcctrla;
1726 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1729 qib7322_readq_port ( qib7322, &ibcctrla,
1730 QIB_7322_IBCCtrlA_0_offset, port );
1731 BIT_SET ( &ibcctrla, IBLinkEn, 1 );
1732 qib7322_writeq_port ( qib7322, &ibcctrla,
1733 QIB_7322_IBCCtrlA_0_offset, port );
1739 * Close Infiniband link
1741 * @v ibdev Infiniband device
1743 static void qib7322_close ( struct ib_device *ibdev ) {
1744 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1745 struct QIB_7322_IBCCtrlA_0 ibcctrla;
1746 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1749 qib7322_readq_port ( qib7322, &ibcctrla,
1750 QIB_7322_IBCCtrlA_0_offset, port );
1751 BIT_SET ( &ibcctrla, IBLinkEn, 0 );
1752 qib7322_writeq_port ( qib7322, &ibcctrla,
1753 QIB_7322_IBCCtrlA_0_offset, port );
1756 /***************************************************************************
1758 * Multicast group operations
1760 ***************************************************************************
1764 * Attach to multicast group
1766 * @v ibdev Infiniband device
1768 * @v gid Multicast GID
1769 * @ret rc Return status code
1771 static int qib7322_mcast_attach ( struct ib_device *ibdev,
1772 struct ib_queue_pair *qp,
1773 union ib_gid *gid ) {
1774 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1783 * Detach from multicast group
1785 * @v ibdev Infiniband device
1787 * @v gid Multicast GID
1789 static void qib7322_mcast_detach ( struct ib_device *ibdev,
1790 struct ib_queue_pair *qp,
1791 union ib_gid *gid ) {
1792 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1799 /** QIB7322 Infiniband operations */
1800 static struct ib_device_operations qib7322_ib_operations = {
1801 .create_cq = qib7322_create_cq,
1802 .destroy_cq = qib7322_destroy_cq,
1803 .create_qp = qib7322_create_qp,
1804 .modify_qp = qib7322_modify_qp,
1805 .destroy_qp = qib7322_destroy_qp,
1806 .post_send = qib7322_post_send,
1807 .post_recv = qib7322_post_recv,
1808 .poll_cq = qib7322_poll_cq,
1809 .poll_eq = qib7322_poll_eq,
1810 .open = qib7322_open,
1811 .close = qib7322_close,
1812 .mcast_attach = qib7322_mcast_attach,
1813 .mcast_detach = qib7322_mcast_detach,
1814 .set_port_info = qib7322_set_port_info,
1815 .set_pkey_table = qib7322_set_pkey_table,
1818 /***************************************************************************
1820 * I2C bus operations
1822 ***************************************************************************
1825 /** QIB7322 I2C bit to GPIO mappings */
1826 static unsigned int qib7322_i2c_bits[] = {
1827 [I2C_BIT_SCL] = ( 1 << QIB7322_GPIO_SCL ),
1828 [I2C_BIT_SDA] = ( 1 << QIB7322_GPIO_SDA ),
1832 * Read QIB7322 I2C line status
1834 * @v basher Bit-bashing interface
1835 * @v bit_id Bit number
1836 * @ret zero Input is a logic 0
1837 * @ret non-zero Input is a logic 1
1839 static int qib7322_i2c_read_bit ( struct bit_basher *basher,
1840 unsigned int bit_id ) {
1841 struct qib7322 *qib7322 =
1842 container_of ( basher, struct qib7322, i2c.basher );
1843 struct QIB_7322_EXTStatus extstatus;
1844 unsigned int status;
1846 DBG_DISABLE ( DBGLVL_IO );
1848 qib7322_readq ( qib7322, &extstatus, QIB_7322_EXTStatus_offset );
1849 status = ( BIT_GET ( &extstatus, GPIOIn ) & qib7322_i2c_bits[bit_id] );
1851 DBG_ENABLE ( DBGLVL_IO );
1857 * Write QIB7322 I2C line status
1859 * @v basher Bit-bashing interface
1860 * @v bit_id Bit number
1861 * @v data Value to write
1863 static void qib7322_i2c_write_bit ( struct bit_basher *basher,
1864 unsigned int bit_id, unsigned long data ) {
1865 struct qib7322 *qib7322 =
1866 container_of ( basher, struct qib7322, i2c.basher );
1867 struct QIB_7322_EXTCtrl extctrl;
1868 struct QIB_7322_GPIO gpioout;
1869 unsigned int bit = qib7322_i2c_bits[bit_id];
1870 unsigned int outputs = 0;
1871 unsigned int output_enables = 0;
1873 DBG_DISABLE ( DBGLVL_IO );
1875 /* Read current GPIO mask and outputs */
1876 qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1877 qib7322_readq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1879 /* Update outputs and output enables. I2C lines are tied
1880 * high, so we always set the output to 0 and use the output
1881 * enable to control the line.
1883 output_enables = BIT_GET ( &extctrl, GPIOOe );
1884 output_enables = ( ( output_enables & ~bit ) | ( ~data & bit ) );
1885 outputs = BIT_GET ( &gpioout, GPIO );
1886 outputs = ( outputs & ~bit );
1887 BIT_SET ( &extctrl, GPIOOe, output_enables );
1888 BIT_SET ( &gpioout, GPIO, outputs );
1890 /* Write the output enable first; that way we avoid logic
1893 qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1894 qib7322_writeq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1897 DBG_ENABLE ( DBGLVL_IO );
1900 /** QIB7322 I2C bit-bashing interface operations */
1901 static struct bit_basher_operations qib7322_i2c_basher_ops = {
1902 .read = qib7322_i2c_read_bit,
1903 .write = qib7322_i2c_write_bit,
1907 * Initialise QIB7322 I2C subsystem
1909 * @v qib7322 QIB7322 device
1910 * @ret rc Return status code
1912 static int qib7322_init_i2c ( struct qib7322 *qib7322 ) {
1913 static int try_eeprom_address[] = { 0x51, 0x50 };
1917 /* Initialise bus */
1918 if ( ( rc = init_i2c_bit_basher ( &qib7322->i2c,
1919 &qib7322_i2c_basher_ops ) ) != 0 ) {
1920 DBGC ( qib7322, "QIB7322 %p could not initialise I2C bus: %s\n",
1921 qib7322, strerror ( rc ) );
1925 /* Probe for devices */
1926 for ( i = 0 ; i < ( sizeof ( try_eeprom_address ) /
1927 sizeof ( try_eeprom_address[0] ) ) ; i++ ) {
1928 init_i2c_eeprom ( &qib7322->eeprom, try_eeprom_address[i] );
1929 if ( ( rc = i2c_check_presence ( &qib7322->i2c.i2c,
1930 &qib7322->eeprom ) ) == 0 ) {
1931 DBGC2 ( qib7322, "QIB7322 %p found EEPROM at %02x\n",
1932 qib7322, try_eeprom_address[i] );
1937 DBGC ( qib7322, "QIB7322 %p could not find EEPROM\n", qib7322 );
1942 * Read EEPROM parameters
1944 * @v qib7322 QIB7322 device
1945 * @ret rc Return status code
1947 static int qib7322_read_eeprom ( struct qib7322 *qib7322 ) {
1948 struct i2c_interface *i2c = &qib7322->i2c.i2c;
1949 union ib_guid *guid = &qib7322->guid;
1953 if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1954 QIB7322_EEPROM_GUID_OFFSET, guid->bytes,
1955 sizeof ( *guid ) ) ) != 0 ) {
1956 DBGC ( qib7322, "QIB7322 %p could not read GUID: %s\n",
1957 qib7322, strerror ( rc ) );
1960 DBGC2 ( qib7322, "QIB7322 %p has GUID " IB_GUID_FMT "\n",
1961 qib7322, IB_GUID_ARGS ( guid ) );
1963 /* Read serial number (debug only) */
1965 uint8_t serial[QIB7322_EEPROM_SERIAL_SIZE + 1];
1967 serial[ sizeof ( serial ) - 1 ] = '\0';
1968 if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1969 QIB7322_EEPROM_SERIAL_OFFSET, serial,
1970 ( sizeof ( serial ) - 1 ) ) ) != 0 ) {
1971 DBGC ( qib7322, "QIB7322 %p could not read serial: "
1972 "%s\n", qib7322, strerror ( rc ) );
1975 DBGC2 ( qib7322, "QIB7322 %p has serial number \"%s\"\n",
1982 /***************************************************************************
1984 * Advanced High-performance Bus (AHB) access
1986 ***************************************************************************
1990 * Wait for AHB transaction to complete
1992 * @v qib7322 QIB7322 device
1993 * @ret rc Return status code
1995 static int qib7322_ahb_wait ( struct qib7322 *qib7322 ) {
1996 struct QIB_7322_ahb_transaction_reg transaction;
1999 /* Wait for Ready bit to be asserted */
2000 for ( i = 0 ; i < QIB7322_AHB_MAX_WAIT_US ; i++ ) {
2001 qib7322_readq ( qib7322, &transaction,
2002 QIB_7322_ahb_transaction_reg_offset );
2003 if ( BIT_GET ( &transaction, ahb_rdy ) )
2008 DBGC ( qib7322, "QIB7322 %p timed out waiting for AHB transaction\n",
2014 * Request ownership of the AHB
2016 * @v qib7322 QIB7322 device
2017 * @v location AHB location
2018 * @ret rc Return status code
2020 static int qib7322_ahb_request ( struct qib7322 *qib7322,
2021 unsigned int location ) {
2022 struct QIB_7322_ahb_access_ctrl access;
2025 /* Request ownership */
2026 memset ( &access, 0, sizeof ( access ) );
2027 BIT_FILL_2 ( &access,
2029 sw_sel_ahb_trgt, QIB7322_AHB_LOC_TARGET ( location ) );
2030 qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2032 /* Wait for ownership to be granted */
2033 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 ) {
2034 DBGC ( qib7322, "QIB7322 %p could not obtain AHB ownership: "
2035 "%s\n", qib7322, strerror ( rc ) );
2043 * Release ownership of the AHB
2045 * @v qib7322 QIB7322 device
2047 static void qib7322_ahb_release ( struct qib7322 *qib7322 ) {
2048 struct QIB_7322_ahb_access_ctrl access;
2050 memset ( &access, 0, sizeof ( access ) );
2051 qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2057 * @v qib7322 QIB7322 device
2058 * @v location AHB location
2059 * @v data Data to read
2060 * @ret rc Return status code
2062 * You must have already acquired ownership of the AHB.
2064 static int qib7322_ahb_read ( struct qib7322 *qib7322, unsigned int location,
2066 struct QIB_7322_ahb_transaction_reg xact;
2069 /* Avoid returning uninitialised data on error */
2072 /* Initiate transaction */
2073 memset ( &xact, 0, sizeof ( xact ) );
2075 ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2076 write_not_read, 0 );
2077 qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2079 /* Wait for transaction to complete */
2080 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2083 /* Read transaction data */
2084 qib7322_readq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2085 *data = BIT_GET ( &xact, ahb_data );
2090 * Write data via AHB
2092 * @v qib7322 QIB7322 device
2093 * @v location AHB location
2094 * @v data Data to write
2095 * @ret rc Return status code
2097 * You must have already acquired ownership of the AHB.
2099 static int qib7322_ahb_write ( struct qib7322 *qib7322, unsigned int location,
2101 struct QIB_7322_ahb_transaction_reg xact;
2104 /* Initiate transaction */
2105 memset ( &xact, 0, sizeof ( xact ) );
2107 ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2110 qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2112 /* Wait for transaction to complete */
2113 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2120 * Read/modify/write AHB register
2122 * @v qib7322 QIB7322 device
2123 * @v location AHB location
2124 * @v value Value to set
2125 * @v mask Mask to apply to old value
2126 * @ret rc Return status code
2128 static int qib7322_ahb_mod_reg ( struct qib7322 *qib7322, unsigned int location,
2129 uint32_t value, uint32_t mask ) {
2134 DBG_DISABLE ( DBGLVL_IO );
2137 assert ( ( value & mask ) == value );
2139 /* Acquire bus ownership */
2140 if ( ( rc = qib7322_ahb_request ( qib7322, location ) ) != 0 )
2143 /* Read existing value */
2144 if ( ( rc = qib7322_ahb_read ( qib7322, location, &old_value ) ) != 0 )
2148 new_value = ( ( old_value & ~mask ) | value );
2149 DBGCP ( qib7322, "QIB7322 %p AHB %x %#08x => %#08x\n",
2150 qib7322, location, old_value, new_value );
2151 if ( ( rc = qib7322_ahb_write ( qib7322, location, new_value ) ) != 0 )
2156 qib7322_ahb_release ( qib7322 );
2158 DBG_ENABLE ( DBGLVL_IO );
2163 * Read/modify/write AHB register across all ports and channels
2165 * @v qib7322 QIB7322 device
2166 * @v reg AHB register
2167 * @v value Value to set
2168 * @v mask Mask to apply to old value
2169 * @ret rc Return status code
2171 static int qib7322_ahb_mod_reg_all ( struct qib7322 *qib7322, unsigned int reg,
2172 uint32_t value, uint32_t mask ) {
2174 unsigned int channel;
2175 unsigned int location;
2178 for ( port = 0 ; port < QIB7322_MAX_PORTS ; port++ ) {
2179 for ( channel = 0 ; channel < QIB7322_MAX_WIDTH ; channel++ ) {
2180 location = QIB7322_AHB_LOCATION ( port, channel, reg );
2181 if ( ( rc = qib7322_ahb_mod_reg ( qib7322, location,
2182 value, mask ) ) != 0 )
2189 /***************************************************************************
2191 * Infiniband SerDes initialisation
2193 ***************************************************************************
2197 * Initialise the IB SerDes
2199 * @v qib7322 QIB7322 device
2200 * @ret rc Return status code
2202 static int qib7322_init_ib_serdes ( struct qib7322 *qib7322 ) {
2203 struct QIB_7322_IBCCtrlA_0 ibcctrla;
2204 struct QIB_7322_IBCCtrlB_0 ibcctrlb;
2205 struct QIB_7322_IBPCSConfig_0 ibpcsconfig;
2207 /* Configure sensible defaults for IBC */
2208 memset ( &ibcctrla, 0, sizeof ( ibcctrla ) );
2209 BIT_FILL_5 ( &ibcctrla, /* Tuning values taken from Linux driver */
2210 FlowCtrlPeriod, 0x03,
2211 FlowCtrlWaterMark, 0x05,
2212 MaxPktLen, ( ( QIB7322_RECV_HEADER_SIZE +
2213 QIB7322_RECV_PAYLOAD_SIZE +
2214 4 /* ICRC */ ) >> 2 ),
2215 PhyerrThreshold, 0xf,
2216 OverrunThreshold, 0xf );
2217 qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_0_offset );
2218 qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_1_offset );
2220 /* Force SDR only to avoid needing all the DDR tuning,
2221 * Mellanox compatibility hacks etc. SDR is plenty for
2222 * boot-time operation.
2224 qib7322_readq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2225 BIT_SET ( &ibcctrlb, IB_ENHANCED_MODE, 0 );
2226 BIT_SET ( &ibcctrlb, SD_SPEED_SDR, 1 );
2227 BIT_SET ( &ibcctrlb, SD_SPEED_DDR, 0 );
2228 BIT_SET ( &ibcctrlb, SD_SPEED_QDR, 0 );
2229 BIT_SET ( &ibcctrlb, IB_NUM_CHANNELS, 1 ); /* 4X only */
2230 BIT_SET ( &ibcctrlb, IB_LANE_REV_SUPPORTED, 0 );
2231 BIT_SET ( &ibcctrlb, HRTBT_ENB, 0 );
2232 BIT_SET ( &ibcctrlb, HRTBT_AUTO, 0 );
2233 qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2234 qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_1_offset );
2237 qib7322_ahb_mod_reg_all ( qib7322, 2, 0, 0x00000e00UL );
2239 /* Bring XGXS out of reset */
2240 memset ( &ibpcsconfig, 0, sizeof ( ibpcsconfig ) );
2241 qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_0_offset );
2242 qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_1_offset );
2247 /***************************************************************************
2249 * PCI layer interface
2251 ***************************************************************************
2257 * @v qib7322 QIB7322 device
2259 * @ret rc Return status code
2261 static void qib7322_reset ( struct qib7322 *qib7322, struct pci_device *pci ) {
2262 struct QIB_7322_Control control;
2263 struct pci_config_backup backup;
2265 /* Back up PCI configuration space */
2266 pci_backup ( pci, &backup, NULL );
2269 memset ( &control, 0, sizeof ( control ) );
2270 BIT_FILL_1 ( &control, SyncReset, 1 );
2271 qib7322_writeq ( qib7322, &control, QIB_7322_Control_offset );
2273 /* Wait for reset to complete */
2276 /* Restore PCI configuration space */
2277 pci_restore ( pci, &backup, NULL );
2285 * @ret rc Return status code
2287 static int qib7322_probe ( struct pci_device *pci ) {
2288 struct qib7322 *qib7322;
2289 struct QIB_7322_Revision revision;
2290 struct ib_device *ibdev;
2291 unsigned int link_speed_supported;
2295 /* Allocate QIB7322 device */
2296 qib7322 = zalloc ( sizeof ( *qib7322 ) );
2299 goto err_alloc_qib7322;
2301 pci_set_drvdata ( pci, qib7322 );
2303 /* Fix up PCI device */
2304 adjust_pci_device ( pci );
2307 qib7322->regs = ioremap ( pci->membase, QIB7322_BAR0_SIZE );
2308 DBGC2 ( qib7322, "QIB7322 %p has BAR at %08lx\n",
2309 qib7322, pci->membase );
2312 qib7322_reset ( qib7322, pci );
2314 /* Print some general data */
2315 qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
2316 DBGC2 ( qib7322, "QIB7322 %p board %02lx v%ld.%ld.%ld.%ld\n", qib7322,
2317 BIT_GET ( &revision, BoardID ),
2318 BIT_GET ( &revision, R_SW ),
2319 BIT_GET ( &revision, R_Arch ),
2320 BIT_GET ( &revision, R_ChipRevMajor ),
2321 BIT_GET ( &revision, R_ChipRevMinor ) );
2323 /* Initialise I2C subsystem */
2324 if ( ( rc = qib7322_init_i2c ( qib7322 ) ) != 0 )
2327 /* Read EEPROM parameters */
2328 if ( ( rc = qib7322_read_eeprom ( qib7322 ) ) != 0 )
2329 goto err_read_eeprom;
2331 /* Initialise send datapath */
2332 if ( ( rc = qib7322_init_send ( qib7322 ) ) != 0 )
2335 /* Initialise receive datapath */
2336 if ( ( rc = qib7322_init_recv ( qib7322 ) ) != 0 )
2339 /* Initialise the IB SerDes */
2340 if ( ( rc = qib7322_init_ib_serdes ( qib7322 ) ) != 0 )
2341 goto err_init_ib_serdes;
2343 /* Allocate Infiniband devices */
2344 for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2345 link_speed_supported =
2346 qib7322_link_speed_supported ( qib7322, i );
2347 if ( ! link_speed_supported )
2349 ibdev = alloc_ibdev ( 0 );
2352 goto err_alloc_ibdev;
2354 qib7322->ibdev[i] = ibdev;
2355 ibdev->dev = &pci->dev;
2356 ibdev->op = &qib7322_ib_operations;
2357 ibdev->port = ( QIB7322_PORT_BASE + i );
2358 ibdev->link_width_enabled = ibdev->link_width_supported =
2359 IB_LINK_WIDTH_4X; /* 1x does not work */
2360 ibdev->link_speed_enabled = ibdev->link_speed_supported =
2361 IB_LINK_SPEED_SDR; /* to avoid need for link tuning */
2362 memcpy ( &ibdev->node_guid, &qib7322->guid,
2363 sizeof ( ibdev->node_guid ) );
2364 memcpy ( &ibdev->gid.s.guid, &qib7322->guid,
2365 sizeof ( ibdev->gid.s.guid ) );
2366 assert ( ( ibdev->gid.s.guid.bytes[7] & i ) == 0 );
2367 ibdev->gid.s.guid.bytes[7] |= i;
2368 ib_set_drvdata ( ibdev, qib7322 );
2371 /* Register Infiniband devices */
2372 for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2373 if ( ! qib7322->ibdev[i] )
2375 if ( ( rc = register_ibdev ( qib7322->ibdev[i] ) ) != 0 ) {
2376 DBGC ( qib7322, "QIB7322 %p port %d could not register "
2377 "IB device: %s\n", qib7322, i, strerror ( rc ) );
2378 goto err_register_ibdev;
2384 i = QIB7322_MAX_PORTS;
2386 for ( i-- ; i >= 0 ; i-- ) {
2387 if ( qib7322->ibdev[i] )
2388 unregister_ibdev ( qib7322->ibdev[i] );
2390 i = QIB7322_MAX_PORTS;
2392 for ( i-- ; i >= 0 ; i-- )
2393 ibdev_put ( qib7322->ibdev[i] );
2395 qib7322_fini_send ( qib7322 );
2397 qib7322_fini_recv ( qib7322 );
2411 static void qib7322_remove ( struct pci_device *pci ) {
2412 struct qib7322 *qib7322 = pci_get_drvdata ( pci );
2415 for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- ) {
2416 if ( qib7322->ibdev[i] )
2417 unregister_ibdev ( qib7322->ibdev[i] );
2419 for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- )
2420 ibdev_put ( qib7322->ibdev[i] );
2421 qib7322_fini_send ( qib7322 );
2422 qib7322_fini_recv ( qib7322 );
2426 static struct pci_device_id qib7322_nics[] = {
2427 PCI_ROM ( 0x1077, 0x7322, "iba7322", "IBA7322 QDR InfiniBand HCA", 0 ),
2430 struct pci_driver qib7322_driver __pci_driver = {
2431 .ids = qib7322_nics,
2432 .id_count = ( sizeof ( qib7322_nics ) / sizeof ( qib7322_nics[0] ) ),
2433 .probe = qib7322_probe,
2434 .remove = qib7322_remove,