5 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 FILE_LICENCE ( GPL2_OR_LATER );
28 * QLogic Linda Infiniband HCA
32 #define BITOPS_LITTLE_ENDIAN
33 #include <ipxe/bitops.h>
34 #include "qib_7220_regs.h"
38 /** A Linda GPIO register */
39 struct QIB_7220_GPIO_pb {
40 pseudo_bit_t GPIO[16];
41 pseudo_bit_t Reserved[48];
43 struct QIB_7220_GPIO {
44 PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIO_pb );
47 /** A Linda general scalar register */
48 struct QIB_7220_scalar_pb {
49 pseudo_bit_t Value[64];
51 struct QIB_7220_scalar {
52 PSEUDO_BIT_STRUCT ( struct QIB_7220_scalar_pb );
55 /** Linda send per-buffer control word */
56 struct QIB_7220_SendPbc_pb {
57 pseudo_bit_t LengthP1_toibc[11];
58 pseudo_bit_t Reserved1[4];
59 pseudo_bit_t LengthP1_trigger[11];
60 pseudo_bit_t Reserved2[3];
61 pseudo_bit_t TestEbp[1];
64 pseudo_bit_t Reserved3[31];
67 struct QIB_7220_SendPbc {
68 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendPbc_pb );
71 /** Linda send buffer availability */
72 struct QIB_7220_SendBufAvail_pb {
73 pseudo_bit_t InUseCheck[144][2];
74 pseudo_bit_t Reserved[32];
76 struct QIB_7220_SendBufAvail {
77 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail_pb );
80 /** DMA alignment for send buffer availability */
81 #define LINDA_SENDBUFAVAIL_ALIGN 64
83 /** A Linda eager receive descriptor */
84 struct QIB_7220_RcvEgr_pb {
85 pseudo_bit_t Addr[37];
86 pseudo_bit_t BufSize[3];
87 pseudo_bit_t Reserved[24];
89 struct QIB_7220_RcvEgr {
90 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvEgr_pb );
93 /** Linda receive header flags */
94 struct QIB_7220_RcvHdrFlags_pb {
95 pseudo_bit_t PktLen[11];
96 pseudo_bit_t RcvType[3];
97 pseudo_bit_t SoftB[1];
98 pseudo_bit_t SoftA[1];
99 pseudo_bit_t EgrIndex[12];
100 pseudo_bit_t Reserved1[3];
101 pseudo_bit_t UseEgrBfr[1];
102 pseudo_bit_t RcvSeq[4];
103 pseudo_bit_t HdrqOffset[11];
104 pseudo_bit_t Reserved2[8];
105 pseudo_bit_t IBErr[1];
106 pseudo_bit_t MKErr[1];
107 pseudo_bit_t TIDErr[1];
108 pseudo_bit_t KHdrErr[1];
109 pseudo_bit_t MTUErr[1];
110 pseudo_bit_t LenErr[1];
111 pseudo_bit_t ParityErr[1];
112 pseudo_bit_t VCRCErr[1];
113 pseudo_bit_t ICRCErr[1];
115 struct QIB_7220_RcvHdrFlags {
116 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrFlags_pb );
119 /** Linda memory BAR size */
120 #define LINDA_BAR0_SIZE 0x400000
122 /** Linda I2C SCL line GPIO number */
123 #define LINDA_GPIO_SCL 0
125 /** Linda I2C SDA line GPIO number */
126 #define LINDA_GPIO_SDA 1
128 /** GUID offset within EEPROM */
129 #define LINDA_EEPROM_GUID_OFFSET 3
131 /** GUID size within EEPROM */
132 #define LINDA_EEPROM_GUID_SIZE 8
134 /** Board serial number offset within EEPROM */
135 #define LINDA_EEPROM_SERIAL_OFFSET 12
137 /** Board serial number size within EEPROM */
138 #define LINDA_EEPROM_SERIAL_SIZE 12
140 /** Maximum number of send buffers used
142 * This is a policy decision. Must be less than or equal to the total
143 * number of send buffers supported by the hardware (128).
145 #define LINDA_MAX_SEND_BUFS 32
147 /** Linda send buffer size */
148 #define LINDA_SEND_BUF_SIZE 4096
150 /** Number of contexts (including kernel context)
152 * This is a policy decision. Must be 5, 9 or 17.
154 #define LINDA_NUM_CONTEXTS 5
156 /** PortCfg values for different numbers of contexts */
158 LINDA_PORTCFG_5CTX = 0,
159 LINDA_PORTCFG_9CTX = 1,
160 LINDA_PORTCFG_17CTX = 2,
163 /** PortCfg values for different numbers of contexts */
164 #define LINDA_EAGER_ARRAY_SIZE_5CTX_0 2048
165 #define LINDA_EAGER_ARRAY_SIZE_5CTX_OTHER 4096
166 #define LINDA_EAGER_ARRAY_SIZE_9CTX_0 2048
167 #define LINDA_EAGER_ARRAY_SIZE_9CTX_OTHER 2048
168 #define LINDA_EAGER_ARRAY_SIZE_17CTX_0 2048
169 #define LINDA_EAGER_ARRAY_SIZE_17CTX_OTHER 1024
171 /** Eager buffer required alignment */
172 #define LINDA_EAGER_BUFFER_ALIGN 2048
174 /** Eager buffer size encodings */
175 enum linda_eager_buffer_size {
176 LINDA_EAGER_BUFFER_NONE = 0,
177 LINDA_EAGER_BUFFER_2K = 1,
178 LINDA_EAGER_BUFFER_4K = 2,
179 LINDA_EAGER_BUFFER_8K = 3,
180 LINDA_EAGER_BUFFER_16K = 4,
181 LINDA_EAGER_BUFFER_32K = 5,
182 LINDA_EAGER_BUFFER_64K = 6,
185 /** Number of RX headers per context
187 * This is a policy decision.
189 #define LINDA_RECV_HEADER_COUNT 8
191 /** Maximum size of each RX header
193 * This is a policy decision. Must be divisible by 4.
195 #define LINDA_RECV_HEADER_SIZE 96
197 /** Total size of an RX header ring */
198 #define LINDA_RECV_HEADERS_SIZE \
199 ( LINDA_RECV_HEADER_SIZE * LINDA_RECV_HEADER_COUNT )
201 /** RX header alignment */
202 #define LINDA_RECV_HEADERS_ALIGN 64
206 * This is a policy decision. Must be a valid eager buffer size.
208 #define LINDA_RECV_PAYLOAD_SIZE 2048
210 /** QPN used for Infinipath Packets
212 * This is a policy decision. Must have bit 0 clear. Must not be a
213 * QPN that we will use.
215 #define LINDA_QP_IDETH 0xdead0
217 /** Maximum time for wait for external parallel bus request, in us */
218 #define LINDA_EPB_REQUEST_MAX_WAIT_US 500
220 /** Maximum time for wait for external parallel bus transaction, in us */
221 #define LINDA_EPB_XACT_MAX_WAIT_US 500
223 /** Linda external parallel bus chip selects */
224 #define LINDA_EPB_CS_SERDES 1
225 #define LINDA_EPB_CS_UC 2
227 /** Linda external parallel bus read/write operations */
228 #define LINDA_EPB_WRITE 0
229 #define LINDA_EPB_READ 1
231 /** Linda external parallel bus register addresses */
232 #define LINDA_EPB_ADDRESS( _channel, _element, _reg ) \
233 ( (_element) | ( (_channel) << 4 ) | ( (_reg) << 9 ) )
234 #define LINDA_EPB_ADDRESS_CHANNEL( _address ) ( ( (_address) >> 4 ) & 0x1f )
235 #define LINDA_EPB_ADDRESS_ELEMENT( _address ) ( ( (_address) >> 0 ) & 0x0f )
236 #define LINDA_EPB_ADDRESS_REG( _address ) ( ( (_address) >> 9 ) & 0x3f )
238 /** Linda external parallel bus locations
240 * The location is used by the driver to encode both the chip select
241 * and the EPB address.
243 #define LINDA_EPB_LOC( _cs, _channel, _element, _reg) \
244 ( ( (_cs) << 16 ) | LINDA_EPB_ADDRESS ( _channel, _element, _reg ) )
245 #define LINDA_EPB_LOC_ADDRESS( _loc ) ( (_loc) & 0xffff )
246 #define LINDA_EPB_LOC_CS( _loc ) ( (_loc) >> 16 )
248 /** Linda external parallel bus microcontroller register addresses */
249 #define LINDA_EPB_UC_CHANNEL 6
250 #define LINDA_EPB_UC_LOC( _reg ) \
251 LINDA_EPB_LOC ( LINDA_EPB_CS_UC, LINDA_EPB_UC_CHANNEL, 0, (_reg) )
252 #define LINDA_EPB_UC_CTL LINDA_EPB_UC_LOC ( 0 )
253 #define LINDA_EPB_UC_CTL_WRITE 1
254 #define LINDA_EPB_UC_CTL_READ 2
255 #define LINDA_EPB_UC_ADDR_LO LINDA_EPB_UC_LOC ( 2 )
256 #define LINDA_EPB_UC_ADDR_HI LINDA_EPB_UC_LOC ( 3 )
257 #define LINDA_EPB_UC_DATA LINDA_EPB_UC_LOC ( 4 )
258 #define LINDA_EPB_UC_CHUNK_SIZE 64
260 extern uint8_t linda_ib_fw[8192];
262 /** Maximum time to wait for "trim done" signal, in ms */
263 #define LINDA_TRIM_DONE_MAX_WAIT_MS 1000
265 /** Linda link states */
266 enum linda_link_state {
267 LINDA_LINK_STATE_DOWN = 0,
268 LINDA_LINK_STATE_INIT = 1,
269 LINDA_LINK_STATE_ARM = 2,
270 LINDA_LINK_STATE_ACTIVE = 3,
271 LINDA_LINK_STATE_ACT_DEFER = 4,
274 /** Maximum time to wait for link state changes, in us */
275 #define LINDA_LINK_STATE_MAX_WAIT_US 20
277 #endif /* _LINDA_H */