1 /******************************************************************************
2 * Copyright (c) 2013 IBM Corporation
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
13 * Definitions for XHCI Controller - Revision 1.0 (5/21/10)
23 #define BIT(x) (1 << x)
25 /* 5.3 Host Controller Capability Registers
28 struct xhci_cap_regs {
36 #define XHCI_HCCPARAMS_CSZ BIT(2)
37 #define XHCI_HCCPARAMS_XECP(x) ((x & 0xFFFF0000) >> 16)
40 } __attribute__ ((packed));
42 /* USB 3.0: Section 7 and 7.2 */
43 #define XHCI_XECP_CAP_ID(x) ((x & 0xF))
44 #define XHCI_XECP_CAP_SP 2
45 #define XHCI_XECP_CAP_SP_MN(x) ((x & 0xFF0000) >> 16)
46 #define XHCI_XECP_CAP_SP_MJ(x) ((x & 0xFF000000) >> 24)
47 #define XHCI_XECP_CAP_SP_PC(x) ((x & 0xFF00) >> 8)
48 #define XHCI_XECP_CAP_SP_PO(x) (x & 0xFF)
49 #define XHCI_XECP_NEXT_PTR(x) ((x & 0xFF00) >> 8)
51 /* Table 27: Host Controller USB Port Register Set */
52 struct xhci_port_regs {
54 #define PORTSC_CCS BIT(0)
55 #define PORTSC_PED BIT(1)
56 #define PORTSC_OCA BIT(3)
57 #define PORTSC_PR BIT(4)
58 #define PORTSC_PLS_MASK (0xF << 5)
59 #define PORTSC_PLS_U0 0
60 #define PORTSC_PLS_U1 1
61 #define PORTSC_PLS_U2 2
62 #define PORTSC_PLS_U3 3
63 #define PORTSC_PLS_DISABLED 4
64 #define PORTSC_PLS_RXDETECT 5
65 #define PORTSC_PLS_INACTIVE 6
66 #define PORTSC_PLS_POLLING 7
67 #define PORTSC_PLS_RECOVERY 8
68 #define PORTSC_PLS_HOTRESET 9
69 #define PORTSC_PLS_COMP_MODE 10
70 #define PORTSC_PLS_TEST_MODE 11
71 #define PORTSC_PLS_RESUME 15
72 #define PORTSC_PP BIT(9)
73 #define PORTSC_PS_MASK (0xF << 10)
74 #define PORTSC_PIC_MASK (0x3 << 14)
75 #define PORTSC_LWS BIT(16)
76 #define PORTSC_CSC BIT(17)
77 #define PORTSC_PEC BIT(18)
78 #define PORTSC_WRC BIT(19)
79 #define PORTSC_OCC BIT(20)
80 #define PORTSC_PRC BIT(21)
81 #define PORTSC_PLC BIT(22)
82 #define PORTSC_CEC BIT(23)
83 #define PORTSC_CAS BIT(24)
84 #define PORTSC_WCE BIT(25)
85 #define PORTSC_WDE BIT(26)
86 #define PORTSC_WOE BIT(27)
87 #define PORTSC_DR BIT(30)
88 #define PORTSC_WPR BIT(31)
93 } __attribute__ ((packed));
105 struct port_state ps_array_usb2[] = {
106 {1, 0, 0, 0, PORTSC_PLS_U0, "ERROR"}
109 struct port_state ps_array_usb3[] = {
110 {0, 0, 0, 0, PORTSC_PLS_DISABLED, "Powered-OFF"},
111 {1, 0, 0, 0, PORTSC_PLS_POLLING, "Polling"},
112 {1, 0, 0, 0, PORTSC_PLS_U0, "Polling"},
113 {1, 0, 0, 0, PORTSC_PLS_RXDETECT, "*** Disconnected ***"},
114 {1, 0, 0, 0, PORTSC_PLS_DISABLED, "Disabled"},
115 {1, 0, 0, 0, PORTSC_PLS_INACTIVE, "Error"},
116 {1, 0, 0, 0, PORTSC_PLS_TEST_MODE,"Loopback"},
117 {1, 0, 0, 0, PORTSC_PLS_COMP_MODE,"Compliancek"},
118 {1, 1, 0, 1, PORTSC_PLS_U0, "****** Reset ******"},
119 {1, 1, 1, 0, PORTSC_PLS_U0, "****** Enabled ******"},
122 /* 5.4 Host Controller Operational Registers
125 struct xhci_op_regs {
127 #define XHCI_USBCMD_RS BIT(0)
128 #define XHCI_USBCMD_HCRST BIT(1)
131 #define XHCI_USBSTS_HCH BIT(0)
132 #define XHCI_USBSTS_CNR BIT(11)
135 uint8_t reserved[8]; /* 0C - 13 */
136 uint32_t dnctrl; /* Device notification control */
137 uint64_t crcr; /* Command ring control */
138 #define XHCI_CRCR_CRP_MASK 0xFFFFFFFFFFFFFFC0
139 #define XHCI_CRCR_CRR BIT(3)
140 #define XHCI_CRCR_CRP_SIZE 4096
142 uint8_t reserved1[16]; /* 20 - 2F */
143 uint64_t dcbaap; /* Device Context Base Address Array Pointer */
144 #define XHCI_DCBAAP_MAX_SIZE 2048
146 uint32_t config; /* Configure */
147 #define XHCI_CONFIG_MAX_SLOT 4
149 uint8_t reserved2[964]; /* 3C - 3FF */
150 /* USB Port register set */
151 #define XHCI_PORT_MAX 256
152 struct xhci_port_regs prs[XHCI_PORT_MAX];
153 } __attribute__ ((packed));
156 * 5.5.2 Interrupter Register Set
157 * Table 42: Interrupter Registers
159 struct xhci_int_regs {
163 #define XHCI_ERST_SIZE_MASK 0xFFFF
166 #define XHCI_ERST_ADDR_MASK (~(0x3FUL))
168 #define XHCI_ERDP_MASK (~(0xFUL))
169 } __attribute__ ((packed));
171 /* 5.5 Host Controller Runtime Registers */
172 struct xhci_run_regs {
173 uint32_t mfindex; /* microframe index */
174 uint8_t reserved[28];
175 #define XHCI_IRS_MAX 1024
176 struct xhci_int_regs irs[XHCI_IRS_MAX];
177 } __attribute__ ((packed));
179 /* 5.6 Doorbell Registers*/
180 struct xhci_db_regs {
182 } __attribute__ ((packed));
184 #define COMP_SUCCESS 1
186 #define TRB_SLOT_ID(x) (((x) & (0xFF << 24)) >> 24)
187 #define TRB_CMD_SLOT_ID(x) ((x & 0xFF) << 24)
188 #define TRB_TYPE(x) (((x) & (0x3F << 10)) >> 10)
189 #define TRB_CMD_TYPE(x) ((x & 0x3F) << 10)
190 #define TRB_STATUS(x) (((x) & (0xFF << 24)) >> 24)
191 #define TRB_ADDR_LOW(x) ((uint32_t)((uint64_t)(x)))
192 #define TRB_ADDR_HIGH(x) ((uint32_t)((uint64_t)(x) >> 32))
193 #define TRB_TRT(x) (((x) & 0x3) << 16 )
194 #define TRB_DIR_IN BIT(16)
195 #define TRB_IOC BIT(5)
196 #define TRB_IDT BIT(6)
198 #define TRB_CYCLE_STATE BIT(0)
200 struct xhci_transfer_trb {
204 } __attribute__ ((packed));
206 struct xhci_link_trb {
210 } __attribute__ ((packed));
213 struct xhci_event_trb {
217 } __attribute__ ((packed));
220 #define TRB_SETUP_STAGE 2
221 #define TRB_DATA_STAGE 3
222 #define TRB_STATUS_STAGE 4
225 #define TRB_EVENT_DATA 7
227 #define TRB_ENABLE_SLOT 9
228 #define TRB_DISABLE_SLOT 10
229 #define TRB_ADDRESS_DEV 11
230 #define TRB_CONFIG_EP 12
231 #define TRB_EVAL_CNTX 13
232 #define TRB_TRANSFER_EVENT 32
233 #define TRB_CMD_COMPLETION 33
234 #define TRB_PORT_STATUS 34
236 struct xhci_command_trb {
238 }__attribute__ ((packed));
241 struct xhci_event_trb event;
242 struct xhci_transfer_trb xfer;
243 struct xhci_command_trb cmd;
244 struct xhci_link_trb link;
255 union xhci_trb *trbs;
256 struct xhci_seg *next;
261 uint32_t cycle_state;
262 enum xhci_seg_type type;
265 #define XHCI_TRB_SIZE 16
266 #define XHCI_EVENT_TRBS_SIZE 4096
267 #define XHCI_CONTROL_TRBS_SIZE 4096
268 #define XHCI_DATA_TRBS_SIZE 4096
269 #define XHCI_ERST_NUM_SEGS 1
271 #define XHCI_MAX_BULK_SIZE 0xF000
273 struct xhci_erst_entry {
277 } __attribute__ ((packed));
280 struct xhci_erst_entry *entries;
282 uint32_t num_segs; /* number of segments */
285 struct xhci_control_ctx {
288 uint32_t reserved[6];
289 } __attribute__ ((packed));
291 struct xhci_slot_ctx {
293 #define SLOT_SPEED_FS BIT(20)
294 #define SLOT_SPEED_LS BIT(21)
295 #define SLOT_SPEED_HS BIT(22)
296 #define SLOT_SPEED_SS BIT(23)
297 #define LAST_CONTEXT(x) (x << 27)
300 #define ROOT_HUB_PORT(x) ((x & 0xff) << 16)
304 #define USB_DEV_ADDRESS(x) (x & 0xFFU)
305 #define SLOT_STATE(x) ((x >> 27) & 0x1FU)
306 #define SLOT_STATE_DIS_ENA 0
307 #define SLOT_STATE_DEFAULT 1
308 #define SLOT_STATE_ADDRESSED 2
309 #define SLOT_STATE_CONFIGURED 3
312 uint32_t reserved[4];
313 } __attribute__ ((packed));
318 #define MAX_PACKET_SIZE(x) (((x) & 0xFFFF) << 16)
319 #define MAX_BURST(x) (((x) & 0xFF) << 8)
320 #define EP_TYPE(x) (((x) & 0x07) << 3)
321 #define EP_ISOC_OUT 1
322 #define EP_BULK_OUT 2
329 #define ERROR_COUNT(x) (((x) & 0x03) << 1)
333 uint32_t reserved[3];
334 } __attribute__ ((packed));
338 #define XHCI_CTX_TYPE_DEVICE 0x1
339 #define XHCI_CTX_TYPE_INPUT 0x2
342 #define XHCI_CTX_BUF_SIZE 4096
349 struct xhci_ctx in_ctx;
350 struct xhci_ctx out_ctx;
351 struct xhci_seg control;
352 struct xhci_seg bulk_in;
353 struct xhci_seg bulk_out;
358 struct xhci_cap_regs *cap_regs;
359 struct xhci_op_regs *op_regs;
360 struct xhci_run_regs *run_regs;
361 struct xhci_db_regs *db_regs;
362 struct usb_hcd_dev *hcidev;
363 struct xhci_dev xdevs[XHCI_CONFIG_MAX_SLOT + 1];
364 struct usb_pipe *freelist;
365 struct usb_pipe *end;
368 struct xhci_seg ering;
369 struct xhci_seg crseg;
370 struct xhci_erst erst;
376 #define XHCI_PIPE_POOL_SIZE 4096
382 struct usb_pipe pipe;
383 struct xhci_seg *seg;
386 #endif /* USB_XHCI_H */