1 /******************************************************************************
2 * Copyright (c) 2007, 2011, 2013 IBM Corporation
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
13 * e1000 Gigabit Ethernet Driver for SLOF
16 * PCI/PCI-X Family of Gigabit Ethernet Controllers
17 * Software Developer's Manual Rev. 3.3, Intel, December 2006
23 #include <byteorder.h>
25 #include <netdriver.h>
30 ******************************************************************************
32 #define E1K_NUM_RX_DESC 128 // do not change
33 #define E1K_NUM_TX_DESC 128 // do not change
34 #define E1K_BUF_SIZE 2096 // do not change
36 #define NUM_MAC_ADDR 16 // number of mac address register pairs
37 #define EEPROM_MAC_OFFS 0 // position of mac address in eeprom
41 ******************************************************************************
45 uint64_t m_devmsk_u64;
50 * e1k common data structures
54 * transmit buffer descriptor
57 uint64_t m_buffer_u64;
64 } __attribute__ ((packed)) e1k_tx_desc_st;
68 * receive buffer descriptor
71 uint64_t m_buffer_u64;
77 } __attribute__ ((packed)) e1k_rx_desc_st;
80 * e1k device structure
84 * device identification mask
86 uint64_t m_device_u64;
89 * memory mapped base address of NIC
91 uint64_t m_baseaddr_u64;
94 * transmit & receive rings
95 * must be 16 byte aligned
97 e1k_tx_desc_st m_tx_ring_pst[E1K_NUM_TX_DESC];
98 e1k_rx_desc_st m_rx_ring_pst[E1K_NUM_RX_DESC];
101 * transmit & receive buffers
102 * must be 16 byte aligned
104 uint8_t m_tx_buffer_pu08[E1K_NUM_TX_DESC][E1K_BUF_SIZE];
105 uint8_t m_rx_buffer_pu08[E1K_NUM_RX_DESC][E1K_BUF_SIZE];
108 * next receive descriptor index
110 uint32_t m_rx_next_u32;
113 * command register storage
115 uint16_t m_com_r_u16;
118 * padding to make the size of the structure a multiple of 16 byte
120 uint16_t m_pad16_u16;
121 uint64_t m_pad64_u32;
123 } __attribute__ ((packed)) e1k_st;
127 ******************************************************************************
129 #define E1K_82540 ((uint64_t) 0x1)
130 #define E1K_82541 ((uint64_t) 0x2)
131 #define E1K_82544 ((uint64_t) 0x4)
132 #define E1K_82545 ((uint64_t) 0x8)
133 #define E1K_82546 ((uint64_t) 0x10)
134 #define E1K_82547 ((uint64_t) 0x20)
136 #define IS_82541 ((m_e1k.m_device_u64 & E1K_82541) != 0)
137 #define IS_82546 ((m_e1k.m_device_u64 & E1K_82546) != 0)
138 #define IS_82547 ((m_e1k.m_device_u64 & E1K_82547) != 0)
140 static const e1k_dev_t e1k_dev[] = {
141 { 0x1019, E1K_82547, "82547EI/GI Copper" },
142 { 0x101A, E1K_82547, "82547EI Mobile" },
143 { 0x1010, E1K_82546, "52546EB Copper, Dual Port" },
144 { 0x1012, E1K_82546, "82546EB Fiber, Dual Port" },
145 /* { 0x101D, E1K_82546, "82546EB Copper, Quad Port" }, */
146 { 0x1079, E1K_82546, "82546GB Copper, Dual Port" },
147 { 0x107A, E1K_82546, "82546GB Fiber, Dual Port" },
148 { 0x107B, E1K_82546, "82546GB SerDes, Dual Port" },
149 { 0x100F, E1K_82545, "82545EM Copper" },
150 { 0x1011, E1K_82545, "82545EM Fiber" },
151 { 0x1026, E1K_82545, "82545GM Copper" },
152 { 0x1027, E1K_82545, "82545GM Fiber" },
153 { 0x1028, E1K_82545, "82545GM SerDes" },
154 { 0x1107, E1K_82544, "82544EI Copper" },
155 { 0x1112, E1K_82544, "82544GC Copper" },
156 { 0x1013, E1K_82541, "82541EI Copper" },
157 { 0x1018, E1K_82541, "82541EI Mobile" },
158 { 0x1076, E1K_82541, "82541GI Copper" },
159 { 0x1077, E1K_82541, "82541GI Mobile" },
160 { 0x1078, E1K_82541, "82541ER Copper" },
161 { 0x107C, E1K_82541, "82541PI" },
162 { 0x1015, E1K_82540, "82540EM Mobile" },
163 { 0x1016, E1K_82540, "82540EP Mobile" },
164 { 0x1017, E1K_82540, "82540EP Desktop" },
165 { 0x100E, E1K_82540, "82540EM Desktop" },
171 ******************************************************************************
173 static e1k_st m_e1k __attribute__ ((aligned(16)));
174 static long dma_offset;
178 ******************************************************************************
181 check_driver(uint16_t vendor_id, uint16_t device_id);
183 static int e1k_init(net_driver_t *driver);
184 static int e1k_term(void);
185 static int e1k_xmit(char *f_buffer_pc, int f_len_i);
186 static int e1k_receive(char *f_buffer_pc, int f_len_i);
189 * Translate virtual to "physical" address, ie. an address
190 * which can be used for DMA transfers.
195 return (uint64_t)addr + dma_offset;
199 dma2virt(uint64_t addr)
201 return (void *)(addr - dma_offset);
205 * local inline functions for e1k register access
206 ******************************************************************************
209 e1k_rd32(uint16_t f_offs_u16)
210 { // caution: shall only be used after initialization!
211 return bswap_32(rd32(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16));
216 e1k_rd16(uint16_t f_offs_u16)
217 { // caution: shall only be used after initialization!
218 return bswap_16(rd16(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16));
223 e1k_rd08(uint16_t f_offs_u16)
224 { // caution: shall only be used after initialization!
225 return rd08(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16);
229 e1k_wr32(uint16_t f_offs_u16, uint32_t f_val_u32)
230 { // caution: shall only be used after initialization!
231 wr32(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16, bswap_32(f_val_u32));
236 e1k_wr16(uint16_t f_offs_u16, uint16_t f_val_u16)
237 { // caution: shall only be used after initialization!
238 wr16(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16, bswap_16(f_val_u16));
243 e1k_wr08(uint16_t f_offs_u16, uint8_t f_val_u08)
244 { // caution: shall only be used after initialization!
245 wr08(m_e1k.m_baseaddr_u64 + (uint64_t) f_offs_u16, f_val_u08);
249 e1k_setb32(uint16_t f_offs_u16, uint32_t f_mask_u32)
253 v = e1k_rd32(f_offs_u16);
255 e1k_wr32(f_offs_u16, v);
260 e1k_setb16(uint16_t f_offs_u16, uint16_t f_mask_u16)
263 v = e1k_rd16(f_offs_u16);
265 e1k_wr16(f_offs_u16, v);
270 e1k_setb08(uint16_t f_offs_u16, uint8_t f_mask_u08)
273 v = e1k_rd08(f_offs_u16);
275 e1k_wr08(f_offs_u16, v);
279 e1k_clrb32(uint16_t f_offs_u16, uint32_t f_mask_u32)
283 v = e1k_rd32(f_offs_u16);
285 e1k_wr32(f_offs_u16, v);
290 e1k_clrb16(uint16_t f_offs_u16, uint16_t f_mask_u16)
294 v = e1k_rd16(f_offs_u16);
296 e1k_wr16(f_offs_u16, v);
301 e1k_clrb08(uint16_t f_offs_u16, uint8_t f_mask_u08)
304 v = e1k_rd08(f_offs_u16);
306 e1k_wr08(f_offs_u16, v);
310 e1k_eep_rd16(uint8_t f_offs_u08, uint16_t *f_data_pu16)
317 if(IS_82541 || IS_82547) {
326 * initiate eeprom read
328 e1k_wr32(EERD, ((uint32_t) f_offs_u08 << addr_shft) | // address
329 BIT32(0)); // start read
332 * wait for read done bit to be set
337 ((v & BIT32(done_shft)) == 0)) {
345 if ((v & BIT32(done_shft)) == 0) {
352 *f_data_pu16 = (uint16_t) ((v >> 16) & 0xffff);
358 * ring initialization
361 e1k_init_receiver(void)
367 * disable receiver for initialization
372 * clear receive desciptors and setup buffer pointers
374 for (i = 0; i < E1K_NUM_RX_DESC; i++) {
375 memset((uint8_t *) &m_e1k.m_rx_ring_pst[i], 0,
376 sizeof(e1k_rx_desc_st));
379 m_e1k.m_rx_ring_pst[i].m_buffer_u64 =
380 bswap_64(virt2dma(&m_e1k.m_rx_buffer_pu08[i][0]));
384 * initialize previously received index
386 m_e1k.m_rx_next_u32 = 0;
389 * setup the base address and the length of the rx descriptor ring
391 addr = virt2dma(&m_e1k.m_rx_ring_pst[0]);
392 e1k_wr32(RDBAH, (uint32_t) ((uint64_t) addr >> 32));
393 e1k_wr32(RDBAL, (uint32_t) ((uint64_t) addr & 0xffffffff));
394 e1k_wr32(RDLEN, E1K_NUM_RX_DESC * sizeof(e1k_rx_desc_st));
397 * setup the rx head and tail descriptor indices
400 e1k_wr32(RDT, E1K_NUM_RX_DESC - 1);
403 * setup the receive delay timer register
408 * setup the receive control register
410 e1k_wr32(RCTL, BIT32( 1) | // enable receiver
411 BIT32( 4) | // enable multicast reception
412 BIT32(15)); // broadcast accept mode
414 // no buffer extension
418 e1k_init_transmitter(void)
424 * clear transmit desciptors and setup buffer pointers
426 for (i = 0; i < E1K_NUM_TX_DESC; i++) {
427 memset((uint8_t *) &m_e1k.m_tx_ring_pst[i], 0,
428 sizeof(e1k_tx_desc_st));
431 m_e1k.m_tx_ring_pst[i].m_buffer_u64 =
432 bswap_64(virt2dma(&m_e1k.m_tx_buffer_pu08[i][0]));
436 * setup the base address and the length of the tx descriptor ring
438 addr = virt2dma(&m_e1k.m_tx_ring_pst[0]);
439 e1k_wr32(TDBAH, (uint32_t) ((uint64_t) addr >> 32));
440 e1k_wr32(TDBAL, (uint32_t) ((uint64_t) addr & 0xffffffff));
441 e1k_wr32(TDLEN, E1K_NUM_TX_DESC * sizeof(e1k_tx_desc_st));
444 * setup the rx head and tail descriptor indices
450 * initialize the transmit control register
452 e1k_wr32(TCTL, BIT32(1) | // enable transmitter
453 BIT32(3) | // pad short packets
454 ((uint32_t) 0x0f << 4) | // collision threshhold
455 ((uint32_t) 0x40 << 12)); // collision distance
459 e1k_mac_init(uint8_t *f_mac_pu08)
467 * Use MAC address from device tree if possible
469 for (i = 0, v = 0; i < 6; i++) {
470 v += (uint32_t) f_mac_pu08[i];
475 * use passed mac address for transmission to nic
477 l_al_u32 = ((uint32_t) f_mac_pu08[3] << 24);
478 l_al_u32 |= ((uint32_t) f_mac_pu08[2] << 16);
479 l_al_u32 |= ((uint32_t) f_mac_pu08[1] << 8);
480 l_al_u32 |= ((uint32_t) f_mac_pu08[0] << 0);
481 l_ah_u32 = ((uint32_t) f_mac_pu08[5] << 8);
482 l_ah_u32 |= ((uint32_t) f_mac_pu08[4] << 0);
485 * read mac address from eeprom
487 uint16_t w[3]; // 3 16 bit words from eeprom
489 for (i = 0; i < 3; i++) {
490 if (e1k_eep_rd16(EEPROM_MAC_OFFS + i, &w[i]) != 0) {
491 printf("Failed to read MAC address from EEPROM!\n");
497 * invert the least significant bit for 82546 dual port
498 * if the second device is in use (remember word is byteswapped)
501 ((e1k_rd32(STATUS) & BIT32(2)) != 0)) {
502 w[2] ^= (uint16_t) 0x100;
506 * store mac address for transmission to nic
508 l_ah_u32 = ((uint32_t) w[2] << 0);
509 l_al_u32 = ((uint32_t) w[1] << 16);
510 l_al_u32 |= ((uint32_t) w[0] << 0);
514 * mac address in eeprom is stored byteswapped
516 f_mac_pu08[1] = (uint8_t) ((w[0] >> 8) & 0xff);
517 f_mac_pu08[0] = (uint8_t) ((w[0] >> 0) & 0xff);
518 f_mac_pu08[3] = (uint8_t) ((w[1] >> 8) & 0xff);
519 f_mac_pu08[2] = (uint8_t) ((w[1] >> 0) & 0xff);
520 f_mac_pu08[5] = (uint8_t) ((w[2] >> 8) & 0xff);
521 f_mac_pu08[4] = (uint8_t) ((w[2] >> 0) & 0xff);
525 * insert mac address in receive address register
528 e1k_wr32(RAL0, l_al_u32);
529 e1k_wr32(RAH0, l_ah_u32 | BIT32(31));
532 * clear remaining receive address registers
534 for (i = 1; i < NUM_MAC_ADDR; i++) {
535 e1k_wr32(RAL0 + i * sizeof(uint64_t), 0);
536 e1k_wr32(RAH0 + i * sizeof(uint64_t), 0);
545 ******************************************************************************
552 e1k_receive(char *f_buffer_pc, int f_len_i)
554 uint32_t l_rdh_u32 = e1k_rd32(RDH); // this includes needed dummy read
559 #ifdef E1K_SHOW_RCV_DATA
565 * check whether new packets have arrived
567 if (m_e1k.m_rx_next_u32 == l_rdh_u32) {
572 * get a pointer to the next rx descriptor for ease of use
574 rx = &m_e1k.m_rx_ring_pst[m_e1k.m_rx_next_u32];
577 * check whether the descriptor done bit is set
579 if ((rx->m_sta_u08 & 0x1) == 0) {
584 * get the length of the packet, throw away checksum
586 l_ret_i = (int) bswap_16(rx->m_len_u16) - (int) 4;
591 memcpy((uint8_t *) f_buffer_pc, dma2virt(bswap_64(rx->m_buffer_u64)),
595 #if defined(E1K_SHOW_RCV) || defined(E1K_SHOW_RCV_DATA)
596 printf("e1k: %d bytes received\n", l_ret_i);
599 #ifdef E1K_SHOW_RCV_DATA
600 for (i = 0; i < l_ret_i; i++) {
602 if ((i & 0x1f) == 0) {
606 printf("%02X ", f_buffer_pc[i]);
614 * clear descriptor for reusage, but leave buffer pointer untouched
616 memset((uint8_t *) &rx->m_len_u16, 0,
617 sizeof(e1k_rx_desc_st) - sizeof(uint64_t));
621 * write new tail pointer
623 e1k_wr32(RDT, m_e1k.m_rx_next_u32);
626 * update next receive index
628 m_e1k.m_rx_next_u32 = (m_e1k.m_rx_next_u32 + 1) & (E1K_NUM_RX_DESC - 1);
634 e1k_xmit(char *f_buffer_pc, int f_len_i)
636 uint32_t l_tdh_u32 = e1k_rd32(TDH);
637 uint32_t l_tdt_u32 = e1k_rd32(TDT);
638 uint32_t l_pre_u32 = (l_tdh_u32 + (E1K_NUM_TX_DESC - 1)) &
639 (E1K_NUM_TX_DESC - 1);
641 #if defined(E1K_DEBUG) && defined(E1K_SHOW_XMIT_DATA)
646 * check for available buffers
648 if (l_pre_u32 == l_tdt_u32) {
653 * get a pointer to the next tx descriptor for ease of use
655 tx = &m_e1k.m_tx_ring_pst[l_tdt_u32];
660 memcpy(dma2virt(bswap_64(tx->m_buffer_u64)), (uint8_t *) f_buffer_pc,
664 * insert length & command flags
666 tx->m_len_u16 = bswap_16((uint16_t) f_len_i);
667 tx->m_cmd_u08 = (BIT08(0) | // EOP
675 l_tdt_u32 = (l_tdt_u32 + 1) & (E1K_NUM_TX_DESC - 1);
676 e1k_wr32(TDT, l_tdt_u32);
679 #if defined(E1K_SHOW_XMIT) || defined(E1K_SHOW_XMIT_DATA)
680 printf("e1k: %d bytes transmitted\n", bswap_16(tx->m_len_u16));
683 #ifdef E1K_SHOW_XMIT_DATA
684 for (i = 0; i < bswap_16(tx->m_len_u16); i++) {
686 if ((i & 0x1f) == 0) {
690 f_buffer_pc = dma2virt(bswap_64(tx->m_buffer_u64));
691 printf("%02X ", f_buffer_pc[i]);
702 check_driver(uint16_t vendor_id, uint16_t device_id)
707 * checks whether the driver is handling this device
708 * by verifying vendor & device id
709 * vendor id 0x8086 == Intel
711 if (vendor_id != 0x8086) {
713 printf("e1k: netdevice with vendor id %04X not supported\n",
719 for (i = 0; e1k_dev[i].m_dev_u32 != 0; i++) {
720 if (e1k_dev[i].m_dev_u32 == (uint32_t) device_id) {
725 if (e1k_dev[i].m_dev_u32 == 0) {
727 printf("e1k: netdevice with device id %04X not supported\n",
734 * initialize static variables
736 m_e1k.m_device_u64 = e1k_dev[i].m_devmsk_u64;
737 m_e1k.m_baseaddr_u64 = 0;
741 printf("e1k: found device %s\n", e1k_dev[i].m_name);
748 e1k_init(net_driver_t *driver)
757 printf("\ne1k: initializing\n");
760 dma_offset = SLOF_dma_map_in(&m_e1k, sizeof(m_e1k), 0);
762 printf("e1k: dma offset: %lx - %lx = %lx\n", dma_offset, (long)&m_e1k,
763 dma_offset - (long)&m_e1k);
765 dma_offset = dma_offset - (long)&m_e1k;
768 * setup register & memory base addresses of NIC
770 //m_e1k.m_baseaddr_u64 = baseaddr;
772 printf("e1k: base address register = 0x%llx\n", m_e1k.m_baseaddr_u64);
776 * e1k hardware initialization
780 * at first disable all interrupts
782 e1k_wr32(IMC, (uint32_t) ~0);
788 printf("e1k: checking link status..\n");
792 v = e1k_rd32(STATUS);
794 ((v & BIT32(1)) == 0)) {
796 v = e1k_rd32(STATUS);
799 if ((v & BIT32(1)) == 0) {
801 printf("e1k: link is down.\n");
802 printf(" terminating.\n");
809 printf("e1k: link is up\n");
811 switch ((v >> 6) & 0x3) {
813 printf(" 10 Mb/s\n");
816 printf(" 100 Mb/s\n");
820 printf(" 1000 Mb/s\n");
824 if ((v & BIT32(0)) == 0) {
825 printf(" half-duplex\n");
827 printf(" full-duplex\n");
832 * initialize mac address
835 printf("e1k: initializing mac address.. ");
837 if (e1k_mac_init((uint8_t *)driver->mac_addr) != 0) {
840 printf(" terminating.\n");
848 printf(" mac address = %02X:%02X:%02X:%02X:%02X:%02X\n",
849 driver->mac_addr[0], driver->mac_addr[1], driver->mac_addr[2],
850 driver->mac_addr[3], driver->mac_addr[4], driver->mac_addr[5]);
854 * initialize transmitter
857 printf("e1k: initializing transmitter.. ");
859 e1k_init_transmitter();
865 * initialize receiver
868 printf("e1k: initializing receiver.. ");
873 printf("e1k: initialization complete\n");
887 e1k_setb32(CTRL, BIT32(31));
893 e1k_setb32(CTRL, BIT32(26));
903 printf("e1k: shutdown.. ");
907 * disable receiver & transmitter
914 * reset the ring indices
922 * disable receive address
924 e1k_clrb32(RAH0, BIT32(31));
932 * Disable DMA translation
934 SLOF_dma_map_out((long)virt2dma(&m_e1k), (void *)&m_e1k, (long)sizeof(m_e1k));
943 net_driver_t *e1k_open(uint64_t baseaddr)
945 net_driver_t *driver;
947 m_e1k.m_baseaddr_u64 = baseaddr;
948 driver = SLOF_alloc_mem(sizeof(*driver));
950 printf("Unable to allocate virtio-net driver\n");
953 memset(driver, 0, sizeof(*driver));
955 if (e1k_init(driver))
960 FAIL: SLOF_free_mem(driver, sizeof(*driver));
966 void e1k_close(net_driver_t *driver)
968 if (driver->running == 0)
973 SLOF_free_mem(driver, sizeof(*driver));
976 int e1k_read(char *buf, int len)
979 return e1k_receive(buf, len);
983 int e1k_write(char *buf, int len)
986 return e1k_xmit(buf, len);
990 int e1k_mac_setup(uint16_t vendor_id, uint16_t device_id,
991 uint64_t baseaddr, char *mac_addr)
993 if (check_driver(vendor_id, device_id))
996 m_e1k.m_baseaddr_u64 = baseaddr;
997 memset(mac_addr, 0, 6);
999 return e1k_mac_init((uint8_t *)mac_addr);