1 /******************************************************************************
2 * Copyright (c) 2004, 2008 IBM Corporation
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
14 #include <netdriver.h>
17 //#define BCM_DEBUG // main debug switch, w/o it the other ones don't work
18 //#define BCM_SHOW_RCV
19 //#define BCM_SHOW_RCV_DATA
20 //#define BCM_SHOW_XMIT
21 //#define BCM_SHOW_XMIT_DATA
22 //#define BCM_SHOW_XMIT_STATS
23 //#define BCM_SHOW_IDX
24 //#define BCM_SHOW_STATS
25 //#define BCM_SHOW_ASF_REGS
27 // Switch to enable SW AUTO-NEG
28 // don't try, it's still incomplete
29 //#define BCM_SW_AUTONEG
32 * used register offsets
34 // PCI command register
35 #define PCI_COM_R ( (uint16_t) 0x0004 )
36 // PCI Cache Line Size register
37 #define PCI_CACHELS_R ( (uint16_t) 0x000c )
39 #define PCI_BAR1_R ( (uint16_t) 0x0010 )
41 #define PCI_BAR2_R ( (uint16_t) 0x0014 )
43 #define PCI_SUBID_R ( (uint16_t) 0x002e )
44 // PCI-X Comand register
45 #define PCI_X_COM_R ( (uint16_t) 0x0042 )
46 // Message Data Register
47 #define MSG_DATA_R ( (uint16_t) 0x0064 )
48 // PCI misc host contrl register
49 #define PCI_MISC_HCTRL_R ( (uint16_t) 0x0068 )
50 // DMA Read/Write Control register
51 #define DMA_RW_CTRL_R ( (uint16_t) 0x006c )
53 #define PCI_STATE_R ( (uint16_t) 0x0070 )
54 // PCI_Clock Control register
55 #define PCI_CLK_CTRL_R ( (uint16_t) 0x0074 )
56 // Register Base Address Register
57 #define REG_BASE_ADDR_REG ( (uint16_t) 0x0078 )
58 // Memory Window Base Address Register
59 #define MEM_BASE_ADDR_REG ( (uint16_t) 0x007c )
60 // Register Data Register
61 #define REG_DATA_REG ( (uint16_t) 0x0080 )
62 // Memory Window Data Register
63 #define MEM_DATA_REG ( (uint16_t) 0x0084 )
64 // MAC Function register
65 #define MAC_FUNC_R ( (uint16_t) 0x00b8 )
66 // Interrupt Mailbox 0 register
67 #define INT_MBX0_R ( (uint16_t) 0x0204 )
68 // Ethernet MAC Mode register
69 #define ETH_MAC_MODE_R ( (uint16_t) 0x0400 )
70 // Ethernet MAC Addresses registers
71 #define MAC_ADDR_OFFS_HI( idx ) ( (uint16_t) ( (idx*2 + 0)*sizeof( uint32_t ) + 0x0410 ) )
72 #define MAC_ADDR_OFFS_LO( idx ) ( (uint16_t) ( (idx*2 + 1)*sizeof( uint32_t ) + 0x0410 ) )
73 // Ethernet MAC Status register
74 #define ETH_MAC_STAT_R ( (uint16_t) 0x0404 )
75 // Ethernet MAC Event Enable register
76 #define ETH_MAC_EVT_EN_R ( (uint16_t) 0x0408 )
77 // Ethernet Transmit Random Backoff register
78 #define ETH_TX_RND_BO_R ( (uint16_t) 0x0438 )
79 // Receive MTU Size register
80 #define RX_MTU_SIZE_R ( (uint16_t) 0x043c )
81 // Transmit 1000BASE-X Auto Negotiation register
82 #define TX_1000BX_AUTONEG_R ( (uint16_t) 0x0444 )
83 // Receive 1000BASE-X Auto Negotiation register
84 #define RX_1000BX_AUTONEG_R ( (uint16_t) 0x0448 )
85 // MI Communication register
86 #define MI_COM_R ( (uint16_t) 0x044c )
88 #define MI_STATUS_R ( (uint16_t) 0x0450 )
90 #define MI_MODE_R ( (uint16_t) 0x0454 )
91 // Transmit MAC Mode register
92 #define TX_MAC_MODE_R ( (uint16_t) 0x045c )
93 // Transmit MAC Length register
94 #define TX_MAC_LEN_R ( (uint16_t) 0x0464 )
95 // Receive MAC Mode register
96 #define RX_MAC_MODE_R ( (uint16_t) 0x0468 )
97 // MAC Hash 0 register* VPD Config:
98 #define MAC_HASH0_R ( (uint16_t) 0x0470 )
99 // MAC Hash 1 register
100 #define MAC_HASH1_R ( (uint16_t) 0x0474 )
101 // MAC Hash 2 register
102 #define MAC_HASH2_R ( (uint16_t) 0x0478 )
103 // MAC Hash 3 register
104 #define MAC_HASH3_R ( (uint16_t) 0x047c )
105 // Receive Rules Control register
106 #define RX_RULE_CTRL_R( idx ) ( (uint16_t) ( idx*8 + 0x0480 ) )
107 // Receive Rules Value register
108 #define RX_RULE_VAL_R( idx ) ( (uint16_t) ( idx*8 + 0x0484 ) )
109 // Receive Rules Configuration register
110 #define RX_RULE_CFG_R ( (uint16_t) 0x0500 )
111 // Low Watermark Max Receive Frames register
112 #define LOW_WMARK_MAX_RXFRAM_R ( (uint16_t) 0x0504 )
113 // SerDes Control Register
114 #define SERDES_CTRL_R ( (uint16_t) 0x0590 )
115 // Hardware Auto Negotiation Control Register
116 #define HW_AUTONEG_CTRL_R ( (uint16_t) 0x05B0 )
117 // Hardware Auto Negotiation Status Register
118 #define HW_AUTONEG_STAT_R ( (uint16_t) 0x05B4 )
119 // Send Data Initiator Mode register
120 #define TX_DAT_INIT_MODE_R ( (uint16_t) 0x0c00 )
121 // Send Data Completion Mode register
122 #define TX_DAT_COMPL_MODE_R ( (uint16_t) 0x1000 )
123 // Send BD Ring Selector Mode register
124 #define TX_BD_RING_SEL_MODE_R ( (uint16_t) 0x1400 )
125 // Send BD Initiator Mode register
126 #define TX_BD_INIT_MODE_R ( (uint16_t) 0x1800 )
127 // Send BD Completion Mode register
128 #define TX_BD_COMPL_MODE_R ( (uint16_t) 0x1c00 )
129 // Receive List Placement Mode register
130 #define RX_LST_PLACE_MODE_R ( (uint16_t) 0x2000 )
131 // Receive List Placement Configuration register
132 #define RX_LST_PLACE_CFG_R ( (uint16_t) 0x2010 )
133 // Receive List Placement Statistics Enable Mask register
134 #define RX_LST_PLACE_STAT_EN_R ( (uint16_t) 0x2018 )
135 // Receive Data & Receive BD Initiator Mode register
136 #define RX_DAT_BD_INIT_MODE_R ( (uint16_t) 0x2400 )
137 // Receive Data Completion Mode register
138 #define RX_DAT_COMPL_MODE_R ( (uint16_t) 0x2800 )
139 // Receive BD Initiator Mode register
140 #define RX_BD_INIT_MODE_R ( (uint16_t) 0x2c00 )
141 // Standard Receive Producer Ring Replenish Threshold register
142 #define STD_RXPR_REP_THR_R ( (uint16_t) 0x2c18 )
143 // Receive BD Completion Mode register
144 #define RX_BD_COMPL_MODE_R ( (uint16_t) 0x3000 )
145 // Receive List Selector Mode register
146 #define RX_LST_SEL_MODE_R ( (uint16_t) 0x3400 )
147 // MBUF Cluster Free Mode register
148 #define MBUF_CLSTR_FREE_MODE_R ( (uint16_t) 0x3800 )
149 // Host Coalescing Mode register
150 #define HOST_COAL_MODE_R ( (uint16_t) 0x3c00 )
151 // Receive Coalescing Ticks register
152 #define RX_COAL_TICKS_R ( (uint16_t) 0x3c08 )
153 // Send Coalescing Ticks register
154 #define TX_COAL_TICKS_R ( (uint16_t) 0x3c0c )
155 // Receive Max Coalesced BD Count register
156 #define RX_COAL_MAX_BD_R ( (uint16_t) 0x3c10 )
157 // Send Max Coalesced BD Count register
158 #define TX_COAL_MAX_BD_R ( (uint16_t) 0x3c14 )
159 // Receive Coalescing Ticks During Int register
160 #define RX_COAL_TICKS_INT_R ( (uint16_t) 0x3c18 )
161 // Send Coalescing Ticks During Int register
162 #define TX_COAL_TICKS_INT_R ( (uint16_t) 0x3c1c )
163 // Receive Max Coalesced BD Count During Int register
164 #define RX_COAL_MAX_BD_INT_R ( (uint16_t) 0x3c18 )
165 // Send Max Coalesced BD Count During Int register
166 #define TX_COAL_MAX_BD_INT_R ( (uint16_t) 0x3c1c )
167 // Statistics Ticks Counter register
168 #define STAT_TICK_CNT_R ( (uint16_t) 0x3c28 )
169 // Status Block Host Address Low register
170 #define STB_HOST_ADDR_HI_R ( (uint16_t) 0x3c38 )
171 // Status Block Host Address High register
172 #define STB_HOST_ADDR_LO_R ( (uint16_t) 0x3c3c )
173 // Statistics Base Address register
174 #define STAT_NIC_ADDR_R ( (uint16_t) 0x3c40 )
175 // Status Block Base Address register
176 #define STB_NIC_ADDR_R ( (uint16_t) 0x3c44 )
177 // Memory Arbiter Mode register
178 #define MEMARB_MODE_R ( (uint16_t) 0x4000 )
179 // Buffer Manager Mode register
180 #define BUF_MAN_MODE_R ( (uint16_t) 0x4400 )
181 // MBuf Pool Address register
182 #define MBUF_POOL_ADDR_R ( (uint16_t) 0x4408 )
183 // MBuf Pool Length register
184 #define MBUF_POOL_LEN_R ( (uint16_t) 0x440c )
185 // Read DMA Mbuf Low Watermark register
186 #define DMA_RMBUF_LOW_WMARK_R ( (uint16_t) 0x4410 )
187 // MAC Rx Mbuf Low Watermark register
188 #define MAC_RXMBUF_LOW_WMARK_R ( (uint16_t) 0x4414 )
189 // Mbuf High Watermark register
190 #define MBUF_HIGH_WMARK_R ( (uint16_t) 0x4418 )
191 // DMA Descriptor Pool Address register
192 #define DMA_DESC_POOL_ADDR_R ( (uint16_t) 0x442c )
193 // DMA Descriptor Pool Length register
194 #define DMA_DESC_POOL_LEN_R ( (uint16_t) 0x4430 )
195 // DMA Descriptor Low Watermark register
196 #define DMA_DESC_LOW_WM_R ( (uint16_t) 0x4434 )
197 // DMA Descriptor HIGH Watermark register
198 #define DMA_DESC_HIGH_WM_R ( (uint16_t) 0x4438 )
199 // Read DMA Mode register
200 #define RD_DMA_MODE_R ( (uint16_t) 0x4800 )
201 // Write DMA Mode register
202 #define WR_DMA_MODE_R ( (uint16_t) 0x4c00 )
203 // FTQ Reset register
204 #define FTQ_RES_R ( (uint16_t) 0x5c00 )
206 #define MSI_MODE_R ( (uint16_t) 0x6000 )
207 // DMA completion Mode register
208 #define DMA_COMPL_MODE_R ( (uint16_t) 0x6400 )
209 // Mode Control register
210 #define MODE_CTRL_R ( (uint16_t) 0x6800 )
211 // Misc Configuration register
212 #define MISC_CFG_R ( (uint16_t) 0x6804 )
213 // Misc Local Control register
214 #define MISC_LOCAL_CTRL_R ( (uint16_t) 0x6808 )
215 // RX-Risc Mode Register
216 #define RX_CPU_MODE_R ( (uint16_t) 0x5000 )
217 // RX-Risc State Register
218 #define RX_CPU_STATE_R ( (uint16_t) 0x5004 )
219 // RX-Risc Program Counter
220 #define RX_CPU_PC_R ( (uint16_t) 0x501c )
221 // RX-Risc Event Register
222 #define RX_CPU_EVENT_R ( (uint16_t) 0x6810 )
223 // MDI Control register
224 #define MDI_CTRL_R ( (uint16_t) 0x6844 )
226 #define WOL_MODE_R ( (uint16_t) 0x6880 )
227 // WOL Config register
228 #define WOL_CFG_R ( (uint16_t) 0x6884 )
229 // WOL Status register
230 #define WOL_STATUS_R ( (uint16_t) 0x6888 )
232 // ASF Control register
233 #define ASF_CTRL_R ( (uint16_t) 0x6c00 )
234 // ASF Watchdog Timer register
235 #define ASF_WATCHDOG_TIMER_R ( (uint16_t) 0x6c0c )
236 // ASF Heartbeat Timer register
237 #define ASF_HEARTBEAT_TIMER_R ( (uint16_t) 0x6c10 )
238 // Poll ASF Timer register
239 #define ASF_POLL_TIMER_R ( (uint16_t) 0x6c14 )
240 // Poll Legacy Timer register
241 #define POLL_LEGACY_TIMER_R ( (uint16_t) 0x6c18 )
242 // Retransmission Timer register
243 #define RETRANSMISSION_TIMER_R ( (uint16_t) 0x6c1c )
244 // Time Stamp Counter register
245 #define TIME_STAMP_COUNTER_R ( (uint16_t) 0x6c20 )
247 // NVM Command register
248 #define NVM_COM_R ( (uint16_t) 0x7000 )
249 // NVM Write register
250 #define NVM_WRITE_R ( (uint16_t) 0x7008 )
251 // NVM Address register
252 #define NVM_ADDR_R ( (uint16_t) 0x700c )
253 // NVM Read registertg3_phy_copper_begin
254 #define NVM_READ_R ( (uint16_t) 0x7010 )
255 // NVM Access register
256 #define NVM_ACC_R ( (uint16_t) 0x7024 )
257 // NVM Config 1 register
258 #define NVM_CFG1_R ( (uint16_t) 0x7014 )
259 // Software arbitration register
260 #define SW_ARB_R ( (uint16_t) 0x7020 )
265 #define rd08(a) ci_read_8((uint8_t *)(a))
266 #define rd16(a) ci_read_16((uint16_t *)(a))
267 #define rd32(a) ci_read_32((uint32_t *)(a))
268 #define wr08(a,v) ci_write_8((uint8_t *)(a), (v))
269 #define wr16(a,v) ci_write_16((uint16_t *)(a), (v))
270 #define wr32(a,v) ci_write_32((uint32_t *)(a), (v))
272 #define BIT08( bit ) ( (uint8_t) 0x1 << (bit) )
273 #define BIT16( bit ) ( (uint16_t) 0x1 << (bit) )
274 #define BIT32( bit ) ( (uint32_t) 0x1 << (bit) )
281 * Constants for different kinds of IOCTL requests
284 #define SIOCETHTOOL 0x1000
287 * special structure and constants for IOCTL requests of type ETHTOOL
290 #define ETHTOOL_GMAC 0x03
291 #define ETHTOOL_SMAC 0x04
292 #define ETHTOOL_VERSION 0x05
297 } ioctl_ethtool_mac_t;
302 } ioctl_ethtool_version_t;
306 * default structure and constants for IOCTL requests
309 #define IF_NAME_SIZE 0xFF
312 char if_name[IF_NAME_SIZE];
315 ioctl_ethtool_mac_t mac;
316 ioctl_ethtool_version_t version;
320 extern net_driver_t *bcm57xx_open(void);
321 extern void bcm57xx_close(net_driver_t *driver);
322 extern int bcm57xx_read(char *buf, int len);
323 extern int bcm57xx_write(char *buf, int len);