1 /******************************************************************************
2 * Copyright (c) 2004, 2008 IBM Corporation
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
15 ******************************************************************************
18 * Host Programmer Interface Specification for the
19 * NetXtreme Family of Highly-Integrated Media Access Controlers
24 #include <byteorder.h>
26 #include <netdriver.h>
31 ******************************************************************************
35 // #define BCM_VLAN_TAG ( (uint32_t) 0x1 )
37 // number of tx/rx rings
38 // NOTE: 5714 only uses 1 rx/tx ring, but memory
39 // for the other rings is cleaned anyways for
40 // sanity & future use
41 #define BCM_MAX_TX_RING 16
42 #define BCM_MAX_RXRET_RING 16
43 #define BCM_MAX_RXPROD_RCB 3
46 #define BCM_RXPROD_RING_SIZE 512 // don't change
47 #define BCM_RXRET_RING_SIZE 512 // don't change
48 #define BCM_TX_RING_SIZE 512 // don't change
49 #define BCM_BUF_SIZE 1536 // don't change
50 #define BCM_MTU_MAX_LEN 1522
51 #define BCM_MAX_RX_BUF 64
52 #define BCM_MAX_TX_BUF 16
54 // number of MAC addresses in NIC
55 #define BCM_NUM_MAC_ADDR 4
56 #define BCM_NUM_MAC5704_ADDR 12
57 // offset of mac address field(s) in bcm register space
58 #define MAC5704_ADDR_OFFS ( (uint16_t) 0x0530 )
60 // offset of NIC memory start address from base address
61 #define BCM_MEMORY_OFFS ( (uint64_t) 0x8000 )
63 // offset of statistics block in NIC memory
64 #define BCM_STATISTIC_OFFS ( (uint64_t) 0x0300 )
65 // size of statistic block in NIC memory
66 #define BCM_STATISTIC_SIZE 0x800
68 // offsets of NIC rx/tx rings in NIC memory
69 #define BCM_NIC_TX_OFFS ( (uint16_t) 0x4000 )
70 #define BCM_NIC_RX_OFFS ( (uint16_t) 0x6000 )
71 #define BCM_NIC_TX_SIZE ( (uint16_t) ( ( BCM_TX_RING_SIZE * BCM_RCB_SIZE_u16 ) / 4 ) )
74 #define BCM_FW_MBX ( (uint16_t) 0x0b50 )
75 #define BCM_FW_MBX_CMD ( (uint16_t) 0x0b78 )
76 #define BCM_FW_MBX_LEN ( (uint16_t) 0x0b7c )
77 #define BCM_FW_MBX_DATA ( (uint16_t) 0x0b80 )
78 #define BCM_NICDRV_STATE_MBX ( (uint16_t) 0x0c04 )
80 // device mailbox commands
81 #define BCM_NICDRV_ALIVE ( (uint32_t) 0x00000001 )
82 #define BCM_NICDRV_PAUSE_FW ( (uint32_t) 0x00000002 )
85 #define BCM_MAGIC_NUMBER ( (uint32_t) 0x4b657654 )
88 #define NIC_FWDRV_STATE_START ( (uint32_t) 0x00000001 )
89 #define NIC_FWDRV_STATE_START_DONE ( (uint32_t) 0x80000001 )
90 #define NIC_FWDRV_STATE_UNLOAD ( (uint32_t) 0x00000002 )
91 #define NIC_FWDRV_STATE_UNLOAD_DONE ( (uint32_t) 0x80000002 )
92 #define NIC_FWDRV_STATE_SUSPEND ( (uint32_t) 0x00000004 )
94 // timer prescaler value
95 #define BCM_TMR_PRESCALE ( (uint32_t) 0x41 )
97 // offset of transmit rcb's in NIC memory
98 #define BCM_TX_RCB_OFFS ( (uint16_t) 0x0100 )
99 // offset of receive return rcb's in NIC memory
100 #define BCM_RXRET_RCB_OFFS ( (uint16_t) 0x0200 )
102 // register offsets for ring indices
103 #define TX_PROD_IND ( (uint16_t) 0x0304 )
104 #define TX_CONS_IND ( (uint16_t) 0x3cc0 )
105 #define RXPROD_PROD_IND ( (uint16_t) 0x026c )
106 #define RXPROD_CONS_IND ( (uint16_t) 0x3c54 )
107 #define RXRET_PROD_IND ( (uint16_t) 0x3c80 )
108 #define RXRET_CONS_IND ( (uint16_t) 0x0284 )
109 // NIC producer index only needed for initialization
110 #define TX_NIC_PROD_IND ( (uint16_t) 0x0384 )
113 * predefined register values used during initialization
114 * may be adapted by user
116 #define DMA_RW_CTRL_VAL_5714 ( (uint32_t) 0x76144000 )
117 #define DMA_RW_CTRL_VAL ( (uint32_t) 0x760F0000 )
118 #define TX_MAC_LEN_VAL ( (uint32_t) 0x00002620 )
120 #define RX_LST_PLC_CFG_VAL ( (uint32_t) 0x00000109 )
121 #define RX_LST_PLC_STAT_EN_VAL ( (uint32_t) 0x007e000f )
122 #define NVM_ADDR_MSK ( (uint32_t) 0x000fffff )
124 // Number of Receive Rules /w or /wo SOL enabled
125 #define RX_RULE_CFG_VAL ( (uint32_t) 0x00000008 )
126 #define NUM_RX_RULE ( (uint32_t) 16 )
127 #define NUM_RX_RULE_ASF ( (uint32_t) ( NUM_RX_RULE - 4 ) )
129 // RCB register offsets
130 #define BCM_RXPROD_RCB_JUM ( (uint16_t) 0x2440 )
131 #define BCM_RXPROD_RCB_STD ( (uint16_t) 0x2450 )
132 #define BCM_RXPROD_RCB_MIN ( (uint16_t) 0x2460 )
134 // macros needed for new addressing method
135 #define BCM_RCB_HOSTADDR_HI_u16( rcb ) ( (uint16_t) rcb + 0x00 )
136 #define BCM_RCB_HOSTADDR_LOW_u16( rcb ) ( (uint16_t) rcb + 0x04 )
137 #define BCM_RCB_LENFLAG_u16( rcb ) ( (uint16_t) rcb + 0x08 )
138 #define BCM_RCB_NICADDR_u16( rcb ) ( (uint16_t) rcb + 0x0c )
139 #define BCM_RCB_SIZE_u16 ( (uint16_t) 0x0010 )
142 #define RCB_FLAG_RING_DISABLED BIT32( 1 )
144 // BCM device ID masks
145 #define BCM_DEV_5714 ( (uint64_t) 0x1 )
146 #define BCM_DEV_5704 ( (uint64_t) 0x2 )
147 #define BCM_DEV_5703 ( (uint64_t) 0x4 )
148 #define BCM_DEV_SERDES ( (uint64_t) 0x80000000 )
149 #define BCM_DEV_COPPER ( (uint64_t) 0x40000000 )
151 #define IS_5714 ( ( bcm_device_u64 & BCM_DEV_5714 ) != 0 )
152 #define IS_5704 ( ( bcm_device_u64 & BCM_DEV_5704 ) != 0 )
153 #define IS_5703 ( ( bcm_device_u64 & BCM_DEV_5703 ) != 0 )
154 #define IS_SERDES ( ( bcm_device_u64 & BCM_DEV_SERDES ) != 0 )
155 #define IS_COPPER_PHY ( ( bcm_device_u64 & BCM_DEV_COPPER ) != 0 )
157 #define BUFFERED_FLASH_PAGE_POS 9
158 #define BUFFERED_FLASH_BYTE_ADDR_MASK ((<<BUFFERED_FLASH_PAGE_POS) - 1)
159 #define BUFFERED_FLASH_PAGE_SIZE 264
160 #define BUFFERED_FLASH_PHY_SIZE 512
161 #define MANUFACTURING_INFO_SIZE 140
162 #define CRC32_POLYNOMIAL 0xEDB88320
166 ******************************************************************************
170 uint64_t m_devmsk_u64;
174 * BCM common data structures
175 * BCM57xx Programmer's Guide: Section 5
179 * 64bit host address in a way the NIC is able to understand it
189 bcm_addr64_t m_hostaddr_st;
190 uint32_t m_lenflags_u32; // upper 16b: len, lower 16b: flags
191 uint32_t m_nicaddr_u32;
195 * tx buffer descriptor
198 bcm_addr64_t m_hostaddr_st;
199 uint32_t m_lenflags_u32; // upper 16b: len, lower 16b: flags
200 uint32_t m_VLANtag_u32; // lower 16b: vtag
204 * rx buffer descriptor
207 bcm_addr64_t m_hostaddr_st;
208 uint32_t m_idxlen_u32; // upper 16b: idx, lower 16b: len
209 uint32_t m_typeflags_u32; // upper 16b: type, lower 16b: flags
210 uint32_t m_chksum_u32; // upper 16b: ip, lower 16b: tcp/udp
211 uint32_t m_errvlan_u32; // upper 16b: err, lower 16b: vlan tag
212 uint32_t m_reserved_u32;
213 uint32_t m_opaque_u32;
218 * NOTE: in fact the status block is not used and configured
219 * so that it is not updated by the NIC. Still it has to be
220 * set up so the NIC is satisfied
223 uint32_t m_st_word_u32;
224 uint32_t m_st_tag_u32;
225 uint16_t m_rxprod_cons_u16;
226 uint16_t m_unused_u16;
227 uint32_t m_unused_u32;
228 uint16_t m_tx_cons_u16;
229 uint16_t m_rxret_prod_u16;
234 ******************************************************************************
236 static const bcm_dev_t bcm_dev[] = {
237 { 0x166b, BCM_DEV_5714 },
238 { 0x1668, BCM_DEV_5714 },
239 { 0x1669, BCM_DEV_5714 },
240 { 0x166a, BCM_DEV_5714 },
241 { 0x1648, BCM_DEV_5704 },
242 { 0x1649, BCM_DEV_5704 | BCM_DEV_SERDES },
243 { 0x16a8, BCM_DEV_5704 | BCM_DEV_SERDES },
244 { 0x16a7, BCM_DEV_5703 | BCM_DEV_SERDES },
245 { 0x16c7, BCM_DEV_5703 | BCM_DEV_SERDES },
251 ******************************************************************************
253 static uint64_t bcm_device_u64;
254 static uint32_t bcm_rxret_ring_sz;
255 static uint64_t bcm_baseaddr_u64;
256 static uint64_t bcm_memaddr_u64;
259 * rings & their buffers
261 // the rings made of buffer descriptors
262 static bcm_txbd_t bcm_tx_ring[BCM_TX_RING_SIZE];
263 static bcm_rxbd_t bcm_rxprod_ring[BCM_RXPROD_RING_SIZE];
264 static bcm_rxbd_t bcm_rxret_ring[BCM_RXRET_RING_SIZE*2];
266 // the buffers used in the rings
267 static uint8_t bcm_tx_buffer_pu08[BCM_MAX_TX_BUF][BCM_BUF_SIZE];
268 static uint8_t bcm_rx_buffer_pu08[BCM_MAX_RX_BUF][BCM_BUF_SIZE];
270 // tx ring index of first/last bd
271 static uint32_t bcm_tx_start_u32;
272 static uint32_t bcm_tx_stop_u32;
273 static uint32_t bcm_tx_bufavail_u32;
278 static bcm_status_t bcm_status;
282 ******************************************************************************
288 ******************************************************************************
293 * local helper functions
294 ******************************************************************************
298 memcpy( char *dest, const char *src, size_t n )
310 memset_ci( char *dest, int c, size_t n )
324 memset( char *dest, int c, size_t n )
336 bcm_nvram_logical_to_physical_address(uint32_t address)
338 uint32_t page_no = address / BUFFERED_FLASH_PAGE_SIZE;
339 uint32_t page_addr = address % BUFFERED_FLASH_PAGE_SIZE;
341 return (page_no << BUFFERED_FLASH_PAGE_POS) + page_addr;
345 * read/write functions to access NIC registers & memory
346 * NOTE: all functions are executed with cache inhibitation (dead slow :-) )
349 bcm_read_mem32( uint16_t f_offs_u16 )
350 { // caution: shall only be used after initialization!
351 return rd32( bcm_memaddr_u64 + (uint64_t) f_offs_u16 );
356 bcm_read_mem16( uint16_t f_offs_u16 )
357 { // caution: shall only be used after initialization!
358 return rd16( bcm_memaddr_u64 + (uint64_t) f_offs_u16 );
362 bcm_read_mem08( uint16_t f_offs_u16 )
363 { // caution: shall only be used after initialization!
364 return rd08( bcm_memaddr_u64 + (uint64_t) f_offs_u16 );
368 bcm_read_reg32_indirect( uint16_t f_offs_u16 )
369 { // caution: shall only be used after initialization!
370 SLOF_pci_config_write32(REG_BASE_ADDR_REG, f_offs_u16);
371 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
377 return bswap_32(SLOF_pci_config_read32(REG_DATA_REG));
378 /*return (uint32_t) bswap_32( snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
386 bcm_read_reg32( uint16_t f_offs_u16 )
387 { // caution: shall only be used after initialization!
388 if(f_offs_u16 >= 0x200 && f_offs_u16 <0x400)
389 return bcm_read_reg32_indirect( f_offs_u16 + 0x5600 );
390 return rd32( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
394 bcm_read_reg16( uint16_t f_offs_u16 )
395 { // caution: shall only be used after initialization!
396 return rd16( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
400 bcm_read_reg08( uint16_t f_offs_u16 )
401 { // caution: shall only be used after initialization!
402 return rd08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
406 bcm_write_mem32_indirect( uint16_t f_offs_u16, uint32_t f_val_u32 )
407 { // caution: shall only be used after initialization!
408 SLOF_pci_config_write32(MEM_BASE_ADDR_REG, f_offs_u16);
409 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
415 SLOF_pci_config_write32(MEM_DATA_REG, bswap_32(f_val_u32));
416 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
421 bswap_32 ( f_val_u32 ) );*/
425 bcm_write_mem32( uint16_t f_offs_u16, uint32_t f_val_u32 )
426 { // caution: shall only be used after initialization!
427 if(f_offs_u16 >= BCM_RXRET_RCB_OFFS &&
428 f_offs_u16 < BCM_RXRET_RCB_OFFS + (BCM_MAX_RXRET_RING*BCM_RCB_SIZE_u16))
429 bcm_write_mem32_indirect( f_offs_u16, f_val_u32 );
430 else if(f_offs_u16 >= BCM_TX_RCB_OFFS &&
431 f_offs_u16 < BCM_TX_RCB_OFFS + (BCM_MAX_TX_RING*BCM_RCB_SIZE_u16))
432 bcm_write_mem32_indirect( f_offs_u16, f_val_u32 );
434 wr32( bcm_memaddr_u64 + (uint64_t) f_offs_u16, f_val_u32 );
438 bcm_write_mem16( uint16_t f_offs_u16, uint16_t f_val_u16 )
439 { // caution: shall only be used after initialization!
440 wr16( bcm_memaddr_u64 + (uint64_t) f_offs_u16, f_val_u16 );
444 bcm_write_mem08( uint16_t f_offs_u16, uint8_t f_val_u08 )
445 { // caution: shall only be used after initialization!
446 wr08( bcm_memaddr_u64 + (uint64_t) f_offs_u16, f_val_u08 );
450 bcm_write_reg32_indirect( uint16_t f_offs_u16, uint32_t f_val_u32 )
451 { // caution: shall only be used after initialization!
452 SLOF_pci_config_write32(REG_BASE_ADDR_REG, f_offs_u16);
453 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
459 SLOF_pci_config_write32(REG_DATA_REG, bswap_32(f_val_u32));
460 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
465 bswap_32 ( f_val_u32 ) );*/
469 bcm_write_reg32( uint16_t f_offs_u16, uint32_t f_val_u32 )
470 { // caution: shall only be used after initialization!
471 if(f_offs_u16 >= 0x200 && f_offs_u16 <0x400)
472 bcm_write_reg32_indirect( f_offs_u16 + 0x5600, f_val_u32 );
474 wr32( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, f_val_u32 );
478 bcm_write_reg16( uint16_t f_offs_u16, uint16_t f_val_u16 )
479 { // caution: shall only be used after initialization!
480 wr16( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, f_val_u16 );
484 bcm_write_reg08( uint16_t f_offs_u16, uint8_t f_val_u08 )
485 { // caution: shall only be used after initialization!
486 wr08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, f_val_u08 );
490 bcm_setb_reg32( uint16_t f_offs_u16, uint32_t f_mask_u32 )
494 v = bcm_read_reg32( f_offs_u16 );
496 bcm_write_reg32( f_offs_u16, v );
500 bcm_setb_reg16( uint16_t f_offs_u16, uint16_t f_mask_u16 )
503 v = rd16( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
505 wr16( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, v );
509 bcm_setb_reg08( uint16_t f_offs_u16, uint8_t f_mask_u08 )
512 v = rd08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
514 wr08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, v );
518 bcm_clrb_reg32( uint16_t f_offs_u16, uint32_t f_mask_u32 )
522 v = bcm_read_reg32( f_offs_u16 );
524 bcm_write_reg32( f_offs_u16, v );
528 bcm_clrb_reg16( uint16_t f_offs_u16, uint16_t f_mask_u16 )
532 v = bcm_read_reg16( f_offs_u16 );
534 bcm_write_reg16( f_offs_u16, v );
538 bcm_clrb_reg08( uint16_t f_offs_u16, uint8_t f_mask_u08 )
541 v = rd08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16 );
543 wr08( bcm_baseaddr_u64 + (uint64_t) f_offs_u16, v );
547 bcm_clr_wait_bit32( uint16_t r, uint32_t b )
551 bcm_clrb_reg32( r, b );
556 if( ( bcm_read_reg32( r ) & b ) == 0 ) {
563 if( ( bcm_read_reg32( r ) & b ) != 0 ) {
564 printf( "bcm57xx: bcm_clear_wait_bit32 failed (0x%04X)!\n", r );
575 bcm_mii_write16( uint32_t f_reg_u32, uint16_t f_value_u16 )
577 static const uint32_t WR_VAL = ( ( ((uint32_t) 0x1) << 21 ) | BIT32( 29 ) | BIT32( 26 ) );
578 int32_t l_autopoll_i32 = 0;
579 uint32_t l_wrval_u32;
583 * only 0x00-0x1f are valid registers
585 if( f_reg_u32 > (uint32_t) 0x1f ) {
590 * disable auto polling if enabled
592 if( ( bcm_read_reg32( MI_MODE_R ) & BIT32( 4 ) ) != 0 ) {
593 l_autopoll_i32 = (int32_t) !0;
594 bcm_clrb_reg32( MI_MODE_R, BIT32( 4 ) );
599 * construct & write mi com register value
601 l_wrval_u32 = ( WR_VAL | ( f_reg_u32 << 16 ) | (uint32_t) f_value_u16 );
602 bcm_write_reg32( MI_COM_R, l_wrval_u32 );
605 * wait for transaction to complete
609 ( ( bcm_read_reg32( MI_COM_R ) & BIT32( 29 ) ) != 0 ) ) {
614 * re-enable auto polling if necessary
616 if( l_autopoll_i32 ) {
617 bcm_setb_reg32( MI_MODE_R, BIT32( 4 ) );
630 bcm_mii_read16( uint32_t f_reg_u32, uint16_t *f_value_pu16 )
632 static const uint32_t RD_VAL = ( ( ((uint32_t) 0x1) << 21 ) | BIT32( 29 ) | BIT32( 27 ) );
633 int32_t l_autopoll_i32 = 0;
634 uint32_t l_rdval_u32;
636 uint16_t first_not_busy;
639 * only 0x00-0x1f are valid registers
641 if( f_reg_u32 > (uint32_t) 0x1f ) {
646 * disable auto polling if enabled
648 if( ( bcm_read_reg32( MI_MODE_R ) & BIT32( 4 ) ) != 0 ) {
649 l_autopoll_i32 = ( int32_t ) !0;
650 bcm_clrb_reg32( MI_MODE_R, BIT32( 4 ) );
655 * construct & write mi com register value
657 l_rdval_u32 = ( RD_VAL | ( f_reg_u32 << 16 ) );
658 bcm_write_reg32( MI_COM_R, l_rdval_u32 );
661 * wait for transaction to complete
662 * ERRATA workaround: must read two "not busy" states to indicate transaction complete
666 l_rdval_u32 = bcm_read_reg32( MI_COM_R );
668 ( (first_not_busy == 0) || ( ( l_rdval_u32 & BIT32( 29 ) ) != 0 ) ) ) {
669 /* Is this the first clear BUSY state? */
670 if ( ( l_rdval_u32 & BIT32( 29 ) ) == 0 )
673 l_rdval_u32 = bcm_read_reg32( MI_COM_R );
677 * re-enable autopolling if necessary
679 if( l_autopoll_i32 ) {
680 bcm_setb_reg32( MI_MODE_R, BIT32( 4 ) );
684 * return on read transaction error
685 * (check read failed bit)
688 ( ( l_rdval_u32 & BIT32( 28 ) ) != 0 ) ) {
695 *f_value_pu16 = (uint16_t) ( l_rdval_u32 & (uint32_t) 0xffff );
701 * ht2000 dump (not complete)
709 printf( "*** DUMP ***********************************************************************\n\n" );
711 printf( "* PCI Configuration Registers:\n" );
712 for( i = 0, j = 0; i < 0x40; i += 4 ) {
714 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
716 if( ( ++j & 0x3 ) == 0 ) {
722 printf( "\n* Private PCI Configuration Registers:\n" );
723 for( i = 0x68, j = 0; i < 0x88; i += 4 ) {
725 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
727 if( ( ++j & 0x3 ) == 0 ) {
733 printf( "\n* VPD Config:\n" );
734 printf( "%04X: %08X \n", 0x94, bcm_read_reg32( 0x94 ) );
736 printf( "\n* Dual MAC Control Registers:\n" );
737 for( i = 0xb8, j = 0; i < 0xd0; i += 4 ) {
739 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
741 if( ( ++j & 0x3 ) == 0 ) {
747 printf( "\n* Ethernet MAC Control Registers:\n" );
748 for( i = 0x400, j = 0; i < 0x590; i += 4 ) {
750 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
752 if( ( ++j & 0x3 ) == 0 ) {
758 printf( "\n* Send Data Initiator Control:\n" );
759 for( i = 0xc00, j = 0; i < 0xc10; i += 4 ) {
761 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
763 if( ( ++j & 0x3 ) == 0 ) {
769 printf( "\n* Send Data Completion Control:\n" );
770 printf( "%04X: %08X ", 0x1000, bcm_read_reg32( 0x1000 ) );
771 printf( "%04X: %08X \n", 0x1008, bcm_read_reg32( 0x1008 ) );
773 printf( "\n* Send BD Ring Selector Control:\n" );
774 printf( "%04X: %08X ", 0x1400, bcm_read_reg32( 0x1400 ) );
775 printf( "%04X: %08X ", 0x1404, bcm_read_reg32( 0x1404 ) );
776 printf( "%04X: %08X \n", 0x1408, bcm_read_reg32( 0x1408 ) );
778 printf( "\n* Send BD Initiator Control:\n" );
779 printf( "%04X: %08X ", 0x1800, bcm_read_reg32( 0x1800 ) );
780 printf( "%04X: %08X \n", 0x1804, bcm_read_reg32( 0x1804 ) );
782 printf( "\n* Send BD Completion Control:\n" );
783 printf( "%04X: %08X ", 0x1c00, bcm_read_reg32( 0x1c00 ) );
785 printf( "\n* Receive List Placement Control:\n" );
786 for( i = 0x2000, j = 0; i < 0x2020; i += 4 ) {
788 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
790 if( ( ++j & 0x3 ) == 0 ) {
796 printf( "\n* Receive Data & Receive BD Initiator Control:\n" );
797 printf( "%04X: %08X ", 0x2400, bcm_read_reg32( 0x2400 ) );
798 printf( "%04X: %08X \n", 0x2404, bcm_read_reg32( 0x2404 ) );
800 printf( "\n* Jumbo Receive BD Ring RCB:\n" );
801 for( i = 0x2440, j = 0; i < 0x2450; i += 4 ) {
803 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
805 if( ( ++j & 0x3 ) == 0 ) {
811 printf( "\n* Standard Receive BD Ring RCB:\n" );
812 for( i = 0x2450, j = 0; i < 0x2460; i += 4 ) {
814 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
816 if( ( ++j & 0x3 ) == 0 ) {
822 printf( "\n* Mini Receive BD Ring RCB:\n" );
823 for( i = 0x2460, j = 0; i < 0x2470; i += 4 ) {
825 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
827 if( ( ++j & 0x3 ) == 0 ) {
833 printf( "\nRDI Timer Mode Register:\n" );
834 printf( "%04X: %08X \n", 0x24f0, bcm_read_reg32( 0x24f0 ) );
836 printf( "\n* Receive BD Initiator Control:\n" );
837 for( i = 0x2c00, j = 0; i < 0x2c20; i += 4 ) {
839 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
841 if( ( ++j & 0x3 ) == 0 ) {
847 printf( "\n* Receive BD Completion Control:\n" );
848 for( i = 0x3000, j = 0; i < 0x3014; i += 4 ) {
850 printf( "%04X: %08X ", i, bcm_read_reg32( i ) );
852 if( ( ++j & 0x3 ) == 0 ) {
867 bcm_nvram_lock( void )
872 * Acquire NVRam lock (REQ0) & wait for arbitration won (ARB0_WON)
874 // bcm_setb_reg32( SW_ARB_R, BIT32( 0 ) );
875 bcm_setb_reg32( SW_ARB_R, BIT32( 1 ) );
879 // ( bcm_read_reg32( SW_ARB_R ) & BIT32( 8 ) ) == 0 ) {
880 ( bcm_read_reg32( SW_ARB_R ) & BIT32( 9 ) ) == 0 ) {
887 printf("bcm57xx: failed to lock nvram");
896 bcm_nvram_unlock( void )
899 * release NVRam lock (CLR0)
901 // bcm_setb_reg32( SW_ARB_R, BIT32( 4 ) );
902 bcm_setb_reg32( SW_ARB_R, BIT32( 5 ) );
906 bcm_nvram_init( void )
909 * enable access to NVRAM registers
912 bcm_setb_reg32( NVM_ACC_R, BIT32( 1 ) | BIT32( 0 ) );
916 * disable bit-bang method 19& disable interface bypass
918 bcm_clrb_reg32( NVM_CFG1_R, BIT32( 31 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 14 ) | BIT32( 16 ) );
919 bcm_setb_reg32( NVM_CFG1_R, BIT32 ( 13 ) | BIT32 ( 17 ));
922 * enable Auto SEEPROM Access
924 bcm_setb_reg32( MISC_LOCAL_CTRL_R, BIT32 ( 24 ) );
929 bcm_setb_reg32( MODE_CTRL_R, BIT32 ( 21 ) );
933 bcm_nvram_read( uint32_t f_addr_u32, uint32_t *f_val_pu32, uint32_t lock )
940 if( f_addr_u32 > NVM_ADDR_MSK ) {
945 * Acquire NVRam lock (REQ0) & wait for arbitration won (ARB0_WON)
947 if( lock && (bcm_nvram_lock() == -1) ) {
952 * setup address to read
954 bcm_write_reg32( NVM_ADDR_R,
955 bcm_nvram_logical_to_physical_address(f_addr_u32) );
956 // bcm_write_reg32( NVM_ADDR_R, f_addr_u32 );
959 * get the command going
961 bcm_write_reg32( NVM_COM_R, BIT32( 8 ) | BIT32( 7 ) |
962 BIT32( 4 ) | BIT32( 3 ) );
965 * wait for command completion
969 ( ( bcm_read_reg32( NVM_COM_R ) & BIT32( 3 ) ) == 0 ) ) {
974 * read back data if no error
980 *f_val_pu32 = bcm_read_reg32( NVM_READ_R );
989 printf("bcm57xx: reading from NVRAM failed\n");
999 bcm_nvram_write( uint32_t f_addr_u32, uint32_t f_value_u32, uint32_t lock )
1006 if( f_addr_u32 > NVM_ADDR_MSK ) {
1011 * Acquire NVRam lock (REQ0) & wait for arbitration won (ARB0_WON)
1013 if( lock && (bcm_nvram_lock() == -1) ) {
1018 * setup address to write
1020 bcm_write_reg32( NVM_ADDR_R, bcm_nvram_logical_to_physical_address( f_addr_u32 ) );
1025 bcm_write_reg32( NVM_WRITE_R, f_value_u32 );
1028 * get the command going
1030 bcm_write_reg32( NVM_COM_R, BIT32( 8 ) | BIT32( 7 ) |
1031 BIT32( 5 ) | BIT32( 4 ) | BIT32( 3 ) );
1034 * wait for command completion
1038 ( ( bcm_read_reg32( NVM_COM_R ) & BIT32( 3 ) ) == 0 ) ) {
1043 * release NVRam lock (CLR0)
1051 printf("bcm57xx: writing to NVRAM failed\n");
1061 * PHY initialization
1064 bcm_mii_phy_init( void )
1066 static const uint32_t PHY_STAT_R = (uint32_t) 0x01;
1067 static const uint32_t AUX_STAT_R = (uint32_t) 0x19;
1068 static const uint32_t MODE_GMII = BIT32( 3 );
1069 static const uint32_t MODE_MII = BIT32( 2 );
1070 static const uint32_t NEG_POLARITY = BIT32( 10 );
1071 static const uint32_t MII_MSK = ( MODE_GMII | MODE_MII );
1072 static const uint16_t GIGA_ETH = ( BIT16( 10 ) | BIT16( 9 ) );
1077 * enable MDI communication
1079 bcm_write_reg32( MDI_CTRL_R, (uint32_t) 0x0 );
1087 // register needs to be read twice!
1088 bcm_mii_read16( PHY_STAT_R, &v );
1089 bcm_mii_read16( PHY_STAT_R, &v );
1091 ( ( v & BIT16( 2 ) ) == 0 ) );
1095 printf( "bcm57xx: link is down\n" );
1101 printf( "bcm57xx: link is up\n" );
1103 if( !IS_COPPER_PHY ) {
1108 * setup GMII or MII interface
1110 i = bcm_read_reg32( ETH_MAC_MODE_R );
1112 * read status register twice, since the first
1113 * read fails once between here and the moon...
1115 bcm_mii_read16( AUX_STAT_R, &v );
1116 bcm_mii_read16( AUX_STAT_R, &v );
1118 if( ( v & GIGA_ETH ) == GIGA_ETH ) {
1120 printf( "bcm57xx: running PHY in GMII mode (1000BaseT)\n" );
1123 if( ( i & MII_MSK ) != MODE_GMII ) {
1130 printf( "bcm57xx: running PHY in MII mode (10/100BaseT)\n" );
1133 if( ( i & MII_MSK ) != MODE_MII ) {
1140 if( IS_5704 && !IS_SERDES ) {
1142 printf( "bcm57xx: set the link ready signal for 5704C to negative polarity\n" );
1144 i |= NEG_POLARITY; // set the link ready signal for 5704C to negative polarity
1147 bcm_write_reg32( ETH_MAC_MODE_R, i );
1153 bcm_tbi_phy_init( void )
1158 * set TBI mode full duplex
1160 bcm_clrb_reg32( ETH_MAC_MODE_R, BIT32( 1 ) );
1161 bcm_setb_reg32( ETH_MAC_MODE_R, BIT32( 2 ) | BIT32( 3 ) );
1164 * enable MDI communication
1166 bcm_write_reg32( MDI_CTRL_R, (uint32_t) 0x0 );
1168 /* Disable link change interrupt. */
1169 bcm_write_reg32( ETH_MAC_EVT_EN_R, 0 );
1174 bcm_clrb_reg32( ETH_MAC_MODE_R, BIT32( 10 ) );
1177 * wait for sync/config changes
1179 for( i = 0; i < 100; i++ ) {
1180 bcm_write_reg32( ETH_MAC_STAT_R,
1181 BIT32( 3 ) | BIT32( 4 ) );
1185 if( ( bcm_read_reg32( ETH_MAC_STAT_R ) &
1186 ( BIT32( 3 ) | BIT32( 4 ) ) ) == 0 ) {
1193 * wait for sync to come up
1195 for( i = 0; i < 100; i++ ) {
1197 if( ( bcm_read_reg32( ETH_MAC_STAT_R ) & BIT32( 0 ) ) != 0 ) {
1204 if( ( bcm_read_reg32( ETH_MAC_STAT_R ) & BIT32( 0 ) ) == 0) {
1206 printf( "bcm57xx: link is down\n" );
1212 * clear all attentions
1214 bcm_write_reg32( ETH_MAC_STAT_R, (uint32_t) ~0 );
1218 printf( "bcm57xx: link is up\n" );
1224 bcm_phy_init( void )
1226 static const uint16_t SRAM_HW_CFG = (uint16_t) 0x0b58;
1228 int32_t l_ret_i32 = 0;
1231 * get HW configuration from SRAM
1233 l_val_u32 = bcm_read_mem32( SRAM_HW_CFG );
1234 l_val_u32 &= ( BIT32( 5 ) | BIT32( 4 ) );
1236 switch( l_val_u32 ) {
1239 printf( "bcm57xx: copper PHY detected\n" );
1242 bcm_device_u64 |= BCM_DEV_COPPER;
1243 l_ret_i32 = bcm_mii_phy_init();
1248 printf( "bcm57xx: fiber PHY detected\n" );
1253 printf( "bcm57xx: running PHY in gmii/mii mode\n" );
1255 l_ret_i32 = bcm_mii_phy_init();
1258 printf( "bcm57xx: running PHY in tbi mode\n" );
1260 l_ret_i32 = bcm_tbi_phy_init();
1267 printf( "bcm57xx: unknown PHY type detected, terminating\n" );
1278 * ring initialization
1281 bcm_init_rxprod_ring( void )
1287 * clear out the whole rx prod ring for sanity
1289 memset( (void *) &bcm_rxprod_ring,
1291 BCM_RXPROD_RING_SIZE * sizeof( bcm_rxbd_t ) );
1295 * assign buffers & indices to the ring members
1297 for( i = 0; i < BCM_MAX_RX_BUF; i++ ) {
1298 bcm_rxprod_ring[i].m_hostaddr_st.m_hi_u32 =
1299 (uint32_t) ( (uint64_t) &bcm_rx_buffer_pu08[i] >> 32 );
1300 bcm_rxprod_ring[i].m_hostaddr_st.m_lo_u32 =
1301 (uint32_t) ( (uint64_t) &bcm_rx_buffer_pu08[i] &
1302 (uint64_t) 0xffffffff );
1303 bcm_rxprod_ring[i].m_idxlen_u32 = ( i << 16 );
1304 bcm_rxprod_ring[i].m_idxlen_u32 += BCM_BUF_SIZE;
1308 * clear rcb registers & disable rings
1309 * NOTE: mini & jumbo rings are not supported,
1310 * still rcb's are cleaned out for sanity
1312 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_JUM ), RCB_FLAG_RING_DISABLED );
1313 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_JUM ), 0 );
1314 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_JUM ), 0 );
1315 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_JUM ), 0 );
1317 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_STD ), RCB_FLAG_RING_DISABLED );
1318 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_STD ), 0 );
1319 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_STD ), 0 );
1320 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_STD ), 0 );
1322 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_MIN ), RCB_FLAG_RING_DISABLED );
1323 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_MIN ), 0 );
1324 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_MIN ), 0 );
1325 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_MIN ), 0 );
1328 * clear rx producer index of std producer ring
1330 bcm_write_reg32( RXPROD_PROD_IND, 0 );
1333 * setup rx standard rcb using recommended NIC addr (hard coded)
1335 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_STD ),
1336 (uint32_t) ( (uint64_t) &bcm_rxprod_ring >> 32 ) );
1337 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_STD ),
1338 (uint32_t) ( (uint64_t) &bcm_rxprod_ring & (uint64_t) 0xffffffff ) );
1339 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_STD ),
1340 (uint32_t) BCM_NIC_RX_OFFS );
1342 if( IS_5704 || IS_5703 ) {
1343 // 5704: length field = max buffer len
1344 v = (uint32_t) BCM_BUF_SIZE << 16;
1346 // 5714: length field = number of ring entries
1347 v = (uint32_t) BCM_RXPROD_RING_SIZE << 16;
1350 v &= (uint32_t) ~RCB_FLAG_RING_DISABLED;
1351 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_STD ), v );
1355 bcm_init_rxret_ring( void )
1361 * clear out the whole rx ret ring for sanity
1363 memset( (void *) &bcm_rxret_ring,
1365 2 * BCM_RXRET_RING_SIZE * sizeof( bcm_rxbd_t ) );
1369 * setup return ring size dependent on installed device
1371 bcm_rxret_ring_sz = BCM_RXRET_RING_SIZE;
1372 if( IS_5704 || IS_5703 ) {
1373 bcm_rxret_ring_sz *= 2;
1377 * clear rcb memory & disable rings
1378 * NOTE: 5714 only supports one return ring,
1379 * still all possible rcb's are cleaned out for sanity
1381 v = BCM_RXRET_RCB_OFFS;
1382 for( i = 0; i < BCM_MAX_RXRET_RING; i++ ) {
1383 bcm_write_mem32( BCM_RCB_LENFLAG_u16( v ), RCB_FLAG_RING_DISABLED );
1384 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( v ), 0 );
1385 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( v ), 0 );
1386 bcm_write_mem32( BCM_RCB_NICADDR_u16( v ), 0 );
1388 v += BCM_RCB_SIZE_u16;
1392 * clear rx consumer index of return ring
1394 bcm_write_reg32( RXRET_CONS_IND, 0 );
1398 * NOTE: NIC address not aplicable in return rings
1400 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXRET_RCB_OFFS ),
1401 (uint32_t) ( (uint64_t) &bcm_rxret_ring >> 32 ) );
1402 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXRET_RCB_OFFS ),
1403 (uint32_t) ( (uint64_t) &bcm_rxret_ring &
1404 (uint64_t) 0xffffffff ) );
1405 bcm_write_mem32( BCM_RCB_NICADDR_u16( BCM_RXRET_RCB_OFFS ), 0 );
1407 i = bcm_rxret_ring_sz;
1409 i &= (uint32_t) ~RCB_FLAG_RING_DISABLED;
1410 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXRET_RCB_OFFS ), i );
1414 bcm_init_tx_ring( void )
1420 * clear out the whole tx ring for sanity
1422 memset( (void *) &bcm_tx_ring,
1424 BCM_TX_RING_SIZE * sizeof( bcm_txbd_t ) );
1428 * assign buffers to the ring members & setup invariant flags
1430 for( i = 0; i < BCM_MAX_TX_BUF; i++ ) {
1431 bcm_tx_ring[i].m_hostaddr_st.m_hi_u32 =
1432 (uint32_t) ( (uint64_t) &bcm_tx_buffer_pu08[i] >> 32 );
1433 bcm_tx_ring[i].m_hostaddr_st.m_lo_u32 =
1434 (uint32_t) ( (uint64_t) &bcm_tx_buffer_pu08[i] &
1435 (uint64_t) 0xffffffff );
1436 // flags: indicate last packet & coal now
1437 // -last packet is always true (only one send packet supported)
1438 // -coal now needed to always get the consumed bd's (since
1439 // only a few bd's are set up which permanently are recycled)
1440 bcm_tx_ring[i].m_lenflags_u32 = ( BIT32( 2 ) | BIT32( 7 ) );
1441 bcm_tx_ring[i].m_VLANtag_u32 = (uint32_t) 0; // not used
1445 * clear rcb memory & disable rings
1446 * NOTE: 5714 only supports one send ring,
1447 * still all possible rcb's are cleaned out for sanity
1449 v = BCM_TX_RCB_OFFS;
1450 for( i = 0; i < BCM_MAX_TX_RING; i++ ) {
1451 bcm_write_mem32( BCM_RCB_LENFLAG_u16( v ), RCB_FLAG_RING_DISABLED );
1452 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( v ), 0 );
1453 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( v ), 0 );
1454 bcm_write_mem32( BCM_RCB_NICADDR_u16( v ), 0 );
1456 v += BCM_RCB_SIZE_u16;
1460 * clear host/nic producer indices
1462 bcm_write_reg32( TX_NIC_PROD_IND, 0 );
1463 bcm_write_reg32( TX_PROD_IND, 0 );
1466 * setup tx rcb using recommended NIC addr (hard coded)
1468 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( BCM_TX_RCB_OFFS ),
1469 (uint32_t) ( (uint64_t) &bcm_tx_ring >> 32 ) );
1470 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( BCM_TX_RCB_OFFS ),
1471 (uint32_t) ( (uint64_t) &bcm_tx_ring &
1472 (uint64_t) 0xffffffff ) );
1473 bcm_write_mem32( BCM_RCB_NICADDR_u16( BCM_TX_RCB_OFFS ),
1474 (uint32_t) BCM_NIC_TX_OFFS );
1476 if( IS_5704 || IS_5703 ) {
1477 // 5704: length field = max buffer len
1478 i = (uint32_t) BCM_BUF_SIZE << 16;
1480 // 5714: length field = number of ring entries
1481 i = (uint32_t) BCM_TX_RING_SIZE << 16;
1484 i &= ( uint32_t ) ~RCB_FLAG_RING_DISABLED;
1485 bcm_write_mem32( BCM_RCB_LENFLAG_u16( BCM_TX_RCB_OFFS ), i );
1488 * remember the next bd index to be used
1489 * & number of available buffers
1491 bcm_tx_stop_u32 = BCM_MAX_TX_BUF;
1492 bcm_tx_bufavail_u32 = BCM_MAX_TX_BUF;
1496 bcm_mac_init( uint8_t *f_mac_pu08 )
1498 static const uint16_t MEM_MAC_LO = (uint16_t) 0x0c18;
1499 static const uint16_t MEM_MAC_HI = (uint16_t) 0x0c14;
1501 uint32_t NVR_MAC_LO = (uint16_t) 0x80;
1502 uint32_t NVR_MAC_HI = (uint16_t) 0x7c;
1504 bcm_addr64_t l_mac_st;
1509 * Use MAC address from device tree if possible
1511 for( i = 0, v = 0; i < 6; i++ ) {
1512 v += (uint32_t) f_mac_pu08[i];
1516 l_mac_st.m_hi_u32 = ( ( (uint32_t) f_mac_pu08[0]) << 8 );
1517 l_mac_st.m_hi_u32 |= ( ( (uint32_t) f_mac_pu08[1]) << 0 );
1518 l_mac_st.m_lo_u32 = ( ( (uint32_t) f_mac_pu08[2]) << 24 );
1519 l_mac_st.m_lo_u32 |= ( ( (uint32_t) f_mac_pu08[3]) << 16 );
1520 l_mac_st.m_lo_u32 |= ( ( (uint32_t) f_mac_pu08[4]) << 8 );
1521 l_mac_st.m_lo_u32 |= ( ( (uint32_t) f_mac_pu08[5]) << 0 );
1524 * try to read MAC address from MAC mailbox
1526 l_mac_st.m_hi_u32 = bcm_read_mem32( MEM_MAC_HI );
1528 if( ( l_mac_st.m_hi_u32 >> 16 ) == (uint32_t) 0x484b ) {
1529 l_mac_st.m_hi_u32 &= (uint32_t) 0xffff;
1530 l_mac_st.m_lo_u32 = bcm_read_mem32( MEM_MAC_LO );
1535 * otherwise retrieve MAC address from NVRam
1537 if( ( bcm_read_reg32( MAC_FUNC_R ) & BIT32( 2 ) ) != 0 ) {
1538 // secondary MAC is in use, address in NVRAM changes
1543 l_err_i32 = bcm_nvram_read( NVR_MAC_LO, &l_mac_st.m_lo_u32, 1 );
1544 l_err_i32 += bcm_nvram_read( NVR_MAC_HI, &l_mac_st.m_hi_u32, 1 );
1546 // return on read error
1547 if( l_err_i32 < 0 ) {
1549 printf( "bcm57xx: failed to retrieve MAC address\n" );
1557 * write the mac addr into the NIC's register area
1559 bcm_write_reg32( MAC_ADDR_OFFS_HI(0), l_mac_st.m_hi_u32 );
1560 bcm_write_reg32( MAC_ADDR_OFFS_LO(0), l_mac_st.m_lo_u32 );
1561 for( i = 1; i < BCM_NUM_MAC_ADDR; i++ ) {
1562 bcm_write_reg32( MAC_ADDR_OFFS_HI(i), 0 );
1563 bcm_write_reg32( MAC_ADDR_OFFS_LO(i), 0 );
1568 * not needed anymore, s.a.
1569 if( IS_5704 != 0 ) {
1571 v = MAC5704_ADDR_OFFS;
1572 for( i = 0; i < BCM_NUM_MAC5704_ADDR; i++ ) {
1573 bcm_write_reg32( v, l_mac_st.m_hi_u32 );
1574 v += sizeof( uint32_t );
1575 bcm_write_reg32( v, l_mac_st.m_lo_u32 );
1576 v += sizeof( uint32_t );
1583 * return MAC address as string
1585 f_mac_pu08[0] = (uint8_t) ( ( l_mac_st.m_hi_u32 >> 8 ) & (uint32_t) 0xff );
1586 f_mac_pu08[1] = (uint8_t) ( ( l_mac_st.m_hi_u32 ) & (uint32_t) 0xff );
1587 f_mac_pu08[2] = (uint8_t) ( ( l_mac_st.m_lo_u32 >> 24 ) & (uint32_t) 0xff );
1588 f_mac_pu08[3] = (uint8_t) ( ( l_mac_st.m_lo_u32 >> 16 ) & (uint32_t) 0xff );
1589 f_mac_pu08[4] = (uint8_t) ( ( l_mac_st.m_lo_u32 >> 8 ) & (uint32_t) 0xff );
1590 f_mac_pu08[5] = (uint8_t) ( ( l_mac_st.m_lo_u32 ) & (uint32_t) 0xff );
1595 printf( "bcm57xx: retrieved MAC address " );
1597 for( i = 0; i < 6; i++ ) {
1598 printf( "%02X", f_mac_pu08[i] );
1615 ******************************************************************************
1617 ******************************************************************************
1622 #ifdef BCM_SHOW_ASF_REGS
1624 bcm_asf_check_register( void )
1628 i = bcm_read_reg32( ASF_CTRL_R );
1629 printf( "bcm57xx: ASF control : %x\n", i );
1631 i = bcm_read_reg32( ASF_WATCHDOG_TIMER_R );
1632 printf( "bcm57xx: ASF Watchdog Timer : %x\n", i );
1634 i = bcm_read_reg32( ASF_HEARTBEAT_TIMER_R );
1635 printf( "bcm57xx: ASF Heartbeat Timer : %x\n", i );
1637 i = bcm_read_reg32( ASF_POLL_TIMER_R );
1638 printf( "bcm57xx: ASF Poll Timer : %x\n", i );
1640 i = bcm_read_reg32( POLL_LEGACY_TIMER_R );
1641 printf( "bcm57xx: Poll Legacy Timer : %x\n", i );
1643 i = bcm_read_reg32( RETRANSMISSION_TIMER_R );
1644 printf( "bcm57xx: Retransmission Timer : %x\n", i );
1646 i = bcm_read_reg32( TIME_STAMP_COUNTER_R );
1647 printf( "bcm57xx: Time Stamp Counter : %x\n", i );
1649 i = bcm_read_reg32( RX_CPU_MODE_R );
1650 printf( "bcm57xx: RX RISC Mode : %x\n", i );
1652 i = bcm_read_reg32( RX_CPU_STATE_R );
1653 printf( "bcm57xx: RX RISC State : %x\n", i );
1655 i = bcm_read_reg32( RX_CPU_PC_R );
1656 printf( "bcm57xx: RX RISC Prg. Counter : %x\n", i );
1666 bcm_write_mem32( BCM_FW_MBX_CMD, BCM_NICDRV_PAUSE_FW );
1667 bcm_setb_reg32( RX_CPU_EVENT_R, BIT32( 14 ) );
1669 /* Wait for RX cpu to ACK the event. */
1670 for (i = 0; i < 100; i++) {
1671 if(bcm_read_reg32( RX_CPU_EVENT_R ) & BIT32( 14 ))
1681 #ifdef BCM_SW_AUTONEG
1683 bcm_sw_autoneg( void ) {
1686 uint32_t SgDigControl;
1687 uint32_t SgDigStatus;
1688 uint32_t ExpectedSgDigControl;
1689 int AutoNegJustInitiated = 0;
1691 // step 1: init TX 1000BX Autoneg. Register to zero
1692 bcm_write_reg32(TX_1000BX_AUTONEG_R, 0);
1694 // step 2&3: set TBI mode
1695 bcm_setb_reg32( ETH_MAC_MODE_R, BIT32( 2 ) | BIT32( 3 ) );
1698 // step 4: enable link attention
1699 bcm_setb_reg32( ETH_MAC_EVT_EN_R, BIT32( 12 ) );
1701 // step 5: preserve voltage regulator bits
1702 SerDesCfg = bcm_read_reg32(SERDES_CTRL_R) & ( BIT32( 20 ) | BIT32( 21 )
1703 | BIT32( 22 ) | BIT32( 23 ) );
1705 // step 6: preserve voltage regulator bits
1706 SgDigControl = bcm_read_reg32(HW_AUTONEG_CTRL_R);
1708 // step 7: if device is NOT set-up for auto negotiation, then go to step 26
1709 // goto bcm_setup_phy_step26;
1711 // We want to use auto negotiation
1713 // step 8: we don't want to use flow control
1714 ExpectedSgDigControl = 0x81388400; // no flow control
1716 // step 9: compare SgDigControl with 0x81388400
1717 if(SgDigControl == ExpectedSgDigControl) {
1718 goto bcm_setup_phy_step17;
1721 printf("bcm57xx: SgDigControl = %08X\n", SgDigControl);
1724 bcm_write_reg32(SERDES_CTRL_R, SerDesCfg | 0xC011880);
1726 // step 11: restart auto negotiation
1727 bcm_write_reg32(HW_AUTONEG_CTRL_R, ExpectedSgDigControl | BIT32( 30 ) );
1729 // step 12: read back HW_AUTONEG_CTRL_R
1730 bcm_read_reg32(HW_AUTONEG_CTRL_R);
1735 // step 14,15,16: same as step 11, but don't restart auto neg.
1736 bcm_write_reg32(HW_AUTONEG_CTRL_R, ExpectedSgDigControl);
1737 AutoNegJustInitiated = 1;
1738 goto bcm_setup_phy_step30;
1741 bcm_setup_phy_step17:
1742 if( ( bcm_read_reg32(ETH_MAC_STAT_R) & ( BIT32( 1 ) | BIT32( 0 ) ) ) == 0 ) {
1743 goto bcm_setup_phy_step30;
1746 // step 18: Get HW Autoneg. Status
1747 SgDigStatus = bcm_read_reg32(HW_AUTONEG_STAT_R);
1750 if( ( SgDigStatus & BIT32(1) )
1751 && ( bcm_read_reg32(ETH_MAC_STAT_R) & BIT32(0) ) ) {
1752 // resolve the current flow control?
1753 AutoNegJustInitiated = 0;
1754 goto bcm_setup_phy_step30;
1758 if( SgDigStatus & BIT32(1) ) {
1759 goto bcm_setup_phy_step30;
1761 if( AutoNegJustInitiated != 0) {
1762 AutoNegJustInitiated = 0;
1763 goto bcm_setup_phy_step29;
1766 // step 21, 22, 23, 24: fallback to 1000Mbps-FullDuplex forced mode
1767 if( ( bcm_read_reg32( MAC_FUNC_R ) & BIT32( 2 ) ) == 0 ) {
1769 bcm_write_reg32( SERDES_CTRL_R, 0xC010880 );
1772 bcm_write_reg32( SERDES_CTRL_R, 0x4010880 );
1774 // set to 1000Mbps-FullDuplex
1775 bcm_write_reg32(HW_AUTONEG_CTRL_R, 0x1388400);
1777 bcm_read_reg32(HW_AUTONEG_CTRL_R);
1780 // step 25: a little bit reduces...
1781 goto bcm_setup_phy_step30;
1783 // step 26: check if auto negotiation bit is NOT set
1784 // bcm_setup_phy_step26:
1785 if( ( SgDigControl & BIT32(31) )== 0 ) {
1786 printf("No autoneg.\n");
1787 goto bcm_setup_phy_step29;
1791 if( ( bcm_read_reg32( MAC_FUNC_R ) & BIT32( 2 ) ) == 0 ) {
1793 bcm_write_reg32( SERDES_CTRL_R, 0xC010880 );
1796 bcm_write_reg32( SERDES_CTRL_R, 0x4010880 );
1799 // step 28: disable auto neg. and force 1000FD mode
1800 bcm_write_reg32(HW_AUTONEG_CTRL_R, 0x1388400);
1802 // step 29-31: omitted for 5704S
1803 bcm_setup_phy_step29:
1804 bcm_setup_phy_step30:
1806 // step 32: clear link attentions
1807 i = bcm_read_reg32( ETH_MAC_STAT_R ) | BIT32( 3 ) | BIT32( 4 );
1810 bcm_write_reg32( ETH_MAC_STAT_R, i );
1811 j = bcm_read_reg32( ETH_MAC_STAT_R );
1812 if( ( j & BIT32( 3 ) ) != 0 )
1813 i = i & ~(BIT32( 3 ));
1814 if( ( j & BIT32( 4 ) ) != 0 )
1815 i = i & ~(BIT32( 4 ));
1820 if( ( bcm_read_reg32( ETH_MAC_STAT_R ) & BIT32( 0 ) ) == 0 ) {
1821 goto bcm_setup_phy_step35;
1825 i = bcm_read_reg32( ETH_MAC_MODE_R );
1827 bcm_write_reg32( ETH_MAC_MODE_R, i );
1831 i = bcm_read_reg32( ETH_MAC_STAT_R );
1833 bcm_write_reg32( ETH_MAC_STAT_R, i );
1835 // step 35 & 36: done
1836 bcm_setup_phy_step35:
1838 printf("bcm57xx: SetupPhy\n");
1845 bcm_handle_events( void ) {
1847 #ifdef BCM_SHOW_ASF_REGS
1848 // ASF REGISTER CHECK
1849 // ------------------
1850 // check if watchdog timer expired
1851 if( bcm_read_reg32( ASF_WATCHDOG_TIMER_R ) == 0 ) {
1852 // Show ASF registers
1853 bcm_asf_check_register();
1855 // rearm watchdog timer
1856 bcm_write_reg32( ASF_WATCHDOG_TIMER_R, 5 );
1861 #ifdef BCM_SW_AUTONEG
1865 // Check event for Auto Negotiation
1866 if( ( bcm_read_reg32( ETH_MAC_STAT_R ) &
1867 ( BIT32( 12 ) | BIT32( 3 ) | BIT32( 0 ) ) ) != 0 ) {
1868 // link timer procedure
1876 // check if heartsbeat timer expired
1877 if( bcm_read_reg32( ASF_HEARTBEAT_TIMER_R ) <= 2) {
1880 // Send heartbeat event
1881 bcm_write_mem32( BCM_FW_MBX_CMD, BCM_NICDRV_ALIVE );
1882 bcm_write_mem32( BCM_FW_MBX_LEN, 4 );
1883 bcm_write_mem32( BCM_FW_MBX_DATA, 5 );
1884 bcm_setb_reg32( RX_CPU_EVENT_R, BIT32( 14 ) );
1886 // Wait for RX cpu to ACK the event.
1887 for (i = 100; i > 0; i--) {
1888 if(bcm_read_reg32( RX_CPU_EVENT_R ) & BIT32( 14 ))
1894 printf( "bcm57xx: RX cpu did not acknowledge heartbeat event\n" );
1899 // rearm heartbeat timer
1900 bcm_write_reg32( ASF_HEARTBEAT_TIMER_R, 5 );
1907 ******************************************************************************
1914 bcm_receive( char *f_buffer_pc, int f_len_i )
1916 uint32_t l_rxret_prod_u32 = bcm_read_reg32( RXRET_PROD_IND );
1917 uint32_t l_rxret_cons_u32 = bcm_read_reg32( RXRET_CONS_IND );
1918 uint32_t l_rxprod_prod_u32 = bcm_read_reg32( RXPROD_PROD_IND );
1921 #ifdef BCM_SHOW_RCV_DATA
1927 * NOTE: dummy read to ensure data has already been DMA'd is
1928 * done by the indice reads
1931 bcm_handle_events();
1934 * if producer index == consumer index then nothing was received
1936 if( l_rxret_prod_u32 == l_rxret_cons_u32 ) {
1941 * discard erroneous packets
1943 if( ( bcm_rxret_ring[l_rxret_cons_u32].m_typeflags_u32 & BIT32( 10 ) ) != 0 ) {
1945 printf( "bcm57xx: erroneous frame received\n" );
1946 printf( " : frame discarded\n" );
1951 * get packet length, throw away checksum (last 4 bytes)
1953 l_ret_i = (int) ( bcm_rxret_ring[l_rxret_cons_u32].m_idxlen_u32 &
1954 (uint32_t) 0xffff ) - (int) 4;
1957 * discard oversized packets
1959 if( l_ret_i > f_len_i ) {
1961 printf( "bcm57xx: receive packet length error:\n" );
1962 printf( " : incoming 0x%X bytes, available buffer 0x%X bytes\n", l_ret_i, f_len_i );
1963 printf( " : frame discarded\n" );
1971 * copy & update data & indices
1973 if( l_ret_i != 0 ) {
1974 uint64_t l_cpyaddr_u64;
1977 ( (uint64_t) bcm_rxret_ring[l_rxret_cons_u32].m_hostaddr_st.m_hi_u32 << 32 );
1979 ( (uint64_t) bcm_rxret_ring[l_rxret_cons_u32].m_hostaddr_st.m_lo_u32 );
1982 if(l_cpyaddr_u64 == 0) {
1984 printf("bcm57xx: NULL address\n");
1989 memcpy( (void *) f_buffer_pc,
1990 (void *) l_cpyaddr_u64,
1996 * replenish bd to producer ring
1998 bcm_rxprod_ring[l_rxprod_prod_u32] =
1999 bcm_rxret_ring[l_rxret_cons_u32];
2000 bcm_rxprod_ring[l_rxprod_prod_u32].m_idxlen_u32 =
2001 ( l_rxprod_prod_u32 << 16 );
2002 bcm_rxprod_ring[l_rxprod_prod_u32].m_idxlen_u32 +=
2003 (uint32_t) BCM_BUF_SIZE;
2006 * update producer ring's producer index
2008 l_rxprod_prod_u32 = ( l_rxprod_prod_u32 + 1 ) & ( BCM_RXPROD_RING_SIZE - 1 );
2011 * move to the next bd in return ring
2013 l_rxret_cons_u32 = ( l_rxret_cons_u32 + 1 ) & ( bcm_rxret_ring_sz - 1 );
2016 * synchronize before new indices are send to NIC
2021 * write back new indices
2023 bcm_write_reg32( RXRET_CONS_IND, l_rxret_cons_u32 );
2024 bcm_write_reg32( RXPROD_PROD_IND, l_rxprod_prod_u32 );
2028 if( l_ret_i != 0 ) {
2029 printf( "bcm57xx: received bytes: %d\n", l_ret_i );
2031 #ifdef BCM_SHOW_RCV_DATA
2032 for( i = 0, j = 0; i < l_ret_i; i++ ) {
2033 printf( "%02X ", ( uint32_t ) f_buffer_pc[i] );
2035 if( ( ++j % 0x18 ) == 0 ) {
2040 if( ( i % 0x18 ) != 0 ) {
2048 * return packet length
2054 bcm_xmit( char *f_buffer_pc, int f_len_i )
2056 uint32_t l_tx_cons_u32 = bcm_read_reg32( TX_CONS_IND );
2057 uint32_t l_tx_prod_u32 = bcm_read_reg32( TX_PROD_IND );
2058 uint64_t l_cpyaddr_u64;
2061 #ifdef BCM_SHOW_XMIT_DATA
2066 printf( "bcm57xx: TX_PROD_IND : 0x%03X\n", l_tx_prod_u32 );
2067 printf( "bcm57xx: TX_CONS_IND : 0x%03X\n", l_tx_cons_u32 );
2068 printf( "bcm57xx: RXPROD_PROD_IND: 0x%03X\n", bcm_read_reg32( RXPROD_PROD_IND ) );
2069 printf( "bcm57xx: RXPROD_CONS_IND: 0x%03X\n", bcm_read_reg32( RXPROD_CONS_IND ) );
2070 printf( "bcm57xx: RXRET_PROD_IND : 0x%03X\n", bcm_read_reg32( RXRET_PROD_IND ) );
2071 printf( "bcm57xx: RXRET_CONS_IND : 0x%03X\n", bcm_read_reg32( RXRET_CONS_IND ) );
2072 printf( "bcm57xx: available txb : 0x%03X\n", bcm_tx_bufavail_u32 );
2074 #ifdef BCM_SHOW_STATS
2075 printf( "bcm57xx: bcm_status.m_st_word_u32: %08X\n", bcm_status.m_st_word_u32 );
2076 printf( "bcm57xx: bcm_status.m_st_tag_u32 : %08X\n", bcm_status.m_st_tag_u32 );
2077 printf( "bcm57xx: bcm_status.m_rxprod_cons_u16: %04X\n", ( uint32_t ) bcm_status.m_rxprod_cons_u16 );
2078 printf( "bcm57xx: bcm_status.m_unused_u16: %04X\n", ( uint32_t ) bcm_status.m_unused_u16 );
2079 printf( "bcm57xx: bcm_status.m_unused_u32: %08X\n", bcm_status.m_unused_u32 );
2080 printf( "bcm57xx: bcm_status.m_tx_cons_u16: %04X\n", ( uint32_t ) bcm_status.m_tx_cons_u16 );
2081 printf( "bcm57xx: bcm_status.m_rxret_prod_u16: %04X\n", ( uint32_t ) bcm_status.m_rxret_prod_u16 );
2085 bcm_handle_events();
2088 * make all consumed bd's available in the ring again
2089 * this way only a few buffers are needed instead of
2090 * having 512 buffers allocated
2092 while( bcm_tx_start_u32 != l_tx_cons_u32 ) {
2093 bcm_tx_ring[bcm_tx_stop_u32] = bcm_tx_ring[bcm_tx_start_u32];
2094 bcm_tx_stop_u32 = ( bcm_tx_stop_u32 + 1 ) & ( BCM_TX_RING_SIZE - 1 );
2095 bcm_tx_start_u32 = ( bcm_tx_start_u32 + 1 ) & ( BCM_TX_RING_SIZE - 1 );
2096 bcm_tx_bufavail_u32++;
2100 * check for tx buffer availability
2102 if( bcm_tx_bufavail_u32 == 0 ) {
2104 printf( "bcm57xx: no more transmit buffers available\n" );
2110 * setup next available bd in tx ring
2112 bcm_tx_ring[l_tx_prod_u32].m_lenflags_u32 = ( BIT32( 2 ) | BIT32( 7 ) /*| BIT32( 6 )*/ );
2113 bcm_tx_ring[l_tx_prod_u32].m_lenflags_u32 += ( (uint32_t) f_len_i << 16 );
2114 // bcm_tx_ring[l_tx_prod_u32].m_VLANtag_u32 = BCM_VLAN_TAG;
2116 l_cpyaddr_u64 = ( (uint64_t) bcm_tx_ring[l_tx_prod_u32].m_hostaddr_st.m_hi_u32 << 32 );
2117 l_cpyaddr_u64 += ( (uint64_t) bcm_tx_ring[l_tx_prod_u32].m_hostaddr_st.m_lo_u32 );
2120 #ifdef BCM_SHOW_XMIT_STATS
2121 printf("bcm57xx: xmit: l_cpyaddr_u64: 0x%lx\n", l_cpyaddr_u64 );
2122 printf(" f_buffer_pc : 0x%lx\n", f_buffer_pc );
2123 printf(" f_len_i : %d\n", f_len_i );
2126 memcpy( (void *) l_cpyaddr_u64, (void *) f_buffer_pc, (size_t) f_len_i );
2129 * update tx producer index & available buffers
2131 l_tx_prod_u32 = ( l_tx_prod_u32 + 1 ) & ( BCM_TX_RING_SIZE - 1 );
2132 bcm_tx_bufavail_u32--;
2135 * synchronize before new index is send to NIC
2139 bcm_write_reg32( TX_PROD_IND, l_tx_prod_u32 );
2142 #ifdef BCM_SHOW_XMIT
2143 printf( "bcm57xx: sent bytes: %d\n", f_len_i );
2144 #ifdef BCM_SHOW_XMIT_DATA
2145 for( i = 0, j = 0; i < f_len_i; i++ ) {
2146 printf( "%02X ", ( uint32_t ) f_buffer_pc[i] );
2148 if( ( ++j % 0x18 ) == 0 ) {
2153 if( ( i % 0x18 ) != 0 ) {
2159 #ifdef BCM_SHOW_STATS
2160 // coalesce status block now
2161 bcm_setb_reg32( HOST_COAL_MODE_R, BIT32( 3 ) | BIT32( 1 ) );
2169 check_driver( uint16_t vendor_id, uint16_t device_id )
2174 * checks whether the driver is handling this device
2175 * by verifying vendor & device id
2176 * vendor id 0x14e4 == Broadcom
2178 if( vendor_id != 0x14e4 ) {
2180 printf( "bcm57xx: netdevice not supported, illegal vendor id\n" );
2185 for( i = 0; bcm_dev[i].m_dev_u32 != 0; i++ ) {
2186 if( bcm_dev[i].m_dev_u32 == (uint32_t) device_id ) {
2192 if(bcm_dev[i].m_dev_u32 == 0) {
2194 printf( "bcm57xx: netdevice not supported, illegal device ID\n" );
2200 * initialize static variables
2202 bcm_device_u64 = bcm_dev[i].m_devmsk_u64;
2203 bcm_rxret_ring_sz = 0;
2204 bcm_baseaddr_u64 = 0;
2205 bcm_memaddr_u64 = 0;
2207 bcm_tx_start_u32 = 0;
2208 bcm_tx_stop_u32 = 0;
2209 bcm_tx_bufavail_u32 = 0;
2215 bcm_wol_activate(void)
2218 uint16_t reg_pwr_cap;
2220 uint16_t reg_pwr_crtl;
2223 wol_mode = bcm_read_reg32( WOL_MODE_R );
2224 bcm_write_reg32( WOL_MODE_R, wol_mode | BIT32(0) );
2227 printf( "bcm57xx: WOL activating..." );
2230 // bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_WOL );
2231 // SLOF_msleep( 100 );
2234 reg_pwr_cap = SLOF_pci_config_read16(0x4a);
2235 /*reg_pwr_cap = snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
2240 printf( "bcm57xx: PM Capability Register: %04X\n", reg_pwr_cap );
2242 /* get curretn power control register */
2243 reg_pwr_crtl = SLOF_pci_config_read16(0x4c);
2244 /*reg_pwr_crtl = snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
2251 printf( "bcm57xx: PM Control/Status Register: %04X\n", reg_pwr_crtl );
2254 /* switch to power state D0 */
2255 reg_pwr_crtl |= 0x8000;
2256 reg_pwr_crtl &= ~(0x0003);
2257 SLOF_pci_config_write16(0x4c, reg_pwr_crtl);
2258 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2267 bcm_write_mem32( BCM_NICDRV_WOL_MBX, BCM_WOL_MAGIC_NUMBER |
2268 NIC_WOLDRV_STATE_SHUTDOWN |
2270 NIC_WOLDRV_SET_MAGIC_PKT );
2273 /* switch to power state D3hot */
2275 reg_pwr_crtl |= 0x0103;
2276 SLOF_pci_config_write16(0x4c, reg_pwr_crtl);
2277 snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2287 reg_pwr_crtl = SLOF_pci_config_read16(0x4c);
2288 /*reg_pwr_crtl = snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
2294 printf( "bcm57xx: PM Control/Status Register: %04X\n", reg_pwr_crtl );
2298 printf( "bcm57xx: WOL activated" );
2303 bcm_init( net_driver_t *driver )
2305 static const uint32_t lc_Maxwait_u32 = (uint32_t) 1000;
2306 uint32_t l_baseaddrL_u32;
2307 uint32_t l_baseaddrH_u32;
2309 uint8_t *mac_addr = driver->mac_addr;
2311 if(driver->running != 0) {
2315 printf( "bcm57xx: detected device " );
2317 printf( "5703S\n" );
2318 } else if( IS_5704 ) {
2327 } else if( IS_5714 ) {
2332 * setup register & memory base addresses of NIC
2334 l_baseaddrL_u32 = (uint32_t) ~0xf &
2335 (uint32_t) SLOF_pci_config_read32(PCI_BAR1_R);
2336 /*l_baseaddrL_u32 = ( (uint32_t) ~0xf &
2337 (uint32_t) snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
2343 l_baseaddrH_u32 = (uint32_t) SLOF_pci_config_read32(PCI_BAR2_R);
2345 (uint32_t) snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
2350 bcm_baseaddr_u64 = (uint64_t) l_baseaddrH_u32;
2351 bcm_baseaddr_u64 <<= 32;
2352 bcm_baseaddr_u64 += (uint64_t) l_baseaddrL_u32;
2354 (uint64_t) SLOF_translate_my_address((void *)bcm_baseaddr_u64);
2355 /*snk_kernel_interface->translate_addr(((void *)&(bcm_baseaddr_u64)));*/
2356 bcm_memaddr_u64 = bcm_baseaddr_u64 + BCM_MEMORY_OFFS;
2359 printf( "bcm57xx: device's register base high address = 0x%08X\n", l_baseaddrH_u32 );
2360 printf( "bcm57xx: device's register base low address = 0x%08X\n", l_baseaddrL_u32 );
2361 printf( "bcm57xx: device's register address = 0x%llx\n", bcm_baseaddr_u64 );
2365 * 57xx hardware initialization
2366 * BCM57xx Programmer's Guide: Section 8, "Initialization"
2367 * steps 1 through 101
2370 // step 1: enable bus master & memory space in command reg
2371 i = ( BIT32( 10 ) | BIT32( 2 ) | BIT32( 1 ) );
2372 SLOF_pci_config_write16(PCI_COM_R, i);
2373 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2379 // step 2: disable & mask interrupts & enable pci byte/word swapping & enable indirect addressing mode
2380 i = ( BIT32( 8 ) | BIT32( 7 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
2382 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
2383 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2391 * from now on access may be made through the local
2392 * read/write functions
2395 // step 3: Save ahche line size register
2396 // omitted, because register is not used for 5704
2398 // step 4: acquire the nvram lock
2399 if( bcm_nvram_lock() != 0 ) {
2401 printf( "bcm57xx: locking NVRAM failed\n" );
2406 // step 5: prepare the chip for writing TG3_MAGIC_NUMBER
2407 bcm_setb_reg32( MEMARB_MODE_R, BIT32( 1 ) );
2408 i = ( BIT32( 8 ) | BIT32( 7 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
2409 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
2410 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2416 bcm_write_reg32( MODE_CTRL_R, BIT32( 23 ) | BIT32( 20 ) |
2417 BIT32( 17 ) | BIT32( 16 ) |
2418 BIT32( 14 ) | BIT32( 13 ) |
2419 BIT32( 5 ) | BIT32( 4 ) |
2420 BIT32( 2 ) | BIT32( 1 ) );
2422 // step 6: write TG3_MAGIC_NUMBER
2423 bcm_write_mem32( BCM_FW_MBX, BCM_MAGIC_NUMBER );
2425 // step 7: reset core clocks
2428 bcm_setb_reg32( MISC_CFG_R, BIT32( 26 ) | BIT32( 0 ) );
2430 bcm_setb_reg32( MISC_CFG_R, BIT32( 0 ) );
2435 // step 9: disable & mask interrupts & enable indirect addressing mode &
2436 // enable pci byte/word swapping initialize the misc host control register
2437 i = ( BIT32( 8 ) | BIT32( 7 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
2438 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
2439 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2446 // step 10: set but master et cetera
2447 i = ( BIT32( 10 ) | BIT32( 2 ) | BIT32( 1 ) );
2448 SLOF_pci_config_write16(PCI_COM_R, i);
2449 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2456 // step 11: disable PCI-X relaxed ordering
2457 bcm_clrb_reg16( PCI_X_COM_R, BIT16( 1 ) );
2459 // step 12: enable the MAC memory arbiter
2460 bcm_setb_reg32( MEMARB_MODE_R, BIT32( 1 ) );
2462 // step 13: omitted, only for BCM5700
2463 // step 14: s. step 10
2464 i = ( BIT32( 8 ) | BIT32( 7 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
2465 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
2466 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2472 // step 15: set byte swapping (incl. step 27/28/29/30)
2473 // included prohibition of tx/rx interrupts
2474 bcm_write_reg32( MODE_CTRL_R, BIT32( 23 ) | BIT32( 20 ) |
2475 BIT32( 17 ) | BIT32( 16 ) |
2476 BIT32( 14 ) | BIT32( 13 ) |
2477 BIT32( 5 ) | BIT32( 4 ) |
2478 BIT32( 2 ) | BIT32( 1 ) );
2482 ( bcm_read_mem32( BCM_FW_MBX ) != ~BCM_MAGIC_NUMBER ) ) {
2490 if( bcm_read_mem32( BCM_FW_MBX ) != ~BCM_MAGIC_NUMBER ) {
2491 printf( "bootcode not loaded: %x\n", bcm_read_mem32( BCM_FW_MBX ) );
2493 printf( "failed\n" );
2499 // if ASF Firmware enabled
2500 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_START );
2503 // step 17: write ethernet mac mode register
2506 * omitted for correct SOL function
2510 bcm_write_reg32( ETH_MAC_MODE_R, (uint32_t) 0xc );
2512 bcm_write_reg32( ETH_MAC_MODE_R, (uint32_t) 0x0 );
2516 // step 18/19: omitted
2517 // step 20: enable hw bugfix for 5704
2518 if( IS_5704 || IS_5703 ) {
2519 bcm_setb_reg32( MSG_DATA_R, BIT32( 26 ) |
2526 // step 23: 5704 clear statistics block
2527 if( IS_5703 || IS_5704 ) {
2528 memset_ci( (void *) ( bcm_memaddr_u64 + BCM_STATISTIC_OFFS ),
2530 BCM_STATISTIC_SIZE );
2533 // step 24/25: omitted
2534 // step 26: set DMA Read/Write Control register
2535 // NOTE: recommended values from the spec are used here
2537 bcm_write_reg32( DMA_RW_CTRL_R, DMA_RW_CTRL_VAL_5714 );
2539 uint32_t l_PCIState_u32 = bcm_read_reg32( PCI_STATE_R );
2540 uint32_t l_DMAVal_u32 = DMA_RW_CTRL_VAL;
2542 if( ( l_PCIState_u32 & BIT32( 2 ) ) != 0 ) { // PCI
2543 l_DMAVal_u32 |= (uint32_t) 0x300000;
2545 l_DMAVal_u32 |= (uint32_t) 0x900000;
2547 if( ( bcm_read_reg32( PCI_CLK_CTRL_R ) & (uint32_t) 0x1f )
2549 l_DMAVal_u32 |= (uint32_t) 0x4000;
2554 bcm_write_reg32( DMA_RW_CTRL_R, l_DMAVal_u32 );
2557 // step 27/28/29: s. step 14
2559 // step 30: Configure TCP/UDP pseudo header checksum offloading
2560 // already done in step 14: offloading disabled
2562 // step 31: setup timer prescaler
2563 i = bcm_read_reg32( MISC_CFG_R );
2564 i &= (uint32_t) ~0xfe; // clear bits 7-1 first
2565 i |= ( BCM_TMR_PRESCALE << 1 );
2566 bcm_write_reg32( MISC_CFG_R, i );
2568 // step 32: 5703/4 configure Mbuf pool address/length
2569 // step 33: 5703/4 configure MAC DMA resource pool
2570 // step 34: configure MAC memory pool watermarks
2571 // step 35: 5703/4 configure DMA resource watermarks
2572 // using recommended settings (hard coded)
2573 if( IS_5703 || IS_5704 ) {
2576 bcm_write_reg32( MBUF_POOL_ADDR_R, (uint32_t) 0x8000 );
2577 bcm_write_reg32( MBUF_POOL_LEN_R, (uint32_t) 0x18000 );
2579 bcm_write_reg32( MBUF_POOL_ADDR_R, (uint32_t) 0x10000 );
2580 bcm_write_reg32( MBUF_POOL_LEN_R, (uint32_t) 0x10000 );
2583 bcm_write_reg32( DMA_DESC_POOL_ADDR_R, (uint32_t) 0x2000 );
2584 bcm_write_reg32( DMA_DESC_POOL_LEN_R, (uint32_t) 0x2000 );
2586 bcm_write_reg32( DMA_RMBUF_LOW_WMARK_R, (uint32_t) 0x50 );
2587 bcm_write_reg32( MAC_RXMBUF_LOW_WMARK_R, (uint32_t) 0x20 );
2588 bcm_write_reg32( MBUF_HIGH_WMARK_R, (uint32_t) 0x60 );
2590 bcm_write_reg32( DMA_DESC_LOW_WM_R, (uint32_t) 5 );
2591 bcm_write_reg32( DMA_DESC_HIGH_WM_R, (uint32_t) 10 );
2593 bcm_write_reg32( DMA_RMBUF_LOW_WMARK_R, (uint32_t) 0x00 );
2594 bcm_write_reg32( MAC_RXMBUF_LOW_WMARK_R, (uint32_t) 0x10 );
2595 bcm_write_reg32( MBUF_HIGH_WMARK_R, (uint32_t) 0x60 );
2599 // step 36: Configure flow control behaviour
2600 // using recommended settings (hard coded)
2601 bcm_write_reg32( LOW_WMARK_MAX_RXFRAM_R, (uint32_t) 0x02 );
2603 // step 37/38: enable buffer manager & wait for successful start
2604 bcm_setb_reg32( BUF_MAN_MODE_R, BIT32( 2 ) | BIT32( 1 ) );
2608 ( ( bcm_read_reg32( BUF_MAN_MODE_R ) & BIT32( 1 ) ) == 0 ) ) {
2615 printf( "bcm57xx: init step 38: enable buffer manager failed\n" );
2620 // step 39: enable internal hardware queues
2621 bcm_write_reg32( FTQ_RES_R, (uint32_t) ~0 );
2622 bcm_write_reg32( FTQ_RES_R, (uint32_t) 0 );
2624 // step 40/41/42: initialize rx producer ring
2625 bcm_init_rxprod_ring();
2627 // step 43: set rx producer ring replenish threshold
2628 // using recommended setting of maximum allocated BD's/8
2629 bcm_write_reg32( STD_RXPR_REP_THR_R, (uint32_t) BCM_MAX_RX_BUF / 8 );
2631 // step 44/45/46: initialize send rings
2633 bcm_init_rxret_ring();
2635 // steps 47-50 done in ring init functions
2636 // step 51: configure MAC unicast address
2638 if( bcm_mac_init( (uint8_t *) mac_addr ) < 0 ) {
2640 printf( "bcm57xx: init step 51: configure MAC unicast address failed\n" );
2644 memcpy(driver->mac_addr, mac_addr, 6);
2646 // step 52: configure backoff random seed for transmit
2647 // using recommended algorithm
2648 i = (uint32_t) mac_addr[0] + (uint32_t) mac_addr[1] +
2649 (uint32_t) mac_addr[2] + (uint32_t) mac_addr[3] +
2650 (uint32_t) mac_addr[4] + (uint32_t) mac_addr[5];
2651 i &= (uint32_t) 0x03ff;
2652 bcm_write_reg32( ETH_TX_RND_BO_R, i );
2654 // step 53: configure message transfer unit MTU size
2655 bcm_write_reg32( RX_MTU_SIZE_R, (uint32_t) BCM_MTU_MAX_LEN );
2657 // step 54: configure IPG for transmit
2658 // using recommended value (through #define)
2659 bcm_write_reg32( TX_MAC_LEN_R, TX_MAC_LEN_VAL );
2661 // step 55: configure receive rules
2663 // set RX rule default class
2664 bcm_write_reg32( RX_RULE_CFG_R, RX_RULE_CFG_VAL );
2666 // step 56: configure the number of receive lists
2667 bcm_write_reg32( RX_LST_PLACE_CFG_R, RX_LST_PLC_CFG_VAL );
2668 bcm_write_reg32( RX_LST_PLACE_STAT_EN_R, RX_LST_PLC_STAT_EN_VAL );
2671 // rule 1: accept frames for our MAC address
2672 bcm_write_reg32( RX_RULE_CTRL_R ( 0 ),
2673 BIT32( 31 ) | // enable rule
2674 BIT32( 30 ) | // and with next
2675 BIT32( 26 ) | // split value register
2676 BIT32( 8 ) ); // class 1
2677 bcm_write_reg32( RX_RULE_VAL_R ( 0 ),
2678 (uint32_t) 0xffff0000 |
2679 ( bcm_read_reg32( MAC_ADDR_OFFS_HI(0) ) &
2680 (uint32_t) 0xffff ) );
2682 bcm_write_reg32( RX_RULE_CTRL_R ( 1 ),
2683 BIT32( 31 ) | // enable rule
2684 BIT32( 8 ) | // class 1
2685 BIT32( 1 ) ); // offset 2
2686 bcm_write_reg32( RX_RULE_VAL_R ( 1 ),
2687 bcm_read_reg32( MAC_ADDR_OFFS_LO(0) ) );
2689 // rule 2: accept broadcast frames
2690 bcm_write_reg32( RX_RULE_CTRL_R ( 2 ),
2691 BIT32( 31 ) | // enable rule
2692 BIT32( 30 ) | // and with next
2693 BIT32( 26 ) | // split value register
2694 BIT32( 8 ) ); // class 1
2695 bcm_write_reg32( RX_RULE_VAL_R ( 2 ),
2698 bcm_write_reg32( RX_RULE_CTRL_R ( 3 ),
2699 BIT32( 31 ) | // enable rule
2700 BIT32( 8 ) | // class 1
2701 BIT32( 1 ) ); // offset 2
2702 bcm_write_reg32( RX_RULE_VAL_R ( 3 ),
2705 for( i=0; i<NUM_RX_RULE_ASF; ++i) {
2706 bcm_write_reg32( RX_RULE_CTRL_R ( i ), 0 );
2707 bcm_write_reg32( RX_RULE_VAL_R ( i ), 0 );
2710 // step 57-60: enable rx/tx statistics
2711 // omitted, no need for statistics (so far)
2713 // step 61/62: disable host coalescing engine/wait 20ms
2714 bcm_write_reg32( HOST_COAL_MODE_R, (uint32_t) 0 );
2716 i = lc_Maxwait_u32 * 2;
2718 ( bcm_read_reg32( HOST_COAL_MODE_R ) != 0 ) ) {
2725 printf( "bcm57xx: init step 62: disable host coal. engine failed\n" );
2730 // step 63-66: initialize coalescing engine
2731 // NOTE: status block is unused in this driver,
2732 // therefore the coal. engine status block
2733 // automatic update is disabled (by writing
2734 // 0 to every counter
2735 bcm_write_reg32( RX_COAL_TICKS_R, 0 );
2736 bcm_write_reg32( TX_COAL_TICKS_R, 0 );
2737 bcm_write_reg32( RX_COAL_MAX_BD_R, 0 );
2738 bcm_write_reg32( TX_COAL_MAX_BD_R, 0 );
2739 bcm_write_reg32( RX_COAL_TICKS_INT_R, 0 );
2740 bcm_write_reg32( TX_COAL_TICKS_INT_R, 0 );
2741 bcm_write_reg32( RX_COAL_MAX_BD_INT_R, 0 );
2742 bcm_write_reg32( TX_COAL_MAX_BD_INT_R, 0 );
2744 // step 67: initialize host status block address
2745 // NOTE: status block is not needed in this driver,
2746 // still it needs to be set up
2747 i = (uint32_t) ( (uint64_t) &bcm_status >> 32 );
2748 bcm_write_reg32( STB_HOST_ADDR_HI_R, i );
2749 i = (uint32_t) ( (uint64_t) &bcm_status & (uint64_t) 0xffffffff );
2750 bcm_write_reg32( STB_HOST_ADDR_LO_R, i );
2753 if( IS_5703 || IS_5704 ) {
2754 // step 68: 5704, for now omitted
2755 // step 69: 5704 set the statistics coalescing tick counter
2756 bcm_write_reg32( STAT_TICK_CNT_R, 0 );
2757 // step 70: 5704 configure statistics block address in NIC memory
2758 // using recommended values (hard coded)
2759 bcm_write_reg32( STAT_NIC_ADDR_R, (uint32_t) 0x300 );
2760 // step 71: 5704 configure status block address in NIC memory
2761 // using recommended values (hard coded)
2762 bcm_write_reg32( STB_NIC_ADDR_R, (uint32_t) 0xb00 );
2765 // step 72: enable host coalescing engine
2766 bcm_setb_reg32( HOST_COAL_MODE_R, BIT32( 12 ) | BIT32( 11 ) | BIT32( 1 ) );
2768 // step 73: enable rx bd completion functional block
2769 bcm_write_reg32( RX_BD_COMPL_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2771 // step 74: enable rx list placement functional block
2772 bcm_write_reg32( RX_LST_PLACE_MODE_R, BIT32( 1 ) );
2774 if( IS_5703 || IS_5704 ) {
2775 // step 75: 5704/3 enable receive list selector func block
2776 bcm_write_reg32( RX_LST_SEL_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2779 // step 76: enable DMA engines
2780 bcm_setb_reg32( ETH_MAC_MODE_R, BIT32( 23 ) | BIT32( 22 ) | BIT32( 21 ) );
2782 * WY 26.10.07 This is wrong for 5714, better leave it alone
2784 bcm_setb_reg32( ETH_MAC_MODE_R, BIT32( 20 ) );
2788 // step 77: omitted, statistics are not used
2789 // step 78: Configure the General Misc Local Control register
2790 // NOTE: as known so far nothing needs to be done here,
2791 // default values should work fine
2792 //bcm_setb_reg32( MISC_LOCAL_CTRL_R, 0 );
2794 // step 79: clear interrupts in INT_MBX0_R low word
2795 bcm_write_reg32( INT_MBX0_R, 0 );
2797 // step 80: 5704/3 enable DMA completion functional block
2798 if( IS_5703 || IS_5704 ) {
2799 bcm_write_reg32( DMA_COMPL_MODE_R, BIT32( 1 ) );
2802 // step 81/82: configure write/read DMA mode registers
2804 bcm_write_reg32( RD_DMA_MODE_R, BIT32( 10 ) | BIT32( 9 ) | BIT32( 8 ) |
2805 BIT32( 7 ) | BIT32( 6 ) | BIT32( 5 ) |
2806 BIT32( 4 ) | BIT32( 3 ) | BIT32( 2 ) |
2808 bcm_write_reg32( WR_DMA_MODE_R, BIT32( 9 ) | BIT32( 8 ) | BIT32( 7 ) |
2809 BIT32( 6 ) | BIT32( 5 ) | BIT32( 4 ) |
2810 BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) );
2811 bcm_clrb_reg32( MSI_MODE_R, BIT32( 1 ) );
2814 // step 83-91: enable all these functional blocks...
2815 bcm_write_reg32( RX_DAT_COMPL_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2817 if( IS_5703 || IS_5704 ) {
2818 bcm_write_reg32( MBUF_CLSTR_FREE_MODE_R, BIT32( 1 ) );
2821 bcm_write_reg32( TX_DAT_COMPL_MODE_R, BIT32( 1 ) );
2822 bcm_write_reg32( TX_BD_COMPL_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2823 bcm_write_reg32( RX_BD_INIT_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2824 bcm_write_reg32( RX_DAT_BD_INIT_MODE_R, BIT32( 1 ) );
2825 bcm_write_reg32( TX_DAT_INIT_MODE_R, BIT32( 1 ) | BIT32( 3 ) );
2826 bcm_write_reg32( TX_BD_INIT_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2827 bcm_write_reg32( TX_BD_RING_SEL_MODE_R, BIT32( 1 ) | BIT32( 2 ) );
2830 // step 93/94: Enable Tx/Rx MAC
2831 bcm_setb_reg32( TX_MAC_MODE_R, BIT32( 1 ) );
2832 // bcm_setb_reg32( RX_MAC_MODE_R, BIT32( 1 ) | BIT32( 2 ) ); // set BIT32( 8 ) for promiscious mode!
2833 bcm_setb_reg32( RX_MAC_MODE_R, BIT32( 1 ) ); // set BIT32( 8 ) for promiscious mode!
2834 // set BIT32( 10) for VLAN
2836 // step 95: disable auto polling:
2837 // bcm_phy_init takes care of this
2839 // step 97: omitted, may change though, but is not important
2840 // step 98: activate link & enable MAC functional block
2841 // NOTE autopolling is enabled so bit 0 needs not to be set
2842 //bcm_setb_reg32( MI_STATUS_R, BIT32( 0 ) );
2844 // step 99: setup PHY
2845 // return if link is down
2846 if( bcm_phy_init() < 0 ) {
2848 printf( "bcm57xx: init step 99: PHY initialization failed\n" );
2853 // step 100: setup multicast filters
2854 bcm_write_reg32( MAC_HASH0_R, (uint32_t) 0 );
2855 bcm_write_reg32( MAC_HASH1_R, (uint32_t) 0 );
2856 bcm_write_reg32( MAC_HASH2_R, (uint32_t) 0 );
2857 bcm_write_reg32( MAC_HASH3_R, (uint32_t) 0 );
2859 // accept all multicast frames
2860 bcm_write_reg32( MAC_HASH0_R, (uint32_t) 0xffffffff );
2861 bcm_write_reg32( MAC_HASH1_R, (uint32_t) 0xffffffff );
2862 bcm_write_reg32( MAC_HASH2_R, (uint32_t) 0xffffffff );
2863 bcm_write_reg32( MAC_HASH3_R, (uint32_t) 0xffffffff );
2865 // step 101: omitted, no interrupts used
2867 // make initial receive buffers available for NIC
2868 // this step has to be done here after RX DMA engine has started (step 94)
2869 bcm_write_reg32( RXPROD_PROD_IND, BCM_MAX_RX_BUF );
2871 // if ASF Firmware enabled
2872 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_START_DONE );
2875 // enable heartbeat timer
2877 bcm_write_reg32( ASF_HEARTBEAT_TIMER_R, 0x5 );
2879 driver->running = 1;
2890 printf( "bcm57xx: resetting controller.." );
2893 bcm_write_mem32( BCM_FW_MBX, BCM_MAGIC_NUMBER );
2896 bcm_setb_reg32( MISC_CFG_R, BIT32( 26 ) | BIT32( 0 ) );
2898 bcm_setb_reg32( MISC_CFG_R, BIT32( 0 ) );
2904 * after reset local read/write functions cannot be used annymore
2905 * until bus master & stuff is set up again
2908 i = ( BIT32( 10 ) | BIT32( 2 ) | BIT32( 1 ) );
2909 SLOF_pci_config_write16(PCI_COM_R, i);
2910 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2917 // step 9 & 13: disable & mask interrupts & enable indirect addressing mode &
2918 // enable pci byte/word swapping initialize the misc host control register
2919 i = ( BIT32( 7 ) | BIT32( 5 ) | BIT32( 4 ) |
2920 BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
2921 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
2922 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
2929 // step 16: poll for bootcode completion by waiting for the one's
2930 // complement of the magic number previously written
2933 ( bcm_read_mem32( BCM_FW_MBX ) != ~BCM_MAGIC_NUMBER ) ) {
2942 if( bcm_read_mem32( BCM_FW_MBX ) != ~BCM_MAGIC_NUMBER ) {
2944 printf( "failed\n" );
2962 printf( "bcm57xx: driver shutdown.." );
2971 * unload ASF firmware
2973 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_UNLOAD );
2976 * disable RX producer rings
2978 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_JUM ), RCB_FLAG_RING_DISABLED );
2979 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_JUM ), 0 );
2980 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_JUM ), 0 );
2981 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_JUM ), 0 );
2983 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_STD ), RCB_FLAG_RING_DISABLED );
2984 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_STD ), 0 );
2985 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_STD ), 0 );
2986 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_STD ), 0 );
2988 bcm_write_reg32( BCM_RCB_LENFLAG_u16( BCM_RXPROD_RCB_MIN ), RCB_FLAG_RING_DISABLED );
2989 bcm_write_reg32( BCM_RCB_HOSTADDR_HI_u16( BCM_RXPROD_RCB_MIN ), 0 );
2990 bcm_write_reg32( BCM_RCB_HOSTADDR_LOW_u16( BCM_RXPROD_RCB_MIN ), 0 );
2991 bcm_write_reg32( BCM_RCB_NICADDR_u16( BCM_RXPROD_RCB_MIN ), 0 );
2994 * disable RX return rings
2996 v = BCM_RXRET_RCB_OFFS;
2997 for( i = 0; i < BCM_MAX_RXRET_RING; i++ ) {
2998 bcm_write_mem32( BCM_RCB_LENFLAG_u16( v ), RCB_FLAG_RING_DISABLED );
2999 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( v ), 0 );
3000 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( v ), 0 );
3001 bcm_write_mem32( BCM_RCB_NICADDR_u16( v ), 0 );
3003 v += BCM_RCB_SIZE_u16;
3009 v = BCM_TX_RCB_OFFS;
3010 for( i = 0; i < BCM_MAX_TX_RING; i++ ) {
3011 bcm_write_mem32( BCM_RCB_LENFLAG_u16( v ), RCB_FLAG_RING_DISABLED );
3012 bcm_write_mem32( BCM_RCB_HOSTADDR_HI_u16( v ), 0 );
3013 bcm_write_mem32( BCM_RCB_HOSTADDR_LOW_u16( v ), 0 );
3014 bcm_write_mem32( BCM_RCB_NICADDR_u16( v ), 0 );
3016 v += BCM_RCB_SIZE_u16;
3020 * remove receive rules
3022 bcm_write_reg32( RX_RULE_CTRL_R ( 0 ), 0 );
3023 bcm_write_reg32( RX_RULE_VAL_R ( 0 ), 0 );
3024 bcm_write_reg32( RX_RULE_CTRL_R ( 1 ), 0 );
3025 bcm_write_reg32( RX_RULE_VAL_R ( 1 ), 0 );
3029 * BCM57xx Programmer's Guide: Section 8, "Shutdown"
3030 * the enable bit of every state machine of the 57xx
3035 * receive path shutdown sequence
3037 bcm_clr_wait_bit32( RX_MAC_MODE_R, BIT32( 1 ) );
3038 bcm_clr_wait_bit32( RX_LST_PLACE_MODE_R, BIT32( 1 ) );
3039 bcm_clr_wait_bit32( RX_BD_INIT_MODE_R, BIT32( 1 ) );
3040 bcm_clr_wait_bit32( RX_DAT_BD_INIT_MODE_R, BIT32( 1 ) );
3041 bcm_clr_wait_bit32( RX_DAT_COMPL_MODE_R, BIT32( 1 ) );
3042 bcm_clr_wait_bit32( RX_BD_COMPL_MODE_R, BIT32( 1 ) );
3044 if( IS_5704 || IS_5703 ) {
3045 bcm_clr_wait_bit32( RX_LST_SEL_MODE_R, BIT32( 1 ) );
3049 * transmit path & memory shutdown sequence
3051 bcm_clr_wait_bit32( TX_BD_RING_SEL_MODE_R, BIT32( 1 ) );
3052 bcm_clr_wait_bit32( TX_BD_INIT_MODE_R, BIT32( 1 ) );
3053 bcm_clr_wait_bit32( TX_DAT_INIT_MODE_R, BIT32( 1 ) );
3054 bcm_clr_wait_bit32( RD_DMA_MODE_R, BIT32( 1 ) );
3055 bcm_clr_wait_bit32( TX_DAT_COMPL_MODE_R, BIT32( 1 ) );
3058 bcm_clr_wait_bit32( DMA_COMPL_MODE_R, BIT32( 1 ) );
3061 bcm_clr_wait_bit32( TX_BD_COMPL_MODE_R, BIT32( 1 ) );
3062 bcm_clr_wait_bit32( ETH_MAC_MODE_R, BIT32( 21 ) );
3063 bcm_clr_wait_bit32( TX_MAC_MODE_R, BIT32( 1 ) );
3065 bcm_clr_wait_bit32( HOST_COAL_MODE_R, BIT32( 1 ) );
3066 bcm_clr_wait_bit32( WR_DMA_MODE_R, BIT32( 1 ) );
3068 if( IS_5704 || IS_5703 ) {
3069 bcm_clr_wait_bit32( MBUF_CLSTR_FREE_MODE_R, BIT32( 1 ) );
3072 bcm_write_reg32( FTQ_RES_R, (uint32_t) ~0 );
3073 bcm_write_reg32( FTQ_RES_R, (uint32_t) 0 );
3075 if( IS_5704 || IS_5703 ) {
3076 bcm_clr_wait_bit32( BUF_MAN_MODE_R, BIT32( 1 ) );
3077 bcm_clr_wait_bit32( MEMARB_MODE_R, BIT32( 1 ) );
3081 printf( "done.\n" );
3086 if( bcm_reset() != 0 ) {
3091 * restart ASF firmware
3093 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_UNLOAD );
3095 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_UNLOAD_DONE );
3097 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_START );
3099 bcm_write_mem32( BCM_NICDRV_STATE_MBX, NIC_FWDRV_STATE_START_DONE );
3102 * activate Wake-on-LAN
3109 bcm_clrb_reg32( PCI_MISC_HCTRL_R, BIT32( 3 ) | BIT32( 2 ) );
3112 * from now on local rw functions cannot be used anymore
3115 // bcm_clrb_reg32( PCI_COM_R, BIT32( 10 ) | BIT32( 2 ) | BIT32( 1 ) );
3117 SLOF_pci_config_write32(PCI_COM_R, BIT32(8) | BIT32(6));
3118 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
3123 BIT32(8) | BIT32(6) );*/
3125 // no more networking...
3130 bcm_getmac(uint32_t addr, char mac[6])
3135 if (bcm_nvram_read(addr, &t1, 1) != 0)
3137 if (bcm_nvram_read(addr+4, &t2, 1) != 0)
3139 t3 = ((uint64_t)t1 << 32) + t2;
3141 mac[0] = (t3 >> 40) & 0xFF;
3142 mac[1] = (t3 >> 32) & 0xFF;
3143 mac[2] = (t3 >> 24) & 0xFF;
3144 mac[3] = (t3 >> 16) & 0xFF;
3145 mac[4] = (t3 >> 8) & 0xFF;
3146 mac[5] = (t3 >> 0) & 0xFF;
3152 print_itoa(char *text, uint32_t value)
3155 text = print_itoa(text, value / 10);
3156 *text = '0' + (value % 10);
3162 bcm_get_version(char *text)
3166 if (bcm_nvram_read(0x94, &t1, 1) != 0)
3169 text = print_itoa(text, (t1 >> 8) & 0xFF);
3171 text = print_itoa(&text[1], t1 & 0xFF);
3177 util_gen_crc( char *pcDatabuf, uint32_t ulDatalen, uint32_t ulCrc_in)
3180 uint32_t idx, bit, crc = ulCrc_in;
3182 for(idx = 0; idx < ulDatalen; idx++) {
3183 data = *pcDatabuf++;
3184 for(bit = 0; bit < 8; bit++, data >>= 1) {
3185 crc = (crc >> 1) ^ (((crc ^ data) & 1) ?
3186 CRC32_POLYNOMIAL : 0);
3189 return bswap_32(~crc);
3193 bcm_setmac(char mac_addr1[6], char mac_addr2[6])
3195 uint64_t mac1 = 0, mac2 = 0;
3196 uint32_t manu[MANUFACTURING_INFO_SIZE/4];
3198 uint32_t crc, val1, val2, val3, val4;
3201 printf("Flashing MAC 1: %02X:%02X:%02X:%02X:%02X:%02X\n",
3202 ((unsigned int) mac_addr1[0]) & 0xFF,
3203 ((unsigned int) mac_addr1[1]) & 0xFF,
3204 ((unsigned int) mac_addr1[2]) & 0xFF,
3205 ((unsigned int) mac_addr1[3]) & 0xFF,
3206 ((unsigned int) mac_addr1[4]) & 0xFF,
3207 ((unsigned int) mac_addr1[5]) & 0xFF);
3209 printf("Flashing MAC 2: %02X:%02X:%02X:%02X:%02X:%02X\n",
3210 ((unsigned int) mac_addr2[0]) & 0xFF,
3211 ((unsigned int) mac_addr2[1]) & 0xFF,
3212 ((unsigned int) mac_addr2[2]) & 0xFF,
3213 ((unsigned int) mac_addr2[3]) & 0xFF,
3214 ((unsigned int) mac_addr2[4]) & 0xFF,
3215 ((unsigned int) mac_addr2[5]) & 0xFF);
3218 mac1 |= ((uint64_t) mac_addr1[0]) & 0xFF; mac1 = mac1 << 8;
3219 mac1 |= ((uint64_t) mac_addr1[1]) & 0xFF; mac1 = mac1 << 8;
3220 mac1 |= ((uint64_t) mac_addr1[2]) & 0xFF; mac1 = mac1 << 8;
3221 mac1 |= ((uint64_t) mac_addr1[3]) & 0xFF; mac1 = mac1 << 8;
3222 mac1 |= ((uint64_t) mac_addr1[4]) & 0xFF; mac1 = mac1 << 8;
3223 mac1 |= ((uint64_t) mac_addr1[5]) & 0xFF;
3225 mac2 |= ((uint64_t) mac_addr2[0]) & 0xFF; mac2 = mac2 << 8;
3226 mac2 |= ((uint64_t) mac_addr2[1]) & 0xFF; mac2 = mac2 << 8;
3227 mac2 |= ((uint64_t) mac_addr2[2]) & 0xFF; mac2 = mac2 << 8;
3228 mac2 |= ((uint64_t) mac_addr2[3]) & 0xFF; mac2 = mac2 << 8;
3229 mac2 |= ((uint64_t) mac_addr2[4]) & 0xFF; mac2 = mac2 << 8;
3230 mac2 |= ((uint64_t) mac_addr2[5]) & 0xFF;
3232 /* Extract the manufacturing data, starts at 0x74 */
3233 if(bcm_nvram_lock() == -1) {
3238 for (i = 0; i < (MANUFACTURING_INFO_SIZE/4); i++) {
3239 if (bcm_nvram_read(addr, &manu[i], 0) != 0) {
3240 printf("\nREAD FAILED\n");
3248 /* Store the new MAC address in the manufacturing data */
3250 val2 = mac1 & 0xFFFFFFFF;
3252 val4 = mac2 & 0xFFFFFFFF;
3253 manu[(0x7C-0x74)/4] = val1;
3254 manu[(0x80-0x74)/4] = val2;
3255 manu[(0xCC-0x74)/4] = val3;
3256 manu[(0xD0-0x74)/4] = val4;
3258 /* Calculate the new manufacturing datas CRC */
3259 crc = util_gen_crc(((char *)manu),
3260 MANUFACTURING_INFO_SIZE - 4, 0xFFFFFFFF);
3262 /* Now write the new MAC addresses and CRC */
3263 if ((bcm_nvram_write(0x7C, val1, 1) != 0) ||
3264 (bcm_nvram_write(0x80, val2, 1) != 0) ||
3265 (bcm_nvram_write(0xCC, val3, 1) != 0) ||
3266 (bcm_nvram_write(0xD0, val4, 1) != 0) ||
3267 (bcm_nvram_write(0xFC, crc, 1) != 0) )
3271 printf("failed to write MAC address\n");
3281 bcm_ioctl( int request, void* data )
3283 uint32_t l_baseaddrL_u32;
3284 uint32_t l_baseaddrH_u32;
3288 ioctl_net_data_t *ioctl_data = (ioctl_net_data_t*) data;
3290 if(request != SIOCETHTOOL) {
3295 printf( "bcm57xx: detected device " );
3298 } else if( IS_5704 ) {
3305 } else if( IS_5714 ) {
3310 * setup register & memory base addresses of NIC
3312 l_baseaddrL_u32 = (uint32_t) ~0xf &
3313 SLOF_pci_config_read32(PCI_BAR1_R);
3314 /*l_baseaddrL_u32 = ( (uint32_t) ~0xf &
3315 (uint32_t) snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
3321 l_baseaddrH_u32 = SLOF_pci_config_read32(PCI_BAR2_R);
3323 (uint32_t) snk_kernel_interface->pci_config_read( bcm_pcicfg_puid,
3329 bcm_baseaddr_u64 = (uint64_t) l_baseaddrH_u32;
3330 bcm_baseaddr_u64 <<= 32;
3331 bcm_baseaddr_u64 += (uint64_t) l_baseaddrL_u32;
3333 (uint64_t)SLOF_translate_my_address((void *)bcm_baseaddr_u64);
3334 /*snk_kernel_interface->translate_addr(((void *)&(bcm_baseaddr_u64)));*/
3335 bcm_memaddr_u64 = bcm_baseaddr_u64 + BCM_MEMORY_OFFS;
3338 * 57xx hardware initialization
3339 * BCM57xx Programmer's Guide: Section 8, "Initialization"
3340 * steps 1 through 101
3343 // step 1: enable bus master & memory space in command reg
3344 i = ( BIT32( 10 ) | BIT32( 2 ) | BIT32( 1 ) );
3345 SLOF_pci_config_write16(PCI_COM_R, i);
3346 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
3353 // step 2: disable & mask interrupts & enable pci byte/word swapping & enable indirect addressing mode
3354 i = ( BIT32( 7 ) | BIT32( 3 ) | BIT32( 2 ) | BIT32( 1 ) | BIT32( 0 ) );
3355 SLOF_pci_config_write32(PCI_MISC_HCTRL_R, i);
3356 /*snk_kernel_interface->pci_config_write( bcm_pcicfg_puid,
3365 switch(ioctl_data->subcmd) {
3367 switch(ioctl_data->data.mac.idx) {
3369 ret_val = bcm_getmac(0x7C, ioctl_data->data.mac.address);
3372 ret_val = bcm_getmac(0xCC, ioctl_data->data.mac.address);
3380 switch(ioctl_data->data.mac.idx) {
3382 ret_val = bcm_getmac(0xCC, mac_addr);
3384 ret_val = bcm_setmac(ioctl_data->data.mac.address, mac_addr);
3387 ret_val = bcm_getmac(0x7C, mac_addr);
3389 ret_val = bcm_setmac(mac_addr, ioctl_data->data.mac.address);
3396 case ETHTOOL_VERSION: {
3397 char *text = ioctl_data->data.version.text;
3398 memcpy(text, " BCM57xx Boot code level: ", 27);
3399 ret_val = bcm_get_version(&text[27]);
3411 net_driver_t *bcm57xx_open(void)
3413 net_driver_t *driver;
3414 uint16_t vendor_id, device_id;
3416 vendor_id = SLOF_pci_config_read16(0);
3417 device_id = SLOF_pci_config_read16(2);
3418 if (check_driver(vendor_id, device_id))
3421 driver = SLOF_alloc_mem(sizeof(*driver));
3423 printf("Unable to allocate virtio-net driver\n");
3426 memset(driver, 0, sizeof(*driver));
3428 if (bcm_init(driver))
3433 FAIL: SLOF_free_mem(driver, sizeof(*driver));
3439 void bcm57xx_close(net_driver_t *driver)
3441 if (driver->running == 0)
3445 driver->running = 0;
3446 SLOF_free_mem(driver, sizeof(*driver));
3449 int bcm57xx_read(char *buf, int len)
3452 return bcm_receive(buf, len);
3456 int bcm57xx_write(char *buf, int len)
3459 return bcm_xmit(buf, len);