qemu/roms/SLOF/include/ppc970/cpu.h

   1 /******************************************************************************
   2  * Copyright (c) 2004, 2008 IBM Corporation
   3  * All rights reserved.
   4  * This program and the accompanying materials
   5  * are made available under the terms of the BSD License
   6  * which accompanies this distribution, and is available at
   7  * http://www.opensource.org/licenses/bsd-license.php
   8  *
   9  * Contributors:
  10  *     IBM Corporation - initial implementation
  11  *****************************************************************************/
  12
  13 #ifndef __PPC970_H
  14 #define __PPC970_H
  15
  16 /* SPRs numbers */
  17
  18 #define CTRL_RD 136
  19 #define CTRL_WR 152
  20 #define PVR     287
  21 #define HSPRG0  304
  22 #define HSPRG1  305
  23 #define HIOR    311
  24 #define HID0    1008
  25 #define HID1    1009
  26 #define HID4    1012
  27 #define HID6    1017
  28 #define PIR     1023
  29
  30 #define SETCI(r)        sync; \
  31                         mfspr   r, HID4; \
  32                         sync; \
  33                         rldicl  r, r, 32,0; \
  34                         ori     r, r, 0x0100; \
  35                         rldicl  r, r, 32,0; \
  36                         sync; \
  37                         slbia; \
  38                         mtspr   HID4, r; \
  39                         isync; \
  40                         eieio;
  41
  42 #define CLRCI(r)        sync; \
  43                         mfspr   r, HID4; \
  44                         sync; \
  45                         rldicl  r, r, 32, 0; \
  46                         ori     r, r, 0x0100; \
  47                         xori    r, r, 0x0100; \
  48                         rldicl  r, r, 32, 0; \
  49                         sync; \
  50                         slbia; \
  51                         mtspr   HID4, r; \
  52                         isync; \
  53                         eieio;
  54
  55 /* This macro uses r0 */
  56 #define FLUSH_CACHE(r, n)       add     n, n, r; \
  57                                 addi    n, n, 127; \
  58                                 rlwinm  r, r, 0,0,24; \
  59                                 rlwinm  n, n, 0,0,24; \
  60                                 sub     n, n, r; \
  61                                 srwi    n, n, 7; \
  62                                 mtctr   n; \
  63                         0:      dcbst   0, r; \
  64                                 sync; \
  65                                 icbi    0, r; \
  66                                 sync; \
  67                                 isync; \
  68                                 addi    r, r, 128; \
  69                                 bdnz    0b;
  70
  71 #ifndef __ASSEMBLER__
  72 #define STRINGIFY(x...) #x
  73 #define EXPAND(x) STRINGIFY(x)
  74
  75 static inline void
  76 set_ci(void)
  77 {
  78         unsigned long tmp;
  79         asm volatile(EXPAND(SETCI(%0)) : "=r"(tmp) :: "memory", "cc");
  80 }
  81
  82 static inline void
  83 clr_ci(void)
  84 {
  85         unsigned long tmp;
  86         asm volatile(EXPAND(CLRCI(%0)) : "=r"(tmp) :: "memory", "cc");
  87 }
  88
  89 static inline void eieio(void)
  90 {
  91         asm volatile ("eieio":::"memory");
  92 }
  93
  94 static inline void barrier(void)
  95 {
  96         asm volatile("" : : : "memory");
  97 }
  98 #define cpu_relax() barrier()
  99
 100 static inline void sync(void)
 101 {
 102         asm volatile ("sync" ::: "memory");
 103 }
 104 #define mb() sync()
 105
 106 static inline void flush_cache(void* r, long n)
 107 {
 108         asm volatile(EXPAND(FLUSH_CACHE(%0, %1)) : "+r"(r), "+r"(n) :: "memory", "cc", "r0", "ctr");
 109 }
 110
 111 #endif /* __ASSEMBLER__ */
 112
 113 #endif