qemu/roms/SLOF/board-qemu/llfw/startup.S

   1 /******************************************************************************
   2  * Copyright (c) 2004, 2011 IBM Corporation
   3  * All rights reserved.
   4  * This program and the accompanying materials
   5  * are made available under the terms of the BSD License
   6  * which accompanies this distribution, and is available at
   7  * http://www.opensource.org/licenses/bsd-license.php
   8  *
   9  * Contributors:
  10  *     IBM Corporation - initial implementation
  11  *****************************************************************************/
  12
  13 /* SLOF for QEMU -- boot code.
  14  * Initial entry point
  15  */
  16
  17 #include <xvect.h>
  18 #include <cpu.h>
  19 #include <macros.h>
  20
  21         /* qemu entry:
  22          *
  23          * __start loaded at 0x100
  24          *
  25          * CPU 0 starts at 0 with GPR3 pointing to the flat devtree
  26          *
  27          * All other CPUs are held in stopped state by qemu and are
  28          * started via RTAS
  29          */
  30         .text
  31         .globl __start
  32 __start:
  33         b       _start
  34         .long 0xDEADBEE0
  35         .long 0x0       /* size */
  36         .long 0x0       /* crc  */
  37         .long relTag - __start
  38
  39         /* Some exception vectors
  40          *
  41          * FIXME: Also need 0280, 0380, 0f20, etc.
  42          */
  43
  44         .irp i, 0x0100,0x0180,0x0200,0x0280,0x0300,0x0380,0x0400,0x0500, \
  45                 0x0600,0x0700,0x0800,0x0900,0x0a00,0x0b00,0x0c00,0x0d00, \
  46                 0x0e00,0x0f00,0x1000,0x1100,0x1200,0x1300,0x1400,0x1500, \
  47                 0x1600,0x1700, \
  48                 0x1800,0x1900,0x1a00,0x1b00,0x1c00,0x1d00,0x1e00,0x1f00, \
  49                 0x2000,0x2100,0x2200,0x2300,0x2400,0x2500,0x2600,0x2700, \
  50                 0x2800,0x2900,0x2a00,0x2b00,0x2c00,0x2d00,0x2e00
  51         . = \i
  52
  53         /* enable this if you get exceptions before the console works    */
  54         /* this will allow using the hardware debugger to see where      */
  55         /* it traps, and with what register values etc.                  */
  56         // b    $
  57
  58         mtsprg  0,r0
  59         mfctr   r0
  60         mtsprg  2,r0
  61         mflr    r0
  62 // 10
  63         mtsprg  3,r0
  64         ld      r0, (\i + 0x60)(0)
  65         mtctr   r0
  66         li      r0, \i + 0x100
  67 // 20
  68         bctr
  69
  70         . = \i + 0x60
  71         .quad   intHandler2C
  72         .endr
  73
  74         . = XVECT_M_HANDLER - 0x100
  75         .quad   0x00
  76         .text
  77
  78         /* Here's the startup code for the master CPU */
  79         .org 0x4000 - 0x100
  80 _start:
  81         /* Save device-tree pointer */
  82         mr      r31,r3
  83
  84         /* Switch to 64-bit mode with 64-bit exceptions */
  85 #define MSR_SF_LG       63              /* Enable 64 bit mode */
  86 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
  87 #define __MASK(X)       (1<<(X))
  88 #define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
  89 #define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode */
  90         mfmsr   r11                     /* grab the current MSR */
  91         li      r12,(MSR_SF | MSR_ISF)@highest
  92         sldi    r12,r12,48
  93         or      r11,r11,r12
  94         mtmsrd  r11
  95         isync
  96
  97         /* Early greet */
  98         li      r3,10
  99         bl      putc
 100         li      r3,13
 101         bl      putc
 102         li      r3,10
 103         bl      putc
 104         li      r3,'S'
 105         bl      putc
 106
 107         li      r3,'L'
 108         bl      putc
 109         li      r3,'O'
 110         bl      putc
 111         li      r3,'F'
 112         bl      putc
 113
 114         bl      print_version
 115
 116         /* go! */
 117         li      r3,__startC@l
 118         mtctr   r3
 119         bctrl
 120
 121         /* write a character to the HV console */
 122 putc:   sldi    r6,r3,(24+32)
 123         li      r3,0x58
 124         li      r4,0
 125         li      r5,1
 126         .long   0x44000022
 127         blr
 128
 129 relTag:
 130         .ascii  RELEASE
 131         .ascii  "\0"
 132         .align  2
 133
 134 C_ENTRY(proceedInterrupt)
 135
 136         ld      r3,exception_stack_frame@got(r2)
 137         ld      r1,0(r3)
 138
 139         .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
 140                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
 141                 27, 28, 29, 30, 31
 142         ld      r\i, 0x30+\i*8 (r1)
 143         .endr
 144
 145         ld      r14,0x138(r1);
 146         mtsrr0  r14
 147
 148         ld      r14,0x140(r1);
 149         mtsrr1  r14
 150
 151         ld      r14,0x148(r1);
 152         mtcr    r14
 153
 154         ld      0,XVECT_M_HANDLER(0)
 155         mtctr   0
 156
 157         ld      r0,0x30(r1); # restore vector number
 158         ld      r1,0x38(r1);
 159
 160         bctr
 161
 162 intHandler2C:
 163         mtctr   r1 # save old stack pointer
 164         lis     r1,0x4
 165         stdu    r1, -0x160(r1)
 166         .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
 167                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
 168                 27, 28, 29, 30, 31
 169         std     r\i, 0x30+\i*8 (r1)
 170         .endr
 171
 172         std     r0,0x30(r1);  # save vector number
 173
 174         mfctr   r14
 175         std     r14,0x38(r1); # save old r1
 176
 177         mfsrr0  r14
 178         std     r14,0x138(r1);
 179
 180         mfsrr1  r14
 181         std     r14,0x140(r1);
 182
 183         mfcr    r14
 184         std     r14,0x148(r1);
 185
 186         mfxer   r14
 187         std     r14,0x150(r1);
 188
 189         bl      toc_init
 190
 191         ld      r3,exception_stack_frame@got(r2)
 192         std     r1,0(r3)
 193
 194
 195         mr      r3,r0
 196         bl      .c_interrupt
 197
 198         ld      r14,0x138(r1);
 199         mtsrr0  r14
 200
 201         ld      r14,0x140(r1);
 202         mtsrr1  r14
 203
 204         ld      r14,0x148(r1);
 205         mtcr    r14
 206
 207         ld      r14,0x150(r1);
 208         mtxer   r14
 209
 210
 211         .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
 212                 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
 213                 27, 28, 29, 30, 31
 214         ld      r\i, 0x30+\i*8 (r1)
 215         .endr
 216
 217         ld      r1,0x38(r1);
 218
 219         mfsprg  r0,2
 220         mtctr   r0
 221         mfsprg  r0,3
 222         mtlr    r0
 223         mfsprg  r0,0
 224         rfid
 225
 226 /* Set exception handler for given exception vector.
 227         r3:     exception vector offset
 228         r4:     exception handler
 229 */
 230         .globl .set_exception
 231 .set_exception:
 232         .globl set_exception
 233 set_exception:
 234         ld r4,0x0(r4)
 235         .globl .set_exception_asm
 236 .set_exception_asm:
 237         .globl set_exception_asm
 238 set_exception_asm:
 239         std     r4, 0x60(r3)    # fixme diff 1f - 0b
 240         blr