3 * MIPS Technologies, Inc., California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
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13 * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Author: Nemanja Lukic (nlukic@mips.com)
32 #ifndef PIXMAN_MIPS_DSPR2_ASM_H
33 #define PIXMAN_MIPS_DSPR2_ASM_H
70 * LEAF_MIPS32R2 - declare leaf routine for MIPS32r2
72 #define LEAF_MIPS32R2(symbol) \
77 .type symbol, @function; \
80 symbol: .frame sp, 0, ra; \
87 * LEAF_MIPS32R2 - declare leaf routine for MIPS DSPr2
89 #define LEAF_MIPS_DSPR2(symbol) \
90 LEAF_MIPS32R2(symbol) \
94 * END - mark end of function
96 #define END(function) \
99 .size function,.-function
102 * Checks if stack offset is big enough for storing/restoring regs_num
103 * number of register to/from stack. Stack offset must be greater than
104 * or equal to the number of bytes needed for storing registers (regs_num*4).
105 * Since MIPS ABI allows usage of first 16 bytes of stack frame (this is
106 * preserved for input arguments of the functions, already stored in a0-a3),
107 * stack size can be further optimized by utilizing this space.
109 .macro CHECK_STACK_OFFSET regs_num, stack_offset
110 .if \stack_offset < \regs_num * 4 - 16
111 .error "Stack offset too small."
116 * Saves set of registers on stack. Maximum number of registers that
117 * can be saved on stack is limitted to 14 (a0-a3, v0-v1 and s0-s7).
118 * Stack offset is number of bytes that are added to stack pointer (sp)
119 * before registers are pushed in order to provide enough space on stack
120 * (offset must be multiple of 4, and must be big enough, as described by
121 * CHECK_STACK_OFFSET macro). This macro is intended to be used in
122 * combination with RESTORE_REGS_FROM_STACK macro. Example:
123 * SAVE_REGS_ON_STACK 4, v0, v1, s0, s1
124 * RESTORE_REGS_FROM_STACK 4, v0, v1, s0, s1
126 .macro SAVE_REGS_ON_STACK stack_offset = 0, r1, \
127 r2 = 0, r3 = 0, r4 = 0, \
128 r5 = 0, r6 = 0, r7 = 0, \
129 r8 = 0, r9 = 0, r10 = 0, \
130 r11 = 0, r12 = 0, r13 = 0, \
132 .if (\stack_offset < 0) || (\stack_offset - (\stack_offset / 4) * 4)
133 .error "Stack offset must be pozitive and multiple of 4."
135 .if \stack_offset != 0
136 addiu sp, sp, -\stack_offset
149 CHECK_STACK_OFFSET 5, \stack_offset
153 CHECK_STACK_OFFSET 6, \stack_offset
157 CHECK_STACK_OFFSET 7, \stack_offset
161 CHECK_STACK_OFFSET 8, \stack_offset
165 CHECK_STACK_OFFSET 9, \stack_offset
169 CHECK_STACK_OFFSET 10, \stack_offset
173 CHECK_STACK_OFFSET 11, \stack_offset
177 CHECK_STACK_OFFSET 12, \stack_offset
181 CHECK_STACK_OFFSET 13, \stack_offset
185 CHECK_STACK_OFFSET 14, \stack_offset
191 * Restores set of registers from stack. Maximum number of registers that
192 * can be restored from stack is limitted to 14 (a0-a3, v0-v1 and s0-s7).
193 * Stack offset is number of bytes that are added to stack pointer (sp)
194 * after registers are restored (offset must be multiple of 4, and must
195 * be big enough, as described by CHECK_STACK_OFFSET macro). This macro is
196 * intended to be used in combination with RESTORE_REGS_FROM_STACK macro.
198 * SAVE_REGS_ON_STACK 4, v0, v1, s0, s1
199 * RESTORE_REGS_FROM_STACK 4, v0, v1, s0, s1
201 .macro RESTORE_REGS_FROM_STACK stack_offset = 0, r1, \
202 r2 = 0, r3 = 0, r4 = 0, \
203 r5 = 0, r6 = 0, r7 = 0, \
204 r8 = 0, r9 = 0, r10 = 0, \
205 r11 = 0, r12 = 0, r13 = 0, \
207 .if (\stack_offset < 0) || (\stack_offset - (\stack_offset/4)*4)
208 .error "Stack offset must be pozitive and multiple of 4."
221 CHECK_STACK_OFFSET 5, \stack_offset
225 CHECK_STACK_OFFSET 6, \stack_offset
229 CHECK_STACK_OFFSET 7, \stack_offset
233 CHECK_STACK_OFFSET 8, \stack_offset
237 CHECK_STACK_OFFSET 9, \stack_offset
241 CHECK_STACK_OFFSET 10, \stack_offset
245 CHECK_STACK_OFFSET 11, \stack_offset
249 CHECK_STACK_OFFSET 12, \stack_offset
253 CHECK_STACK_OFFSET 13, \stack_offset
257 CHECK_STACK_OFFSET 14, \stack_offset
260 .if \stack_offset != 0
261 addiu sp, sp, \stack_offset
266 * Conversion of single r5g6b5 pixel (in_565) to single a8r8g8b8 pixel
267 * returned in (out_8888) register. Requires two temporary registers
268 * (scratch1 and scratch2).
270 .macro CONVERT_1x0565_TO_1x8888 in_565, \
273 lui \out_8888, 0xff00
274 sll \scratch1, \in_565, 0x3
275 andi \scratch2, \scratch1, 0xff
276 ext \scratch1, \in_565, 0x2, 0x3
277 or \scratch1, \scratch2, \scratch1
278 or \out_8888, \out_8888, \scratch1
280 sll \scratch1, \in_565, 0x5
281 andi \scratch1, \scratch1, 0xfc00
282 srl \scratch2, \in_565, 0x1
283 andi \scratch2, \scratch2, 0x300
284 or \scratch2, \scratch1, \scratch2
285 or \out_8888, \out_8888, \scratch2
287 andi \scratch1, \in_565, 0xf800
288 srl \scratch2, \scratch1, 0x5
289 andi \scratch2, \scratch2, 0xff00
290 or \scratch1, \scratch1, \scratch2
291 sll \scratch1, \scratch1, 0x8
292 or \out_8888, \out_8888, \scratch1
296 * Conversion of two r5g6b5 pixels (in1_565 and in2_565) to two a8r8g8b8 pixels
297 * returned in (out1_8888 and out2_8888) registers. Requires four scratch
298 * registers (scratch1 ... scratch4). It also requires maskG and maskB for
299 * color component extractions. These masks must have following values:
300 * li maskG, 0x07e007e0
301 * li maskB, 0x001F001F
303 .macro CONVERT_2x0565_TO_2x8888 in1_565, in2_565, \
304 out1_8888, out2_8888, \
306 scratch1, scratch2, scratch3, scratch4
307 sll \scratch1, \in1_565, 16
308 or \scratch1, \scratch1, \in2_565
309 lui \out2_8888, 0xff00
310 ori \out2_8888, \out2_8888, 0xff00
311 shrl.ph \scratch2, \scratch1, 11
312 and \scratch3, \scratch1, \maskG
313 shra.ph \scratch4, \scratch2, 2
314 shll.ph \scratch2, \scratch2, 3
315 shll.ph \scratch3, \scratch3, 5
316 or \scratch2, \scratch2, \scratch4
317 shrl.qb \scratch4, \scratch3, 6
318 or \out2_8888, \out2_8888, \scratch2
319 or \scratch3, \scratch3, \scratch4
320 and \scratch1, \scratch1, \maskB
321 shll.ph \scratch2, \scratch1, 3
322 shra.ph \scratch4, \scratch1, 2
323 or \scratch2, \scratch2, \scratch4
324 or \scratch3, \scratch2, \scratch3
325 precrq.ph.w \out1_8888, \out2_8888, \scratch3
326 precr_sra.ph.w \out2_8888, \scratch3, 0
330 * Conversion of single a8r8g8b8 pixel (in_8888) to single r5g6b5 pixel
331 * returned in (out_565) register. Requires two temporary registers
332 * (scratch1 and scratch2).
334 .macro CONVERT_1x8888_TO_1x0565 in_8888, \
337 ext \out_565, \in_8888, 0x3, 0x5
338 srl \scratch1, \in_8888, 0x5
339 andi \scratch1, \scratch1, 0x07e0
340 srl \scratch2, \in_8888, 0x8
341 andi \scratch2, \scratch2, 0xf800
342 or \out_565, \out_565, \scratch1
343 or \out_565, \out_565, \scratch2
347 * Conversion of two a8r8g8b8 pixels (in1_8888 and in2_8888) to two r5g6b5
348 * pixels returned in (out1_565 and out2_565) registers. Requires two temporary
349 * registers (scratch1 and scratch2). It also requires maskR, maskG and maskB
350 * for color component extractions. These masks must have following values:
351 * li maskR, 0xf800f800
352 * li maskG, 0x07e007e0
353 * li maskB, 0x001F001F
354 * Value of input register in2_8888 is lost.
356 .macro CONVERT_2x8888_TO_2x0565 in1_8888, in2_8888, \
357 out1_565, out2_565, \
358 maskR, maskG, maskB, \
360 precr.qb.ph \scratch1, \in2_8888, \in1_8888
361 precrq.qb.ph \in2_8888, \in2_8888, \in1_8888
362 and \out1_565, \scratch1, \maskR
363 shrl.ph \scratch1, \scratch1, 3
364 shll.ph \in2_8888, \in2_8888, 3
365 and \scratch1, \scratch1, \maskB
366 or \out1_565, \out1_565, \scratch1
367 and \in2_8888, \in2_8888, \maskG
368 or \out1_565, \out1_565, \in2_8888
369 srl \out2_565, \out1_565, 16
373 * Multiply pixel (a8) with single pixel (a8r8g8b8). It requires maskLSR needed
374 * for rounding process. maskLSR must have following value:
375 * li maskLSR, 0x00ff00ff
377 .macro MIPS_UN8x4_MUL_UN8 s_8888, \
381 scratch1, scratch2, scratch3
382 replv.ph \m_8, \m_8 /* 0 | M | 0 | M */
383 muleu_s.ph.qbl \scratch1, \s_8888, \m_8 /* A*M | R*M */
384 muleu_s.ph.qbr \scratch2, \s_8888, \m_8 /* G*M | B*M */
385 shra_r.ph \scratch3, \scratch1, 8
386 shra_r.ph \d_8888, \scratch2, 8
387 and \scratch3, \scratch3, \maskLSR /* 0 |A*M| 0 |R*M */
388 and \d_8888, \d_8888, \maskLSR /* 0 |G*M| 0 |B*M */
389 addq.ph \scratch1, \scratch1, \scratch3 /* A*M+A*M | R*M+R*M */
390 addq.ph \scratch2, \scratch2, \d_8888 /* G*M+G*M | B*M+B*M */
391 shra_r.ph \scratch1, \scratch1, 8
392 shra_r.ph \scratch2, \scratch2, 8
393 precr.qb.ph \d_8888, \scratch1, \scratch2
397 * Multiply two pixels (a8) with two pixels (a8r8g8b8). It requires maskLSR
398 * needed for rounding process. maskLSR must have following value:
399 * li maskLSR, 0x00ff00ff
401 .macro MIPS_2xUN8x4_MUL_2xUN8 s1_8888, \
408 scratch1, scratch2, scratch3, \
409 scratch4, scratch5, scratch6
410 replv.ph \m1_8, \m1_8 /* 0 | M1 | 0 | M1 */
411 replv.ph \m2_8, \m2_8 /* 0 | M2 | 0 | M2 */
412 muleu_s.ph.qbl \scratch1, \s1_8888, \m1_8 /* A1*M1 | R1*M1 */
413 muleu_s.ph.qbr \scratch2, \s1_8888, \m1_8 /* G1*M1 | B1*M1 */
414 muleu_s.ph.qbl \scratch3, \s2_8888, \m2_8 /* A2*M2 | R2*M2 */
415 muleu_s.ph.qbr \scratch4, \s2_8888, \m2_8 /* G2*M2 | B2*M2 */
416 shra_r.ph \scratch5, \scratch1, 8
417 shra_r.ph \d1_8888, \scratch2, 8
418 shra_r.ph \scratch6, \scratch3, 8
419 shra_r.ph \d2_8888, \scratch4, 8
420 and \scratch5, \scratch5, \maskLSR /* 0 |A1*M1| 0 |R1*M1 */
421 and \d1_8888, \d1_8888, \maskLSR /* 0 |G1*M1| 0 |B1*M1 */
422 and \scratch6, \scratch6, \maskLSR /* 0 |A2*M2| 0 |R2*M2 */
423 and \d2_8888, \d2_8888, \maskLSR /* 0 |G2*M2| 0 |B2*M2 */
424 addq.ph \scratch1, \scratch1, \scratch5
425 addq.ph \scratch2, \scratch2, \d1_8888
426 addq.ph \scratch3, \scratch3, \scratch6
427 addq.ph \scratch4, \scratch4, \d2_8888
428 shra_r.ph \scratch1, \scratch1, 8
429 shra_r.ph \scratch2, \scratch2, 8
430 shra_r.ph \scratch3, \scratch3, 8
431 shra_r.ph \scratch4, \scratch4, 8
432 precr.qb.ph \d1_8888, \scratch1, \scratch2
433 precr.qb.ph \d2_8888, \scratch3, \scratch4
437 * Multiply pixel (a8r8g8b8) with single pixel (a8r8g8b8). It requires maskLSR
438 * needed for rounding process. maskLSR must have following value:
439 * li maskLSR, 0x00ff00ff
441 .macro MIPS_UN8x4_MUL_UN8x4 s_8888, \
445 scratch1, scratch2, scratch3, scratch4
446 preceu.ph.qbl \scratch1, \m_8888 /* 0 | A | 0 | R */
447 preceu.ph.qbr \scratch2, \m_8888 /* 0 | G | 0 | B */
448 muleu_s.ph.qbl \scratch3, \s_8888, \scratch1 /* A*A | R*R */
449 muleu_s.ph.qbr \scratch4, \s_8888, \scratch2 /* G*G | B*B */
450 shra_r.ph \scratch1, \scratch3, 8
451 shra_r.ph \scratch2, \scratch4, 8
452 and \scratch1, \scratch1, \maskLSR /* 0 |A*A| 0 |R*R */
453 and \scratch2, \scratch2, \maskLSR /* 0 |G*G| 0 |B*B */
454 addq.ph \scratch1, \scratch1, \scratch3
455 addq.ph \scratch2, \scratch2, \scratch4
456 shra_r.ph \scratch1, \scratch1, 8
457 shra_r.ph \scratch2, \scratch2, 8
458 precr.qb.ph \d_8888, \scratch1, \scratch2
462 * Multiply two pixels (a8r8g8b8) with two pixels (a8r8g8b8). It requires
463 * maskLSR needed for rounding process. maskLSR must have following value:
464 * li maskLSR, 0x00ff00ff
467 .macro MIPS_2xUN8x4_MUL_2xUN8x4 s1_8888, \
474 scratch1, scratch2, scratch3, \
475 scratch4, scratch5, scratch6
476 preceu.ph.qbl \scratch1, \m1_8888 /* 0 | A | 0 | R */
477 preceu.ph.qbr \scratch2, \m1_8888 /* 0 | G | 0 | B */
478 preceu.ph.qbl \scratch3, \m2_8888 /* 0 | A | 0 | R */
479 preceu.ph.qbr \scratch4, \m2_8888 /* 0 | G | 0 | B */
480 muleu_s.ph.qbl \scratch5, \s1_8888, \scratch1 /* A*A | R*R */
481 muleu_s.ph.qbr \scratch6, \s1_8888, \scratch2 /* G*G | B*B */
482 muleu_s.ph.qbl \scratch1, \s2_8888, \scratch3 /* A*A | R*R */
483 muleu_s.ph.qbr \scratch2, \s2_8888, \scratch4 /* G*G | B*B */
484 shra_r.ph \scratch3, \scratch5, 8
485 shra_r.ph \scratch4, \scratch6, 8
486 shra_r.ph \d1_8888, \scratch1, 8
487 shra_r.ph \d2_8888, \scratch2, 8
488 and \scratch3, \scratch3, \maskLSR /* 0 |A*A| 0 |R*R */
489 and \scratch4, \scratch4, \maskLSR /* 0 |G*G| 0 |B*B */
490 and \d1_8888, \d1_8888, \maskLSR /* 0 |A*A| 0 |R*R */
491 and \d2_8888, \d2_8888, \maskLSR /* 0 |G*G| 0 |B*B */
492 addq.ph \scratch3, \scratch3, \scratch5
493 addq.ph \scratch4, \scratch4, \scratch6
494 addq.ph \d1_8888, \d1_8888, \scratch1
495 addq.ph \d2_8888, \d2_8888, \scratch2
496 shra_r.ph \scratch3, \scratch3, 8
497 shra_r.ph \scratch4, \scratch4, 8
498 shra_r.ph \scratch5, \d1_8888, 8
499 shra_r.ph \scratch6, \d2_8888, 8
500 precr.qb.ph \d1_8888, \scratch3, \scratch4
501 precr.qb.ph \d2_8888, \scratch5, \scratch6
505 * OVER operation on single a8r8g8b8 source pixel (s_8888) and single a8r8g8b8
506 * destination pixel (d_8888) using a8 mask (m_8). It also requires maskLSR
507 * needed for rounding process. maskLSR must have following value:
508 * li maskLSR, 0x00ff00ff
510 .macro OVER_8888_8_8888 s_8888, \
515 scratch1, scratch2, scratch3, scratch4
516 MIPS_UN8x4_MUL_UN8 \s_8888, \m_8, \
517 \scratch1, \maskLSR, \
518 \scratch2, \scratch3, \scratch4
520 not \scratch2, \scratch1
521 srl \scratch2, \scratch2, 24
523 MIPS_UN8x4_MUL_UN8 \d_8888, \scratch2, \
525 \scratch3, \scratch4, \out_8888
527 addu_s.qb \out_8888, \d_8888, \scratch1
531 * OVER operation on two a8r8g8b8 source pixels (s1_8888 and s2_8888) and two
532 * a8r8g8b8 destination pixels (d1_8888 and d2_8888) using a8 masks (m1_8 and
533 * m2_8). It also requires maskLSR needed for rounding process. maskLSR must
534 * have following value:
535 * li maskLSR, 0x00ff00ff
537 .macro OVER_2x8888_2x8_2x8888 s1_8888, \
546 scratch1, scratch2, scratch3, \
547 scratch4, scratch5, scratch6
548 MIPS_2xUN8x4_MUL_2xUN8 \s1_8888, \s2_8888, \
550 \scratch1, \scratch2, \
552 \scratch3, \scratch4, \out1_8888, \
553 \out2_8888, \scratch5, \scratch6
555 not \scratch3, \scratch1
556 srl \scratch3, \scratch3, 24
557 not \scratch4, \scratch2
558 srl \scratch4, \scratch4, 24
560 MIPS_2xUN8x4_MUL_2xUN8 \d1_8888, \d2_8888, \
561 \scratch3, \scratch4, \
562 \d1_8888, \d2_8888, \
564 \scratch5, \scratch6, \out1_8888, \
565 \out2_8888, \scratch3, \scratch4
567 addu_s.qb \out1_8888, \d1_8888, \scratch1
568 addu_s.qb \out2_8888, \d2_8888, \scratch2
572 * OVER operation on single a8r8g8b8 source pixel (s_8888) and single a8r8g8b8
573 * destination pixel (d_8888). It also requires maskLSR needed for rounding
574 * process. maskLSR must have following value:
575 * li maskLSR, 0x00ff00ff
577 .macro OVER_8888_8888 s_8888, \
581 scratch1, scratch2, scratch3, scratch4
582 not \scratch1, \s_8888
583 srl \scratch1, \scratch1, 24
585 MIPS_UN8x4_MUL_UN8 \d_8888, \scratch1, \
586 \out_8888, \maskLSR, \
587 \scratch2, \scratch3, \scratch4
589 addu_s.qb \out_8888, \out_8888, \s_8888
593 * OVER operation on two a8r8g8b8 source pixels (s1_8888 and s2_8888) and two
594 * a8r8g8b8 destination pixels (d1_8888 and d2_8888). It also requires maskLSR
595 * needed for rounding process. maskLSR must have following value:
596 * li maskLSR, 0x00ff00ff
598 .macro OVER_2x8888_2x8888 s1_8888, \
605 scratch1, scratch2, scratch3, \
606 scratch4, scratch5, scratch6
607 not \scratch1, \s1_8888
608 srl \scratch1, \scratch1, 24
609 not \scratch2, \s2_8888
610 srl \scratch2, \scratch2, 24
611 MIPS_2xUN8x4_MUL_2xUN8 \d1_8888, \d2_8888, \
612 \scratch1, \scratch2, \
613 \out1_8888, \out2_8888, \
615 \scratch3, \scratch4, \scratch5, \
616 \scratch6, \d1_8888, \d2_8888
618 addu_s.qb \out1_8888, \out1_8888, \s1_8888
619 addu_s.qb \out2_8888, \out2_8888, \s2_8888
622 .macro MIPS_UN8x4_MUL_UN8_ADD_UN8x4 s_8888, \
627 scratch1, scratch2, scratch3
628 MIPS_UN8x4_MUL_UN8 \s_8888, \m_8, \
629 \out_8888, \maskLSR, \
630 \scratch1, \scratch2, \scratch3
632 addu_s.qb \out_8888, \out_8888, \d_8888
635 .macro MIPS_2xUN8x4_MUL_2xUN8_ADD_2xUN8x4 s1_8888, \
644 scratch1, scratch2, scratch3, \
645 scratch4, scratch5, scratch6
646 MIPS_2xUN8x4_MUL_2xUN8 \s1_8888, \s2_8888, \
648 \out1_8888, \out2_8888, \
650 \scratch1, \scratch2, \scratch3, \
651 \scratch4, \scratch5, \scratch6
653 addu_s.qb \out1_8888, \out1_8888, \d1_8888
654 addu_s.qb \out2_8888, \out2_8888, \d2_8888
657 .macro BILINEAR_INTERPOLATE_SINGLE_PIXEL tl, tr, bl, br, \
658 scratch1, scratch2, \
659 alpha, red, green, blue \
661 andi \scratch1, \tl, 0xff
662 andi \scratch2, \tr, 0xff
663 andi \alpha, \bl, 0xff
666 multu $ac0, \wt1, \scratch1
667 maddu $ac0, \wt2, \scratch2
668 maddu $ac0, \wb1, \alpha
669 maddu $ac0, \wb2, \red
671 ext \scratch1, \tl, 8, 8
672 ext \scratch2, \tr, 8, 8
673 ext \alpha, \bl, 8, 8
676 multu $ac1, \wt1, \scratch1
677 maddu $ac1, \wt2, \scratch2
678 maddu $ac1, \wb1, \alpha
679 maddu $ac1, \wb2, \red
681 ext \scratch1, \tl, 16, 8
682 ext \scratch2, \tr, 16, 8
683 ext \alpha, \bl, 16, 8
688 multu $ac2, \wt1, \scratch1
689 maddu $ac2, \wt2, \scratch2
690 maddu $ac2, \wb1, \alpha
691 maddu $ac2, \wb2, \red
693 ext \scratch1, \tl, 24, 8
694 ext \scratch2, \tr, 24, 8
695 ext \alpha, \bl, 24, 8
700 multu $ac3, \wt1, \scratch1
701 maddu $ac3, \wt2, \scratch2
702 maddu $ac3, \wb1, \alpha
703 maddu $ac3, \wb2, \red
708 precr.qb.ph \alpha, \alpha, \red
709 precr.qb.ph \scratch1, \green, \blue
710 precrq.qb.ph \tl, \alpha, \scratch1
713 #endif //PIXMAN_MIPS_DSPR2_ASM_H