qemu/include/hw/pci/pcie_regs.h

   1 /*
   2  * constants for pcie configurations space from pci express spec.
   3  *
   4  * TODO:
   5  * Those constants and macros should go to Linux pci_regs.h
   6  * Once they're merged, they will go away.
   7  */
   8 #ifndef QEMU_PCIE_REGS_H
   9 #define QEMU_PCIE_REGS_H
  10
  11
  12 /* express capability */
  13
  14 #define PCI_EXP_VER2_SIZEOF             0x3c /* express capability of ver. 2 */
  15 #define PCI_EXT_CAP_VER_SHIFT           16
  16 #define PCI_EXT_CAP_NEXT_SHIFT          20
  17 #define PCI_EXT_CAP_NEXT_MASK           (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
  18
  19 #define PCI_EXT_CAP(id, ver, next)                                      \
  20     ((id) |                                                             \
  21      ((ver) << PCI_EXT_CAP_VER_SHIFT) |                                 \
  22      ((next) << PCI_EXT_CAP_NEXT_SHIFT))
  23
  24 #define PCI_EXT_CAP_ALIGN               4
  25 #define PCI_EXT_CAP_ALIGNUP(x)                                  \
  26     (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
  27
  28 /* PCI_EXP_FLAGS */
  29 #define PCI_EXP_FLAGS_VER2              2 /* for now, supports only ver. 2 */
  30 #define PCI_EXP_FLAGS_IRQ_SHIFT         ctz32(PCI_EXP_FLAGS_IRQ)
  31 #define PCI_EXP_FLAGS_TYPE_SHIFT        ctz32(PCI_EXP_FLAGS_TYPE)
  32
  33
  34 /* PCI_EXP_LINK{CAP, STA} */
  35 /* link speed */
  36 #define PCI_EXP_LNK_LS_25               1
  37
  38 #define PCI_EXP_LNK_MLW_SHIFT           ctz32(PCI_EXP_LNKCAP_MLW)
  39 #define PCI_EXP_LNK_MLW_1               (1 << PCI_EXP_LNK_MLW_SHIFT)
  40
  41 /* PCI_EXP_LINKCAP */
  42 #define PCI_EXP_LNKCAP_ASPMS_SHIFT      ctz32(PCI_EXP_LNKCAP_ASPMS)
  43 #define PCI_EXP_LNKCAP_ASPMS_0S         (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
  44
  45 #define PCI_EXP_LNKCAP_PN_SHIFT         ctz32(PCI_EXP_LNKCAP_PN)
  46
  47 #define PCI_EXP_SLTCAP_PSN_SHIFT        ctz32(PCI_EXP_SLTCAP_PSN)
  48
  49 #define PCI_EXP_SLTCTL_IND_RESERVED     0x0
  50 #define PCI_EXP_SLTCTL_IND_ON           0x1
  51 #define PCI_EXP_SLTCTL_IND_BLINK        0x2
  52 #define PCI_EXP_SLTCTL_IND_OFF          0x3
  53 #define PCI_EXP_SLTCTL_AIC_SHIFT        ctz32(PCI_EXP_SLTCTL_AIC)
  54 #define PCI_EXP_SLTCTL_AIC_OFF                          \
  55     (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT)
  56
  57 #define PCI_EXP_SLTCTL_PIC_SHIFT        ctz32(PCI_EXP_SLTCTL_PIC)
  58 #define PCI_EXP_SLTCTL_PIC_OFF                          \
  59     (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT)
  60 #define PCI_EXP_SLTCTL_PIC_ON                          \
  61     (PCI_EXP_SLTCTL_IND_ON << PCI_EXP_SLTCTL_PIC_SHIFT)
  62
  63 #define PCI_EXP_SLTCTL_SUPPORTED        \
  64             (PCI_EXP_SLTCTL_ABPE |      \
  65              PCI_EXP_SLTCTL_PDCE |      \
  66              PCI_EXP_SLTCTL_CCIE |      \
  67              PCI_EXP_SLTCTL_HPIE |      \
  68              PCI_EXP_SLTCTL_AIC |       \
  69              PCI_EXP_SLTCTL_PCC |       \
  70              PCI_EXP_SLTCTL_EIC)
  71
  72 #define PCI_EXP_DEVCAP2_EFF             0x100000
  73 #define PCI_EXP_DEVCAP2_EETLPP          0x200000
  74
  75 #define PCI_EXP_DEVCTL2_EETLPPB         0x8000
  76
  77 /* ARI */
  78 #define PCI_ARI_VER                     1
  79 #define PCI_ARI_SIZEOF                  8
  80
  81 /* AER */
  82 #define PCI_ERR_VER                     2
  83 #define PCI_ERR_SIZEOF                  0x48
  84
  85 #define PCI_ERR_UNC_SDN                 0x00000020      /* surprise down */
  86 #define PCI_ERR_UNC_ACSV                0x00200000      /* ACS Violation */
  87 #define PCI_ERR_UNC_INTN                0x00400000      /* Internal Error */
  88 #define PCI_ERR_UNC_MCBTLP              0x00800000      /* MC Blcoked TLP */
  89 #define PCI_ERR_UNC_ATOP_EBLOCKED       0x01000000      /* atomic op egress blocked */
  90 #define PCI_ERR_UNC_TLP_PRF_BLOCKED     0x02000000      /* TLP Prefix Blocked */
  91 #define PCI_ERR_COR_ADV_NONFATAL        0x00002000      /* Advisory Non-Fatal */
  92 #define PCI_ERR_COR_INTERNAL            0x00004000      /* Corrected Internal */
  93 #define PCI_ERR_COR_HL_OVERFLOW         0x00008000      /* Header Long Overflow */
  94 #define PCI_ERR_CAP_FEP_MASK            0x0000001f
  95 #define PCI_ERR_CAP_MHRC                0x00000200
  96 #define PCI_ERR_CAP_MHRE                0x00000400
  97 #define PCI_ERR_CAP_TLP                 0x00000800
  98
  99 #define PCI_ERR_HEADER_LOG_SIZE         16
 100 #define PCI_ERR_TLP_PREFIX_LOG          0x38
 101 #define PCI_ERR_TLP_PREFIX_LOG_SIZE     16
 102
 103 #define PCI_SEC_STATUS_RCV_SYSTEM_ERROR         0x4000
 104
 105 /* aer root error command/status */
 106 #define PCI_ERR_ROOT_CMD_EN_MASK        (PCI_ERR_ROOT_CMD_COR_EN |      \
 107                                          PCI_ERR_ROOT_CMD_NONFATAL_EN | \
 108                                          PCI_ERR_ROOT_CMD_FATAL_EN)
 109
 110 #define PCI_ERR_ROOT_IRQ_MAX            32
 111 #define PCI_ERR_ROOT_IRQ                0xf8000000
 112 #define PCI_ERR_ROOT_IRQ_SHIFT          ctz32(PCI_ERR_ROOT_IRQ)
 113 #define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV |         \
 114                                          PCI_ERR_ROOT_MULTI_COR_RCV |   \
 115                                          PCI_ERR_ROOT_UNCOR_RCV |       \
 116                                          PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
 117                                          PCI_ERR_ROOT_FIRST_FATAL |     \
 118                                          PCI_ERR_ROOT_NONFATAL_RCV |    \
 119                                          PCI_ERR_ROOT_FATAL_RCV)
 120
 121 #define PCI_ERR_UNC_SUPPORTED           (PCI_ERR_UNC_DLP |              \
 122                                          PCI_ERR_UNC_SDN |              \
 123                                          PCI_ERR_UNC_POISON_TLP |       \
 124                                          PCI_ERR_UNC_FCP |              \
 125                                          PCI_ERR_UNC_COMP_TIME |        \
 126                                          PCI_ERR_UNC_COMP_ABORT |       \
 127                                          PCI_ERR_UNC_UNX_COMP |         \
 128                                          PCI_ERR_UNC_RX_OVER |          \
 129                                          PCI_ERR_UNC_MALF_TLP |         \
 130                                          PCI_ERR_UNC_ECRC |             \
 131                                          PCI_ERR_UNC_UNSUP |            \
 132                                          PCI_ERR_UNC_ACSV |             \
 133                                          PCI_ERR_UNC_INTN |             \
 134                                          PCI_ERR_UNC_MCBTLP |           \
 135                                          PCI_ERR_UNC_ATOP_EBLOCKED |    \
 136                                          PCI_ERR_UNC_TLP_PRF_BLOCKED)
 137
 138 #define PCI_ERR_UNC_SEVERITY_DEFAULT    (PCI_ERR_UNC_DLP |              \
 139                                          PCI_ERR_UNC_SDN |              \
 140                                          PCI_ERR_UNC_FCP |              \
 141                                          PCI_ERR_UNC_RX_OVER |          \
 142                                          PCI_ERR_UNC_MALF_TLP |         \
 143                                          PCI_ERR_UNC_INTN)
 144
 145 #define PCI_ERR_COR_SUPPORTED           (PCI_ERR_COR_RCVR |             \
 146                                          PCI_ERR_COR_BAD_TLP |          \
 147                                          PCI_ERR_COR_BAD_DLLP |         \
 148                                          PCI_ERR_COR_REP_ROLL |         \
 149                                          PCI_ERR_COR_REP_TIMER |        \
 150                                          PCI_ERR_COR_ADV_NONFATAL |     \
 151                                          PCI_ERR_COR_INTERNAL |         \
 152                                          PCI_ERR_COR_HL_OVERFLOW)
 153
 154 #define PCI_ERR_COR_MASK_DEFAULT        (PCI_ERR_COR_ADV_NONFATAL |     \
 155                                          PCI_ERR_COR_INTERNAL |         \
 156                                          PCI_ERR_COR_HL_OVERFLOW)
 157
 158 #endif /* QEMU_PCIE_REGS_H */