2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2015 Imagination Technologies
13 #define TYPE_MIPS_GCR "mips-gcr"
14 #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
16 #define GCR_BASE_ADDR 0x1fbf8000ULL
17 #define GCR_ADDRSPACE_SZ 0x8000
19 /* Offsets to register blocks */
20 #define MIPS_GCB_OFS 0x0000 /* Global Control Block */
21 #define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
22 #define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
23 #define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
25 /* Global Control Block Register Map */
26 #define GCR_CONFIG_OFS 0x0000
27 #define GCR_BASE_OFS 0x0008
28 #define GCR_REV_OFS 0x0030
29 #define GCR_CPC_BASE_OFS 0x0088
30 #define GCR_CPC_STATUS_OFS 0x00F0
31 #define GCR_L2_CONFIG_OFS 0x0130
33 /* Core Local and Core Other Block Register Map */
34 #define GCR_CL_CONFIG_OFS 0x0010
35 #define GCR_CL_OTHER_OFS 0x0018
37 /* GCR_L2_CONFIG register fields */
38 #define GCR_L2_CONFIG_BYPASS_SHF 20
39 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
41 /* GCR_CPC_BASE register fields */
42 #define GCR_CPC_BASE_CPCEN_MSK 1
43 #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
44 #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
46 typedef struct MIPSGCRState MIPSGCRState;
48 SysBusDevice parent_obj;
59 #endif /* _MIPS_GCR_H */