4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef HW_ARM_GIC_COMMON_H
22 #define HW_ARM_GIC_COMMON_H
24 #include "hw/sysbus.h"
26 /* Maximum number of possible interrupts, determined by the GIC architecture */
27 #define GIC_MAXIRQ 1020
28 /* First 32 are private to each CPU (SGIs and PPIs). */
29 #define GIC_INTERNAL 32
30 #define GIC_NR_SGIS 16
31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
34 #define MAX_NR_GROUP_PRIO 128
35 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
38 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
40 typedef struct gic_irq_state {
41 /* The enable bits are only banked for per-cpu interrupts. */
46 bool model; /* 0 = N:N, 1 = 1:N */
47 bool edge_trigger; /* true: edge-triggered, false: level-triggered */
51 typedef struct GICState {
53 SysBusDevice parent_obj;
56 qemu_irq parent_irq[GIC_NCPU];
57 qemu_irq parent_fiq[GIC_NCPU];
58 /* GICD_CTLR; for a GIC with the security extensions the NS banked version
59 * of this register is just an alias of bit 1 of the S banked version.
62 /* GICC_CTLR; again, the NS banked version is just aliases of bits of
63 * the S banked register, so our state only needs to store the S version.
65 uint32_t cpu_ctlr[GIC_NCPU];
67 gic_irq_state irq_state[GIC_MAXIRQ];
68 uint8_t irq_target[GIC_MAXIRQ];
69 uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
70 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
71 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
72 /* For each SGI on the target CPU, we store 8 bits
73 * indicating which source CPUs have made this SGI
74 * pending on the target CPU. These correspond to
75 * the bytes in the GIC_SPENDSGIR* registers as
76 * read by the target CPU.
78 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
80 uint16_t priority_mask[GIC_NCPU];
81 uint16_t running_irq[GIC_NCPU];
82 uint16_t running_priority[GIC_NCPU];
83 uint16_t current_pending[GIC_NCPU];
85 /* If we present the GICv2 without security extensions to a guest,
86 * the guest can configure the GICC_CTLR to configure group 1 binary point
88 * For a GIC with Security Extensions we use use bpr for the
89 * secure copy and abpr as storage for the non-secure copy of the register.
91 uint8_t bpr[GIC_NCPU];
92 uint8_t abpr[GIC_NCPU];
94 /* The APR is implementation defined, so we choose a layout identical to
95 * the KVM ABI layout for QEMU's implementation of the gic:
96 * If an interrupt for preemption level X is active, then
97 * APRn[X mod 32] == 0b1, where n = X / 32
98 * otherwise the bit is clear.
100 * TODO: rewrite the interrupt acknowlege/complete routines to use
101 * the APR registers to track the necessary information to update
102 * s->running_priority[] on interrupt completion (ie completely remove
103 * last_active[][] and running_irq[]). This will be necessary if we ever
104 * want to support TCG<->KVM migration, or TCG guests which can
105 * do power management involving powering down and restarting
108 uint32_t apr[GIC_NR_APRS][GIC_NCPU];
112 MemoryRegion iomem; /* Distributor */
113 /* This is just so we can have an opaque pointer which identifies
114 * both this GIC and which CPU interface we should be accessing.
116 struct GICState *backref[GIC_NCPU];
117 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
121 int dev_fd; /* kvm device fd if backed by kvm vgic support */
124 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
125 #define ARM_GIC_COMMON(obj) \
126 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
127 #define ARM_GIC_COMMON_CLASS(klass) \
128 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
129 #define ARM_GIC_COMMON_GET_CLASS(obj) \
130 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
132 typedef struct ARMGICCommonClass {
134 SysBusDeviceClass parent_class;
137 void (*pre_save)(GICState *s);
138 void (*post_load)(GICState *s);