2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 #include "qemu-common.h"
21 #include "hw/arm/arm.h"
22 #include "hw/intc/arm_gic.h"
23 #include "hw/net/cadence_gem.h"
24 #include "hw/char/cadence_uart.h"
26 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
27 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
30 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
31 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
32 #define XLNX_ZYNQMP_NUM_GEMS 4
33 #define XLNX_ZYNQMP_NUM_UARTS 2
35 #define XLNX_ZYNQMP_GIC_REGIONS 2
37 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
38 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
39 * aligned address in the 64k region. To implement each GIC region needs a
40 * number of memory region aliases.
43 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000
44 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
46 typedef struct XlnxZynqMPState {
48 DeviceState parent_obj;
51 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
52 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
54 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
55 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
56 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];