qemu/hw/usb/hcd-ehci-sysbus.c

   1 /*
   2  * QEMU USB EHCI Emulation
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or(at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "hw/usb/hcd-ehci.h"
  19
  20 static const VMStateDescription vmstate_ehci_sysbus = {
  21     .name        = "ehci-sysbus",
  22     .version_id  = 2,
  23     .minimum_version_id  = 1,
  24     .fields = (VMStateField[]) {
  25         VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
  26         VMSTATE_END_OF_LIST()
  27     }
  28 };
  29
  30 static Property ehci_sysbus_properties[] = {
  31     DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
  32     DEFINE_PROP_END_OF_LIST(),
  33 };
  34
  35 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
  36 {
  37     SysBusDevice *d = SYS_BUS_DEVICE(dev);
  38     EHCISysBusState *i = SYS_BUS_EHCI(dev);
  39     EHCIState *s = &i->ehci;
  40
  41     usb_ehci_realize(s, dev, errp);
  42     sysbus_init_irq(d, &s->irq);
  43 }
  44
  45 static void usb_ehci_sysbus_reset(DeviceState *dev)
  46 {
  47     SysBusDevice *d = SYS_BUS_DEVICE(dev);
  48     EHCISysBusState *i = SYS_BUS_EHCI(d);
  49     EHCIState *s = &i->ehci;
  50
  51     ehci_reset(s);
  52 }
  53
  54 static void ehci_sysbus_init(Object *obj)
  55 {
  56     SysBusDevice *d = SYS_BUS_DEVICE(obj);
  57     EHCISysBusState *i = SYS_BUS_EHCI(obj);
  58     SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
  59     EHCIState *s = &i->ehci;
  60
  61     s->capsbase = sec->capsbase;
  62     s->opregbase = sec->opregbase;
  63     s->portscbase = sec->portscbase;
  64     s->portnr = sec->portnr;
  65     s->as = &address_space_memory;
  66
  67     usb_ehci_init(s, DEVICE(obj));
  68     sysbus_init_mmio(d, &s->mem);
  69 }
  70
  71 static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
  72 {
  73     DeviceClass *dc = DEVICE_CLASS(klass);
  74     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
  75
  76     sec->portscbase = 0x44;
  77     sec->portnr = NB_PORTS;
  78
  79     dc->realize = usb_ehci_sysbus_realize;
  80     dc->vmsd = &vmstate_ehci_sysbus;
  81     dc->props = ehci_sysbus_properties;
  82     dc->reset = usb_ehci_sysbus_reset;
  83     set_bit(DEVICE_CATEGORY_USB, dc->categories);
  84 }
  85
  86 static const TypeInfo ehci_type_info = {
  87     .name          = TYPE_SYS_BUS_EHCI,
  88     .parent        = TYPE_SYS_BUS_DEVICE,
  89     .instance_size = sizeof(EHCISysBusState),
  90     .instance_init = ehci_sysbus_init,
  91     .abstract      = true,
  92     .class_init    = ehci_sysbus_class_init,
  93     .class_size    = sizeof(SysBusEHCIClass),
  94 };
  95
  96 static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
  97 {
  98     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
  99     DeviceClass *dc = DEVICE_CLASS(oc);
 100
 101     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 102     sec->capsbase = 0x100;
 103     sec->opregbase = 0x140;
 104 }
 105
 106 static const TypeInfo ehci_xlnx_type_info = {
 107     .name          = "xlnx,ps7-usb",
 108     .parent        = TYPE_SYS_BUS_EHCI,
 109     .class_init    = ehci_xlnx_class_init,
 110 };
 111
 112 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
 113 {
 114     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 115     DeviceClass *dc = DEVICE_CLASS(oc);
 116
 117     sec->capsbase = 0x0;
 118     sec->opregbase = 0x10;
 119     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 120 }
 121
 122 static const TypeInfo ehci_exynos4210_type_info = {
 123     .name          = TYPE_EXYNOS4210_EHCI,
 124     .parent        = TYPE_SYS_BUS_EHCI,
 125     .class_init    = ehci_exynos4210_class_init,
 126 };
 127
 128 static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
 129 {
 130     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 131     DeviceClass *dc = DEVICE_CLASS(oc);
 132
 133     sec->capsbase = 0x100;
 134     sec->opregbase = 0x140;
 135     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 136 }
 137
 138 static const TypeInfo ehci_tegra2_type_info = {
 139     .name          = TYPE_TEGRA2_EHCI,
 140     .parent        = TYPE_SYS_BUS_EHCI,
 141     .class_init    = ehci_tegra2_class_init,
 142 };
 143
 144 /*
 145  * Faraday FUSBH200 USB 2.0 EHCI
 146  */
 147
 148 /**
 149  * FUSBH200EHCIRegs:
 150  * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
 151  * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
 152  */
 153 enum FUSBH200EHCIRegs {
 154     FUSBH200_REG_EOF_ASTR = 0x34,
 155     FUSBH200_REG_BMCSR    = 0x40,
 156 };
 157
 158 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
 159 {
 160     EHCIState *s = opaque;
 161     hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
 162
 163     switch (off) {
 164     case FUSBH200_REG_EOF_ASTR:
 165         return 0x00000041;
 166     case FUSBH200_REG_BMCSR:
 167         /* High-Speed, VBUS valid, interrupt level-high active */
 168         return (2 << 9) | (1 << 8) | (1 << 3);
 169     }
 170
 171     return 0;
 172 }
 173
 174 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
 175                                 unsigned size)
 176 {
 177 }
 178
 179 static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
 180     .read = fusbh200_ehci_read,
 181     .write = fusbh200_ehci_write,
 182     .valid.min_access_size = 4,
 183     .valid.max_access_size = 4,
 184     .endianness = DEVICE_LITTLE_ENDIAN,
 185 };
 186
 187 static void fusbh200_ehci_init(Object *obj)
 188 {
 189     EHCISysBusState *i = SYS_BUS_EHCI(obj);
 190     FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
 191     EHCIState *s = &i->ehci;
 192
 193     memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
 194                           "fusbh200", 0x4c);
 195     memory_region_add_subregion(&s->mem,
 196                                 s->opregbase + s->portscbase + 4 * s->portnr,
 197                                 &f->mem_vendor);
 198 }
 199
 200 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
 201 {
 202     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 203     DeviceClass *dc = DEVICE_CLASS(oc);
 204
 205     sec->capsbase = 0x0;
 206     sec->opregbase = 0x10;
 207     sec->portscbase = 0x20;
 208     sec->portnr = 1;
 209     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 210 }
 211
 212 static const TypeInfo ehci_fusbh200_type_info = {
 213     .name          = TYPE_FUSBH200_EHCI,
 214     .parent        = TYPE_SYS_BUS_EHCI,
 215     .instance_size = sizeof(FUSBH200EHCIState),
 216     .instance_init = fusbh200_ehci_init,
 217     .class_init    = fusbh200_ehci_class_init,
 218 };
 219
 220 static void ehci_sysbus_register_types(void)
 221 {
 222     type_register_static(&ehci_type_info);
 223     type_register_static(&ehci_xlnx_type_info);
 224     type_register_static(&ehci_exynos4210_type_info);
 225     type_register_static(&ehci_tegra2_type_info);
 226     type_register_static(&ehci_fusbh200_type_info);
 227 }
 228
 229 type_init(ehci_sysbus_register_types)