qemu/hw/usb/hcd-ehci-sysbus.c

   1 /*
   2  * QEMU USB EHCI Emulation
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or(at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "hw/usb/hcd-ehci.h"
  20
  21 static const VMStateDescription vmstate_ehci_sysbus = {
  22     .name        = "ehci-sysbus",
  23     .version_id  = 2,
  24     .minimum_version_id  = 1,
  25     .fields = (VMStateField[]) {
  26         VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
  27         VMSTATE_END_OF_LIST()
  28     }
  29 };
  30
  31 static Property ehci_sysbus_properties[] = {
  32     DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
  33     DEFINE_PROP_END_OF_LIST(),
  34 };
  35
  36 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
  37 {
  38     SysBusDevice *d = SYS_BUS_DEVICE(dev);
  39     EHCISysBusState *i = SYS_BUS_EHCI(dev);
  40     EHCIState *s = &i->ehci;
  41
  42     usb_ehci_realize(s, dev, errp);
  43     sysbus_init_irq(d, &s->irq);
  44 }
  45
  46 static void usb_ehci_sysbus_reset(DeviceState *dev)
  47 {
  48     SysBusDevice *d = SYS_BUS_DEVICE(dev);
  49     EHCISysBusState *i = SYS_BUS_EHCI(d);
  50     EHCIState *s = &i->ehci;
  51
  52     ehci_reset(s);
  53 }
  54
  55 static void ehci_sysbus_init(Object *obj)
  56 {
  57     SysBusDevice *d = SYS_BUS_DEVICE(obj);
  58     EHCISysBusState *i = SYS_BUS_EHCI(obj);
  59     SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
  60     EHCIState *s = &i->ehci;
  61
  62     s->capsbase = sec->capsbase;
  63     s->opregbase = sec->opregbase;
  64     s->portscbase = sec->portscbase;
  65     s->portnr = sec->portnr;
  66     s->as = &address_space_memory;
  67
  68     usb_ehci_init(s, DEVICE(obj));
  69     sysbus_init_mmio(d, &s->mem);
  70 }
  71
  72 static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
  73 {
  74     DeviceClass *dc = DEVICE_CLASS(klass);
  75     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
  76
  77     sec->portscbase = 0x44;
  78     sec->portnr = NB_PORTS;
  79
  80     dc->realize = usb_ehci_sysbus_realize;
  81     dc->vmsd = &vmstate_ehci_sysbus;
  82     dc->props = ehci_sysbus_properties;
  83     dc->reset = usb_ehci_sysbus_reset;
  84     set_bit(DEVICE_CATEGORY_USB, dc->categories);
  85 }
  86
  87 static const TypeInfo ehci_type_info = {
  88     .name          = TYPE_SYS_BUS_EHCI,
  89     .parent        = TYPE_SYS_BUS_DEVICE,
  90     .instance_size = sizeof(EHCISysBusState),
  91     .instance_init = ehci_sysbus_init,
  92     .abstract      = true,
  93     .class_init    = ehci_sysbus_class_init,
  94     .class_size    = sizeof(SysBusEHCIClass),
  95 };
  96
  97 static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
  98 {
  99     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 100     DeviceClass *dc = DEVICE_CLASS(oc);
 101
 102     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 103     sec->capsbase = 0x100;
 104     sec->opregbase = 0x140;
 105 }
 106
 107 static const TypeInfo ehci_xlnx_type_info = {
 108     .name          = "xlnx,ps7-usb",
 109     .parent        = TYPE_SYS_BUS_EHCI,
 110     .class_init    = ehci_xlnx_class_init,
 111 };
 112
 113 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
 114 {
 115     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 116     DeviceClass *dc = DEVICE_CLASS(oc);
 117
 118     sec->capsbase = 0x0;
 119     sec->opregbase = 0x10;
 120     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 121 }
 122
 123 static const TypeInfo ehci_exynos4210_type_info = {
 124     .name          = TYPE_EXYNOS4210_EHCI,
 125     .parent        = TYPE_SYS_BUS_EHCI,
 126     .class_init    = ehci_exynos4210_class_init,
 127 };
 128
 129 static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
 130 {
 131     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 132     DeviceClass *dc = DEVICE_CLASS(oc);
 133
 134     sec->capsbase = 0x100;
 135     sec->opregbase = 0x140;
 136     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 137 }
 138
 139 static const TypeInfo ehci_tegra2_type_info = {
 140     .name          = TYPE_TEGRA2_EHCI,
 141     .parent        = TYPE_SYS_BUS_EHCI,
 142     .class_init    = ehci_tegra2_class_init,
 143 };
 144
 145 /*
 146  * Faraday FUSBH200 USB 2.0 EHCI
 147  */
 148
 149 /**
 150  * FUSBH200EHCIRegs:
 151  * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
 152  * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
 153  */
 154 enum FUSBH200EHCIRegs {
 155     FUSBH200_REG_EOF_ASTR = 0x34,
 156     FUSBH200_REG_BMCSR    = 0x40,
 157 };
 158
 159 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
 160 {
 161     EHCIState *s = opaque;
 162     hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
 163
 164     switch (off) {
 165     case FUSBH200_REG_EOF_ASTR:
 166         return 0x00000041;
 167     case FUSBH200_REG_BMCSR:
 168         /* High-Speed, VBUS valid, interrupt level-high active */
 169         return (2 << 9) | (1 << 8) | (1 << 3);
 170     }
 171
 172     return 0;
 173 }
 174
 175 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
 176                                 unsigned size)
 177 {
 178 }
 179
 180 static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
 181     .read = fusbh200_ehci_read,
 182     .write = fusbh200_ehci_write,
 183     .valid.min_access_size = 4,
 184     .valid.max_access_size = 4,
 185     .endianness = DEVICE_LITTLE_ENDIAN,
 186 };
 187
 188 static void fusbh200_ehci_init(Object *obj)
 189 {
 190     EHCISysBusState *i = SYS_BUS_EHCI(obj);
 191     FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
 192     EHCIState *s = &i->ehci;
 193
 194     memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
 195                           "fusbh200", 0x4c);
 196     memory_region_add_subregion(&s->mem,
 197                                 s->opregbase + s->portscbase + 4 * s->portnr,
 198                                 &f->mem_vendor);
 199 }
 200
 201 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
 202 {
 203     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
 204     DeviceClass *dc = DEVICE_CLASS(oc);
 205
 206     sec->capsbase = 0x0;
 207     sec->opregbase = 0x10;
 208     sec->portscbase = 0x20;
 209     sec->portnr = 1;
 210     set_bit(DEVICE_CATEGORY_USB, dc->categories);
 211 }
 212
 213 static const TypeInfo ehci_fusbh200_type_info = {
 214     .name          = TYPE_FUSBH200_EHCI,
 215     .parent        = TYPE_SYS_BUS_EHCI,
 216     .instance_size = sizeof(FUSBH200EHCIState),
 217     .instance_init = fusbh200_ehci_init,
 218     .class_init    = fusbh200_ehci_class_init,
 219 };
 220
 221 static void ehci_sysbus_register_types(void)
 222 {
 223     type_register_static(&ehci_type_info);
 224     type_register_static(&ehci_xlnx_type_info);
 225     type_register_static(&ehci_exynos4210_type_info);
 226     type_register_static(&ehci_tegra2_type_info);
 227     type_register_static(&ehci_fusbh200_type_info);
 228 }
 229
 230 type_init(ehci_sysbus_register_types)