2 * ARM AMBA PrimeCell PL031 RTC
4 * Copyright (c) 2007 CodeSourcery
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
14 #include "hw/sysbus.h"
15 #include "qemu/timer.h"
16 #include "sysemu/sysemu.h"
21 #define DPRINTF(fmt, ...) \
22 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
24 #define DPRINTF(fmt, ...) do {} while(0)
27 #define RTC_DR 0x00 /* Data read register */
28 #define RTC_MR 0x04 /* Match register */
29 #define RTC_LR 0x08 /* Data load register */
30 #define RTC_CR 0x0c /* Control register */
31 #define RTC_IMSC 0x10 /* Interrupt mask and set register */
32 #define RTC_RIS 0x14 /* Raw interrupt status register */
33 #define RTC_MIS 0x18 /* Masked interrupt status register */
34 #define RTC_ICR 0x1c /* Interrupt clear register */
36 #define TYPE_PL031 "pl031"
37 #define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
39 typedef struct PL031State {
40 SysBusDevice parent_obj;
46 /* Needed to preserve the tick_count across migration, even if the
47 * absolute value of the rtc_clock is different on the source and
50 uint32_t tick_offset_vmstate;
60 static const unsigned char pl031_id[] = {
61 0x31, 0x10, 0x14, 0x00, /* Device ID */
62 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
65 static void pl031_update(PL031State *s)
67 qemu_set_irq(s->irq, s->is & s->im);
70 static void pl031_interrupt(void * opaque)
72 PL031State *s = (PL031State *)opaque;
75 DPRINTF("Alarm raised\n");
79 static uint32_t pl031_get_count(PL031State *s)
81 int64_t now = qemu_clock_get_ns(rtc_clock);
82 return s->tick_offset + now / get_ticks_per_sec();
85 static void pl031_set_alarm(PL031State *s)
89 /* The timer wraps around. This subtraction also wraps in the same way,
90 and gives correct results when alarm < now_ticks. */
91 ticks = s->mr - pl031_get_count(s);
92 DPRINTF("Alarm set in %ud ticks\n", ticks);
97 int64_t now = qemu_clock_get_ns(rtc_clock);
98 timer_mod(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
102 static uint64_t pl031_read(void *opaque, hwaddr offset,
105 PL031State *s = (PL031State *)opaque;
107 if (offset >= 0xfe0 && offset < 0x1000)
108 return pl031_id[(offset - 0xfe0) >> 2];
112 return pl031_get_count(s);
122 /* RTC is permanently enabled. */
125 return s->is & s->im;
127 qemu_log_mask(LOG_GUEST_ERROR,
128 "pl031: read of write-only register at offset 0x%x\n",
132 qemu_log_mask(LOG_GUEST_ERROR,
133 "pl031_read: Bad offset 0x%x\n", (int)offset);
140 static void pl031_write(void * opaque, hwaddr offset,
141 uint64_t value, unsigned size)
143 PL031State *s = (PL031State *)opaque;
148 s->tick_offset += value - pl031_get_count(s);
157 DPRINTF("Interrupt mask %d\n", s->im);
161 /* The PL031 documentation (DDI0224B) states that the interrupt is
162 cleared when bit 0 of the written value is set. However the
163 arm926e documentation (DDI0287B) states that the interrupt is
164 cleared when any value is written. */
165 DPRINTF("Interrupt cleared");
170 /* Written value is ignored. */
176 qemu_log_mask(LOG_GUEST_ERROR,
177 "pl031: write to read-only register at offset 0x%x\n",
182 qemu_log_mask(LOG_GUEST_ERROR,
183 "pl031_write: Bad offset 0x%x\n", (int)offset);
188 static const MemoryRegionOps pl031_ops = {
190 .write = pl031_write,
191 .endianness = DEVICE_NATIVE_ENDIAN,
194 static int pl031_init(SysBusDevice *dev)
196 PL031State *s = PL031(dev);
199 memory_region_init_io(&s->iomem, OBJECT(s), &pl031_ops, s, "pl031", 0x1000);
200 sysbus_init_mmio(dev, &s->iomem);
202 sysbus_init_irq(dev, &s->irq);
203 qemu_get_timedate(&tm, 0);
204 s->tick_offset = mktimegm(&tm) -
205 qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec();
207 s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
211 static void pl031_pre_save(void *opaque)
213 PL031State *s = opaque;
215 /* tick_offset is base_time - rtc_clock base time. Instead, we want to
216 * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
217 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
218 s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
221 static int pl031_post_load(void *opaque, int version_id)
223 PL031State *s = opaque;
225 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
226 s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
231 static const VMStateDescription vmstate_pl031 = {
234 .minimum_version_id = 1,
235 .pre_save = pl031_pre_save,
236 .post_load = pl031_post_load,
237 .fields = (VMStateField[]) {
238 VMSTATE_UINT32(tick_offset_vmstate, PL031State),
239 VMSTATE_UINT32(mr, PL031State),
240 VMSTATE_UINT32(lr, PL031State),
241 VMSTATE_UINT32(cr, PL031State),
242 VMSTATE_UINT32(im, PL031State),
243 VMSTATE_UINT32(is, PL031State),
244 VMSTATE_END_OF_LIST()
248 static void pl031_class_init(ObjectClass *klass, void *data)
250 DeviceClass *dc = DEVICE_CLASS(klass);
251 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
253 k->init = pl031_init;
254 dc->vmsd = &vmstate_pl031;
257 static const TypeInfo pl031_info = {
259 .parent = TYPE_SYS_BUS_DEVICE,
260 .instance_size = sizeof(PL031State),
261 .class_init = pl031_class_init,
264 static void pl031_register_types(void)
266 type_register_static(&pl031_info);
269 type_init(pl031_register_types)