2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/timer/m48t59.h"
27 #include "qemu/timer.h"
28 #include "sysemu/sysemu.h"
29 #include "hw/sysbus.h"
30 #include "hw/isa/isa.h"
31 #include "exec/address-spaces.h"
35 #if defined(DEBUG_NVRAM)
36 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
38 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
41 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
42 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
43 OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
44 #define M48TXX_SYS_BUS_CLASS(klass) \
45 OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
46 #define M48TXX_SYS_BUS(obj) \
47 OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
49 #define TYPE_M48TXX_ISA "isa-m48txx"
50 #define M48TXX_ISA_GET_CLASS(obj) \
51 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
52 #define M48TXX_ISA_CLASS(klass) \
53 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
54 #define M48TXX_ISA(obj) \
55 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
58 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
59 * alarm and a watchdog timer and related control registers. In the
60 * PPC platform there is also a nvram lock function.
63 typedef struct M48txxInfo {
65 const char *sysbus_name;
66 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
72 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
73 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
74 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
77 typedef struct M48t59State {
78 /* Hardware parameters */
86 /* Alarm & watchdog */
88 QEMUTimer *alrm_timer;
92 /* Model parameters */
93 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
99 typedef struct M48txxISAState {
100 ISADevice parent_obj;
106 typedef struct M48txxISADeviceClass {
107 ISADeviceClass parent_class;
109 } M48txxISADeviceClass;
111 typedef struct M48txxSysBusState {
112 SysBusDevice parent_obj;
117 typedef struct M48txxSysBusDeviceClass {
118 SysBusDeviceClass parent_class;
120 } M48txxSysBusDeviceClass;
122 static M48txxInfo m48txx_info[] = {
124 .sysbus_name = "sysbus-m48t02",
128 .sysbus_name = "sysbus-m48t08",
132 .sysbus_name = "sysbus-m48t59",
136 .isa_name = "isa-m48t59",
143 /* Fake timer functions */
145 /* Alarm management */
146 static void alarm_cb (void *opaque)
150 M48t59State *NVRAM = opaque;
152 qemu_set_irq(NVRAM->IRQ, 1);
153 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
154 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
155 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
156 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
157 /* Repeat once a month */
158 qemu_get_timedate(&tm, NVRAM->time_offset);
160 if (tm.tm_mon == 13) {
164 next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
165 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
166 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
167 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
168 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
169 /* Repeat once a day */
170 next_time = 24 * 60 * 60;
171 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
172 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
173 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
174 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
175 /* Repeat once an hour */
177 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
178 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
179 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
180 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
181 /* Repeat once a minute */
184 /* Repeat once a second */
187 timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
189 qemu_set_irq(NVRAM->IRQ, 0);
192 static void set_alarm(M48t59State *NVRAM)
195 if (NVRAM->alrm_timer != NULL) {
196 timer_del(NVRAM->alrm_timer);
197 diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
199 timer_mod(NVRAM->alrm_timer, diff * 1000);
203 /* RTC management helpers */
204 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
206 qemu_get_timedate(tm, NVRAM->time_offset);
209 static void set_time(M48t59State *NVRAM, struct tm *tm)
211 NVRAM->time_offset = qemu_timedate_diff(tm);
215 /* Watchdog management */
216 static void watchdog_cb (void *opaque)
218 M48t59State *NVRAM = opaque;
220 NVRAM->buffer[0x1FF0] |= 0x80;
221 if (NVRAM->buffer[0x1FF7] & 0x80) {
222 NVRAM->buffer[0x1FF7] = 0x00;
223 NVRAM->buffer[0x1FFC] &= ~0x40;
224 /* May it be a hw CPU Reset instead ? */
225 qemu_system_reset_request();
227 qemu_set_irq(NVRAM->IRQ, 1);
228 qemu_set_irq(NVRAM->IRQ, 0);
232 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
234 uint64_t interval; /* in 1/16 seconds */
236 NVRAM->buffer[0x1FF0] &= ~0x80;
237 if (NVRAM->wd_timer != NULL) {
238 timer_del(NVRAM->wd_timer);
240 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
241 timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
242 ((interval * 1000) >> 4));
247 /* Direct access to NVRAM */
248 static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
253 if (addr > 0x1FF8 && addr < 0x2000)
254 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
256 /* check for NVRAM access */
257 if ((NVRAM->model == 2 && addr < 0x7f8) ||
258 (NVRAM->model == 8 && addr < 0x1ff8) ||
259 (NVRAM->model == 59 && addr < 0x1ff0)) {
266 /* flags register : read-only */
273 tmp = from_bcd(val & 0x7F);
274 if (tmp >= 0 && tmp <= 59) {
275 NVRAM->alarm.tm_sec = tmp;
276 NVRAM->buffer[0x1FF2] = val;
282 tmp = from_bcd(val & 0x7F);
283 if (tmp >= 0 && tmp <= 59) {
284 NVRAM->alarm.tm_min = tmp;
285 NVRAM->buffer[0x1FF3] = val;
291 tmp = from_bcd(val & 0x3F);
292 if (tmp >= 0 && tmp <= 23) {
293 NVRAM->alarm.tm_hour = tmp;
294 NVRAM->buffer[0x1FF4] = val;
300 tmp = from_bcd(val & 0x3F);
302 NVRAM->alarm.tm_mday = tmp;
303 NVRAM->buffer[0x1FF5] = val;
309 NVRAM->buffer[0x1FF6] = val;
313 NVRAM->buffer[0x1FF7] = val;
314 set_up_watchdog(NVRAM, val);
319 NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
324 tmp = from_bcd(val & 0x7F);
325 if (tmp >= 0 && tmp <= 59) {
326 get_time(NVRAM, &tm);
328 set_time(NVRAM, &tm);
330 if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
332 NVRAM->stop_time = time(NULL);
334 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
335 NVRAM->stop_time = 0;
338 NVRAM->buffer[addr] = val & 0x80;
343 tmp = from_bcd(val & 0x7F);
344 if (tmp >= 0 && tmp <= 59) {
345 get_time(NVRAM, &tm);
347 set_time(NVRAM, &tm);
353 tmp = from_bcd(val & 0x3F);
354 if (tmp >= 0 && tmp <= 23) {
355 get_time(NVRAM, &tm);
357 set_time(NVRAM, &tm);
362 /* day of the week / century */
363 tmp = from_bcd(val & 0x07);
364 get_time(NVRAM, &tm);
366 set_time(NVRAM, &tm);
367 NVRAM->buffer[addr] = val & 0x40;
372 tmp = from_bcd(val & 0x3F);
374 get_time(NVRAM, &tm);
376 set_time(NVRAM, &tm);
382 tmp = from_bcd(val & 0x1F);
383 if (tmp >= 1 && tmp <= 12) {
384 get_time(NVRAM, &tm);
386 set_time(NVRAM, &tm);
393 if (tmp >= 0 && tmp <= 99) {
394 get_time(NVRAM, &tm);
395 tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
396 set_time(NVRAM, &tm);
400 /* Check lock registers state */
401 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
403 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
406 if (addr < NVRAM->size) {
407 NVRAM->buffer[addr] = val & 0xFF;
413 static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
416 uint32_t retval = 0xFF;
418 /* check for NVRAM access */
419 if ((NVRAM->model == 2 && addr < 0x078f) ||
420 (NVRAM->model == 8 && addr < 0x1ff8) ||
421 (NVRAM->model == 59 && addr < 0x1ff0)) {
450 /* A read resets the watchdog */
451 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
460 get_time(NVRAM, &tm);
461 retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
466 get_time(NVRAM, &tm);
467 retval = to_bcd(tm.tm_min);
472 get_time(NVRAM, &tm);
473 retval = to_bcd(tm.tm_hour);
477 /* day of the week / century */
478 get_time(NVRAM, &tm);
479 retval = NVRAM->buffer[addr] | tm.tm_wday;
484 get_time(NVRAM, &tm);
485 retval = to_bcd(tm.tm_mday);
490 get_time(NVRAM, &tm);
491 retval = to_bcd(tm.tm_mon + 1);
496 get_time(NVRAM, &tm);
497 retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
500 /* Check lock registers state */
501 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
503 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
506 if (addr < NVRAM->size) {
507 retval = NVRAM->buffer[addr];
511 if (addr > 0x1FF9 && addr < 0x2000)
512 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
517 static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
519 NVRAM->lock ^= 1 << lock;
522 /* IO access to NVRAM */
523 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
526 M48t59State *NVRAM = opaque;
528 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
531 NVRAM->addr &= ~0x00FF;
535 NVRAM->addr &= ~0xFF00;
536 NVRAM->addr |= val << 8;
539 m48t59_write(NVRAM, NVRAM->addr, val);
540 NVRAM->addr = 0x0000;
547 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
549 M48t59State *NVRAM = opaque;
554 retval = m48t59_read(NVRAM, NVRAM->addr);
560 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
565 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
567 M48t59State *NVRAM = opaque;
569 m48t59_write(NVRAM, addr, value & 0xff);
572 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
574 M48t59State *NVRAM = opaque;
576 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
577 m48t59_write(NVRAM, addr + 1, value & 0xff);
580 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
582 M48t59State *NVRAM = opaque;
584 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
585 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
586 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
587 m48t59_write(NVRAM, addr + 3, value & 0xff);
590 static uint32_t nvram_readb (void *opaque, hwaddr addr)
592 M48t59State *NVRAM = opaque;
595 retval = m48t59_read(NVRAM, addr);
599 static uint32_t nvram_readw (void *opaque, hwaddr addr)
601 M48t59State *NVRAM = opaque;
604 retval = m48t59_read(NVRAM, addr) << 8;
605 retval |= m48t59_read(NVRAM, addr + 1);
609 static uint32_t nvram_readl (void *opaque, hwaddr addr)
611 M48t59State *NVRAM = opaque;
614 retval = m48t59_read(NVRAM, addr) << 24;
615 retval |= m48t59_read(NVRAM, addr + 1) << 16;
616 retval |= m48t59_read(NVRAM, addr + 2) << 8;
617 retval |= m48t59_read(NVRAM, addr + 3);
621 static const MemoryRegionOps nvram_ops = {
623 .read = { nvram_readb, nvram_readw, nvram_readl, },
624 .write = { nvram_writeb, nvram_writew, nvram_writel, },
626 .endianness = DEVICE_NATIVE_ENDIAN,
629 static const VMStateDescription vmstate_m48t59 = {
632 .minimum_version_id = 1,
633 .fields = (VMStateField[]) {
634 VMSTATE_UINT8(lock, M48t59State),
635 VMSTATE_UINT16(addr, M48t59State),
636 VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
637 VMSTATE_END_OF_LIST()
641 static void m48t59_reset_common(M48t59State *NVRAM)
645 if (NVRAM->alrm_timer != NULL)
646 timer_del(NVRAM->alrm_timer);
648 if (NVRAM->wd_timer != NULL)
649 timer_del(NVRAM->wd_timer);
652 static void m48t59_reset_isa(DeviceState *d)
654 M48txxISAState *isa = M48TXX_ISA(d);
655 M48t59State *NVRAM = &isa->state;
657 m48t59_reset_common(NVRAM);
660 static void m48t59_reset_sysbus(DeviceState *d)
662 M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
663 M48t59State *NVRAM = &sys->state;
665 m48t59_reset_common(NVRAM);
668 static const MemoryRegionOps m48t59_io_ops = {
670 .write = NVRAM_writeb,
672 .min_access_size = 1,
673 .max_access_size = 1,
675 .endianness = DEVICE_LITTLE_ENDIAN,
678 /* Initialisation routine */
679 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
680 uint32_t io_base, uint16_t size, int base_year,
687 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
688 if (!m48txx_info[i].sysbus_name ||
689 m48txx_info[i].size != size ||
690 m48txx_info[i].model != model) {
694 dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
695 qdev_prop_set_int32(dev, "base-year", base_year);
696 qdev_init_nofail(dev);
697 s = SYS_BUS_DEVICE(dev);
698 sysbus_connect_irq(s, 0, IRQ);
700 memory_region_add_subregion(get_system_io(), io_base,
701 sysbus_mmio_get_region(s, 1));
704 sysbus_mmio_map(s, 0, mem_base);
714 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
715 int base_year, int model)
720 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
721 if (!m48txx_info[i].isa_name ||
722 m48txx_info[i].size != size ||
723 m48txx_info[i].model != model) {
727 dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
728 qdev_prop_set_uint32(dev, "iobase", io_base);
729 qdev_prop_set_int32(dev, "base-year", base_year);
730 qdev_init_nofail(dev);
738 static void m48t59_realize_common(M48t59State *s, Error **errp)
740 s->buffer = g_malloc0(s->size);
741 if (s->model == 59) {
742 s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
743 s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
745 qemu_get_timedate(&s->alarm, 0);
747 vmstate_register(NULL, -1, &vmstate_m48t59, s);
750 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
752 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
753 ISADevice *isadev = ISA_DEVICE(dev);
754 M48txxISAState *d = M48TXX_ISA(dev);
755 M48t59State *s = &d->state;
757 s->model = u->info.model;
758 s->size = u->info.size;
759 isa_init_irq(isadev, &s->IRQ, 8);
760 m48t59_realize_common(s, errp);
761 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
762 if (d->io_base != 0) {
763 isa_register_ioport(isadev, &d->io, d->io_base);
767 static int m48t59_init1(SysBusDevice *dev)
769 M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
770 M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
771 Object *o = OBJECT(dev);
772 M48t59State *s = &d->state;
775 s->model = u->info.model;
776 s->size = u->info.size;
777 sysbus_init_irq(dev, &s->IRQ);
779 memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
781 memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
782 sysbus_init_mmio(dev, &s->iomem);
783 sysbus_init_mmio(dev, &d->io);
784 m48t59_realize_common(s, &err);
793 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
795 M48txxISAState *d = M48TXX_ISA(obj);
796 return m48t59_read(&d->state, addr);
799 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
801 M48txxISAState *d = M48TXX_ISA(obj);
802 m48t59_write(&d->state, addr, val);
805 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
807 M48txxISAState *d = M48TXX_ISA(obj);
808 m48t59_toggle_lock(&d->state, lock);
811 static Property m48t59_isa_properties[] = {
812 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
813 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
814 DEFINE_PROP_END_OF_LIST(),
817 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
819 DeviceClass *dc = DEVICE_CLASS(klass);
820 NvramClass *nc = NVRAM_CLASS(klass);
822 dc->realize = m48t59_isa_realize;
823 dc->reset = m48t59_reset_isa;
824 dc->props = m48t59_isa_properties;
825 nc->read = m48txx_isa_read;
826 nc->write = m48txx_isa_write;
827 nc->toggle_lock = m48txx_isa_toggle_lock;
830 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
832 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
833 M48txxInfo *info = data;
838 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
840 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
841 return m48t59_read(&d->state, addr);
844 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
846 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
847 m48t59_write(&d->state, addr, val);
850 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
852 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
853 m48t59_toggle_lock(&d->state, lock);
856 static Property m48t59_sysbus_properties[] = {
857 DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
858 DEFINE_PROP_END_OF_LIST(),
861 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
863 DeviceClass *dc = DEVICE_CLASS(klass);
864 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
865 NvramClass *nc = NVRAM_CLASS(klass);
867 k->init = m48t59_init1;
868 dc->reset = m48t59_reset_sysbus;
869 dc->props = m48t59_sysbus_properties;
870 nc->read = m48txx_sysbus_read;
871 nc->write = m48txx_sysbus_write;
872 nc->toggle_lock = m48txx_sysbus_toggle_lock;
875 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
877 M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
878 M48txxInfo *info = data;
883 static const TypeInfo nvram_info = {
885 .parent = TYPE_INTERFACE,
886 .class_size = sizeof(NvramClass),
889 static const TypeInfo m48txx_sysbus_type_info = {
890 .name = TYPE_M48TXX_SYS_BUS,
891 .parent = TYPE_SYS_BUS_DEVICE,
892 .instance_size = sizeof(M48txxSysBusState),
894 .class_init = m48txx_sysbus_class_init,
895 .interfaces = (InterfaceInfo[]) {
901 static const TypeInfo m48txx_isa_type_info = {
902 .name = TYPE_M48TXX_ISA,
903 .parent = TYPE_ISA_DEVICE,
904 .instance_size = sizeof(M48txxISAState),
906 .class_init = m48txx_isa_class_init,
907 .interfaces = (InterfaceInfo[]) {
913 static void m48t59_register_types(void)
915 TypeInfo sysbus_type_info = {
916 .parent = TYPE_M48TXX_SYS_BUS,
917 .class_size = sizeof(M48txxSysBusDeviceClass),
918 .class_init = m48txx_sysbus_concrete_class_init,
920 TypeInfo isa_type_info = {
921 .parent = TYPE_M48TXX_ISA,
922 .class_size = sizeof(M48txxISADeviceClass),
923 .class_init = m48txx_isa_concrete_class_init,
927 type_register_static(&nvram_info);
928 type_register_static(&m48txx_sysbus_type_info);
929 type_register_static(&m48txx_isa_type_info);
931 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
932 if (m48txx_info[i].sysbus_name) {
933 sysbus_type_info.name = m48txx_info[i].sysbus_name;
934 sysbus_type_info.class_data = &m48txx_info[i];
935 type_register(&sysbus_type_info);
938 if (m48txx_info[i].isa_name) {
939 isa_type_info.name = m48txx_info[i].isa_name;
940 isa_type_info.class_data = &m48txx_info[i];
941 type_register(&isa_type_info);
946 type_init(m48t59_register_types)