qemu/hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/i386/ioapic.h"
  36 #include "qapi/visitor.h"
  37
  38 /*
  39  * I440FX chipset data sheet.
  40  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  41  */
  42
  43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
  44 #define I440FX_PCI_HOST_BRIDGE(obj) \
  45     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  46
  47 typedef struct I440FXState {
  48     PCIHostState parent_obj;
  49     PcPciInfo pci_info;
  50     uint64_t pci_hole64_size;
  51     uint32_t short_root_bus;
  52 } I440FXState;
  53
  54 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  55 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  56 #define XEN_PIIX_NUM_PIRQS      128ULL
  57 #define PIIX_PIRQC              0x60
  58
  59 /*
  60  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  61  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  62  */
  63 #define RCR_IOPORT 0xcf9
  64
  65 typedef struct PIIX3State {
  66     PCIDevice dev;
  67
  68     /*
  69      * bitmap to track pic levels.
  70      * The pic level is the logical OR of all the PCI irqs mapped to it
  71      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  72      *
  73      * PIRQ is mapped to PIC pins, we track it by
  74      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  75      * pic_irq * PIIX_NUM_PIRQS + pirq
  76      */
  77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  78 #error "unable to encode pic state in 64bit in pic_levels."
  79 #endif
  80     uint64_t pic_levels;
  81
  82     qemu_irq *pic;
  83
  84     /* This member isn't used. Just for save/load compatibility */
  85     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  86
  87     /* Reset Control Register contents */
  88     uint8_t rcr;
  89
  90     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  91     MemoryRegion rcr_mem;
  92 } PIIX3State;
  93
  94 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
  95 #define PIIX3_PCI_DEVICE(obj) \
  96     OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
  97
  98 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  99 #define I440FX_PCI_DEVICE(obj) \
 100     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 101
 102 struct PCII440FXState {
 103     /*< private >*/
 104     PCIDevice parent_obj;
 105     /*< public >*/
 106
 107     MemoryRegion *system_memory;
 108     MemoryRegion *pci_address_space;
 109     MemoryRegion *ram_memory;
 110     PAMMemoryRegion pam_regions[13];
 111     MemoryRegion smram_region;
 112     MemoryRegion smram, low_smram;
 113 };
 114
 115
 116 #define I440FX_PAM      0x59
 117 #define I440FX_PAM_SIZE 7
 118 #define I440FX_SMRAM    0x72
 119
 120 static void piix3_set_irq(void *opaque, int pirq, int level);
 121 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 122 static void piix3_write_config_xen(PCIDevice *dev,
 123                                uint32_t address, uint32_t val, int len);
 124
 125 /* return the global irq number corresponding to a given device irq
 126    pin. We could also use the bus number to have a more precise
 127    mapping. */
 128 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 129 {
 130     int slot_addend;
 131     slot_addend = (pci_dev->devfn >> 3) - 1;
 132     return (pci_intx + slot_addend) & 3;
 133 }
 134
 135 static void i440fx_update_memory_mappings(PCII440FXState *d)
 136 {
 137     int i;
 138     PCIDevice *pd = PCI_DEVICE(d);
 139
 140     memory_region_transaction_begin();
 141     for (i = 0; i < 13; i++) {
 142         pam_update(&d->pam_regions[i], i,
 143                    pd->config[I440FX_PAM + ((i + 1) / 2)]);
 144     }
 145     memory_region_set_enabled(&d->smram_region,
 146                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
 147     memory_region_set_enabled(&d->smram,
 148                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
 149     memory_region_transaction_commit();
 150 }
 151
 152
 153 static void i440fx_write_config(PCIDevice *dev,
 154                                 uint32_t address, uint32_t val, int len)
 155 {
 156     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 157
 158     /* XXX: implement SMRAM.D_LOCK */
 159     pci_default_write_config(dev, address, val, len);
 160     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 161         range_covers_byte(address, len, I440FX_SMRAM)) {
 162         i440fx_update_memory_mappings(d);
 163     }
 164 }
 165
 166 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 167 {
 168     PCII440FXState *d = opaque;
 169     PCIDevice *pd = PCI_DEVICE(d);
 170     int ret, i;
 171     uint8_t smm_enabled;
 172
 173     ret = pci_device_load(pd, f);
 174     if (ret < 0)
 175         return ret;
 176     i440fx_update_memory_mappings(d);
 177     qemu_get_8s(f, &smm_enabled);
 178
 179     if (version_id == 2) {
 180         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 181             qemu_get_be32(f); /* dummy load for compatibility */
 182         }
 183     }
 184
 185     return 0;
 186 }
 187
 188 static int i440fx_post_load(void *opaque, int version_id)
 189 {
 190     PCII440FXState *d = opaque;
 191
 192     i440fx_update_memory_mappings(d);
 193     return 0;
 194 }
 195
 196 static const VMStateDescription vmstate_i440fx = {
 197     .name = "I440FX",
 198     .version_id = 3,
 199     .minimum_version_id = 3,
 200     .minimum_version_id_old = 1,
 201     .load_state_old = i440fx_load_old,
 202     .post_load = i440fx_post_load,
 203     .fields = (VMStateField[]) {
 204         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 205         /* Used to be smm_enabled, which was basically always zero because
 206          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 207          */
 208         VMSTATE_UNUSED(1),
 209         VMSTATE_END_OF_LIST()
 210     }
 211 };
 212
 213 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 214                                               void *opaque, const char *name,
 215                                               Error **errp)
 216 {
 217     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 218     uint32_t value = s->pci_info.w32.begin;
 219
 220     visit_type_uint32(v, &value, name, errp);
 221 }
 222
 223 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 224                                             void *opaque, const char *name,
 225                                             Error **errp)
 226 {
 227     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 228     uint32_t value = s->pci_info.w32.end;
 229
 230     visit_type_uint32(v, &value, name, errp);
 231 }
 232
 233 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 234                                                 void *opaque, const char *name,
 235                                                 Error **errp)
 236 {
 237     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 238     Range w64;
 239
 240     pci_bus_get_w64_range(h->bus, &w64);
 241
 242     visit_type_uint64(v, &w64.begin, name, errp);
 243 }
 244
 245 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 246                                               void *opaque, const char *name,
 247                                               Error **errp)
 248 {
 249     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 250     Range w64;
 251
 252     pci_bus_get_w64_range(h->bus, &w64);
 253
 254     visit_type_uint64(v, &w64.end, name, errp);
 255 }
 256
 257 static void i440fx_pcihost_initfn(Object *obj)
 258 {
 259     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 260     I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
 261
 262     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 263                           "pci-conf-idx", 4);
 264     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 265                           "pci-conf-data", 4);
 266
 267     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 268                         i440fx_pcihost_get_pci_hole_start,
 269                         NULL, NULL, NULL, NULL);
 270
 271     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 272                         i440fx_pcihost_get_pci_hole_end,
 273                         NULL, NULL, NULL, NULL);
 274
 275     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 276                         i440fx_pcihost_get_pci_hole64_start,
 277                         NULL, NULL, NULL, NULL);
 278
 279     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 280                         i440fx_pcihost_get_pci_hole64_end,
 281                         NULL, NULL, NULL, NULL);
 282
 283     d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 284 }
 285
 286 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 287 {
 288     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 289     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 290
 291     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 292     sysbus_init_ioports(sbd, 0xcf8, 4);
 293
 294     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 295     sysbus_init_ioports(sbd, 0xcfc, 4);
 296 }
 297
 298 static void i440fx_realize(PCIDevice *dev, Error **errp)
 299 {
 300     dev->config[I440FX_SMRAM] = 0x02;
 301 }
 302
 303 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
 304                     int *piix3_devfn,
 305                     ISABus **isa_bus, qemu_irq *pic,
 306                     MemoryRegion *address_space_mem,
 307                     MemoryRegion *address_space_io,
 308                     ram_addr_t ram_size,
 309                     ram_addr_t below_4g_mem_size,
 310                     ram_addr_t above_4g_mem_size,
 311                     MemoryRegion *pci_address_space,
 312                     MemoryRegion *ram_memory)
 313 {
 314     DeviceState *dev;
 315     PCIBus *b;
 316     PCIDevice *d;
 317     PCIHostState *s;
 318     PIIX3State *piix3;
 319     PCII440FXState *f;
 320     unsigned i;
 321     I440FXState *i440fx;
 322
 323     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
 324     s = PCI_HOST_BRIDGE(dev);
 325     b = pci_bus_new(dev, NULL, pci_address_space,
 326                     address_space_io, 0, TYPE_PCI_BUS);
 327     s->bus = b;
 328     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 329     qdev_init_nofail(dev);
 330
 331     d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
 332     *pi440fx_state = I440FX_PCI_DEVICE(d);
 333     f = *pi440fx_state;
 334     f->system_memory = address_space_mem;
 335     f->pci_address_space = pci_address_space;
 336     f->ram_memory = ram_memory;
 337
 338     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 339     i440fx->pci_info.w32.begin = below_4g_mem_size;
 340
 341     /* setup pci memory mapping */
 342     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 343                            f->pci_address_space);
 344
 345     /* if *disabled* show SMRAM to all CPUs */
 346     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 347                              f->pci_address_space, 0xa0000, 0x20000);
 348     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 349                                         &f->smram_region, 1);
 350     memory_region_set_enabled(&f->smram_region, true);
 351
 352     /* smram, as seen by SMM CPUs */
 353     memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
 354     memory_region_set_enabled(&f->smram, true);
 355     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 356                              f->ram_memory, 0xa0000, 0x20000);
 357     memory_region_set_enabled(&f->low_smram, true);
 358     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 359     object_property_add_const_link(qdev_get_machine(), "smram",
 360                                    OBJECT(&f->smram), &error_abort);
 361
 362     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 363              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 364     for (i = 0; i < 12; ++i) {
 365         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 366                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 367                  PAM_EXPAN_SIZE);
 368     }
 369
 370     /* Xen supports additional interrupt routes from the PCI devices to
 371      * the IOAPIC: the four pins of each PCI device on the bus are also
 372      * connected to the IOAPIC directly.
 373      * These additional routes can be discovered through ACPI. */
 374     if (xen_enabled()) {
 375         PCIDevice *pci_dev = pci_create_simple_multifunction(b,
 376                              -1, true, "PIIX3-xen");
 377         piix3 = PIIX3_PCI_DEVICE(pci_dev);
 378         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 379                 piix3, XEN_PIIX_NUM_PIRQS);
 380     } else {
 381         PCIDevice *pci_dev = pci_create_simple_multifunction(b,
 382                              -1, true, "PIIX3");
 383         piix3 = PIIX3_PCI_DEVICE(pci_dev);
 384         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 385                 PIIX_NUM_PIRQS);
 386         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 387     }
 388     piix3->pic = pic;
 389     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 390
 391     *piix3_devfn = piix3->dev.devfn;
 392
 393     ram_size = ram_size / 8 / 1024 / 1024;
 394     if (ram_size > 255) {
 395         ram_size = 255;
 396     }
 397     d->config[0x57] = ram_size;
 398
 399     i440fx_update_memory_mappings(f);
 400
 401     return b;
 402 }
 403
 404 PCIBus *find_i440fx(void)
 405 {
 406     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 407                                    object_resolve_path("/machine/i440fx", NULL),
 408                                    TYPE_PCI_HOST_BRIDGE);
 409     return s ? s->bus : NULL;
 410 }
 411
 412 /* PIIX3 PCI to ISA bridge */
 413 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 414 {
 415     qemu_set_irq(piix3->pic[pic_irq],
 416                  !!(piix3->pic_levels &
 417                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 418                      (pic_irq * PIIX_NUM_PIRQS))));
 419 }
 420
 421 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
 422 {
 423     int pic_irq;
 424     uint64_t mask;
 425
 426     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 427     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 428         return;
 429     }
 430
 431     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 432     piix3->pic_levels &= ~mask;
 433     piix3->pic_levels |= mask * !!level;
 434 }
 435
 436 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 437 {
 438     int pic_irq;
 439
 440     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 441     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 442         return;
 443     }
 444
 445     piix3_set_irq_level_internal(piix3, pirq, level);
 446
 447     piix3_set_irq_pic(piix3, pic_irq);
 448 }
 449
 450 static void piix3_set_irq(void *opaque, int pirq, int level)
 451 {
 452     PIIX3State *piix3 = opaque;
 453     piix3_set_irq_level(piix3, pirq, level);
 454 }
 455
 456 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 457 {
 458     PIIX3State *piix3 = opaque;
 459     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 460     PCIINTxRoute route;
 461
 462     if (irq < PIIX_NUM_PIC_IRQS) {
 463         route.mode = PCI_INTX_ENABLED;
 464         route.irq = irq;
 465     } else {
 466         route.mode = PCI_INTX_DISABLED;
 467         route.irq = -1;
 468     }
 469     return route;
 470 }
 471
 472 /* irq routing is changed. so rebuild bitmap */
 473 static void piix3_update_irq_levels(PIIX3State *piix3)
 474 {
 475     int pirq;
 476
 477     piix3->pic_levels = 0;
 478     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 479         piix3_set_irq_level(piix3, pirq,
 480                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 481     }
 482 }
 483
 484 static void piix3_write_config(PCIDevice *dev,
 485                                uint32_t address, uint32_t val, int len)
 486 {
 487     pci_default_write_config(dev, address, val, len);
 488     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 489         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 490         int pic_irq;
 491
 492         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 493         piix3_update_irq_levels(piix3);
 494         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 495             piix3_set_irq_pic(piix3, pic_irq);
 496         }
 497     }
 498 }
 499
 500 static void piix3_write_config_xen(PCIDevice *dev,
 501                                uint32_t address, uint32_t val, int len)
 502 {
 503     xen_piix_pci_write_config_client(address, val, len);
 504     piix3_write_config(dev, address, val, len);
 505 }
 506
 507 static void piix3_reset(void *opaque)
 508 {
 509     PIIX3State *d = opaque;
 510     uint8_t *pci_conf = d->dev.config;
 511
 512     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 513     pci_conf[0x05] = 0x00;
 514     pci_conf[0x06] = 0x00;
 515     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 516     pci_conf[0x4c] = 0x4d;
 517     pci_conf[0x4e] = 0x03;
 518     pci_conf[0x4f] = 0x00;
 519     pci_conf[0x60] = 0x80;
 520     pci_conf[0x61] = 0x80;
 521     pci_conf[0x62] = 0x80;
 522     pci_conf[0x63] = 0x80;
 523     pci_conf[0x69] = 0x02;
 524     pci_conf[0x70] = 0x80;
 525     pci_conf[0x76] = 0x0c;
 526     pci_conf[0x77] = 0x0c;
 527     pci_conf[0x78] = 0x02;
 528     pci_conf[0x79] = 0x00;
 529     pci_conf[0x80] = 0x00;
 530     pci_conf[0x82] = 0x00;
 531     pci_conf[0xa0] = 0x08;
 532     pci_conf[0xa2] = 0x00;
 533     pci_conf[0xa3] = 0x00;
 534     pci_conf[0xa4] = 0x00;
 535     pci_conf[0xa5] = 0x00;
 536     pci_conf[0xa6] = 0x00;
 537     pci_conf[0xa7] = 0x00;
 538     pci_conf[0xa8] = 0x0f;
 539     pci_conf[0xaa] = 0x00;
 540     pci_conf[0xab] = 0x00;
 541     pci_conf[0xac] = 0x00;
 542     pci_conf[0xae] = 0x00;
 543
 544     d->pic_levels = 0;
 545     d->rcr = 0;
 546 }
 547
 548 static int piix3_post_load(void *opaque, int version_id)
 549 {
 550     PIIX3State *piix3 = opaque;
 551     int pirq;
 552
 553     /* Because the i8259 has not been deserialized yet, qemu_irq_raise
 554      * might bring the system to a different state than the saved one;
 555      * for example, the interrupt could be masked but the i8259 would
 556      * not know that yet and would trigger an interrupt in the CPU.
 557      *
 558      * Here, we update irq levels without raising the interrupt.
 559      * Interrupt state will be deserialized separately through the i8259.
 560      */
 561     piix3->pic_levels = 0;
 562     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 563         piix3_set_irq_level_internal(piix3, pirq,
 564                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 565     }
 566     return 0;
 567 }
 568
 569 static void piix3_pre_save(void *opaque)
 570 {
 571     int i;
 572     PIIX3State *piix3 = opaque;
 573
 574     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 575         piix3->pci_irq_levels_vmstate[i] =
 576             pci_bus_get_irq_level(piix3->dev.bus, i);
 577     }
 578 }
 579
 580 static bool piix3_rcr_needed(void *opaque)
 581 {
 582     PIIX3State *piix3 = opaque;
 583
 584     return (piix3->rcr != 0);
 585 }
 586
 587 static const VMStateDescription vmstate_piix3_rcr = {
 588     .name = "PIIX3/rcr",
 589     .version_id = 1,
 590     .minimum_version_id = 1,
 591     .needed = piix3_rcr_needed,
 592     .fields = (VMStateField[]) {
 593         VMSTATE_UINT8(rcr, PIIX3State),
 594         VMSTATE_END_OF_LIST()
 595     }
 596 };
 597
 598 static const VMStateDescription vmstate_piix3 = {
 599     .name = "PIIX3",
 600     .version_id = 3,
 601     .minimum_version_id = 2,
 602     .post_load = piix3_post_load,
 603     .pre_save = piix3_pre_save,
 604     .fields = (VMStateField[]) {
 605         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 606         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 607                               PIIX_NUM_PIRQS, 3),
 608         VMSTATE_END_OF_LIST()
 609     },
 610     .subsections = (const VMStateDescription*[]) {
 611         &vmstate_piix3_rcr,
 612         NULL
 613     }
 614 };
 615
 616
 617 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 618 {
 619     PIIX3State *d = opaque;
 620
 621     if (val & 4) {
 622         qemu_system_reset_request();
 623         return;
 624     }
 625     d->rcr = val & 2; /* keep System Reset type only */
 626 }
 627
 628 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 629 {
 630     PIIX3State *d = opaque;
 631
 632     return d->rcr;
 633 }
 634
 635 static const MemoryRegionOps rcr_ops = {
 636     .read = rcr_read,
 637     .write = rcr_write,
 638     .endianness = DEVICE_LITTLE_ENDIAN
 639 };
 640
 641 static void piix3_realize(PCIDevice *dev, Error **errp)
 642 {
 643     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 644
 645     isa_bus_new(DEVICE(d), get_system_memory(),
 646                 pci_address_space_io(dev));
 647
 648     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 649                           "piix3-reset-control", 1);
 650     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 651                                         &d->rcr_mem, 1);
 652
 653     qemu_register_reset(piix3_reset, d);
 654 }
 655
 656 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 657 {
 658     DeviceClass *dc = DEVICE_CLASS(klass);
 659     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 660
 661     dc->desc        = "ISA bridge";
 662     dc->vmsd        = &vmstate_piix3;
 663     dc->hotpluggable   = false;
 664     k->realize      = piix3_realize;
 665     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 666     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 667     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 668     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 669     /*
 670      * Reason: part of PIIX3 southbridge, needs to be wired up by
 671      * pc_piix.c's pc_init1()
 672      */
 673     dc->cannot_instantiate_with_device_add_yet = true;
 674 }
 675
 676 static const TypeInfo piix3_pci_type_info = {
 677     .name = TYPE_PIIX3_PCI_DEVICE,
 678     .parent = TYPE_PCI_DEVICE,
 679     .instance_size = sizeof(PIIX3State),
 680     .abstract = true,
 681     .class_init = pci_piix3_class_init,
 682 };
 683
 684 static void piix3_class_init(ObjectClass *klass, void *data)
 685 {
 686     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 687
 688     k->config_write = piix3_write_config;
 689 }
 690
 691 static const TypeInfo piix3_info = {
 692     .name          = "PIIX3",
 693     .parent        = TYPE_PIIX3_PCI_DEVICE,
 694     .class_init    = piix3_class_init,
 695 };
 696
 697 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 698 {
 699     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 700
 701     k->config_write = piix3_write_config_xen;
 702 };
 703
 704 static const TypeInfo piix3_xen_info = {
 705     .name          = "PIIX3-xen",
 706     .parent        = TYPE_PIIX3_PCI_DEVICE,
 707     .class_init    = piix3_xen_class_init,
 708 };
 709
 710 static void i440fx_class_init(ObjectClass *klass, void *data)
 711 {
 712     DeviceClass *dc = DEVICE_CLASS(klass);
 713     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 714
 715     k->realize = i440fx_realize;
 716     k->config_write = i440fx_write_config;
 717     k->vendor_id = PCI_VENDOR_ID_INTEL;
 718     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 719     k->revision = 0x02;
 720     k->class_id = PCI_CLASS_BRIDGE_HOST;
 721     dc->desc = "Host bridge";
 722     dc->vmsd = &vmstate_i440fx;
 723     /*
 724      * PCI-facing part of the host bridge, not usable without the
 725      * host-facing part, which can't be device_add'ed, yet.
 726      */
 727     dc->cannot_instantiate_with_device_add_yet = true;
 728     dc->hotpluggable   = false;
 729 }
 730
 731 static const TypeInfo i440fx_info = {
 732     .name          = TYPE_I440FX_PCI_DEVICE,
 733     .parent        = TYPE_PCI_DEVICE,
 734     .instance_size = sizeof(PCII440FXState),
 735     .class_init    = i440fx_class_init,
 736 };
 737
 738 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 739                                                 PCIBus *rootbus)
 740 {
 741     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 742
 743     /* For backwards compat with old device paths */
 744     if (s->short_root_bus) {
 745         return "0000";
 746     }
 747     return "0000:00";
 748 }
 749
 750 static Property i440fx_props[] = {
 751     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 752                      pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 753     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 754     DEFINE_PROP_END_OF_LIST(),
 755 };
 756
 757 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 758 {
 759     DeviceClass *dc = DEVICE_CLASS(klass);
 760     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 761
 762     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 763     dc->realize = i440fx_pcihost_realize;
 764     dc->fw_name = "pci";
 765     dc->props = i440fx_props;
 766 }
 767
 768 static const TypeInfo i440fx_pcihost_info = {
 769     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 770     .parent        = TYPE_PCI_HOST_BRIDGE,
 771     .instance_size = sizeof(I440FXState),
 772     .instance_init = i440fx_pcihost_initfn,
 773     .class_init    = i440fx_pcihost_class_init,
 774 };
 775
 776 static void i440fx_register_types(void)
 777 {
 778     type_register_static(&i440fx_info);
 779     type_register_static(&piix3_pci_type_info);
 780     type_register_static(&piix3_info);
 781     type_register_static(&piix3_xen_info);
 782     type_register_static(&i440fx_pcihost_info);
 783 }
 784
 785 type_init(i440fx_register_types)