2 * QEMU rocker switch emulation - PCI device
4 * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
5 * Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include "hw/pci/pci.h"
20 #include "hw/pci/msix.h"
24 #include "qemu/bitops.h"
25 #include "qmp-commands.h"
28 #include "rocker_hw.h"
29 #include "rocker_fp.h"
30 #include "rocker_desc.h"
31 #include "rocker_tlv.h"
32 #include "rocker_world.h"
33 #include "rocker_of_dpa.h"
41 MemoryRegion msix_bar;
43 /* switch configuration */
44 char *name; /* switch name */
45 uint32_t fp_ports; /* front-panel port count */
46 NICPeers *fp_ports_peers;
47 MACAddr fp_start_macaddr; /* front-panel port 0 mac addr */
48 uint64_t switch_id; /* switch id */
50 /* front-panel ports */
51 FpPort *fp_port[ROCKER_FP_PORTS_MAX];
53 /* register backings */
56 dma_addr_t test_dma_addr;
57 uint32_t test_dma_size;
58 uint64_t lower32; /* lower 32-bit val in 2-part 64-bit access */
64 World *worlds[ROCKER_WORLD_TYPE_MAX];
67 QLIST_ENTRY(rocker) next;
70 #define ROCKER "rocker"
72 #define to_rocker(obj) \
73 OBJECT_CHECK(Rocker, (obj), ROCKER)
75 static QLIST_HEAD(, rocker) rockers;
77 Rocker *rocker_find(const char *name)
81 QLIST_FOREACH(r, &rockers, next)
82 if (strcmp(r->name, name) == 0) {
89 World *rocker_get_world(Rocker *r, enum rocker_world_type type)
91 if (type < ROCKER_WORLD_TYPE_MAX) {
92 return r->worlds[type];
97 RockerSwitch *qmp_query_rocker(const char *name, Error **errp)
102 r = rocker_find(name);
104 error_set(errp, ERROR_CLASS_GENERIC_ERROR,
105 "rocker %s not found", name);
109 rocker = g_new0(RockerSwitch, 1);
110 rocker->name = g_strdup(r->name);
111 rocker->id = r->switch_id;
112 rocker->ports = r->fp_ports;
117 RockerPortList *qmp_query_rocker_ports(const char *name, Error **errp)
119 RockerPortList *list = NULL;
123 r = rocker_find(name);
125 error_set(errp, ERROR_CLASS_GENERIC_ERROR,
126 "rocker %s not found", name);
130 for (i = r->fp_ports - 1; i >= 0; i--) {
131 RockerPortList *info = g_malloc0(sizeof(*info));
132 info->value = g_malloc0(sizeof(*info->value));
133 struct fp_port *port = r->fp_port[i];
135 fp_port_get_info(port, info);
143 uint32_t rocker_fp_ports(Rocker *r)
148 static uint32_t rocker_get_pport_by_tx_ring(Rocker *r,
151 return (desc_ring_index(ring) - 2) / 2 + 1;
154 static int tx_consume(Rocker *r, DescInfo *info)
156 PCIDevice *dev = PCI_DEVICE(r);
157 char *buf = desc_get_buf(info, true);
159 RockerTlv *tlvs[ROCKER_TLV_TX_MAX + 1];
160 struct iovec iov[ROCKER_TX_FRAGS_MAX] = { { 0, }, };
163 uint16_t tx_offload = ROCKER_TX_OFFLOAD_NONE;
164 uint16_t tx_l3_csum_off = 0;
165 uint16_t tx_tso_mss = 0;
166 uint16_t tx_tso_hdr_len = 0;
173 return -ROCKER_ENXIO;
176 rocker_tlv_parse(tlvs, ROCKER_TLV_TX_MAX, buf, desc_tlv_size(info));
178 if (!tlvs[ROCKER_TLV_TX_FRAGS]) {
179 return -ROCKER_EINVAL;
182 pport = rocker_get_pport_by_tx_ring(r, desc_get_ring(info));
183 if (!fp_port_from_pport(pport, &port)) {
184 return -ROCKER_EINVAL;
187 if (tlvs[ROCKER_TLV_TX_OFFLOAD]) {
188 tx_offload = rocker_tlv_get_u8(tlvs[ROCKER_TLV_TX_OFFLOAD]);
191 switch (tx_offload) {
192 case ROCKER_TX_OFFLOAD_L3_CSUM:
193 if (!tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {
194 return -ROCKER_EINVAL;
197 case ROCKER_TX_OFFLOAD_TSO:
198 if (!tlvs[ROCKER_TLV_TX_TSO_MSS] ||
199 !tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {
200 return -ROCKER_EINVAL;
205 if (tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {
206 tx_l3_csum_off = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]);
209 if (tlvs[ROCKER_TLV_TX_TSO_MSS]) {
210 tx_tso_mss = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_MSS]);
213 if (tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {
214 tx_tso_hdr_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]);
217 rocker_tlv_for_each_nested(tlv_frag, tlvs[ROCKER_TLV_TX_FRAGS], rem) {
221 if (rocker_tlv_type(tlv_frag) != ROCKER_TLV_TX_FRAG) {
222 err = -ROCKER_EINVAL;
226 rocker_tlv_parse_nested(tlvs, ROCKER_TLV_TX_FRAG_ATTR_MAX, tlv_frag);
228 if (!tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR] ||
229 !tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]) {
230 err = -ROCKER_EINVAL;
234 frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR]);
235 frag_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]);
237 iov[iovcnt].iov_len = frag_len;
238 iov[iovcnt].iov_base = g_malloc(frag_len);
239 if (!iov[iovcnt].iov_base) {
240 err = -ROCKER_ENOMEM;
244 if (pci_dma_read(dev, frag_addr, iov[iovcnt].iov_base,
245 iov[iovcnt].iov_len)) {
250 if (++iovcnt > ROCKER_TX_FRAGS_MAX) {
251 goto err_too_many_frags;
256 /* XXX perform Tx offloads */
257 /* XXX silence compiler for now */
258 tx_l3_csum_off += tx_tso_mss = tx_tso_hdr_len = 0;
261 err = fp_port_eg(r->fp_port[port], iov, iovcnt);
267 for (i = 0; i < ROCKER_TX_FRAGS_MAX; i++) {
268 if (iov[i].iov_base) {
269 g_free(iov[i].iov_base);
276 static int cmd_get_port_settings(Rocker *r,
277 DescInfo *info, char *buf,
278 RockerTlv *cmd_info_tlv)
280 RockerTlv *tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MAX + 1];
291 enum rocker_world_type mode;
296 rocker_tlv_parse_nested(tlvs, ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
299 if (!tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_PPORT]) {
300 return -ROCKER_EINVAL;
303 pport = rocker_tlv_get_le32(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_PPORT]);
304 if (!fp_port_from_pport(pport, &port)) {
305 return -ROCKER_EINVAL;
307 fp_port = r->fp_port[port];
309 err = fp_port_get_settings(fp_port, &speed, &duplex, &autoneg);
314 fp_port_get_macaddr(fp_port, &macaddr);
315 mode = world_type(fp_port_get_world(fp_port));
316 learning = fp_port_get_learning(fp_port);
317 phys_name = fp_port_get_name(fp_port);
319 tlv_size = rocker_tlv_total_size(0) + /* nest */
320 rocker_tlv_total_size(sizeof(uint32_t)) + /* pport */
321 rocker_tlv_total_size(sizeof(uint32_t)) + /* speed */
322 rocker_tlv_total_size(sizeof(uint8_t)) + /* duplex */
323 rocker_tlv_total_size(sizeof(uint8_t)) + /* autoneg */
324 rocker_tlv_total_size(sizeof(macaddr.a)) + /* macaddr */
325 rocker_tlv_total_size(sizeof(uint8_t)) + /* mode */
326 rocker_tlv_total_size(sizeof(uint8_t)) + /* learning */
327 rocker_tlv_total_size(strlen(phys_name));
329 if (tlv_size > desc_buf_size(info)) {
330 return -ROCKER_EMSGSIZE;
334 nest = rocker_tlv_nest_start(buf, &pos, ROCKER_TLV_CMD_INFO);
335 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, pport);
336 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, speed);
337 rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, duplex);
338 rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, autoneg);
339 rocker_tlv_put(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR,
340 sizeof(macaddr.a), macaddr.a);
341 rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_MODE, mode);
342 rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING,
344 rocker_tlv_put(buf, &pos, ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME,
345 strlen(phys_name), phys_name);
346 rocker_tlv_nest_end(buf, &pos, nest);
348 return desc_set_buf(info, tlv_size);
351 static int cmd_set_port_settings(Rocker *r,
352 RockerTlv *cmd_info_tlv)
354 RockerTlv *tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MAX + 1];
363 enum rocker_world_type mode;
366 rocker_tlv_parse_nested(tlvs, ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
369 if (!tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_PPORT]) {
370 return -ROCKER_EINVAL;
373 pport = rocker_tlv_get_le32(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_PPORT]);
374 if (!fp_port_from_pport(pport, &port)) {
375 return -ROCKER_EINVAL;
377 fp_port = r->fp_port[port];
379 if (tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_SPEED] &&
380 tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX] &&
381 tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG]) {
383 speed = rocker_tlv_get_le32(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_SPEED]);
384 duplex = rocker_tlv_get_u8(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX]);
385 autoneg = rocker_tlv_get_u8(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG]);
387 err = fp_port_set_settings(fp_port, speed, duplex, autoneg);
393 if (tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR]) {
394 if (rocker_tlv_len(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR]) !=
396 return -ROCKER_EINVAL;
399 rocker_tlv_data(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR]),
401 fp_port_set_macaddr(fp_port, &macaddr);
404 if (tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MODE]) {
405 mode = rocker_tlv_get_u8(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_MODE]);
406 fp_port_set_world(fp_port, r->worlds[mode]);
409 if (tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING]) {
411 rocker_tlv_get_u8(tlvs[ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING]);
412 fp_port_set_learning(fp_port, learning);
418 static int cmd_consume(Rocker *r, DescInfo *info)
420 char *buf = desc_get_buf(info, false);
421 RockerTlv *tlvs[ROCKER_TLV_CMD_MAX + 1];
428 return -ROCKER_ENXIO;
431 rocker_tlv_parse(tlvs, ROCKER_TLV_CMD_MAX, buf, desc_tlv_size(info));
433 if (!tlvs[ROCKER_TLV_CMD_TYPE] || !tlvs[ROCKER_TLV_CMD_INFO]) {
434 return -ROCKER_EINVAL;
437 cmd = rocker_tlv_get_le16(tlvs[ROCKER_TLV_CMD_TYPE]);
438 info_tlv = tlvs[ROCKER_TLV_CMD_INFO];
440 /* This might be reworked to something like this:
441 * Every world will have an array of command handlers from
442 * ROCKER_TLV_CMD_TYPE_UNSPEC to ROCKER_TLV_CMD_TYPE_MAX. There is
443 * up to each world to implement whatever command it want.
444 * It can reference "generic" commands as cmd_set_port_settings or
445 * cmd_get_port_settings
449 case ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD:
450 case ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD:
451 case ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL:
452 case ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS:
453 case ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD:
454 case ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD:
455 case ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL:
456 case ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS:
457 world = r->worlds[ROCKER_WORLD_TYPE_OF_DPA];
458 err = world_do_cmd(world, info, buf, cmd, info_tlv);
460 case ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS:
461 err = cmd_get_port_settings(r, info, buf, info_tlv);
463 case ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS:
464 err = cmd_set_port_settings(r, info_tlv);
467 err = -ROCKER_EINVAL;
474 static void rocker_msix_irq(Rocker *r, unsigned vector)
476 PCIDevice *dev = PCI_DEVICE(r);
478 DPRINTF("MSI-X notify request for vector %d\n", vector);
479 if (vector >= ROCKER_MSIX_VEC_COUNT(r->fp_ports)) {
480 DPRINTF("incorrect vector %d\n", vector);
483 msix_notify(dev, vector);
486 int rocker_event_link_changed(Rocker *r, uint32_t pport, bool link_up)
488 DescRing *ring = r->rings[ROCKER_RING_EVENT];
489 DescInfo *info = desc_ring_fetch_desc(ring);
497 return -ROCKER_ENOBUFS;
500 tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) + /* event type */
501 rocker_tlv_total_size(0) + /* nest */
502 rocker_tlv_total_size(sizeof(uint32_t)) + /* pport */
503 rocker_tlv_total_size(sizeof(uint8_t)); /* link up */
505 if (tlv_size > desc_buf_size(info)) {
506 err = -ROCKER_EMSGSIZE;
510 buf = desc_get_buf(info, false);
512 err = -ROCKER_ENOMEM;
517 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_TYPE,
518 ROCKER_TLV_EVENT_TYPE_LINK_CHANGED);
519 nest = rocker_tlv_nest_start(buf, &pos, ROCKER_TLV_EVENT_INFO);
520 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, pport);
521 rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP,
523 rocker_tlv_nest_end(buf, &pos, nest);
525 err = desc_set_buf(info, tlv_size);
529 if (desc_ring_post_desc(ring, err)) {
530 rocker_msix_irq(r, ROCKER_MSIX_VEC_EVENT);
536 int rocker_event_mac_vlan_seen(Rocker *r, uint32_t pport, uint8_t *addr,
539 DescRing *ring = r->rings[ROCKER_RING_EVENT];
549 if (!fp_port_from_pport(pport, &port)) {
550 return -ROCKER_EINVAL;
552 fp_port = r->fp_port[port];
553 if (!fp_port_get_learning(fp_port)) {
557 info = desc_ring_fetch_desc(ring);
559 return -ROCKER_ENOBUFS;
562 tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) + /* event type */
563 rocker_tlv_total_size(0) + /* nest */
564 rocker_tlv_total_size(sizeof(uint32_t)) + /* pport */
565 rocker_tlv_total_size(ETH_ALEN) + /* mac addr */
566 rocker_tlv_total_size(sizeof(uint16_t)); /* vlan_id */
568 if (tlv_size > desc_buf_size(info)) {
569 err = -ROCKER_EMSGSIZE;
573 buf = desc_get_buf(info, false);
575 err = -ROCKER_ENOMEM;
580 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_TYPE,
581 ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN);
582 nest = rocker_tlv_nest_start(buf, &pos, ROCKER_TLV_EVENT_INFO);
583 rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_MAC_VLAN_PPORT, pport);
584 rocker_tlv_put(buf, &pos, ROCKER_TLV_EVENT_MAC_VLAN_MAC, ETH_ALEN, addr);
585 rocker_tlv_put_u16(buf, &pos, ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, vlan_id);
586 rocker_tlv_nest_end(buf, &pos, nest);
588 err = desc_set_buf(info, tlv_size);
592 if (desc_ring_post_desc(ring, err)) {
593 rocker_msix_irq(r, ROCKER_MSIX_VEC_EVENT);
599 static DescRing *rocker_get_rx_ring_by_pport(Rocker *r,
602 return r->rings[(pport - 1) * 2 + 3];
605 int rx_produce(World *world, uint32_t pport,
606 const struct iovec *iov, int iovcnt, uint8_t copy_to_cpu)
608 Rocker *r = world_rocker(world);
609 PCIDevice *dev = (PCIDevice *)r;
610 DescRing *ring = rocker_get_rx_ring_by_pport(r, pport);
611 DescInfo *info = desc_ring_fetch_desc(ring);
613 size_t data_size = iov_size(iov, iovcnt);
615 uint16_t rx_flags = 0;
616 uint16_t rx_csum = 0;
618 RockerTlv *tlvs[ROCKER_TLV_RX_MAX + 1];
620 uint16_t frag_max_len;
625 return -ROCKER_ENOBUFS;
628 buf = desc_get_buf(info, false);
633 rocker_tlv_parse(tlvs, ROCKER_TLV_RX_MAX, buf, desc_tlv_size(info));
635 if (!tlvs[ROCKER_TLV_RX_FRAG_ADDR] ||
636 !tlvs[ROCKER_TLV_RX_FRAG_MAX_LEN]) {
637 err = -ROCKER_EINVAL;
641 frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_RX_FRAG_ADDR]);
642 frag_max_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_RX_FRAG_MAX_LEN]);
644 if (data_size > frag_max_len) {
645 err = -ROCKER_EMSGSIZE;
650 rx_flags |= ROCKER_RX_FLAGS_FWD_OFFLOAD;
653 /* XXX calc rx flags/csum */
655 tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) + /* flags */
656 rocker_tlv_total_size(sizeof(uint16_t)) + /* scum */
657 rocker_tlv_total_size(sizeof(uint64_t)) + /* frag addr */
658 rocker_tlv_total_size(sizeof(uint16_t)) + /* frag max len */
659 rocker_tlv_total_size(sizeof(uint16_t)); /* frag len */
661 if (tlv_size > desc_buf_size(info)) {
662 err = -ROCKER_EMSGSIZE;
667 * iov dma write can be optimized in similar way e1000 does it in
668 * e1000_receive_iov. But maybe if would make sense to introduce
669 * generic helper iov_dma_write.
672 data = g_malloc(data_size);
674 err = -ROCKER_ENOMEM;
677 iov_to_buf(iov, iovcnt, 0, data, data_size);
678 pci_dma_write(dev, frag_addr, data, data_size);
682 rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FLAGS, rx_flags);
683 rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_CSUM, rx_csum);
684 rocker_tlv_put_le64(buf, &pos, ROCKER_TLV_RX_FRAG_ADDR, frag_addr);
685 rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FRAG_MAX_LEN, frag_max_len);
686 rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FRAG_LEN, data_size);
688 err = desc_set_buf(info, tlv_size);
691 if (desc_ring_post_desc(ring, err)) {
692 rocker_msix_irq(r, ROCKER_MSIX_VEC_RX(pport - 1));
698 int rocker_port_eg(Rocker *r, uint32_t pport,
699 const struct iovec *iov, int iovcnt)
704 if (!fp_port_from_pport(pport, &port)) {
705 return -ROCKER_EINVAL;
708 fp_port = r->fp_port[port];
710 return fp_port_eg(fp_port, iov, iovcnt);
713 static void rocker_test_dma_ctrl(Rocker *r, uint32_t val)
715 PCIDevice *dev = PCI_DEVICE(r);
719 buf = g_malloc(r->test_dma_size);
722 DPRINTF("test dma buffer alloc failed");
727 case ROCKER_TEST_DMA_CTRL_CLEAR:
728 memset(buf, 0, r->test_dma_size);
730 case ROCKER_TEST_DMA_CTRL_FILL:
731 memset(buf, 0x96, r->test_dma_size);
733 case ROCKER_TEST_DMA_CTRL_INVERT:
734 pci_dma_read(dev, r->test_dma_addr, buf, r->test_dma_size);
735 for (i = 0; i < r->test_dma_size; i++) {
740 DPRINTF("not test dma control val=0x%08x\n", val);
743 pci_dma_write(dev, r->test_dma_addr, buf, r->test_dma_size);
745 rocker_msix_irq(r, ROCKER_MSIX_VEC_TEST);
751 static void rocker_reset(DeviceState *dev);
753 static void rocker_control(Rocker *r, uint32_t val)
755 if (val & ROCKER_CONTROL_RESET) {
756 rocker_reset(DEVICE(r));
760 static int rocker_pci_ring_count(Rocker *r)
765 * - tx and rx ring per each port
767 return 2 + (2 * r->fp_ports);
770 static bool rocker_addr_is_desc_reg(Rocker *r, hwaddr addr)
772 hwaddr start = ROCKER_DMA_DESC_BASE;
773 hwaddr end = start + (ROCKER_DMA_DESC_SIZE * rocker_pci_ring_count(r));
775 return addr >= start && addr < end;
778 static void rocker_port_phys_enable_write(Rocker *r, uint64_t new)
785 for (i = 0; i < r->fp_ports; i++) {
786 fp_port = r->fp_port[i];
787 old_enabled = fp_port_enabled(fp_port);
788 new_enabled = (new >> (i + 1)) & 0x1;
789 if (new_enabled == old_enabled) {
793 fp_port_enable(r->fp_port[i]);
795 fp_port_disable(r->fp_port[i]);
800 static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val)
804 if (rocker_addr_is_desc_reg(r, addr)) {
805 unsigned index = ROCKER_RING_INDEX(addr);
806 unsigned offset = addr & ROCKER_DMA_DESC_MASK;
809 case ROCKER_DMA_DESC_ADDR_OFFSET:
810 r->lower32 = (uint64_t)val;
812 case ROCKER_DMA_DESC_ADDR_OFFSET + 4:
813 desc_ring_set_base_addr(r->rings[index],
814 ((uint64_t)val) << 32 | r->lower32);
817 case ROCKER_DMA_DESC_SIZE_OFFSET:
818 desc_ring_set_size(r->rings[index], val);
820 case ROCKER_DMA_DESC_HEAD_OFFSET:
821 if (desc_ring_set_head(r->rings[index], val)) {
822 rocker_msix_irq(r, desc_ring_get_msix_vector(r->rings[index]));
825 case ROCKER_DMA_DESC_CTRL_OFFSET:
826 desc_ring_set_ctrl(r->rings[index], val);
828 case ROCKER_DMA_DESC_CREDITS_OFFSET:
829 if (desc_ring_ret_credits(r->rings[index], val)) {
830 rocker_msix_irq(r, desc_ring_get_msix_vector(r->rings[index]));
834 DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx
835 " val=0x%08x (ring %d, addr=0x%02x)\n",
836 addr, val, index, offset);
843 case ROCKER_TEST_REG:
846 case ROCKER_TEST_REG64:
847 case ROCKER_TEST_DMA_ADDR:
848 case ROCKER_PORT_PHYS_ENABLE:
849 r->lower32 = (uint64_t)val;
851 case ROCKER_TEST_REG64 + 4:
852 r->test_reg64 = ((uint64_t)val) << 32 | r->lower32;
855 case ROCKER_TEST_IRQ:
856 rocker_msix_irq(r, val);
858 case ROCKER_TEST_DMA_SIZE:
859 r->test_dma_size = val;
861 case ROCKER_TEST_DMA_ADDR + 4:
862 r->test_dma_addr = ((uint64_t)val) << 32 | r->lower32;
865 case ROCKER_TEST_DMA_CTRL:
866 rocker_test_dma_ctrl(r, val);
869 rocker_control(r, val);
871 case ROCKER_PORT_PHYS_ENABLE + 4:
872 rocker_port_phys_enable_write(r, ((uint64_t)val) << 32 | r->lower32);
876 DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx
877 " val=0x%08x\n", addr, val);
882 static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val)
886 if (rocker_addr_is_desc_reg(r, addr)) {
887 unsigned index = ROCKER_RING_INDEX(addr);
888 unsigned offset = addr & ROCKER_DMA_DESC_MASK;
891 case ROCKER_DMA_DESC_ADDR_OFFSET:
892 desc_ring_set_base_addr(r->rings[index], val);
895 DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx
896 " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n",
897 addr, val, index, offset);
904 case ROCKER_TEST_REG64:
907 case ROCKER_TEST_DMA_ADDR:
908 r->test_dma_addr = val;
910 case ROCKER_PORT_PHYS_ENABLE:
911 rocker_port_phys_enable_write(r, val);
914 DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx
915 " val=0x" TARGET_FMT_plx "\n", addr, val);
921 #define regname(reg) case (reg): return #reg
922 static const char *rocker_reg_name(void *opaque, hwaddr addr)
926 if (rocker_addr_is_desc_reg(r, addr)) {
927 unsigned index = ROCKER_RING_INDEX(addr);
928 unsigned offset = addr & ROCKER_DMA_DESC_MASK;
929 static char buf[100];
934 sprintf(ring_name, "cmd");
937 sprintf(ring_name, "event");
940 sprintf(ring_name, "%s-%d", index % 2 ? "rx" : "tx",
945 case ROCKER_DMA_DESC_ADDR_OFFSET:
946 sprintf(buf, "Ring[%s] ADDR", ring_name);
948 case ROCKER_DMA_DESC_ADDR_OFFSET+4:
949 sprintf(buf, "Ring[%s] ADDR+4", ring_name);
951 case ROCKER_DMA_DESC_SIZE_OFFSET:
952 sprintf(buf, "Ring[%s] SIZE", ring_name);
954 case ROCKER_DMA_DESC_HEAD_OFFSET:
955 sprintf(buf, "Ring[%s] HEAD", ring_name);
957 case ROCKER_DMA_DESC_TAIL_OFFSET:
958 sprintf(buf, "Ring[%s] TAIL", ring_name);
960 case ROCKER_DMA_DESC_CTRL_OFFSET:
961 sprintf(buf, "Ring[%s] CTRL", ring_name);
963 case ROCKER_DMA_DESC_CREDITS_OFFSET:
964 sprintf(buf, "Ring[%s] CREDITS", ring_name);
967 sprintf(buf, "Ring[%s] ???", ring_name);
972 regname(ROCKER_BOGUS_REG0);
973 regname(ROCKER_BOGUS_REG1);
974 regname(ROCKER_BOGUS_REG2);
975 regname(ROCKER_BOGUS_REG3);
976 regname(ROCKER_TEST_REG);
977 regname(ROCKER_TEST_REG64);
978 regname(ROCKER_TEST_REG64+4);
979 regname(ROCKER_TEST_IRQ);
980 regname(ROCKER_TEST_DMA_ADDR);
981 regname(ROCKER_TEST_DMA_ADDR+4);
982 regname(ROCKER_TEST_DMA_SIZE);
983 regname(ROCKER_TEST_DMA_CTRL);
984 regname(ROCKER_CONTROL);
985 regname(ROCKER_PORT_PHYS_COUNT);
986 regname(ROCKER_PORT_PHYS_LINK_STATUS);
987 regname(ROCKER_PORT_PHYS_LINK_STATUS+4);
988 regname(ROCKER_PORT_PHYS_ENABLE);
989 regname(ROCKER_PORT_PHYS_ENABLE+4);
990 regname(ROCKER_SWITCH_ID);
991 regname(ROCKER_SWITCH_ID+4);
997 static const char *rocker_reg_name(void *opaque, hwaddr addr)
1003 static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1006 DPRINTF("Write %s addr " TARGET_FMT_plx
1007 ", size %u, val " TARGET_FMT_plx "\n",
1008 rocker_reg_name(opaque, addr), addr, size, val);
1012 rocker_io_writel(opaque, addr, val);
1015 rocker_io_writeq(opaque, addr, val);
1020 static uint64_t rocker_port_phys_link_status(Rocker *r)
1023 uint64_t status = 0;
1025 for (i = 0; i < r->fp_ports; i++) {
1026 FpPort *port = r->fp_port[i];
1028 if (fp_port_get_link_up(port)) {
1029 status |= 1 << (i + 1);
1035 static uint64_t rocker_port_phys_enable_read(Rocker *r)
1040 for (i = 0; i < r->fp_ports; i++) {
1041 FpPort *port = r->fp_port[i];
1043 if (fp_port_enabled(port)) {
1044 ret |= 1 << (i + 1);
1050 static uint32_t rocker_io_readl(void *opaque, hwaddr addr)
1055 if (rocker_addr_is_desc_reg(r, addr)) {
1056 unsigned index = ROCKER_RING_INDEX(addr);
1057 unsigned offset = addr & ROCKER_DMA_DESC_MASK;
1060 case ROCKER_DMA_DESC_ADDR_OFFSET:
1061 ret = (uint32_t)desc_ring_get_base_addr(r->rings[index]);
1063 case ROCKER_DMA_DESC_ADDR_OFFSET + 4:
1064 ret = (uint32_t)(desc_ring_get_base_addr(r->rings[index]) >> 32);
1066 case ROCKER_DMA_DESC_SIZE_OFFSET:
1067 ret = desc_ring_get_size(r->rings[index]);
1069 case ROCKER_DMA_DESC_HEAD_OFFSET:
1070 ret = desc_ring_get_head(r->rings[index]);
1072 case ROCKER_DMA_DESC_TAIL_OFFSET:
1073 ret = desc_ring_get_tail(r->rings[index]);
1075 case ROCKER_DMA_DESC_CREDITS_OFFSET:
1076 ret = desc_ring_get_credits(r->rings[index]);
1079 DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx
1080 " (ring %d, addr=0x%02x)\n", addr, index, offset);
1088 case ROCKER_BOGUS_REG0:
1089 case ROCKER_BOGUS_REG1:
1090 case ROCKER_BOGUS_REG2:
1091 case ROCKER_BOGUS_REG3:
1094 case ROCKER_TEST_REG:
1095 ret = r->test_reg * 2;
1097 case ROCKER_TEST_REG64:
1098 ret = (uint32_t)(r->test_reg64 * 2);
1100 case ROCKER_TEST_REG64 + 4:
1101 ret = (uint32_t)((r->test_reg64 * 2) >> 32);
1103 case ROCKER_TEST_DMA_SIZE:
1104 ret = r->test_dma_size;
1106 case ROCKER_TEST_DMA_ADDR:
1107 ret = (uint32_t)r->test_dma_addr;
1109 case ROCKER_TEST_DMA_ADDR + 4:
1110 ret = (uint32_t)(r->test_dma_addr >> 32);
1112 case ROCKER_PORT_PHYS_COUNT:
1115 case ROCKER_PORT_PHYS_LINK_STATUS:
1116 ret = (uint32_t)rocker_port_phys_link_status(r);
1118 case ROCKER_PORT_PHYS_LINK_STATUS + 4:
1119 ret = (uint32_t)(rocker_port_phys_link_status(r) >> 32);
1121 case ROCKER_PORT_PHYS_ENABLE:
1122 ret = (uint32_t)rocker_port_phys_enable_read(r);
1124 case ROCKER_PORT_PHYS_ENABLE + 4:
1125 ret = (uint32_t)(rocker_port_phys_enable_read(r) >> 32);
1127 case ROCKER_SWITCH_ID:
1128 ret = (uint32_t)r->switch_id;
1130 case ROCKER_SWITCH_ID + 4:
1131 ret = (uint32_t)(r->switch_id >> 32);
1134 DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr);
1141 static uint64_t rocker_io_readq(void *opaque, hwaddr addr)
1146 if (rocker_addr_is_desc_reg(r, addr)) {
1147 unsigned index = ROCKER_RING_INDEX(addr);
1148 unsigned offset = addr & ROCKER_DMA_DESC_MASK;
1150 switch (addr & ROCKER_DMA_DESC_MASK) {
1151 case ROCKER_DMA_DESC_ADDR_OFFSET:
1152 ret = desc_ring_get_base_addr(r->rings[index]);
1155 DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx
1156 " (ring %d, addr=0x%02x)\n", addr, index, offset);
1164 case ROCKER_BOGUS_REG0:
1165 case ROCKER_BOGUS_REG2:
1166 ret = 0xDEADBABEDEADBABEULL;
1168 case ROCKER_TEST_REG64:
1169 ret = r->test_reg64 * 2;
1171 case ROCKER_TEST_DMA_ADDR:
1172 ret = r->test_dma_addr;
1174 case ROCKER_PORT_PHYS_LINK_STATUS:
1175 ret = rocker_port_phys_link_status(r);
1177 case ROCKER_PORT_PHYS_ENABLE:
1178 ret = rocker_port_phys_enable_read(r);
1180 case ROCKER_SWITCH_ID:
1184 DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr);
1191 static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size)
1193 DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n",
1194 rocker_reg_name(opaque, addr), addr, size);
1198 return rocker_io_readl(opaque, addr);
1200 return rocker_io_readq(opaque, addr);
1206 static const MemoryRegionOps rocker_mmio_ops = {
1207 .read = rocker_mmio_read,
1208 .write = rocker_mmio_write,
1209 .endianness = DEVICE_LITTLE_ENDIAN,
1211 .min_access_size = 4,
1212 .max_access_size = 8,
1215 .min_access_size = 4,
1216 .max_access_size = 8,
1220 static void rocker_msix_vectors_unuse(Rocker *r,
1221 unsigned int num_vectors)
1223 PCIDevice *dev = PCI_DEVICE(r);
1226 for (i = 0; i < num_vectors; i++) {
1227 msix_vector_unuse(dev, i);
1231 static int rocker_msix_vectors_use(Rocker *r,
1232 unsigned int num_vectors)
1234 PCIDevice *dev = PCI_DEVICE(r);
1238 for (i = 0; i < num_vectors; i++) {
1239 err = msix_vector_use(dev, i);
1247 rocker_msix_vectors_unuse(r, i);
1251 static int rocker_msix_init(Rocker *r)
1253 PCIDevice *dev = PCI_DEVICE(r);
1256 err = msix_init(dev, ROCKER_MSIX_VEC_COUNT(r->fp_ports),
1258 ROCKER_PCI_MSIX_BAR_IDX, ROCKER_PCI_MSIX_TABLE_OFFSET,
1260 ROCKER_PCI_MSIX_BAR_IDX, ROCKER_PCI_MSIX_PBA_OFFSET,
1266 err = rocker_msix_vectors_use(r, ROCKER_MSIX_VEC_COUNT(r->fp_ports));
1268 goto err_msix_vectors_use;
1273 err_msix_vectors_use:
1274 msix_uninit(dev, &r->msix_bar, &r->msix_bar);
1278 static void rocker_msix_uninit(Rocker *r)
1280 PCIDevice *dev = PCI_DEVICE(r);
1282 msix_uninit(dev, &r->msix_bar, &r->msix_bar);
1283 rocker_msix_vectors_unuse(r, ROCKER_MSIX_VEC_COUNT(r->fp_ports));
1286 static int pci_rocker_init(PCIDevice *dev)
1288 Rocker *r = to_rocker(dev);
1289 const MACAddr zero = { .a = { 0, 0, 0, 0, 0, 0 } };
1290 const MACAddr dflt = { .a = { 0x52, 0x54, 0x00, 0x12, 0x35, 0x01 } };
1291 static int sw_index;
1294 /* allocate worlds */
1296 r->worlds[ROCKER_WORLD_TYPE_OF_DPA] = of_dpa_world_alloc(r);
1297 r->world_dflt = r->worlds[ROCKER_WORLD_TYPE_OF_DPA];
1299 for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
1300 if (!r->worlds[i]) {
1301 goto err_world_alloc;
1305 /* set up memory-mapped region at BAR0 */
1307 memory_region_init_io(&r->mmio, OBJECT(r), &rocker_mmio_ops, r,
1308 "rocker-mmio", ROCKER_PCI_BAR0_SIZE);
1309 pci_register_bar(dev, ROCKER_PCI_BAR0_IDX,
1310 PCI_BASE_ADDRESS_SPACE_MEMORY, &r->mmio);
1312 /* set up memory-mapped region for MSI-X */
1314 memory_region_init(&r->msix_bar, OBJECT(r), "rocker-msix-bar",
1315 ROCKER_PCI_MSIX_BAR_SIZE);
1316 pci_register_bar(dev, ROCKER_PCI_MSIX_BAR_IDX,
1317 PCI_BASE_ADDRESS_SPACE_MEMORY, &r->msix_bar);
1321 err = rocker_msix_init(r);
1326 /* validate switch properties */
1329 r->name = g_strdup(ROCKER);
1332 if (rocker_find(r->name)) {
1337 /* Rocker name is passed in port name requests to OS with the intention
1338 * that the name is used in interface names. Limit the length of the
1339 * rocker name to avoid naming problems in the OS. Also, adding the
1340 * port number as p# and unganged breakout b#, where # is at most 2
1341 * digits, so leave room for it too (-1 for string terminator, -3 for
1344 #define ROCKER_IFNAMSIZ 16
1345 #define MAX_ROCKER_NAME_LEN (ROCKER_IFNAMSIZ - 1 - 3 - 3)
1346 if (strlen(r->name) > MAX_ROCKER_NAME_LEN) {
1348 "rocker: name too long; please shorten to at most %d chars\n",
1349 MAX_ROCKER_NAME_LEN);
1353 if (memcmp(&r->fp_start_macaddr, &zero, sizeof(zero)) == 0) {
1354 memcpy(&r->fp_start_macaddr, &dflt, sizeof(dflt));
1355 r->fp_start_macaddr.a[4] += (sw_index++);
1358 if (!r->switch_id) {
1359 memcpy(&r->switch_id, &r->fp_start_macaddr,
1360 sizeof(r->fp_start_macaddr));
1363 if (r->fp_ports > ROCKER_FP_PORTS_MAX) {
1364 r->fp_ports = ROCKER_FP_PORTS_MAX;
1367 r->rings = g_malloc(sizeof(DescRing *) * rocker_pci_ring_count(r));
1369 goto err_rings_alloc;
1372 /* Rings are ordered like this:
1383 for (i = 0; i < rocker_pci_ring_count(r); i++) {
1384 DescRing *ring = desc_ring_alloc(r, i);
1387 goto err_ring_alloc;
1390 if (i == ROCKER_RING_CMD) {
1391 desc_ring_set_consume(ring, cmd_consume, ROCKER_MSIX_VEC_CMD);
1392 } else if (i == ROCKER_RING_EVENT) {
1393 desc_ring_set_consume(ring, NULL, ROCKER_MSIX_VEC_EVENT);
1394 } else if (i % 2 == 0) {
1395 desc_ring_set_consume(ring, tx_consume,
1396 ROCKER_MSIX_VEC_TX((i - 2) / 2));
1397 } else if (i % 2 == 1) {
1398 desc_ring_set_consume(ring, NULL, ROCKER_MSIX_VEC_RX((i - 3) / 2));
1404 for (i = 0; i < r->fp_ports; i++) {
1406 fp_port_alloc(r, r->name, &r->fp_start_macaddr,
1407 i, &r->fp_ports_peers[i]);
1410 goto err_port_alloc;
1413 r->fp_port[i] = port;
1414 fp_port_set_world(port, r->world_dflt);
1417 QLIST_INSERT_HEAD(&rockers, r, next);
1422 for (--i; i >= 0; i--) {
1423 FpPort *port = r->fp_port[i];
1426 i = rocker_pci_ring_count(r);
1428 for (--i; i >= 0; i--) {
1429 desc_ring_free(r->rings[i]);
1434 rocker_msix_uninit(r);
1436 object_unparent(OBJECT(&r->msix_bar));
1437 object_unparent(OBJECT(&r->mmio));
1439 for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
1441 world_free(r->worlds[i]);
1447 static void pci_rocker_uninit(PCIDevice *dev)
1449 Rocker *r = to_rocker(dev);
1452 QLIST_REMOVE(r, next);
1454 for (i = 0; i < r->fp_ports; i++) {
1455 FpPort *port = r->fp_port[i];
1458 r->fp_port[i] = NULL;
1461 for (i = 0; i < rocker_pci_ring_count(r); i++) {
1463 desc_ring_free(r->rings[i]);
1468 rocker_msix_uninit(r);
1469 object_unparent(OBJECT(&r->msix_bar));
1470 object_unparent(OBJECT(&r->mmio));
1472 for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
1474 world_free(r->worlds[i]);
1477 g_free(r->fp_ports_peers);
1480 static void rocker_reset(DeviceState *dev)
1482 Rocker *r = to_rocker(dev);
1485 for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) {
1487 world_reset(r->worlds[i]);
1490 for (i = 0; i < r->fp_ports; i++) {
1491 fp_port_reset(r->fp_port[i]);
1492 fp_port_set_world(r->fp_port[i], r->world_dflt);
1497 r->test_dma_addr = 0;
1498 r->test_dma_size = 0;
1500 for (i = 0; i < rocker_pci_ring_count(r); i++) {
1501 desc_ring_reset(r->rings[i]);
1504 DPRINTF("Reset done\n");
1507 static Property rocker_properties[] = {
1508 DEFINE_PROP_STRING("name", Rocker, name),
1509 DEFINE_PROP_MACADDR("fp_start_macaddr", Rocker,
1511 DEFINE_PROP_UINT64("switch_id", Rocker,
1513 DEFINE_PROP_ARRAY("ports", Rocker, fp_ports,
1514 fp_ports_peers, qdev_prop_netdev, NICPeers),
1515 DEFINE_PROP_END_OF_LIST(),
1518 static const VMStateDescription rocker_vmsd = {
1523 static void rocker_class_init(ObjectClass *klass, void *data)
1525 DeviceClass *dc = DEVICE_CLASS(klass);
1526 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1528 k->init = pci_rocker_init;
1529 k->exit = pci_rocker_uninit;
1530 k->vendor_id = PCI_VENDOR_ID_REDHAT;
1531 k->device_id = PCI_DEVICE_ID_REDHAT_ROCKER;
1532 k->revision = ROCKER_PCI_REVISION;
1533 k->class_id = PCI_CLASS_NETWORK_OTHER;
1534 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1535 dc->desc = "Rocker Switch";
1536 dc->reset = rocker_reset;
1537 dc->props = rocker_properties;
1538 dc->vmsd = &rocker_vmsd;
1541 static const TypeInfo rocker_info = {
1543 .parent = TYPE_PCI_DEVICE,
1544 .instance_size = sizeof(Rocker),
1545 .class_init = rocker_class_init,
1548 static void rocker_register_types(void)
1550 type_register_static(&rocker_info);
1553 type_init(rocker_register_types)