2 * QEMU Freescale eTSEC Emulator
4 * Copyright (c) 2011-2013 AdaCore
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "registers.h"
29 /* #define DEBUG_MIIM */
31 #define MIIM_CONTROL 0
33 #define MIIM_PHY_ID_1 2
34 #define MIIM_PHY_ID_2 3
35 #define MIIM_T2_STATUS 10
36 #define MIIM_EXT_STATUS 15
38 static void miim_read_cycle(eTSEC *etsec)
44 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F;
45 (void)phy; /* Unreferenced */
46 addr = etsec->regs[MIIMADD].value & 0x1F;
50 value = etsec->phy_control;
53 value = etsec->phy_status;
56 value = 0x1800; /* Local and remote receivers OK */
64 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value);
67 etsec->regs[MIIMSTAT].value = value;
70 static void miim_write_cycle(eTSEC *etsec)
76 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F;
77 (void)phy; /* Unreferenced */
78 addr = etsec->regs[MIIMADD].value & 0x1F;
79 value = etsec->regs[MIIMCON].value & 0xffff;
82 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value);
87 etsec->phy_control = value & ~(0x8100);
94 void etsec_write_miim(eTSEC *etsec,
103 /* Read and scan cycle */
105 if ((!(reg->value & MIIMCOM_READ)) && (value & MIIMCOM_READ)) {
107 miim_read_cycle(etsec);
113 reg->value = value & 0xffff;
114 miim_write_cycle(etsec);
118 /* Default handling */
119 switch (reg->access) {
127 reg->value &= ~value;
132 /* Read Only or Unknown register */
139 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc)
141 /* Set link status */
143 etsec->phy_status &= ~MII_SR_LINK_STATUS;
145 etsec->phy_status |= MII_SR_LINK_STATUS;