qemu/hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/hw.h"
  22 #include "hw/block/flash.h"
  23 #include "hw/devices.h"
  24 #include "hw/boards.h"
  25 #include "hw/loader.h"
  26 #include "sysemu/block-backend.h"
  27 #include "elf.h"
  28 #include "lm32_hwsetup.h"
  29 #include "lm32.h"
  30 #include "exec/address-spaces.h"
  31
  32 typedef struct {
  33     LM32CPU *cpu;
  34     hwaddr bootstrap_pc;
  35     hwaddr flash_base;
  36     hwaddr hwsetup_base;
  37     hwaddr initrd_base;
  38     size_t initrd_size;
  39     hwaddr cmdline_base;
  40 } ResetInfo;
  41
  42 static void cpu_irq_handler(void *opaque, int irq, int level)
  43 {
  44     LM32CPU *cpu = opaque;
  45     CPUState *cs = CPU(cpu);
  46
  47     if (level) {
  48         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  49     } else {
  50         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  51     }
  52 }
  53
  54 static void main_cpu_reset(void *opaque)
  55 {
  56     ResetInfo *reset_info = opaque;
  57     CPULM32State *env = &reset_info->cpu->env;
  58
  59     cpu_reset(CPU(reset_info->cpu));
  60
  61     /* init defaults */
  62     env->pc = (uint32_t)reset_info->bootstrap_pc;
  63     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  64     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  65     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  66     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  67         reset_info->initrd_size);
  68     env->eba = reset_info->flash_base;
  69     env->deba = reset_info->flash_base;
  70 }
  71
  72 static void lm32_evr_init(MachineState *machine)
  73 {
  74     const char *cpu_model = machine->cpu_model;
  75     const char *kernel_filename = machine->kernel_filename;
  76     LM32CPU *cpu;
  77     CPULM32State *env;
  78     DriveInfo *dinfo;
  79     MemoryRegion *address_space_mem =  get_system_memory();
  80     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  81     qemu_irq irq[32];
  82     ResetInfo *reset_info;
  83     int i;
  84
  85     /* memory map */
  86     hwaddr flash_base  = 0x04000000;
  87     size_t flash_sector_size       = 256 * 1024;
  88     size_t flash_size              = 32 * 1024 * 1024;
  89     hwaddr ram_base    = 0x08000000;
  90     size_t ram_size                = 64 * 1024 * 1024;
  91     hwaddr timer0_base = 0x80002000;
  92     hwaddr uart0_base  = 0x80006000;
  93     hwaddr timer1_base = 0x8000a000;
  94     int uart0_irq                  = 0;
  95     int timer0_irq                 = 1;
  96     int timer1_irq                 = 3;
  97
  98     reset_info = g_malloc0(sizeof(ResetInfo));
  99
 100     if (cpu_model == NULL) {
 101         cpu_model = "lm32-full";
 102     }
 103     cpu = cpu_lm32_init(cpu_model);
 104     if (cpu == NULL) {
 105         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 106         exit(1);
 107     }
 108
 109     env = &cpu->env;
 110     reset_info->cpu = cpu;
 111
 112     reset_info->flash_base = flash_base;
 113
 114     memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
 115                                          ram_size);
 116     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 117
 118     dinfo = drive_get(IF_PFLASH, 0, 0);
 119     /* Spansion S29NS128P */
 120     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
 121                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 122                           flash_sector_size, flash_size / flash_sector_size,
 123                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 124
 125     /* create irq lines */
 126     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
 127     for (i = 0; i < 32; i++) {
 128         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 129     }
 130
 131     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 132     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 133     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 134
 135     /* make sure juart isn't the first chardev */
 136     env->juart_state = lm32_juart_init();
 137
 138     reset_info->bootstrap_pc = flash_base;
 139
 140     if (kernel_filename) {
 141         uint64_t entry;
 142         int kernel_size;
 143
 144         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 145                                1, ELF_MACHINE, 0);
 146         reset_info->bootstrap_pc = entry;
 147
 148         if (kernel_size < 0) {
 149             kernel_size = load_image_targphys(kernel_filename, ram_base,
 150                                               ram_size);
 151             reset_info->bootstrap_pc = ram_base;
 152         }
 153
 154         if (kernel_size < 0) {
 155             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 156                     kernel_filename);
 157             exit(1);
 158         }
 159     }
 160
 161     qemu_register_reset(main_cpu_reset, reset_info);
 162 }
 163
 164 static void lm32_uclinux_init(MachineState *machine)
 165 {
 166     const char *cpu_model = machine->cpu_model;
 167     const char *kernel_filename = machine->kernel_filename;
 168     const char *kernel_cmdline = machine->kernel_cmdline;
 169     const char *initrd_filename = machine->initrd_filename;
 170     LM32CPU *cpu;
 171     CPULM32State *env;
 172     DriveInfo *dinfo;
 173     MemoryRegion *address_space_mem =  get_system_memory();
 174     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 175     qemu_irq irq[32];
 176     HWSetup *hw;
 177     ResetInfo *reset_info;
 178     int i;
 179
 180     /* memory map */
 181     hwaddr flash_base   = 0x04000000;
 182     size_t flash_sector_size        = 256 * 1024;
 183     size_t flash_size               = 32 * 1024 * 1024;
 184     hwaddr ram_base     = 0x08000000;
 185     size_t ram_size                 = 64 * 1024 * 1024;
 186     hwaddr uart0_base   = 0x80000000;
 187     hwaddr timer0_base  = 0x80002000;
 188     hwaddr timer1_base  = 0x80010000;
 189     hwaddr timer2_base  = 0x80012000;
 190     int uart0_irq                   = 0;
 191     int timer0_irq                  = 1;
 192     int timer1_irq                  = 20;
 193     int timer2_irq                  = 21;
 194     hwaddr hwsetup_base = 0x0bffe000;
 195     hwaddr cmdline_base = 0x0bfff000;
 196     hwaddr initrd_base  = 0x08400000;
 197     size_t initrd_max               = 0x01000000;
 198
 199     reset_info = g_malloc0(sizeof(ResetInfo));
 200
 201     if (cpu_model == NULL) {
 202         cpu_model = "lm32-full";
 203     }
 204     cpu = cpu_lm32_init(cpu_model);
 205     if (cpu == NULL) {
 206         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 207         exit(1);
 208     }
 209
 210     env = &cpu->env;
 211     reset_info->cpu = cpu;
 212
 213     reset_info->flash_base = flash_base;
 214
 215     memory_region_allocate_system_memory(phys_ram, NULL,
 216                                          "lm32_uclinux.sdram", ram_size);
 217     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 218
 219     dinfo = drive_get(IF_PFLASH, 0, 0);
 220     /* Spansion S29NS128P */
 221     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
 222                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 223                           flash_sector_size, flash_size / flash_sector_size,
 224                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 225
 226     /* create irq lines */
 227     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
 228     for (i = 0; i < 32; i++) {
 229         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 230     }
 231
 232     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 233     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 234     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 235     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 236
 237     /* make sure juart isn't the first chardev */
 238     env->juart_state = lm32_juart_init();
 239
 240     reset_info->bootstrap_pc = flash_base;
 241
 242     if (kernel_filename) {
 243         uint64_t entry;
 244         int kernel_size;
 245
 246         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 247                                1, ELF_MACHINE, 0);
 248         reset_info->bootstrap_pc = entry;
 249
 250         if (kernel_size < 0) {
 251             kernel_size = load_image_targphys(kernel_filename, ram_base,
 252                                               ram_size);
 253             reset_info->bootstrap_pc = ram_base;
 254         }
 255
 256         if (kernel_size < 0) {
 257             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 258                     kernel_filename);
 259             exit(1);
 260         }
 261     }
 262
 263     /* generate a rom with the hardware description */
 264     hw = hwsetup_init();
 265     hwsetup_add_cpu(hw, "LM32", 75000000);
 266     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 267     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 268     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 269     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 270     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 271     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 272     hwsetup_add_trailer(hw);
 273     hwsetup_create_rom(hw, hwsetup_base);
 274     hwsetup_free(hw);
 275
 276     reset_info->hwsetup_base = hwsetup_base;
 277
 278     if (kernel_cmdline && strlen(kernel_cmdline)) {
 279         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 280                 kernel_cmdline);
 281         reset_info->cmdline_base = cmdline_base;
 282     }
 283
 284     if (initrd_filename) {
 285         size_t initrd_size;
 286         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 287                 initrd_max);
 288         reset_info->initrd_base = initrd_base;
 289         reset_info->initrd_size = initrd_size;
 290     }
 291
 292     qemu_register_reset(main_cpu_reset, reset_info);
 293 }
 294
 295 static QEMUMachine lm32_evr_machine = {
 296     .name = "lm32-evr",
 297     .desc = "LatticeMico32 EVR32 eval system",
 298     .init = lm32_evr_init,
 299     .is_default = 1,
 300 };
 301
 302 static QEMUMachine lm32_uclinux_machine = {
 303     .name = "lm32-uclinux",
 304     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
 305     .init = lm32_uclinux_init,
 306     .is_default = 0,
 307 };
 308
 309 static void lm32_machine_init(void)
 310 {
 311     qemu_register_machine(&lm32_uclinux_machine);
 312     qemu_register_machine(&lm32_evr_machine);
 313 }
 314
 315 machine_init(lm32_machine_init);