qemu/hw/intc/arm_gic_common.c

   1 /*
   2  * ARM GIC support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "gic_internal.h"
  22
  23 static void gic_pre_save(void *opaque)
  24 {
  25     GICState *s = (GICState *)opaque;
  26     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  27
  28     if (c->pre_save) {
  29         c->pre_save(s);
  30     }
  31 }
  32
  33 static int gic_post_load(void *opaque, int version_id)
  34 {
  35     GICState *s = (GICState *)opaque;
  36     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  37
  38     if (c->post_load) {
  39         c->post_load(s);
  40     }
  41     return 0;
  42 }
  43
  44 static const VMStateDescription vmstate_gic_irq_state = {
  45     .name = "arm_gic_irq_state",
  46     .version_id = 1,
  47     .minimum_version_id = 1,
  48     .fields = (VMStateField[]) {
  49         VMSTATE_UINT8(enabled, gic_irq_state),
  50         VMSTATE_UINT8(pending, gic_irq_state),
  51         VMSTATE_UINT8(active, gic_irq_state),
  52         VMSTATE_UINT8(level, gic_irq_state),
  53         VMSTATE_BOOL(model, gic_irq_state),
  54         VMSTATE_BOOL(edge_trigger, gic_irq_state),
  55         VMSTATE_UINT8(group, gic_irq_state),
  56         VMSTATE_END_OF_LIST()
  57     }
  58 };
  59
  60 static const VMStateDescription vmstate_gic = {
  61     .name = "arm_gic",
  62     .version_id = 10,
  63     .minimum_version_id = 10,
  64     .pre_save = gic_pre_save,
  65     .post_load = gic_post_load,
  66     .fields = (VMStateField[]) {
  67         VMSTATE_UINT32(ctlr, GICState),
  68         VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
  69         VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
  70                              vmstate_gic_irq_state, gic_irq_state),
  71         VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
  72         VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
  73         VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
  74         VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
  75         VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
  76         VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
  77         VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
  78         VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
  79         VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
  80         VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
  81         VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
  82         VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
  83         VMSTATE_END_OF_LIST()
  84     }
  85 };
  86
  87 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
  88 {
  89     GICState *s = ARM_GIC_COMMON(dev);
  90     int num_irq = s->num_irq;
  91
  92     if (s->num_cpu > GIC_NCPU) {
  93         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
  94                    s->num_cpu, GIC_NCPU);
  95         return;
  96     }
  97     s->num_irq += GIC_BASE_IRQ;
  98     if (s->num_irq > GIC_MAXIRQ) {
  99         error_setg(errp,
 100                    "requested %u interrupt lines exceeds GIC maximum %d",
 101                    num_irq, GIC_MAXIRQ);
 102         return;
 103     }
 104     /* ITLinesNumber is represented as (N / 32) - 1 (see
 105      * gic_dist_readb) so this is an implementation imposed
 106      * restriction, not an architectural one:
 107      */
 108     if (s->num_irq < 32 || (s->num_irq % 32)) {
 109         error_setg(errp,
 110                    "%d interrupt lines unsupported: not divisible by 32",
 111                    num_irq);
 112         return;
 113     }
 114
 115     if (s->security_extn &&
 116         (s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
 117         error_setg(errp, "this GIC revision does not implement "
 118                    "the security extensions");
 119         return;
 120     }
 121 }
 122
 123 static void arm_gic_common_reset(DeviceState *dev)
 124 {
 125     GICState *s = ARM_GIC_COMMON(dev);
 126     int i, j;
 127     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 128     for (i = 0 ; i < s->num_cpu; i++) {
 129         if (s->revision == REV_11MPCORE) {
 130             s->priority_mask[i] = 0xf0;
 131         } else {
 132             s->priority_mask[i] = 0;
 133         }
 134         s->current_pending[i] = 1023;
 135         s->running_irq[i] = 1023;
 136         s->running_priority[i] = 0x100;
 137         s->cpu_ctlr[i] = 0;
 138         s->bpr[i] = GIC_MIN_BPR;
 139         s->abpr[i] = GIC_MIN_ABPR;
 140         for (j = 0; j < GIC_INTERNAL; j++) {
 141             s->priority1[j][i] = 0;
 142         }
 143         for (j = 0; j < GIC_NR_SGIS; j++) {
 144             s->sgi_pending[j][i] = 0;
 145         }
 146     }
 147     for (i = 0; i < GIC_NR_SGIS; i++) {
 148         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 149         GIC_SET_EDGE_TRIGGER(i);
 150     }
 151
 152     for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
 153         s->priority2[i] = 0;
 154     }
 155
 156     for (i = 0; i < GIC_MAXIRQ; i++) {
 157         /* For uniprocessor GICs all interrupts always target the sole CPU */
 158         if (s->num_cpu == 1) {
 159             s->irq_target[i] = 1;
 160         } else {
 161             s->irq_target[i] = 0;
 162         }
 163     }
 164     s->ctlr = 0;
 165 }
 166
 167 static Property arm_gic_common_properties[] = {
 168     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
 169     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
 170     /* Revision can be 1 or 2 for GIC architecture specification
 171      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
 172      * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
 173      */
 174     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
 175     /* True if the GIC should implement the security extensions */
 176     DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
 177     DEFINE_PROP_END_OF_LIST(),
 178 };
 179
 180 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 181 {
 182     DeviceClass *dc = DEVICE_CLASS(klass);
 183
 184     dc->reset = arm_gic_common_reset;
 185     dc->realize = arm_gic_common_realize;
 186     dc->props = arm_gic_common_properties;
 187     dc->vmsd = &vmstate_gic;
 188 }
 189
 190 static const TypeInfo arm_gic_common_type = {
 191     .name = TYPE_ARM_GIC_COMMON,
 192     .parent = TYPE_SYS_BUS_DEVICE,
 193     .instance_size = sizeof(GICState),
 194     .class_size = sizeof(ARMGICCommonClass),
 195     .class_init = arm_gic_common_class_init,
 196     .abstract = true,
 197 };
 198
 199 static void register_types(void)
 200 {
 201     type_register_static(&arm_gic_common_type);
 202 }
 203
 204 type_init(register_types)