qemu/hw/intc/allwinner-a10-pic.c

   1 /*
   2  * Allwinner A10 interrupt controller device emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "hw/sysbus.h"
  20 #include "hw/devices.h"
  21 #include "sysemu/sysemu.h"
  22 #include "hw/intc/allwinner-a10-pic.h"
  23
  24 static void aw_a10_pic_update(AwA10PICState *s)
  25 {
  26     uint8_t i;
  27     int irq = 0, fiq = 0, zeroes;
  28
  29     s->vector = 0;
  30
  31     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
  32         irq |= s->irq_pending[i] & ~s->mask[i];
  33         fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
  34
  35         if (!s->vector) {
  36             zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);
  37             if (zeroes != 32) {
  38                 s->vector = (i * 32 + zeroes) * 4;
  39             }
  40         }
  41     }
  42
  43     qemu_set_irq(s->parent_irq, !!irq);
  44     qemu_set_irq(s->parent_fiq, !!fiq);
  45 }
  46
  47 static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
  48 {
  49     AwA10PICState *s = opaque;
  50
  51     if (level) {
  52         set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  53     } else {
  54         clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  55     }
  56     aw_a10_pic_update(s);
  57 }
  58
  59 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
  60 {
  61     AwA10PICState *s = opaque;
  62     uint8_t index = (offset & 0xc) / 4;
  63
  64     switch (offset) {
  65     case AW_A10_PIC_VECTOR:
  66         return s->vector;
  67     case AW_A10_PIC_BASE_ADDR:
  68         return s->base_addr;
  69     case AW_A10_PIC_PROTECT:
  70         return s->protect;
  71     case AW_A10_PIC_NMI:
  72         return s->nmi;
  73     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
  74         return s->irq_pending[index];
  75     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
  76         return s->fiq_pending[index];
  77     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  78         return s->select[index];
  79     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
  80         return s->enable[index];
  81     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
  82         return s->mask[index];
  83     default:
  84         qemu_log_mask(LOG_GUEST_ERROR,
  85                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  86         break;
  87     }
  88
  89     return 0;
  90 }
  91
  92 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
  93                              unsigned size)
  94 {
  95     AwA10PICState *s = opaque;
  96     uint8_t index = (offset & 0xc) / 4;
  97
  98     switch (offset) {
  99     case AW_A10_PIC_BASE_ADDR:
 100         s->base_addr = value & ~0x3;
 101         break;
 102     case AW_A10_PIC_PROTECT:
 103         s->protect = value;
 104         break;
 105     case AW_A10_PIC_NMI:
 106         s->nmi = value;
 107         break;
 108     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
 109         /*
 110          * The register is read-only; nevertheless, Linux (including
 111          * the version originally shipped by Allwinner) pretends to
 112          * write to the register. Just ignore it.
 113          */
 114         break;
 115     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
 116         s->fiq_pending[index] &= ~value;
 117         break;
 118     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
 119         s->select[index] = value;
 120         break;
 121     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
 122         s->enable[index] = value;
 123         break;
 124     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
 125         s->mask[index] = value;
 126         break;
 127     default:
 128         qemu_log_mask(LOG_GUEST_ERROR,
 129                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
 130         break;
 131     }
 132
 133     aw_a10_pic_update(s);
 134 }
 135
 136 static const MemoryRegionOps aw_a10_pic_ops = {
 137     .read = aw_a10_pic_read,
 138     .write = aw_a10_pic_write,
 139     .endianness = DEVICE_NATIVE_ENDIAN,
 140 };
 141
 142 static const VMStateDescription vmstate_aw_a10_pic = {
 143     .name = "a10.pic",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .fields = (VMStateField[]) {
 147         VMSTATE_UINT32(vector, AwA10PICState),
 148         VMSTATE_UINT32(base_addr, AwA10PICState),
 149         VMSTATE_UINT32(protect, AwA10PICState),
 150         VMSTATE_UINT32(nmi, AwA10PICState),
 151         VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
 152         VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
 153         VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
 154         VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
 155         VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
 156         VMSTATE_END_OF_LIST()
 157     }
 158 };
 159
 160 static void aw_a10_pic_init(Object *obj)
 161 {
 162     AwA10PICState *s = AW_A10_PIC(obj);
 163     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 164
 165      qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
 166      sysbus_init_irq(dev, &s->parent_irq);
 167      sysbus_init_irq(dev, &s->parent_fiq);
 168      memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
 169                            TYPE_AW_A10_PIC, 0x400);
 170      sysbus_init_mmio(dev, &s->iomem);
 171 }
 172
 173 static void aw_a10_pic_reset(DeviceState *d)
 174 {
 175     AwA10PICState *s = AW_A10_PIC(d);
 176     uint8_t i;
 177
 178     s->base_addr = 0;
 179     s->protect = 0;
 180     s->nmi = 0;
 181     s->vector = 0;
 182     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
 183         s->irq_pending[i] = 0;
 184         s->fiq_pending[i] = 0;
 185         s->select[i] = 0;
 186         s->enable[i] = 0;
 187         s->mask[i] = 0;
 188     }
 189 }
 190
 191 static void aw_a10_pic_class_init(ObjectClass *klass, void *data)
 192 {
 193     DeviceClass *dc = DEVICE_CLASS(klass);
 194
 195     dc->reset = aw_a10_pic_reset;
 196     dc->desc = "allwinner a10 pic";
 197     dc->vmsd = &vmstate_aw_a10_pic;
 198  }
 199
 200 static const TypeInfo aw_a10_pic_info = {
 201     .name = TYPE_AW_A10_PIC,
 202     .parent = TYPE_SYS_BUS_DEVICE,
 203     .instance_size = sizeof(AwA10PICState),
 204     .instance_init = aw_a10_pic_init,
 205     .class_init = aw_a10_pic_class_init,
 206 };
 207
 208 static void aw_a10_register_types(void)
 209 {
 210     type_register_static(&aw_a10_pic_info);
 211 }
 212
 213 type_init(aw_a10_register_types);