qemu/hw/cpu/arm11mpcore.c

   1 /*
   2  * ARM11MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/cpu/arm11mpcore.h"
  11 #include "hw/intc/realview_gic.h"
  12
  13
  14 static void mpcore_priv_set_irq(void *opaque, int irq, int level)
  15 {
  16     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  17
  18     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  19 }
  20
  21 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
  22 {
  23     int i;
  24     SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
  25     DeviceState *gicdev = DEVICE(&s->gic);
  26     SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
  27     SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
  28     SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
  29
  30     memory_region_add_subregion(&s->container, 0,
  31                                 sysbus_mmio_get_region(scubusdev, 0));
  32     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
  33      * at 0x200, 0x300...
  34      */
  35     for (i = 0; i < (s->num_cpu + 1); i++) {
  36         hwaddr offset = 0x100 + (i * 0x100);
  37         memory_region_add_subregion(&s->container, offset,
  38                                     sysbus_mmio_get_region(gicbusdev, i + 1));
  39     }
  40     /* Add the regions for timer and watchdog for "current CPU" and
  41      * for each specific CPU.
  42      */
  43     for (i = 0; i < (s->num_cpu + 1); i++) {
  44         /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
  45         hwaddr offset = 0x600 + i * 0x100;
  46         memory_region_add_subregion(&s->container, offset,
  47                                     sysbus_mmio_get_region(timerbusdev, i));
  48         memory_region_add_subregion(&s->container, offset + 0x20,
  49                                     sysbus_mmio_get_region(wdtbusdev, i));
  50     }
  51     memory_region_add_subregion(&s->container, 0x1000,
  52                                 sysbus_mmio_get_region(gicbusdev, 0));
  53     /* Wire up the interrupt from each watchdog and timer.
  54      * For each core the timer is PPI 29 and the watchdog PPI 30.
  55      */
  56     for (i = 0; i < s->num_cpu; i++) {
  57         int ppibase = (s->num_irq - 32) + i * 32;
  58         sysbus_connect_irq(timerbusdev, i,
  59                            qdev_get_gpio_in(gicdev, ppibase + 29));
  60         sysbus_connect_irq(wdtbusdev, i,
  61                            qdev_get_gpio_in(gicdev, ppibase + 30));
  62     }
  63 }
  64
  65 static void mpcore_priv_realize(DeviceState *dev, Error **errp)
  66 {
  67     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  68     ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
  69     DeviceState *scudev = DEVICE(&s->scu);
  70     DeviceState *gicdev = DEVICE(&s->gic);
  71     DeviceState *mptimerdev = DEVICE(&s->mptimer);
  72     DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
  73     Error *err = NULL;
  74
  75     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  76     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
  77     if (err != NULL) {
  78         error_propagate(errp, err);
  79         return;
  80     }
  81
  82     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  83     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  84     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  85     if (err != NULL) {
  86         error_propagate(errp, err);
  87         return;
  88     }
  89
  90     /* Pass through outbound IRQ lines from the GIC */
  91     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
  92
  93     /* Pass through inbound GPIO lines to the GIC */
  94     qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
  95
  96     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
  97     object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
  98     if (err != NULL) {
  99         error_propagate(errp, err);
 100         return;
 101     }
 102
 103     qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
 104     object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
 105     if (err != NULL) {
 106         error_propagate(errp, err);
 107         return;
 108     }
 109
 110     mpcore_priv_map_setup(s);
 111 }
 112
 113 static void mpcore_priv_initfn(Object *obj)
 114 {
 115     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 116     ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
 117
 118     memory_region_init(&s->container, OBJECT(s),
 119                        "mpcore-priv-container", 0x2000);
 120     sysbus_init_mmio(sbd, &s->container);
 121
 122     object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
 123     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 124
 125     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
 126     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 127     /* Request the legacy 11MPCore GIC behaviour: */
 128     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
 129
 130     object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
 131     qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
 132
 133     object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER);
 134     qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
 135 }
 136
 137 static Property mpcore_priv_properties[] = {
 138     DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
 139     /* The ARM11 MPCORE TRM says the on-chip controller may have
 140      * anything from 0 to 224 external interrupt IRQ lines (with another
 141      * 32 internal). We default to 32+32, which is the number provided by
 142      * the ARM11 MPCore test chip in the Realview Versatile Express
 143      * coretile. Other boards may differ and should set this property
 144      * appropriately. Some Linux kernels may not boot if the hardware
 145      * has more IRQ lines than the kernel expects.
 146      */
 147     DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
 148     DEFINE_PROP_END_OF_LIST(),
 149 };
 150
 151 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
 152 {
 153     DeviceClass *dc = DEVICE_CLASS(klass);
 154
 155     dc->realize = mpcore_priv_realize;
 156     dc->props = mpcore_priv_properties;
 157 }
 158
 159 static const TypeInfo mpcore_priv_info = {
 160     .name          = TYPE_ARM11MPCORE_PRIV,
 161     .parent        = TYPE_SYS_BUS_DEVICE,
 162     .instance_size = sizeof(ARM11MPCorePriveState),
 163     .instance_init = mpcore_priv_initfn,
 164     .class_init    = mpcore_priv_class_init,
 165 };
 166
 167 static void arm11mpcore_register_types(void)
 168 {
 169     type_register_static(&mpcore_priv_info);
 170 }
 171
 172 type_init(arm11mpcore_register_types)