qemu/hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25
  26 #define GIC_NUM_SPI_INTR 160
  27
  28 #define ARM_PHYS_TIMER_PPI  30
  29 #define ARM_VIRT_TIMER_PPI  27
  30
  31 #define GIC_BASE_ADDR       0xf9000000
  32 #define GIC_DIST_ADDR       0xf9010000
  33 #define GIC_CPU_ADDR        0xf9020000
  34
  35 #define SATA_INTR           133
  36 #define SATA_ADDR           0xFD0C0000
  37 #define SATA_NUM_PORTS      2
  38
  39 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  40     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  41 };
  42
  43 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  44     57, 59, 61, 63,
  45 };
  46
  47 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  48     0xFF000000, 0xFF010000,
  49 };
  50
  51 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  52     21, 22,
  53 };
  54
  55 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  56     0xFF160000, 0xFF170000,
  57 };
  58
  59 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  60     48, 49,
  61 };
  62
  63 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  64     0xFF040000, 0xFF050000,
  65 };
  66
  67 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  68     19, 20,
  69 };
  70
  71 typedef struct XlnxZynqMPGICRegion {
  72     int region_index;
  73     uint32_t address;
  74 } XlnxZynqMPGICRegion;
  75
  76 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  77     { .region_index = 0, .address = GIC_DIST_ADDR, },
  78     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  79 };
  80
  81 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  82 {
  83     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  84 }
  85
  86 static void xlnx_zynqmp_init(Object *obj)
  87 {
  88     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  89     int i;
  90
  91     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
  92         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
  93                           "cortex-a53-" TYPE_ARM_CPU);
  94         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
  95                                   &error_abort);
  96     }
  97
  98     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
  99         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 100                           "cortex-r5-" TYPE_ARM_CPU);
 101         object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
 102                                   &error_abort);
 103     }
 104
 105     object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
 106                              (Object **)&s->ddr_ram,
 107                              qdev_prop_allow_set_link_before_realize,
 108                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 109
 110     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
 111     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 112
 113     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 114         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 115         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 116     }
 117
 118     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 119         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 120         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 121     }
 122
 123     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 124     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 125
 126     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 127         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 128                           TYPE_SYSBUS_SDHCI);
 129         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 130                             sysbus_get_default());
 131     }
 132
 133     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 134         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 135                           TYPE_XILINX_SPIPS);
 136         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 137     }
 138 }
 139
 140 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 141 {
 142     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 143     MemoryRegion *system_memory = get_system_memory();
 144     uint8_t i;
 145     uint64_t ram_size;
 146     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 147     ram_addr_t ddr_low_size, ddr_high_size;
 148     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 149     Error *err = NULL;
 150
 151     ram_size = memory_region_size(s->ddr_ram);
 152
 153     /* Create the DDR Memory Regions. User friendly checks should happen at
 154      * the board level
 155      */
 156     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 157         /* The RAM size is above the maximum available for the low DDR.
 158          * Create the high DDR memory region as well.
 159          */
 160         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 161         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 162         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 163
 164         memory_region_init_alias(&s->ddr_ram_high, NULL,
 165                                  "ddr-ram-high", s->ddr_ram,
 166                                   ddr_low_size, ddr_high_size);
 167         memory_region_add_subregion(get_system_memory(),
 168                                     XLNX_ZYNQMP_HIGH_RAM_START,
 169                                     &s->ddr_ram_high);
 170     } else {
 171         /* RAM must be non-zero */
 172         assert(ram_size);
 173         ddr_low_size = ram_size;
 174     }
 175
 176     memory_region_init_alias(&s->ddr_ram_low, NULL,
 177                              "ddr-ram-low", s->ddr_ram,
 178                               0, ddr_low_size);
 179     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 180
 181     /* Create the four OCM banks */
 182     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 183         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 184
 185         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 186                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 187         vmstate_register_ram_global(&s->ocm_ram[i]);
 188         memory_region_add_subregion(get_system_memory(),
 189                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 190                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 191                                     &s->ocm_ram[i]);
 192
 193         g_free(ocm_name);
 194     }
 195
 196     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 197     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 198     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 199     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 200     if (err) {
 201         error_propagate(errp, err);
 202         return;
 203     }
 204     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 205     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 206         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 207         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 208         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 209         uint32_t addr = r->address;
 210         int j;
 211
 212         sysbus_mmio_map(gic, r->region_index, addr);
 213
 214         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 215             MemoryRegion *alias = &s->gic_mr[i][j];
 216
 217             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 218             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 219                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 220             memory_region_add_subregion(system_memory, addr, alias);
 221         }
 222     }
 223
 224     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 225         qemu_irq irq;
 226         char *name;
 227
 228         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 229                                 "psci-conduit", &error_abort);
 230
 231         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 232         if (strcmp(name, boot_cpu)) {
 233             /* Secondary CPUs start in PSCI powered-down state */
 234             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 235                                      "start-powered-off", &error_abort);
 236         } else {
 237             s->boot_cpu_ptr = &s->apu_cpu[i];
 238         }
 239         g_free(name);
 240
 241         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 242                                 "reset-cbar", &error_abort);
 243         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 244                                  &err);
 245         if (err) {
 246             error_propagate(errp, err);
 247             return;
 248         }
 249
 250         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 251                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 252                                             ARM_CPU_IRQ));
 253         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 254                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 255         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 256         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 257                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 258         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 259     }
 260
 261     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
 262         char *name;
 263
 264         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 265         if (strcmp(name, boot_cpu)) {
 266             /* Secondary CPUs start in PSCI powered-down state */
 267             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 268                                      "start-powered-off", &error_abort);
 269         } else {
 270             s->boot_cpu_ptr = &s->rpu_cpu[i];
 271         }
 272         g_free(name);
 273
 274         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 275                                  &error_abort);
 276         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 277                                  &err);
 278         if (err) {
 279             error_propagate(errp, err);
 280             return;
 281         }
 282     }
 283
 284     if (!s->boot_cpu_ptr) {
 285         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 286         return;
 287     }
 288
 289     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 290         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 291     }
 292
 293     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 294         NICInfo *nd = &nd_table[i];
 295
 296         if (nd->used) {
 297             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 298             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 299         }
 300         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 301         if (err) {
 302             error_propagate(errp, err);
 303             return;
 304         }
 305         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 306         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 307                            gic_spi[gem_intr[i]]);
 308     }
 309
 310     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 311         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 312         if (err) {
 313             error_propagate(errp, err);
 314             return;
 315         }
 316         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 317         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 318                            gic_spi[uart_intr[i]]);
 319     }
 320
 321     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 322                             &error_abort);
 323     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 324     if (err) {
 325         error_propagate(errp, err);
 326         return;
 327     }
 328
 329     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 330     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 331
 332     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 333         char *bus_name;
 334
 335         object_property_set_bool(OBJECT(&s->sdhci[i]), true,
 336                                  "realized", &err);
 337         if (err) {
 338             error_propagate(errp, err);
 339             return;
 340         }
 341         sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 342                         sdhci_addr[i]);
 343         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 344                            gic_spi[sdhci_intr[i]]);
 345         /* Alias controller SD bus to the SoC itself */
 346         bus_name = g_strdup_printf("sd-bus%d", i);
 347         object_property_add_alias(OBJECT(s), bus_name,
 348                                   OBJECT(&s->sdhci[i]), "sd-bus",
 349                                   &error_abort);
 350         g_free(bus_name);
 351     }
 352
 353     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 354         gchar *bus_name;
 355
 356         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 357
 358         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 359         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 360                            gic_spi[spi_intr[i]]);
 361
 362         /* Alias controller SPI bus to the SoC itself */
 363         bus_name = g_strdup_printf("spi%d", i);
 364         object_property_add_alias(OBJECT(s), bus_name,
 365                                   OBJECT(&s->spi[i]), "spi0",
 366                                   &error_abort);
 367         g_free(bus_name);
 368     }
 369 }
 370
 371 static Property xlnx_zynqmp_props[] = {
 372     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 373     DEFINE_PROP_END_OF_LIST()
 374 };
 375
 376 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 377 {
 378     DeviceClass *dc = DEVICE_CLASS(oc);
 379
 380     dc->props = xlnx_zynqmp_props;
 381     dc->realize = xlnx_zynqmp_realize;
 382
 383     /*
 384      * Reason: creates an ARM CPU, thus use after free(), see
 385      * arm_cpu_class_init()
 386      */
 387     dc->cannot_destroy_with_object_finalize_yet = true;
 388 }
 389
 390 static const TypeInfo xlnx_zynqmp_type_info = {
 391     .name = TYPE_XLNX_ZYNQMP,
 392     .parent = TYPE_DEVICE,
 393     .instance_size = sizeof(XlnxZynqMPState),
 394     .instance_init = xlnx_zynqmp_init,
 395     .class_init = xlnx_zynqmp_class_init,
 396 };
 397
 398 static void xlnx_zynqmp_register_types(void)
 399 {
 400     type_register_static(&xlnx_zynqmp_type_info);
 401 }
 402
 403 type_init(xlnx_zynqmp_register_types)