qemu/hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/isa/apm.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/acpi/acpi.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qapi/error.h"
  30 #include "qemu/range.h"
  31 #include "exec/ioport.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "exec/address-spaces.h"
  34 #include "hw/acpi/piix4.h"
  35 #include "hw/acpi/pcihp.h"
  36 #include "hw/acpi/cpu_hotplug.h"
  37 #include "hw/hotplug.h"
  38 #include "hw/mem/pc-dimm.h"
  39 #include "hw/acpi/memory_hotplug.h"
  40 #include "hw/acpi/acpi_dev_interface.h"
  41 #include "hw/xen/xen.h"
  42
  43 //#define DEBUG
  44
  45 #ifdef DEBUG
  46 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  47 #else
  48 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  49 #endif
  50
  51 #define GPE_BASE 0xafe0
  52 #define GPE_LEN 4
  53
  54 struct pci_status {
  55     uint32_t up; /* deprecated, maintained for migration compatibility */
  56     uint32_t down;
  57 };
  58
  59 typedef struct PIIX4PMState {
  60     /*< private >*/
  61     PCIDevice parent_obj;
  62     /*< public >*/
  63
  64     MemoryRegion io;
  65     uint32_t io_base;
  66
  67     MemoryRegion io_gpe;
  68     ACPIREGS ar;
  69
  70     APMState apm;
  71
  72     PMSMBus smb;
  73     uint32_t smb_io_base;
  74
  75     qemu_irq irq;
  76     qemu_irq smi_irq;
  77     int smm_enabled;
  78     Notifier machine_ready;
  79     Notifier powerdown_notifier;
  80
  81     AcpiPciHpState acpi_pci_hotplug;
  82     bool use_acpi_pci_hotplug;
  83
  84     uint8_t disable_s3;
  85     uint8_t disable_s4;
  86     uint8_t s4_val;
  87
  88     AcpiCpuHotplug gpe_cpu;
  89
  90     MemHotplugState acpi_memory_hotplug;
  91 } PIIX4PMState;
  92
  93 #define TYPE_PIIX4_PM "PIIX4_PM"
  94
  95 #define PIIX4_PM(obj) \
  96     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  97
  98 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  99                                            PCIBus *bus, PIIX4PMState *s);
 100
 101 #define ACPI_ENABLE 0xf1
 102 #define ACPI_DISABLE 0xf0
 103
 104 static void pm_tmr_timer(ACPIREGS *ar)
 105 {
 106     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 107     acpi_update_sci(&s->ar, s->irq);
 108 }
 109
 110 static void apm_ctrl_changed(uint32_t val, void *arg)
 111 {
 112     PIIX4PMState *s = arg;
 113     PCIDevice *d = PCI_DEVICE(s);
 114
 115     /* ACPI specs 3.0, 4.7.2.5 */
 116     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 117     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 118         return;
 119     }
 120
 121     if (d->config[0x5b] & (1 << 1)) {
 122         if (s->smi_irq) {
 123             qemu_irq_raise(s->smi_irq);
 124         }
 125     }
 126 }
 127
 128 static void pm_io_space_update(PIIX4PMState *s)
 129 {
 130     PCIDevice *d = PCI_DEVICE(s);
 131
 132     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 133     s->io_base &= 0xffc0;
 134
 135     memory_region_transaction_begin();
 136     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 137     memory_region_set_address(&s->io, s->io_base);
 138     memory_region_transaction_commit();
 139 }
 140
 141 static void smbus_io_space_update(PIIX4PMState *s)
 142 {
 143     PCIDevice *d = PCI_DEVICE(s);
 144
 145     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 146     s->smb_io_base &= 0xffc0;
 147
 148     memory_region_transaction_begin();
 149     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 150     memory_region_set_address(&s->smb.io, s->smb_io_base);
 151     memory_region_transaction_commit();
 152 }
 153
 154 static void pm_write_config(PCIDevice *d,
 155                             uint32_t address, uint32_t val, int len)
 156 {
 157     pci_default_write_config(d, address, val, len);
 158     if (range_covers_byte(address, len, 0x80) ||
 159         ranges_overlap(address, len, 0x40, 4)) {
 160         pm_io_space_update((PIIX4PMState *)d);
 161     }
 162     if (range_covers_byte(address, len, 0xd2) ||
 163         ranges_overlap(address, len, 0x90, 4)) {
 164         smbus_io_space_update((PIIX4PMState *)d);
 165     }
 166 }
 167
 168 static int vmstate_acpi_post_load(void *opaque, int version_id)
 169 {
 170     PIIX4PMState *s = opaque;
 171
 172     pm_io_space_update(s);
 173     return 0;
 174 }
 175
 176 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 177  {                                                                   \
 178      .name       = (stringify(_field)),                              \
 179      .version_id = 0,                                                \
 180      .info       = &vmstate_info_uint16,                             \
 181      .size       = sizeof(uint16_t),                                 \
 182      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 183      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 184  }
 185
 186 static const VMStateDescription vmstate_gpe = {
 187     .name = "gpe",
 188     .version_id = 1,
 189     .minimum_version_id = 1,
 190     .fields = (VMStateField[]) {
 191         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 192         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 193         VMSTATE_END_OF_LIST()
 194     }
 195 };
 196
 197 static const VMStateDescription vmstate_pci_status = {
 198     .name = "pci_status",
 199     .version_id = 1,
 200     .minimum_version_id = 1,
 201     .fields = (VMStateField[]) {
 202         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 203         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 204         VMSTATE_END_OF_LIST()
 205     }
 206 };
 207
 208 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 209 {
 210     PIIX4PMState *s = opaque;
 211     int ret, i;
 212     uint16_t temp;
 213
 214     ret = pci_device_load(PCI_DEVICE(s), f);
 215     if (ret < 0) {
 216         return ret;
 217     }
 218     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 219     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 220     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 221
 222     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 223     if (ret) {
 224         return ret;
 225     }
 226
 227     timer_get(f, s->ar.tmr.timer);
 228     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 229
 230     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 231     for (i = 0; i < 3; i++) {
 232         qemu_get_be16s(f, &temp);
 233     }
 234
 235     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 236     for (i = 0; i < 3; i++) {
 237         qemu_get_be16s(f, &temp);
 238     }
 239
 240     ret = vmstate_load_state(f, &vmstate_pci_status,
 241         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 242     return ret;
 243 }
 244
 245 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 246 {
 247     PIIX4PMState *s = opaque;
 248     return s->use_acpi_pci_hotplug;
 249 }
 250
 251 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 252 {
 253     PIIX4PMState *s = opaque;
 254     return !s->use_acpi_pci_hotplug;
 255 }
 256
 257 static bool vmstate_test_use_memhp(void *opaque)
 258 {
 259     PIIX4PMState *s = opaque;
 260     return s->acpi_memory_hotplug.is_enabled;
 261 }
 262
 263 static const VMStateDescription vmstate_memhp_state = {
 264     .name = "piix4_pm/memhp",
 265     .version_id = 1,
 266     .minimum_version_id = 1,
 267     .minimum_version_id_old = 1,
 268     .needed = vmstate_test_use_memhp,
 269     .fields      = (VMStateField[]) {
 270         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 271         VMSTATE_END_OF_LIST()
 272     }
 273 };
 274
 275 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 276  * To support incoming qemu-kvm 1.2 migration, change version_id
 277  * and minimum_version_id to 2 below (which breaks migration from
 278  * qemu 1.2).
 279  *
 280  */
 281 static const VMStateDescription vmstate_acpi = {
 282     .name = "piix4_pm",
 283     .version_id = 3,
 284     .minimum_version_id = 3,
 285     .minimum_version_id_old = 1,
 286     .load_state_old = acpi_load_old,
 287     .post_load = vmstate_acpi_post_load,
 288     .fields = (VMStateField[]) {
 289         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 290         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 291         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 292         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 293         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 294         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 295         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 296         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 297         VMSTATE_STRUCT_TEST(
 298             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 299             PIIX4PMState,
 300             vmstate_test_no_use_acpi_pci_hotplug,
 301             2, vmstate_pci_status,
 302             struct AcpiPciHpPciStatus),
 303         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 304                             vmstate_test_use_acpi_pci_hotplug),
 305         VMSTATE_END_OF_LIST()
 306     },
 307     .subsections = (const VMStateDescription*[]) {
 308          &vmstate_memhp_state,
 309          NULL
 310     }
 311 };
 312
 313 static void piix4_reset(void *opaque)
 314 {
 315     PIIX4PMState *s = opaque;
 316     PCIDevice *d = PCI_DEVICE(s);
 317     uint8_t *pci_conf = d->config;
 318
 319     pci_conf[0x58] = 0;
 320     pci_conf[0x59] = 0;
 321     pci_conf[0x5a] = 0;
 322     pci_conf[0x5b] = 0;
 323
 324     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 325     pci_conf[0x80] = 0;
 326
 327     if (!s->smm_enabled) {
 328         /* Mark SMM as already inited (until KVM supports SMM). */
 329         pci_conf[0x5B] = 0x02;
 330     }
 331     pm_io_space_update(s);
 332     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 333 }
 334
 335 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 336 {
 337     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 338
 339     assert(s != NULL);
 340     acpi_pm1_evt_power_down(&s->ar);
 341 }
 342
 343 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 344                                  DeviceState *dev, Error **errp)
 345 {
 346     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 347
 348     if (s->acpi_memory_hotplug.is_enabled &&
 349         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 350         acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp);
 351     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 352         acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 353                                   errp);
 354     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 355         acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp);
 356     } else {
 357         error_setg(errp, "acpi: device plug request for not supported device"
 358                    " type: %s", object_get_typename(OBJECT(dev)));
 359     }
 360 }
 361
 362 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 363                                            DeviceState *dev, Error **errp)
 364 {
 365     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 366
 367     if (s->acpi_memory_hotplug.is_enabled &&
 368         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 369         acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug,
 370                                       dev, errp);
 371     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 372         acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 373                                     errp);
 374     } else {
 375         error_setg(errp, "acpi: device unplug request for not supported device"
 376                    " type: %s", object_get_typename(OBJECT(dev)));
 377     }
 378 }
 379
 380 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 381                                    DeviceState *dev, Error **errp)
 382 {
 383     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 384
 385     if (s->acpi_memory_hotplug.is_enabled &&
 386         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 387         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 388     } else {
 389         error_setg(errp, "acpi: device unplug for not supported device"
 390                    " type: %s", object_get_typename(OBJECT(dev)));
 391     }
 392 }
 393
 394 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 395 {
 396     PIIX4PMState *s = opaque;
 397
 398     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 399 }
 400
 401 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 402 {
 403     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 404     PCIDevice *d = PCI_DEVICE(s);
 405     MemoryRegion *io_as = pci_address_space_io(d);
 406     uint8_t *pci_conf;
 407
 408     pci_conf = d->config;
 409     pci_conf[0x5f] = 0x10 |
 410         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 411     pci_conf[0x63] = 0x60;
 412     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 413         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 414
 415     if (s->use_acpi_pci_hotplug) {
 416         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 417     } else {
 418         piix4_update_bus_hotplug(d->bus, s);
 419     }
 420 }
 421
 422 static void piix4_pm_add_propeties(PIIX4PMState *s)
 423 {
 424     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 425     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 426     static const uint32_t gpe0_blk = GPE_BASE;
 427     static const uint32_t gpe0_blk_len = GPE_LEN;
 428     static const uint16_t sci_int = 9;
 429
 430     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 431                                   &acpi_enable_cmd, NULL);
 432     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 433                                   &acpi_disable_cmd, NULL);
 434     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 435                                   &gpe0_blk, NULL);
 436     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 437                                   &gpe0_blk_len, NULL);
 438     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 439                                   &sci_int, NULL);
 440     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 441                                   &s->io_base, NULL);
 442 }
 443
 444 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 445 {
 446     PIIX4PMState *s = PIIX4_PM(dev);
 447     uint8_t *pci_conf;
 448
 449     pci_conf = dev->config;
 450     pci_conf[0x06] = 0x80;
 451     pci_conf[0x07] = 0x02;
 452     pci_conf[0x09] = 0x00;
 453     pci_conf[0x3d] = 0x01; // interrupt pin 1
 454
 455     /* APM */
 456     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 457
 458     if (!s->smm_enabled) {
 459         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 460          * support SMM mode. */
 461         pci_conf[0x5B] = 0x02;
 462     }
 463
 464     /* XXX: which specification is used ? The i82731AB has different
 465        mappings */
 466     pci_conf[0x90] = s->smb_io_base | 1;
 467     pci_conf[0x91] = s->smb_io_base >> 8;
 468     pci_conf[0xd2] = 0x09;
 469     pm_smbus_init(DEVICE(dev), &s->smb);
 470     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 471     memory_region_add_subregion(pci_address_space_io(dev),
 472                                 s->smb_io_base, &s->smb.io);
 473
 474     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 475     memory_region_set_enabled(&s->io, false);
 476     memory_region_add_subregion(pci_address_space_io(dev),
 477                                 0, &s->io);
 478
 479     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 480     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 481     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 482     acpi_gpe_init(&s->ar, GPE_LEN);
 483
 484     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 485     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 486
 487     s->machine_ready.notify = piix4_pm_machine_ready;
 488     qemu_add_machine_init_done_notifier(&s->machine_ready);
 489     qemu_register_reset(piix4_reset, s);
 490
 491     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 492
 493     piix4_pm_add_propeties(s);
 494 }
 495
 496 Object *piix4_pm_find(void)
 497 {
 498     bool ambig;
 499     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 500
 501     if (ambig || !o) {
 502         return NULL;
 503     }
 504     return o;
 505 }
 506
 507 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 508                       qemu_irq sci_irq, qemu_irq smi_irq,
 509                       int smm_enabled, DeviceState **piix4_pm)
 510 {
 511     DeviceState *dev;
 512     PIIX4PMState *s;
 513
 514     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 515     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 516     if (piix4_pm) {
 517         *piix4_pm = dev;
 518     }
 519
 520     s = PIIX4_PM(dev);
 521     s->irq = sci_irq;
 522     s->smi_irq = smi_irq;
 523     s->smm_enabled = smm_enabled;
 524     if (xen_enabled()) {
 525         s->use_acpi_pci_hotplug = false;
 526     }
 527
 528     qdev_init_nofail(dev);
 529
 530     return s->smb.smbus;
 531 }
 532
 533 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 534 {
 535     PIIX4PMState *s = opaque;
 536     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 537
 538     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 539     return val;
 540 }
 541
 542 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 543                        unsigned width)
 544 {
 545     PIIX4PMState *s = opaque;
 546
 547     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 548     acpi_update_sci(&s->ar, s->irq);
 549
 550     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 551 }
 552
 553 static const MemoryRegionOps piix4_gpe_ops = {
 554     .read = gpe_readb,
 555     .write = gpe_writeb,
 556     .valid.min_access_size = 1,
 557     .valid.max_access_size = 4,
 558     .impl.min_access_size = 1,
 559     .impl.max_access_size = 1,
 560     .endianness = DEVICE_LITTLE_ENDIAN,
 561 };
 562
 563 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 564                                            PCIBus *bus, PIIX4PMState *s)
 565 {
 566     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 567                           "acpi-gpe0", GPE_LEN);
 568     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 569
 570     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 571                     s->use_acpi_pci_hotplug);
 572
 573     acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 574                           PIIX4_CPU_HOTPLUG_IO_BASE);
 575
 576     if (s->acpi_memory_hotplug.is_enabled) {
 577         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
 578     }
 579 }
 580
 581 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 582 {
 583     PIIX4PMState *s = PIIX4_PM(adev);
 584
 585     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 586 }
 587
 588 static Property piix4_pm_properties[] = {
 589     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 590     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 591     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 592     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 593     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 594                      use_acpi_pci_hotplug, true),
 595     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 596                      acpi_memory_hotplug.is_enabled, true),
 597     DEFINE_PROP_END_OF_LIST(),
 598 };
 599
 600 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 601 {
 602     DeviceClass *dc = DEVICE_CLASS(klass);
 603     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 604     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 605     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 606
 607     k->realize = piix4_pm_realize;
 608     k->config_write = pm_write_config;
 609     k->vendor_id = PCI_VENDOR_ID_INTEL;
 610     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 611     k->revision = 0x03;
 612     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 613     dc->desc = "PM";
 614     dc->vmsd = &vmstate_acpi;
 615     dc->props = piix4_pm_properties;
 616     /*
 617      * Reason: part of PIIX4 southbridge, needs to be wired up,
 618      * e.g. by mips_malta_init()
 619      */
 620     dc->cannot_instantiate_with_device_add_yet = true;
 621     dc->hotpluggable = false;
 622     hc->plug = piix4_device_plug_cb;
 623     hc->unplug_request = piix4_device_unplug_request_cb;
 624     hc->unplug = piix4_device_unplug_cb;
 625     adevc->ospm_status = piix4_ospm_status;
 626 }
 627
 628 static const TypeInfo piix4_pm_info = {
 629     .name          = TYPE_PIIX4_PM,
 630     .parent        = TYPE_PCI_DEVICE,
 631     .instance_size = sizeof(PIIX4PMState),
 632     .class_init    = piix4_pm_class_init,
 633     .interfaces = (InterfaceInfo[]) {
 634         { TYPE_HOTPLUG_HANDLER },
 635         { TYPE_ACPI_DEVICE_IF },
 636         { }
 637     }
 638 };
 639
 640 static void piix4_pm_register_types(void)
 641 {
 642     type_register_static(&piix4_pm_info);
 643 }
 644
 645 type_init(piix4_pm_register_types)