qemu/hw/acpi/ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   8  *
   9  * This is based on acpi.c.
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License version 2 as published by the Free Software Foundation.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  22  *
  23  * Contributions after 2012-01-13 are licensed under the terms of the
  24  * GNU GPL, version 2 or (at your option) any later version.
  25  */
  26 #include "hw/hw.h"
  27 #include "qapi/visitor.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/pci/pci.h"
  30 #include "qemu/timer.h"
  31 #include "sysemu/sysemu.h"
  32 #include "hw/acpi/acpi.h"
  33 #include "hw/acpi/tco.h"
  34 #include "sysemu/kvm.h"
  35 #include "exec/address-spaces.h"
  36
  37 #include "hw/i386/ich9.h"
  38 #include "hw/mem/pc-dimm.h"
  39
  40 //#define DEBUG
  41
  42 #ifdef DEBUG
  43 #define ICH9_DEBUG(fmt, ...) \
  44 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
  45 #else
  46 #define ICH9_DEBUG(fmt, ...)    do { } while (0)
  47 #endif
  48
  49 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
  50 {
  51     ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
  52     acpi_update_sci(&pm->acpi_regs, pm->irq);
  53 }
  54
  55 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
  56 {
  57     ICH9LPCPMRegs *pm = opaque;
  58     return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
  59 }
  60
  61 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
  62                             unsigned width)
  63 {
  64     ICH9LPCPMRegs *pm = opaque;
  65     acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
  66     acpi_update_sci(&pm->acpi_regs, pm->irq);
  67 }
  68
  69 static const MemoryRegionOps ich9_gpe_ops = {
  70     .read = ich9_gpe_readb,
  71     .write = ich9_gpe_writeb,
  72     .valid.min_access_size = 1,
  73     .valid.max_access_size = 4,
  74     .impl.min_access_size = 1,
  75     .impl.max_access_size = 1,
  76     .endianness = DEVICE_LITTLE_ENDIAN,
  77 };
  78
  79 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
  80 {
  81     ICH9LPCPMRegs *pm = opaque;
  82     switch (addr) {
  83     case 0:
  84         return pm->smi_en;
  85     case 4:
  86         return pm->smi_sts;
  87     default:
  88         return 0;
  89     }
  90 }
  91
  92 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
  93                             unsigned width)
  94 {
  95     ICH9LPCPMRegs *pm = opaque;
  96     TCOIORegs *tr = &pm->tco_regs;
  97     uint64_t tco_en;
  98
  99     switch (addr) {
 100     case 0:
 101         tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
 102         /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
 103         if (tr->tco.cnt1 & TCO_LOCK) {
 104             val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
 105         }
 106         pm->smi_en &= ~pm->smi_en_wmask;
 107         pm->smi_en |= (val & pm->smi_en_wmask);
 108         break;
 109     }
 110 }
 111
 112 static const MemoryRegionOps ich9_smi_ops = {
 113     .read = ich9_smi_readl,
 114     .write = ich9_smi_writel,
 115     .valid.min_access_size = 4,
 116     .valid.max_access_size = 4,
 117     .endianness = DEVICE_LITTLE_ENDIAN,
 118 };
 119
 120 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
 121 {
 122     ICH9_DEBUG("to 0x%x\n", pm_io_base);
 123
 124     assert((pm_io_base & ICH9_PMIO_MASK) == 0);
 125
 126     pm->pm_io_base = pm_io_base;
 127     memory_region_transaction_begin();
 128     memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
 129     memory_region_set_address(&pm->io, pm->pm_io_base);
 130     memory_region_transaction_commit();
 131 }
 132
 133 static int ich9_pm_post_load(void *opaque, int version_id)
 134 {
 135     ICH9LPCPMRegs *pm = opaque;
 136     uint32_t pm_io_base = pm->pm_io_base;
 137     pm->pm_io_base = 0;
 138     ich9_pm_iospace_update(pm, pm_io_base);
 139     return 0;
 140 }
 141
 142 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 143  {                                                                   \
 144      .name       = (stringify(_field)),                              \
 145      .version_id = 0,                                                \
 146      .num        = ICH9_PMIO_GPE0_LEN,                               \
 147      .info       = &vmstate_info_uint8,                              \
 148      .size       = sizeof(uint8_t),                                  \
 149      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 150      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 151  }
 152
 153 static bool vmstate_test_use_memhp(void *opaque)
 154 {
 155     ICH9LPCPMRegs *s = opaque;
 156     return s->acpi_memory_hotplug.is_enabled;
 157 }
 158
 159 static const VMStateDescription vmstate_memhp_state = {
 160     .name = "ich9_pm/memhp",
 161     .version_id = 1,
 162     .minimum_version_id = 1,
 163     .minimum_version_id_old = 1,
 164     .needed = vmstate_test_use_memhp,
 165     .fields      = (VMStateField[]) {
 166         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
 167         VMSTATE_END_OF_LIST()
 168     }
 169 };
 170
 171 static bool vmstate_test_use_tco(void *opaque)
 172 {
 173     ICH9LPCPMRegs *s = opaque;
 174     return s->enable_tco;
 175 }
 176
 177 static const VMStateDescription vmstate_tco_io_state = {
 178     .name = "ich9_pm/tco",
 179     .version_id = 1,
 180     .minimum_version_id = 1,
 181     .minimum_version_id_old = 1,
 182     .needed = vmstate_test_use_tco,
 183     .fields      = (VMStateField[]) {
 184         VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
 185                        TCOIORegs),
 186         VMSTATE_END_OF_LIST()
 187     }
 188 };
 189
 190 const VMStateDescription vmstate_ich9_pm = {
 191     .name = "ich9_pm",
 192     .version_id = 1,
 193     .minimum_version_id = 1,
 194     .post_load = ich9_pm_post_load,
 195     .fields = (VMStateField[]) {
 196         VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
 197         VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
 198         VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
 199         VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
 200         VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
 201         VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
 202         VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
 203         VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
 204         VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
 205         VMSTATE_END_OF_LIST()
 206     },
 207     .subsections = (const VMStateDescription*[]) {
 208         &vmstate_memhp_state,
 209         &vmstate_tco_io_state,
 210         NULL
 211     }
 212 };
 213
 214 static void pm_reset(void *opaque)
 215 {
 216     ICH9LPCPMRegs *pm = opaque;
 217     ich9_pm_iospace_update(pm, 0);
 218
 219     acpi_pm1_evt_reset(&pm->acpi_regs);
 220     acpi_pm1_cnt_reset(&pm->acpi_regs);
 221     acpi_pm_tmr_reset(&pm->acpi_regs);
 222     acpi_gpe_reset(&pm->acpi_regs);
 223
 224     pm->smi_en = 0;
 225     if (!pm->smm_enabled) {
 226         /* Mark SMM as already inited to prevent SMM from running. */
 227         pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
 228     }
 229     pm->smi_en_wmask = ~0;
 230
 231     acpi_update_sci(&pm->acpi_regs, pm->irq);
 232 }
 233
 234 static void pm_powerdown_req(Notifier *n, void *opaque)
 235 {
 236     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
 237
 238     acpi_pm1_evt_power_down(&pm->acpi_regs);
 239 }
 240
 241 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
 242                   bool smm_enabled, bool enable_tco,
 243                   qemu_irq sci_irq)
 244 {
 245     memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
 246     memory_region_set_enabled(&pm->io, false);
 247     memory_region_add_subregion(pci_address_space_io(lpc_pci),
 248                                 0, &pm->io);
 249
 250     acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 251     acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 252     acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
 253                       pm->s4_val);
 254
 255     acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
 256     memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
 257                           "acpi-gpe0", ICH9_PMIO_GPE0_LEN);
 258     memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
 259
 260     memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
 261                           "acpi-smi", 8);
 262     memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
 263
 264     pm->smm_enabled = smm_enabled;
 265
 266     pm->enable_tco = enable_tco;
 267     if (pm->enable_tco) {
 268         acpi_pm_tco_init(&pm->tco_regs, &pm->io);
 269     }
 270
 271     pm->irq = sci_irq;
 272     qemu_register_reset(pm_reset, pm);
 273     pm->powerdown_notifier.notify = pm_powerdown_req;
 274     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 275
 276     acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
 277                           &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
 278
 279     if (pm->acpi_memory_hotplug.is_enabled) {
 280         acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
 281                                  &pm->acpi_memory_hotplug);
 282     }
 283 }
 284
 285 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
 286                                  void *opaque, const char *name,
 287                                  Error **errp)
 288 {
 289     ICH9LPCPMRegs *pm = opaque;
 290     uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
 291
 292     visit_type_uint32(v, &value, name, errp);
 293 }
 294
 295 static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp)
 296 {
 297     ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
 298
 299     return s->pm.acpi_memory_hotplug.is_enabled;
 300 }
 301
 302 static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
 303                                                Error **errp)
 304 {
 305     ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
 306
 307     s->pm.acpi_memory_hotplug.is_enabled = value;
 308 }
 309
 310 static void ich9_pm_get_disable_s3(Object *obj, Visitor *v,
 311                                    void *opaque, const char *name,
 312                                    Error **errp)
 313 {
 314     ICH9LPCPMRegs *pm = opaque;
 315     uint8_t value = pm->disable_s3;
 316
 317     visit_type_uint8(v, &value, name, errp);
 318 }
 319
 320 static void ich9_pm_set_disable_s3(Object *obj, Visitor *v,
 321                                    void *opaque, const char *name,
 322                                    Error **errp)
 323 {
 324     ICH9LPCPMRegs *pm = opaque;
 325     Error *local_err = NULL;
 326     uint8_t value;
 327
 328     visit_type_uint8(v, &value, name, &local_err);
 329     if (local_err) {
 330         goto out;
 331     }
 332     pm->disable_s3 = value;
 333 out:
 334     error_propagate(errp, local_err);
 335 }
 336
 337 static void ich9_pm_get_disable_s4(Object *obj, Visitor *v,
 338                                    void *opaque, const char *name,
 339                                    Error **errp)
 340 {
 341     ICH9LPCPMRegs *pm = opaque;
 342     uint8_t value = pm->disable_s4;
 343
 344     visit_type_uint8(v, &value, name, errp);
 345 }
 346
 347 static void ich9_pm_set_disable_s4(Object *obj, Visitor *v,
 348                                    void *opaque, const char *name,
 349                                    Error **errp)
 350 {
 351     ICH9LPCPMRegs *pm = opaque;
 352     Error *local_err = NULL;
 353     uint8_t value;
 354
 355     visit_type_uint8(v, &value, name, &local_err);
 356     if (local_err) {
 357         goto out;
 358     }
 359     pm->disable_s4 = value;
 360 out:
 361     error_propagate(errp, local_err);
 362 }
 363
 364 static void ich9_pm_get_s4_val(Object *obj, Visitor *v,
 365                                void *opaque, const char *name,
 366                                Error **errp)
 367 {
 368     ICH9LPCPMRegs *pm = opaque;
 369     uint8_t value = pm->s4_val;
 370
 371     visit_type_uint8(v, &value, name, errp);
 372 }
 373
 374 static void ich9_pm_set_s4_val(Object *obj, Visitor *v,
 375                                void *opaque, const char *name,
 376                                Error **errp)
 377 {
 378     ICH9LPCPMRegs *pm = opaque;
 379     Error *local_err = NULL;
 380     uint8_t value;
 381
 382     visit_type_uint8(v, &value, name, &local_err);
 383     if (local_err) {
 384         goto out;
 385     }
 386     pm->s4_val = value;
 387 out:
 388     error_propagate(errp, local_err);
 389 }
 390
 391 static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
 392 {
 393     ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
 394     return s->pm.enable_tco;
 395 }
 396
 397 static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
 398 {
 399     ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
 400     s->pm.enable_tco = value;
 401 }
 402
 403 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
 404 {
 405     static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
 406     pm->acpi_memory_hotplug.is_enabled = true;
 407     pm->disable_s3 = 0;
 408     pm->disable_s4 = 0;
 409     pm->s4_val = 2;
 410
 411     object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
 412                                    &pm->pm_io_base, errp);
 413     object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
 414                         ich9_pm_get_gpe0_blk,
 415                         NULL, NULL, pm, NULL);
 416     object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
 417                                    &gpe0_len, errp);
 418     object_property_add_bool(obj, "memory-hotplug-support",
 419                              ich9_pm_get_memory_hotplug_support,
 420                              ich9_pm_set_memory_hotplug_support,
 421                              NULL);
 422     object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
 423                         ich9_pm_get_disable_s3,
 424                         ich9_pm_set_disable_s3,
 425                         NULL, pm, NULL);
 426     object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8",
 427                         ich9_pm_get_disable_s4,
 428                         ich9_pm_set_disable_s4,
 429                         NULL, pm, NULL);
 430     object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8",
 431                         ich9_pm_get_s4_val,
 432                         ich9_pm_set_s4_val,
 433                         NULL, pm, NULL);
 434     object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
 435                              ich9_pm_get_enable_tco,
 436                              ich9_pm_set_enable_tco,
 437                              NULL);
 438 }
 439
 440 void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)
 441 {
 442     if (pm->acpi_memory_hotplug.is_enabled &&
 443         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 444         acpi_memory_plug_cb(&pm->acpi_regs, pm->irq, &pm->acpi_memory_hotplug,
 445                             dev, errp);
 446     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 447         acpi_cpu_plug_cb(&pm->acpi_regs, pm->irq, &pm->gpe_cpu, dev, errp);
 448     } else {
 449         error_setg(errp, "acpi: device plug request for not supported device"
 450                    " type: %s", object_get_typename(OBJECT(dev)));
 451     }
 452 }
 453
 454 void ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
 455                                       Error **errp)
 456 {
 457     if (pm->acpi_memory_hotplug.is_enabled &&
 458         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 459         acpi_memory_unplug_request_cb(&pm->acpi_regs, pm->irq,
 460                                       &pm->acpi_memory_hotplug, dev, errp);
 461     } else {
 462         error_setg(errp, "acpi: device unplug request for not supported device"
 463                    " type: %s", object_get_typename(OBJECT(dev)));
 464     }
 465 }
 466
 467 void ich9_pm_device_unplug_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
 468                               Error **errp)
 469 {
 470     if (pm->acpi_memory_hotplug.is_enabled &&
 471         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 472         acpi_memory_unplug_cb(&pm->acpi_memory_hotplug, dev, errp);
 473     } else {
 474         error_setg(errp, "acpi: device unplug for not supported device"
 475                    " type: %s", object_get_typename(OBJECT(dev)));
 476     }
 477 }
 478
 479 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 480 {
 481     ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
 482
 483     acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
 484 }