qemu/disas/mips.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "disas/bfd.h"
  23
  24 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  25    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  26    Free Software Foundation, Inc.
  27    Contributed by Ralph Campbell and OSF
  28    Commented and modified by Ian Lance Taylor, Cygnus Support
  29
  30 This file is part of GDB, GAS, and the GNU binutils.
  31
  32 GDB, GAS, and the GNU binutils are free software; you can redistribute
  33 them and/or modify them under the terms of the GNU General Public
  34 License as published by the Free Software Foundation; either version
  35 1, or (at your option) any later version.
  36
  37 GDB, GAS, and the GNU binutils are distributed in the hope that they
  38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  40 the GNU General Public License for more details.
  41
  42 You should have received a copy of the GNU General Public License
  43 along with this file; see the file COPYING.  If not,
  44 see <http://www.gnu.org/licenses/>.  */
  45
  46 /* These are bit masks and shift counts to use to access the various
  47    fields of an instruction.  To retrieve the X field of an
  48    instruction, use the expression
  49         (i >> OP_SH_X) & OP_MASK_X
  50    To set the same field (to j), use
  51         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  52
  53    Make sure you use fields that are appropriate for the instruction,
  54    of course.
  55
  56    The 'i' format uses OP, RS, RT and IMMEDIATE.
  57
  58    The 'j' format uses OP and TARGET.
  59
  60    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  61
  62    The 'b' format uses OP, RS, RT and DELTA.
  63
  64    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  65
  66    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  67
  68    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  69    breakpoint instruction are not defined; Kane says the breakpoint
  70    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  71    only use ten bits).  An optional two-operand form of break/sdbbp
  72    allows the lower ten bits to be set too, and MIPS32 and later
  73    architectures allow 20 bits to be set with a signal operand
  74    (using CODE20).
  75
  76    The syscall instruction uses CODE20.
  77
  78    The general coprocessor instructions use COPZ.  */
  79
  80 #define OP_MASK_OP              0x3f
  81 #define OP_SH_OP                26
  82 #define OP_MASK_RS              0x1f
  83 #define OP_SH_RS                21
  84 #define OP_MASK_FR              0x1f
  85 #define OP_SH_FR                21
  86 #define OP_MASK_FMT             0x1f
  87 #define OP_SH_FMT               21
  88 #define OP_MASK_BCC             0x7
  89 #define OP_SH_BCC               18
  90 #define OP_MASK_CODE            0x3ff
  91 #define OP_SH_CODE              16
  92 #define OP_MASK_CODE2           0x3ff
  93 #define OP_SH_CODE2             6
  94 #define OP_MASK_RT              0x1f
  95 #define OP_SH_RT                16
  96 #define OP_MASK_FT              0x1f
  97 #define OP_SH_FT                16
  98 #define OP_MASK_CACHE           0x1f
  99 #define OP_SH_CACHE             16
 100 #define OP_MASK_RD              0x1f
 101 #define OP_SH_RD                11
 102 #define OP_MASK_FS              0x1f
 103 #define OP_SH_FS                11
 104 #define OP_MASK_PREFX           0x1f
 105 #define OP_SH_PREFX             11
 106 #define OP_MASK_CCC             0x7
 107 #define OP_SH_CCC               8
 108 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 109 #define OP_SH_CODE20            6
 110 #define OP_MASK_SHAMT           0x1f
 111 #define OP_SH_SHAMT             6
 112 #define OP_MASK_FD              0x1f
 113 #define OP_SH_FD                6
 114 #define OP_MASK_TARGET          0x3ffffff
 115 #define OP_SH_TARGET            0
 116 #define OP_MASK_COPZ            0x1ffffff
 117 #define OP_SH_COPZ              0
 118 #define OP_MASK_IMMEDIATE       0xffff
 119 #define OP_SH_IMMEDIATE         0
 120 #define OP_MASK_DELTA           0xffff
 121 #define OP_SH_DELTA             0
 122 #define OP_MASK_DELTA_R6        0x1ff
 123 #define OP_SH_DELTA_R6          7
 124 #define OP_MASK_FUNCT           0x3f
 125 #define OP_SH_FUNCT             0
 126 #define OP_MASK_SPEC            0x3f
 127 #define OP_SH_SPEC              0
 128 #define OP_SH_LOCC              8       /* FP condition code.  */
 129 #define OP_SH_HICC              18      /* FP condition code.  */
 130 #define OP_MASK_CC              0x7
 131 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 132 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 133 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 134 #define OP_MASK_COP1SPEC        0xf
 135 #define OP_MASK_COP1SCLR        0x4
 136 #define OP_MASK_COP1CMP         0x3
 137 #define OP_SH_COP1CMP           4
 138 #define OP_SH_FORMAT            21      /* FP short format field.  */
 139 #define OP_MASK_FORMAT          0x7
 140 #define OP_SH_TRUE              16
 141 #define OP_MASK_TRUE            0x1
 142 #define OP_SH_GE                17
 143 #define OP_MASK_GE              0x01
 144 #define OP_SH_UNSIGNED          16
 145 #define OP_MASK_UNSIGNED        0x1
 146 #define OP_SH_HINT              16
 147 #define OP_MASK_HINT            0x1f
 148 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 149 #define OP_MASK_MMI             0x3f
 150 #define OP_SH_MMISUB            6
 151 #define OP_MASK_MMISUB          0x1f
 152 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 153 #define OP_SH_PERFREG           1
 154 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 155 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 156 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 157 #define OP_MASK_CODE19          0x7ffff
 158 #define OP_SH_ALN               21
 159 #define OP_MASK_ALN             0x7
 160 #define OP_SH_VSEL              21
 161 #define OP_MASK_VSEL            0x1f
 162 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 163                                            but 0x8-0xf don't select bytes.  */
 164 #define OP_SH_VECBYTE           22
 165 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 166 #define OP_SH_VECALIGN          21
 167 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 168 #define OP_SH_INSMSB            11
 169 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 170 #define OP_SH_EXTMSBD           11
 171
 172 #define OP_OP_COP0              0x10
 173 #define OP_OP_COP1              0x11
 174 #define OP_OP_COP2              0x12
 175 #define OP_OP_COP3              0x13
 176 #define OP_OP_LWC1              0x31
 177 #define OP_OP_LWC2              0x32
 178 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 179 #define OP_OP_LDC1              0x35
 180 #define OP_OP_LDC2              0x36
 181 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 182 #define OP_OP_SWC1              0x39
 183 #define OP_OP_SWC2              0x3a
 184 #define OP_OP_SWC3              0x3b
 185 #define OP_OP_SDC1              0x3d
 186 #define OP_OP_SDC2              0x3e
 187 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 188
 189 /* MIPS DSP ASE */
 190 #define OP_SH_DSPACC            11
 191 #define OP_MASK_DSPACC          0x3
 192 #define OP_SH_DSPACC_S          21
 193 #define OP_MASK_DSPACC_S        0x3
 194 #define OP_SH_DSPSFT            20
 195 #define OP_MASK_DSPSFT          0x3f
 196 #define OP_SH_DSPSFT_7          19
 197 #define OP_MASK_DSPSFT_7        0x7f
 198 #define OP_SH_SA3               21
 199 #define OP_MASK_SA3             0x7
 200 #define OP_SH_SA4               21
 201 #define OP_MASK_SA4             0xf
 202 #define OP_SH_IMM8              16
 203 #define OP_MASK_IMM8            0xff
 204 #define OP_SH_IMM10             16
 205 #define OP_MASK_IMM10           0x3ff
 206 #define OP_SH_WRDSP             11
 207 #define OP_MASK_WRDSP           0x3f
 208 #define OP_SH_RDDSP             16
 209 #define OP_MASK_RDDSP           0x3f
 210 #define OP_SH_BP                11
 211 #define OP_MASK_BP              0x3
 212
 213 /* MIPS MT ASE */
 214 #define OP_SH_MT_U              5
 215 #define OP_MASK_MT_U            0x1
 216 #define OP_SH_MT_H              4
 217 #define OP_MASK_MT_H            0x1
 218 #define OP_SH_MTACC_T           18
 219 #define OP_MASK_MTACC_T         0x3
 220 #define OP_SH_MTACC_D           13
 221 #define OP_MASK_MTACC_D         0x3
 222
 223 /* MSA */
 224 #define OP_MASK_1BIT            0x1
 225 #define OP_SH_1BIT              16
 226 #define OP_MASK_2BIT            0x3
 227 #define OP_SH_2BIT              16
 228 #define OP_MASK_3BIT            0x7
 229 #define OP_SH_3BIT              16
 230 #define OP_MASK_4BIT            0xf
 231 #define OP_SH_4BIT              16
 232 #define OP_MASK_5BIT            0x1f
 233 #define OP_SH_5BIT              16
 234 #define OP_MASK_10BIT           0x3ff
 235 #define OP_SH_10BIT             11
 236 #define OP_MASK_MSACR11         0x1f
 237 #define OP_SH_MSACR11           11
 238 #define OP_MASK_MSACR6          0x1f
 239 #define OP_SH_MSACR6            6
 240 #define OP_MASK_GPR             0x1f
 241 #define OP_SH_GPR               6
 242 #define OP_MASK_1_TO_4          0x3
 243 #define OP_SH_1_TO_4            6
 244
 245 #define OP_OP_COP0              0x10
 246 #define OP_OP_COP1              0x11
 247 #define OP_OP_COP2              0x12
 248 #define OP_OP_COP3              0x13
 249 #define OP_OP_LWC1              0x31
 250 #define OP_OP_LWC2              0x32
 251 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 252 #define OP_OP_LDC1              0x35
 253 #define OP_OP_LDC2              0x36
 254 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 255 #define OP_OP_SWC1              0x39
 256 #define OP_OP_SWC2              0x3a
 257 #define OP_OP_SWC3              0x3b
 258 #define OP_OP_SDC1              0x3d
 259 #define OP_OP_SDC2              0x3e
 260 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 261
 262 /* Values in the 'VSEL' field.  */
 263 #define MDMX_FMTSEL_IMM_QH      0x1d
 264 #define MDMX_FMTSEL_IMM_OB      0x1e
 265 #define MDMX_FMTSEL_VEC_QH      0x15
 266 #define MDMX_FMTSEL_VEC_OB      0x16
 267
 268 /* UDI */
 269 #define OP_SH_UDI1              6
 270 #define OP_MASK_UDI1            0x1f
 271 #define OP_SH_UDI2              6
 272 #define OP_MASK_UDI2            0x3ff
 273 #define OP_SH_UDI3              6
 274 #define OP_MASK_UDI3            0x7fff
 275 #define OP_SH_UDI4              6
 276 #define OP_MASK_UDI4            0xfffff
 277 /* This structure holds information for a particular instruction.  */
 278
 279 struct mips_opcode
 280 {
 281   /* The name of the instruction.  */
 282   const char *name;
 283   /* A string describing the arguments for this instruction.  */
 284   const char *args;
 285   /* The basic opcode for the instruction.  When assembling, this
 286      opcode is modified by the arguments to produce the actual opcode
 287      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 288   unsigned long match;
 289   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 290      relevant portions of the opcode when disassembling.  If the
 291      actual opcode anded with the match field equals the opcode field,
 292      then we have found the correct instruction.  If pinfo is
 293      INSN_MACRO, then this field is the macro identifier.  */
 294   unsigned long mask;
 295   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 296      of bits describing the instruction, notably any relevant hazard
 297      information.  */
 298   unsigned long pinfo;
 299   /* A collection of additional bits describing the instruction. */
 300   unsigned long pinfo2;
 301   /* A collection of bits describing the instruction sets of which this
 302      instruction or macro is a member. */
 303   unsigned long membership;
 304 };
 305
 306 /* These are the characters which may appear in the args field of an
 307    instruction.  They appear in the order in which the fields appear
 308    when the instruction is used.  Commas and parentheses in the args
 309    string are ignored when assembling, and written into the output
 310    when disassembling.
 311
 312    Each of these characters corresponds to a mask field defined above.
 313
 314    "<" 5 bit shift amount (OP_*_SHAMT)
 315    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 316    "a" 26 bit target address (OP_*_TARGET)
 317    "b" 5 bit base register (OP_*_RS)
 318    "c" 10 bit breakpoint code (OP_*_CODE)
 319    "d" 5 bit destination register specifier (OP_*_RD)
 320    "h" 5 bit prefx hint (OP_*_PREFX)
 321    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 322    "j" 16 bit signed immediate (OP_*_DELTA)
 323    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 324        Also used for immediate operands in vr5400 vector insns.
 325    "o" 16 bit signed offset (OP_*_DELTA)
 326    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 327    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 328    "r" 5 bit same register used as both source and target (OP_*_RS)
 329    "s" 5 bit source register specifier (OP_*_RS)
 330    "t" 5 bit target register (OP_*_RT)
 331    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 332    "v" 5 bit same register used as both source and destination (OP_*_RS)
 333    "w" 5 bit same register used as both target and destination (OP_*_RT)
 334    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 335        (used by clo and clz)
 336    "C" 25 bit coprocessor function code (OP_*_COPZ)
 337    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 338    "J" 19 bit wait function code (OP_*_CODE19)
 339    "x" accept and ignore register name
 340    "z" must be zero register
 341    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 342    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 343         LSB (OP_*_SHAMT).
 344         Enforces: 0 <= pos < 32.
 345    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 346         Requires that "+A" or "+E" occur first to set position.
 347         Enforces: 0 < (pos+size) <= 32.
 348    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 349         Requires that "+A" or "+E" occur first to set position.
 350         Enforces: 0 < (pos+size) <= 32.
 351         (Also used by "dext" w/ different limits, but limits for
 352         that are checked by the M_DEXT macro.)
 353    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 354         Enforces: 32 <= pos < 64.
 355    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 356         Requires that "+A" or "+E" occur first to set position.
 357         Enforces: 32 < (pos+size) <= 64.
 358    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 359         Requires that "+A" or "+E" occur first to set position.
 360         Enforces: 32 < (pos+size) <= 64.
 361    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 362         Requires that "+A" or "+E" occur first to set position.
 363         Enforces: 32 < (pos+size) <= 64.
 364
 365    Floating point instructions:
 366    "D" 5 bit destination register (OP_*_FD)
 367    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 368    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 369    "S" 5 bit fs source 1 register (OP_*_FS)
 370    "T" 5 bit ft source 2 register (OP_*_FT)
 371    "R" 5 bit fr source 3 register (OP_*_FR)
 372    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 373    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 374
 375    Coprocessor instructions:
 376    "E" 5 bit target register (OP_*_RT)
 377    "G" 5 bit destination register (OP_*_RD)
 378    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 379    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 380    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 381    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 382    see also "k" above
 383    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 384         for pretty-printing in disassembly only.
 385
 386    Macro instructions:
 387    "A" General 32 bit expression
 388    "I" 32 bit immediate (value placed in imm_expr).
 389    "+I" 32 bit immediate (value placed in imm2_expr).
 390    "F" 64 bit floating point constant in .rdata
 391    "L" 64 bit floating point constant in .lit8
 392    "f" 32 bit floating point constant
 393    "l" 32 bit floating point constant in .lit4
 394
 395    MDMX instruction operands (note that while these use the FP register
 396    fields, they accept both $fN and $vN names for the registers):
 397    "O"  MDMX alignment offset (OP_*_ALN)
 398    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 399    "X"  MDMX destination register (OP_*_FD)
 400    "Y"  MDMX source register (OP_*_FS)
 401    "Z"  MDMX source register (OP_*_FT)
 402
 403    DSP ASE usage:
 404    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 405    "3" 3 bit unsigned immediate (OP_*_SA3)
 406    "4" 4 bit unsigned immediate (OP_*_SA4)
 407    "5" 8 bit unsigned immediate (OP_*_IMM8)
 408    "6" 5 bit unsigned immediate (OP_*_RS)
 409    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 410    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 411    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 412    "0" 6 bit signed immediate (OP_*_DSPSFT)
 413    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 414    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 415    "@" 10 bit signed immediate (OP_*_IMM10)
 416
 417    MT ASE usage:
 418    "!" 1 bit usermode flag (OP_*_MT_U)
 419    "$" 1 bit load high flag (OP_*_MT_H)
 420    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 421    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 422    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 423    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 424    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 425
 426    UDI immediates:
 427    "+1" UDI immediate bits 6-10
 428    "+2" UDI immediate bits 6-15
 429    "+3" UDI immediate bits 6-20
 430    "+4" UDI immediate bits 6-25
 431
 432    R6 immediates/displacements :
 433    (adding suffix to 'o' to avoid adding new characters)
 434    "+o"  9 bits immediate/displacement (shift = 7)
 435    "+o1" 18 bits immediate/displacement (shift = 0)
 436    "+o2" 19 bits immediate/displacement (shift = 0)
 437
 438    Other:
 439    "()" parens surrounding optional value
 440    ","  separates operands
 441    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 442    "+"  Start of extension sequence.
 443
 444    Characters used so far, for quick reference when adding more:
 445    "234567890"
 446    "%[]<>(),+:'@!$*&"
 447    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 448    "abcdefghijklopqrstuvwxz"
 449
 450    Extension character sequences used so far ("+" followed by the
 451    following), for quick reference when adding more:
 452    "1234"
 453    "ABCDEFGHIT"
 454    "t"
 455 */
 456
 457 /* These are the bits which may be set in the pinfo field of an
 458    instructions, if it is not equal to INSN_MACRO.  */
 459
 460 /* Modifies the general purpose register in OP_*_RD.  */
 461 #define INSN_WRITE_GPR_D            0x00000001
 462 /* Modifies the general purpose register in OP_*_RT.  */
 463 #define INSN_WRITE_GPR_T            0x00000002
 464 /* Modifies general purpose register 31.  */
 465 #define INSN_WRITE_GPR_31           0x00000004
 466 /* Modifies the floating point register in OP_*_FD.  */
 467 #define INSN_WRITE_FPR_D            0x00000008
 468 /* Modifies the floating point register in OP_*_FS.  */
 469 #define INSN_WRITE_FPR_S            0x00000010
 470 /* Modifies the floating point register in OP_*_FT.  */
 471 #define INSN_WRITE_FPR_T            0x00000020
 472 /* Reads the general purpose register in OP_*_RS.  */
 473 #define INSN_READ_GPR_S             0x00000040
 474 /* Reads the general purpose register in OP_*_RT.  */
 475 #define INSN_READ_GPR_T             0x00000080
 476 /* Reads the floating point register in OP_*_FS.  */
 477 #define INSN_READ_FPR_S             0x00000100
 478 /* Reads the floating point register in OP_*_FT.  */
 479 #define INSN_READ_FPR_T             0x00000200
 480 /* Reads the floating point register in OP_*_FR.  */
 481 #define INSN_READ_FPR_R             0x00000400
 482 /* Modifies coprocessor condition code.  */
 483 #define INSN_WRITE_COND_CODE        0x00000800
 484 /* Reads coprocessor condition code.  */
 485 #define INSN_READ_COND_CODE         0x00001000
 486 /* TLB operation.  */
 487 #define INSN_TLB                    0x00002000
 488 /* Reads coprocessor register other than floating point register.  */
 489 #define INSN_COP                    0x00004000
 490 /* Instruction loads value from memory, requiring delay.  */
 491 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 492 /* Instruction loads value from coprocessor, requiring delay.  */
 493 #define INSN_LOAD_COPROC_DELAY      0x00010000
 494 /* Instruction has unconditional branch delay slot.  */
 495 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 496 /* Instruction has conditional branch delay slot.  */
 497 #define INSN_COND_BRANCH_DELAY      0x00040000
 498 /* Conditional branch likely: if branch not taken, insn nullified.  */
 499 #define INSN_COND_BRANCH_LIKELY     0x00080000
 500 /* Moves to coprocessor register, requiring delay.  */
 501 #define INSN_COPROC_MOVE_DELAY      0x00100000
 502 /* Loads coprocessor register from memory, requiring delay.  */
 503 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 504 /* Reads the HI register.  */
 505 #define INSN_READ_HI                0x00400000
 506 /* Reads the LO register.  */
 507 #define INSN_READ_LO                0x00800000
 508 /* Modifies the HI register.  */
 509 #define INSN_WRITE_HI               0x01000000
 510 /* Modifies the LO register.  */
 511 #define INSN_WRITE_LO               0x02000000
 512 /* Takes a trap (easier to keep out of delay slot).  */
 513 #define INSN_TRAP                   0x04000000
 514 /* Instruction stores value into memory.  */
 515 #define INSN_STORE_MEMORY           0x08000000
 516 /* Instruction uses single precision floating point.  */
 517 #define FP_S                        0x10000000
 518 /* Instruction uses double precision floating point.  */
 519 #define FP_D                        0x20000000
 520 /* Instruction is part of the tx39's integer multiply family.    */
 521 #define INSN_MULT                   0x40000000
 522 /* Instruction synchronize shared memory.  */
 523 #define INSN_SYNC                   0x80000000
 524
 525 /* These are the bits which may be set in the pinfo2 field of an
 526    instruction. */
 527
 528 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 529 #define INSN2_ALIAS                 0x00000001
 530 /* Instruction reads MDMX accumulator. */
 531 #define INSN2_READ_MDMX_ACC         0x00000002
 532 /* Instruction writes MDMX accumulator. */
 533 #define INSN2_WRITE_MDMX_ACC        0x00000004
 534
 535 /* Reads the general purpose register in OP_*_RD.  */
 536 #define INSN2_READ_GPR_D    0x00000200
 537
 538 /* Instruction is actually a macro.  It should be ignored by the
 539    disassembler, and requires special treatment by the assembler.  */
 540 #define INSN_MACRO                  0xffffffff
 541
 542 /* Masks used to mark instructions to indicate which MIPS ISA level
 543    they were introduced in.  ISAs, as defined below, are logical
 544    ORs of these bits, indicating that they support the instructions
 545    defined at the given level.  */
 546
 547 #define INSN_ISA_MASK             0x00000fff
 548 #define INSN_ISA1                 0x00000001
 549 #define INSN_ISA2                 0x00000002
 550 #define INSN_ISA3                 0x00000004
 551 #define INSN_ISA4                 0x00000008
 552 #define INSN_ISA5                 0x00000010
 553 #define INSN_ISA32                0x00000020
 554 #define INSN_ISA64                0x00000040
 555 #define INSN_ISA32R2              0x00000080
 556 #define INSN_ISA64R2              0x00000100
 557 #define INSN_ISA32R6              0x00000200
 558 #define INSN_ISA64R6              0x00000400
 559
 560 /* Masks used for MIPS-defined ASEs.  */
 561 #define INSN_ASE_MASK             0x0000f000
 562
 563 /* DSP ASE */
 564 #define INSN_DSP                  0x00001000
 565 #define INSN_DSP64                0x00002000
 566 /* MIPS 16 ASE */
 567 #define INSN_MIPS16               0x00004000
 568 /* MIPS-3D ASE */
 569 #define INSN_MIPS3D               0x00008000
 570
 571 /* Chip specific instructions.  These are bitmasks.  */
 572
 573 /* MIPS R4650 instruction.  */
 574 #define INSN_4650                 0x00010000
 575 /* LSI R4010 instruction.  */
 576 #define INSN_4010                 0x00020000
 577 /* NEC VR4100 instruction.  */
 578 #define INSN_4100                 0x00040000
 579 /* Toshiba R3900 instruction.  */
 580 #define INSN_3900                 0x00080000
 581 /* MIPS R10000 instruction.  */
 582 #define INSN_10000                0x00100000
 583 /* Broadcom SB-1 instruction.  */
 584 #define INSN_SB1                  0x00200000
 585 /* NEC VR4111/VR4181 instruction.  */
 586 #define INSN_4111                 0x00400000
 587 /* NEC VR4120 instruction.  */
 588 #define INSN_4120                 0x00800000
 589 /* NEC VR5400 instruction.  */
 590 #define INSN_5400                 0x01000000
 591 /* NEC VR5500 instruction.  */
 592 #define INSN_5500                 0x02000000
 593
 594 /* MDMX ASE */
 595 #define INSN_MDMX                 0x00000000    /* Deprecated */
 596
 597 /* MIPS MSA Extension */
 598 #define INSN_MSA                  0x04000000
 599 #define INSN_MSA64                0x04000000
 600
 601 /* MT ASE */
 602 #define INSN_MT                   0x08000000
 603 /* SmartMIPS ASE  */
 604 #define INSN_SMARTMIPS            0x10000000
 605 /* DSP R2 ASE  */
 606 #define INSN_DSPR2                0x20000000
 607
 608 /* ST Microelectronics Loongson 2E.  */
 609 #define INSN_LOONGSON_2E          0x40000000
 610 /* ST Microelectronics Loongson 2F.  */
 611 #define INSN_LOONGSON_2F          0x80000000
 612
 613 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 614
 615 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 616 #define       ISA_MIPS1       (INSN_ISA1)
 617 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 618 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 619 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 620 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 621
 622 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 623 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 624
 625 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 626 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 627
 628 #define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
 629 #define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
 630
 631 /* CPU defines, use instead of hardcoding processor number. Keep this
 632    in sync with bfd/archures.c in order for machine selection to work.  */
 633 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 634 #define CPU_R3000       3000
 635 #define CPU_R3900       3900
 636 #define CPU_R4000       4000
 637 #define CPU_R4010       4010
 638 #define CPU_VR4100      4100
 639 #define CPU_R4111       4111
 640 #define CPU_VR4120      4120
 641 #define CPU_R4300       4300
 642 #define CPU_R4400       4400
 643 #define CPU_R4600       4600
 644 #define CPU_R4650       4650
 645 #define CPU_R5000       5000
 646 #define CPU_VR5400      5400
 647 #define CPU_VR5500      5500
 648 #define CPU_R6000       6000
 649 #define CPU_RM7000      7000
 650 #define CPU_R8000       8000
 651 #define CPU_R10000      10000
 652 #define CPU_R12000      12000
 653 #define CPU_MIPS16      16
 654 #define CPU_MIPS32      32
 655 #define CPU_MIPS32R2    33
 656 #define CPU_MIPS5       5
 657 #define CPU_MIPS64      64
 658 #define CPU_MIPS64R2    65
 659 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 660
 661 /* Test for membership in an ISA including chip specific ISAs.  INSN
 662    is pointer to an element of the opcode table; ISA is the specified
 663    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 664    test, or zero if no CPU specific ISA test is desired.  */
 665
 666 #if 0
 667 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 668     (((insn)->membership & isa) != 0                                    \
 669      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 670      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 671      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 672      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 673      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 674      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 675      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 676          && ((insn)->membership & INSN_10000) != 0)                     \
 677      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 678      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 679      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 680      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 681      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 682      || 0)      /* Please keep this term for easier source merging.  */
 683 #else
 684 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 685     (1 != 0)
 686 #endif
 687
 688 /* This is a list of macro expanded instructions.
 689
 690    _I appended means immediate
 691    _A appended means address
 692    _AB appended means address with base register
 693    _D appended means 64 bit floating point constant
 694    _S appended means 32 bit floating point constant.  */
 695
 696 enum
 697 {
 698   M_ABS,
 699   M_ADD_I,
 700   M_ADDU_I,
 701   M_AND_I,
 702   M_BALIGN,
 703   M_BEQ,
 704   M_BEQ_I,
 705   M_BEQL_I,
 706   M_BGE,
 707   M_BGEL,
 708   M_BGE_I,
 709   M_BGEL_I,
 710   M_BGEU,
 711   M_BGEUL,
 712   M_BGEU_I,
 713   M_BGEUL_I,
 714   M_BGT,
 715   M_BGTL,
 716   M_BGT_I,
 717   M_BGTL_I,
 718   M_BGTU,
 719   M_BGTUL,
 720   M_BGTU_I,
 721   M_BGTUL_I,
 722   M_BLE,
 723   M_BLEL,
 724   M_BLE_I,
 725   M_BLEL_I,
 726   M_BLEU,
 727   M_BLEUL,
 728   M_BLEU_I,
 729   M_BLEUL_I,
 730   M_BLT,
 731   M_BLTL,
 732   M_BLT_I,
 733   M_BLTL_I,
 734   M_BLTU,
 735   M_BLTUL,
 736   M_BLTU_I,
 737   M_BLTUL_I,
 738   M_BNE,
 739   M_BNE_I,
 740   M_BNEL_I,
 741   M_CACHE_AB,
 742   M_DABS,
 743   M_DADD_I,
 744   M_DADDU_I,
 745   M_DDIV_3,
 746   M_DDIV_3I,
 747   M_DDIVU_3,
 748   M_DDIVU_3I,
 749   M_DEXT,
 750   M_DINS,
 751   M_DIV_3,
 752   M_DIV_3I,
 753   M_DIVU_3,
 754   M_DIVU_3I,
 755   M_DLA_AB,
 756   M_DLCA_AB,
 757   M_DLI,
 758   M_DMUL,
 759   M_DMUL_I,
 760   M_DMULO,
 761   M_DMULO_I,
 762   M_DMULOU,
 763   M_DMULOU_I,
 764   M_DREM_3,
 765   M_DREM_3I,
 766   M_DREMU_3,
 767   M_DREMU_3I,
 768   M_DSUB_I,
 769   M_DSUBU_I,
 770   M_DSUBU_I_2,
 771   M_J_A,
 772   M_JAL_1,
 773   M_JAL_2,
 774   M_JAL_A,
 775   M_L_DOB,
 776   M_L_DAB,
 777   M_LA_AB,
 778   M_LB_A,
 779   M_LB_AB,
 780   M_LBU_A,
 781   M_LBU_AB,
 782   M_LCA_AB,
 783   M_LD_A,
 784   M_LD_OB,
 785   M_LD_AB,
 786   M_LDC1_AB,
 787   M_LDC2_AB,
 788   M_LDC3_AB,
 789   M_LDL_AB,
 790   M_LDR_AB,
 791   M_LH_A,
 792   M_LH_AB,
 793   M_LHU_A,
 794   M_LHU_AB,
 795   M_LI,
 796   M_LI_D,
 797   M_LI_DD,
 798   M_LI_S,
 799   M_LI_SS,
 800   M_LL_AB,
 801   M_LLD_AB,
 802   M_LS_A,
 803   M_LW_A,
 804   M_LW_AB,
 805   M_LWC0_A,
 806   M_LWC0_AB,
 807   M_LWC1_A,
 808   M_LWC1_AB,
 809   M_LWC2_A,
 810   M_LWC2_AB,
 811   M_LWC3_A,
 812   M_LWC3_AB,
 813   M_LWL_A,
 814   M_LWL_AB,
 815   M_LWR_A,
 816   M_LWR_AB,
 817   M_LWU_AB,
 818   M_MOVE,
 819   M_MUL,
 820   M_MUL_I,
 821   M_MULO,
 822   M_MULO_I,
 823   M_MULOU,
 824   M_MULOU_I,
 825   M_NOR_I,
 826   M_OR_I,
 827   M_REM_3,
 828   M_REM_3I,
 829   M_REMU_3,
 830   M_REMU_3I,
 831   M_DROL,
 832   M_ROL,
 833   M_DROL_I,
 834   M_ROL_I,
 835   M_DROR,
 836   M_ROR,
 837   M_DROR_I,
 838   M_ROR_I,
 839   M_S_DA,
 840   M_S_DOB,
 841   M_S_DAB,
 842   M_S_S,
 843   M_SC_AB,
 844   M_SCD_AB,
 845   M_SD_A,
 846   M_SD_OB,
 847   M_SD_AB,
 848   M_SDC1_AB,
 849   M_SDC2_AB,
 850   M_SDC3_AB,
 851   M_SDL_AB,
 852   M_SDR_AB,
 853   M_SEQ,
 854   M_SEQ_I,
 855   M_SGE,
 856   M_SGE_I,
 857   M_SGEU,
 858   M_SGEU_I,
 859   M_SGT,
 860   M_SGT_I,
 861   M_SGTU,
 862   M_SGTU_I,
 863   M_SLE,
 864   M_SLE_I,
 865   M_SLEU,
 866   M_SLEU_I,
 867   M_SLT_I,
 868   M_SLTU_I,
 869   M_SNE,
 870   M_SNE_I,
 871   M_SB_A,
 872   M_SB_AB,
 873   M_SH_A,
 874   M_SH_AB,
 875   M_SW_A,
 876   M_SW_AB,
 877   M_SWC0_A,
 878   M_SWC0_AB,
 879   M_SWC1_A,
 880   M_SWC1_AB,
 881   M_SWC2_A,
 882   M_SWC2_AB,
 883   M_SWC3_A,
 884   M_SWC3_AB,
 885   M_SWL_A,
 886   M_SWL_AB,
 887   M_SWR_A,
 888   M_SWR_AB,
 889   M_SUB_I,
 890   M_SUBU_I,
 891   M_SUBU_I_2,
 892   M_TEQ_I,
 893   M_TGE_I,
 894   M_TGEU_I,
 895   M_TLT_I,
 896   M_TLTU_I,
 897   M_TNE_I,
 898   M_TRUNCWD,
 899   M_TRUNCWS,
 900   M_ULD,
 901   M_ULD_A,
 902   M_ULH,
 903   M_ULH_A,
 904   M_ULHU,
 905   M_ULHU_A,
 906   M_ULW,
 907   M_ULW_A,
 908   M_USH,
 909   M_USH_A,
 910   M_USW,
 911   M_USW_A,
 912   M_USD,
 913   M_USD_A,
 914   M_XOR_I,
 915   M_COP0,
 916   M_COP1,
 917   M_COP2,
 918   M_COP3,
 919   M_NUM_MACROS
 920 };
 921
 922
 923 /* The order of overloaded instructions matters.  Label arguments and
 924    register arguments look the same. Instructions that can have either
 925    for arguments must apear in the correct order in this table for the
 926    assembler to pick the right one. In other words, entries with
 927    immediate operands must apear after the same instruction with
 928    registers.
 929
 930    Many instructions are short hand for other instructions (i.e., The
 931    jal <register> instruction is short for jalr <register>).  */
 932
 933 extern const struct mips_opcode mips_builtin_opcodes[];
 934 extern const int bfd_mips_num_builtin_opcodes;
 935 extern struct mips_opcode *mips_opcodes;
 936 extern int bfd_mips_num_opcodes;
 937 #define NUMOPCODES bfd_mips_num_opcodes
 938
 939 \f
 940 /* The rest of this file adds definitions for the mips16 TinyRISC
 941    processor.  */
 942
 943 /* These are the bitmasks and shift counts used for the different
 944    fields in the instruction formats.  Other than OP, no masks are
 945    provided for the fixed portions of an instruction, since they are
 946    not needed.
 947
 948    The I format uses IMM11.
 949
 950    The RI format uses RX and IMM8.
 951
 952    The RR format uses RX, and RY.
 953
 954    The RRI format uses RX, RY, and IMM5.
 955
 956    The RRR format uses RX, RY, and RZ.
 957
 958    The RRI_A format uses RX, RY, and IMM4.
 959
 960    The SHIFT format uses RX, RY, and SHAMT.
 961
 962    The I8 format uses IMM8.
 963
 964    The I8_MOVR32 format uses RY and REGR32.
 965
 966    The IR_MOV32R format uses REG32R and MOV32Z.
 967
 968    The I64 format uses IMM8.
 969
 970    The RI64 format uses RY and IMM5.
 971    */
 972
 973 #define MIPS16OP_MASK_OP        0x1f
 974 #define MIPS16OP_SH_OP          11
 975 #define MIPS16OP_MASK_IMM11     0x7ff
 976 #define MIPS16OP_SH_IMM11       0
 977 #define MIPS16OP_MASK_RX        0x7
 978 #define MIPS16OP_SH_RX          8
 979 #define MIPS16OP_MASK_IMM8      0xff
 980 #define MIPS16OP_SH_IMM8        0
 981 #define MIPS16OP_MASK_RY        0x7
 982 #define MIPS16OP_SH_RY          5
 983 #define MIPS16OP_MASK_IMM5      0x1f
 984 #define MIPS16OP_SH_IMM5        0
 985 #define MIPS16OP_MASK_RZ        0x7
 986 #define MIPS16OP_SH_RZ          2
 987 #define MIPS16OP_MASK_IMM4      0xf
 988 #define MIPS16OP_SH_IMM4        0
 989 #define MIPS16OP_MASK_REGR32    0x1f
 990 #define MIPS16OP_SH_REGR32      0
 991 #define MIPS16OP_MASK_REG32R    0x1f
 992 #define MIPS16OP_SH_REG32R      3
 993 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 994 #define MIPS16OP_MASK_MOVE32Z   0x7
 995 #define MIPS16OP_SH_MOVE32Z     0
 996 #define MIPS16OP_MASK_IMM6      0x3f
 997 #define MIPS16OP_SH_IMM6        5
 998
 999 /* These are the characters which may appears in the args field of an
1000    instruction.  They appear in the order in which the fields appear
1001    when the instruction is used.  Commas and parentheses in the args
1002    string are ignored when assembling, and written into the output
1003    when disassembling.
1004
1005    "y" 3 bit register (MIPS16OP_*_RY)
1006    "x" 3 bit register (MIPS16OP_*_RX)
1007    "z" 3 bit register (MIPS16OP_*_RZ)
1008    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1009    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1010    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1011    "0" zero register ($0)
1012    "S" stack pointer ($sp or $29)
1013    "P" program counter
1014    "R" return address register ($ra or $31)
1015    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1016    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1017    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1018    "a" 26 bit jump address
1019    "e" 11 bit extension value
1020    "l" register list for entry instruction
1021    "L" register list for exit instruction
1022
1023    The remaining codes may be extended.  Except as otherwise noted,
1024    the full extended operand is a 16 bit signed value.
1025    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1026    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1027    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1028    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1029    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1030    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1031    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1032    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1033    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1034    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1035    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1036    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1037    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1038    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1039    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1040    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1041    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1042    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1043    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1044    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1045    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1046    */
1047
1048 /* Save/restore encoding for the args field when all 4 registers are
1049    either saved as arguments or saved/restored as statics.  */
1050 #define MIPS16_ALL_ARGS    0xe
1051 #define MIPS16_ALL_STATICS 0xb
1052
1053 /* For the mips16, we use the same opcode table format and a few of
1054    the same flags.  However, most of the flags are different.  */
1055
1056 /* Modifies the register in MIPS16OP_*_RX.  */
1057 #define MIPS16_INSN_WRITE_X                 0x00000001
1058 /* Modifies the register in MIPS16OP_*_RY.  */
1059 #define MIPS16_INSN_WRITE_Y                 0x00000002
1060 /* Modifies the register in MIPS16OP_*_RZ.  */
1061 #define MIPS16_INSN_WRITE_Z                 0x00000004
1062 /* Modifies the T ($24) register.  */
1063 #define MIPS16_INSN_WRITE_T                 0x00000008
1064 /* Modifies the SP ($29) register.  */
1065 #define MIPS16_INSN_WRITE_SP                0x00000010
1066 /* Modifies the RA ($31) register.  */
1067 #define MIPS16_INSN_WRITE_31                0x00000020
1068 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1069 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1070 /* Reads the register in MIPS16OP_*_RX.  */
1071 #define MIPS16_INSN_READ_X                  0x00000080
1072 /* Reads the register in MIPS16OP_*_RY.  */
1073 #define MIPS16_INSN_READ_Y                  0x00000100
1074 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1075 #define MIPS16_INSN_READ_Z                  0x00000200
1076 /* Reads the T ($24) register.  */
1077 #define MIPS16_INSN_READ_T                  0x00000400
1078 /* Reads the SP ($29) register.  */
1079 #define MIPS16_INSN_READ_SP                 0x00000800
1080 /* Reads the RA ($31) register.  */
1081 #define MIPS16_INSN_READ_31                 0x00001000
1082 /* Reads the program counter.  */
1083 #define MIPS16_INSN_READ_PC                 0x00002000
1084 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1085 #define MIPS16_INSN_READ_GPR_X              0x00004000
1086 /* Is a branch insn. */
1087 #define MIPS16_INSN_BRANCH                  0x00010000
1088
1089 /* The following flags have the same value for the mips16 opcode
1090    table:
1091    INSN_UNCOND_BRANCH_DELAY
1092    INSN_COND_BRANCH_DELAY
1093    INSN_COND_BRANCH_LIKELY (never used)
1094    INSN_READ_HI
1095    INSN_READ_LO
1096    INSN_WRITE_HI
1097    INSN_WRITE_LO
1098    INSN_TRAP
1099    INSN_ISA3
1100    */
1101
1102 extern const struct mips_opcode mips16_opcodes[];
1103 extern const int bfd_mips16_num_opcodes;
1104
1105 /* Short hand so the lines aren't too long.  */
1106
1107 #define LDD     INSN_LOAD_MEMORY_DELAY
1108 #define LCD     INSN_LOAD_COPROC_DELAY
1109 #define UBD     INSN_UNCOND_BRANCH_DELAY
1110 #define CBD     INSN_COND_BRANCH_DELAY
1111 #define COD     INSN_COPROC_MOVE_DELAY
1112 #define CLD     INSN_COPROC_MEMORY_DELAY
1113 #define CBL     INSN_COND_BRANCH_LIKELY
1114 #define TRAP    INSN_TRAP
1115 #define SM      INSN_STORE_MEMORY
1116
1117 #define WR_d    INSN_WRITE_GPR_D
1118 #define WR_t    INSN_WRITE_GPR_T
1119 #define WR_31   INSN_WRITE_GPR_31
1120 #define WR_D    INSN_WRITE_FPR_D
1121 #define WR_T    INSN_WRITE_FPR_T
1122 #define WR_S    INSN_WRITE_FPR_S
1123 #define RD_s    INSN_READ_GPR_S
1124 #define RD_b    INSN_READ_GPR_S
1125 #define RD_t    INSN_READ_GPR_T
1126 #define RD_S    INSN_READ_FPR_S
1127 #define RD_T    INSN_READ_FPR_T
1128 #define RD_R    INSN_READ_FPR_R
1129 #define WR_CC   INSN_WRITE_COND_CODE
1130 #define RD_CC   INSN_READ_COND_CODE
1131 #define RD_C0   INSN_COP
1132 #define RD_C1   INSN_COP
1133 #define RD_C2   INSN_COP
1134 #define RD_C3   INSN_COP
1135 #define WR_C0   INSN_COP
1136 #define WR_C1   INSN_COP
1137 #define WR_C2   INSN_COP
1138 #define WR_C3   INSN_COP
1139
1140 #define WR_HI   INSN_WRITE_HI
1141 #define RD_HI   INSN_READ_HI
1142 #define MOD_HI  WR_HI|RD_HI
1143
1144 #define WR_LO   INSN_WRITE_LO
1145 #define RD_LO   INSN_READ_LO
1146 #define MOD_LO  WR_LO|RD_LO
1147
1148 #define WR_HILO WR_HI|WR_LO
1149 #define RD_HILO RD_HI|RD_LO
1150 #define MOD_HILO WR_HILO|RD_HILO
1151
1152 #define IS_M    INSN_MULT
1153
1154 #define WR_MACC INSN2_WRITE_MDMX_ACC
1155 #define RD_MACC INSN2_READ_MDMX_ACC
1156
1157 #define I1      INSN_ISA1
1158 #define I2      INSN_ISA2
1159 #define I3      INSN_ISA3
1160 #define I4      INSN_ISA4
1161 #define I5      INSN_ISA5
1162 #define I32     INSN_ISA32
1163 #define I64     INSN_ISA64
1164 #define I33     INSN_ISA32R2
1165 #define I65     INSN_ISA64R2
1166 #define I32R6   INSN_ISA32R6
1167 #define I64R6   INSN_ISA64R6
1168
1169 /* MIPS64 MIPS-3D ASE support.  */
1170 #define I16     INSN_MIPS16
1171
1172 /* MIPS32 SmartMIPS ASE support.  */
1173 #define SMT     INSN_SMARTMIPS
1174
1175 /* MIPS64 MIPS-3D ASE support.  */
1176 #define M3D     INSN_MIPS3D
1177
1178 /* MIPS64 MDMX ASE support.  */
1179 #define MX      INSN_MDMX
1180
1181 #define IL2E    (INSN_LOONGSON_2E)
1182 #define IL2F    (INSN_LOONGSON_2F)
1183
1184 #define P3      INSN_4650
1185 #define L1      INSN_4010
1186 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1187 #define T3      INSN_3900
1188 #define M1      INSN_10000
1189 #define SB1     INSN_SB1
1190 #define N411    INSN_4111
1191 #define N412    INSN_4120
1192 #define N5      (INSN_5400 | INSN_5500)
1193 #define N54     INSN_5400
1194 #define N55     INSN_5500
1195
1196 #define G1      (T3             \
1197                  )
1198
1199 #define G2      (T3             \
1200                  )
1201
1202 #define G3      (I4             \
1203                  )
1204
1205 /* MIPS DSP ASE support.
1206    NOTE:
1207    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1208    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1209    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1210    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1211    (RD_HILO) attributes, such that HILO dependencies are maintained
1212    conservatively.
1213
1214    2. For some mul. instructions that use integer registers as destinations
1215    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1216
1217    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1218    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1219    certain fields of the DSP control register.  For simplicity, we decide not
1220    to track dependencies of these fields.
1221    However, "bposge32" is a branch instruction that depends on the "pos"
1222    field.  In order to make sure that GAS does not reorder DSP instructions
1223    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1224    attribute to those instructions that write the "pos" field.  */
1225
1226 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1227 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1228 #define MOD_a   WR_a|RD_a
1229 #define DSP_VOLA        INSN_TRAP
1230 #define D32     INSN_DSP
1231 #define D33     INSN_DSPR2
1232 #define D64     INSN_DSP64
1233
1234 /* MIPS MT ASE support.  */
1235 #define MT32    INSN_MT
1236
1237 /* MSA */
1238 #define MSA     INSN_MSA
1239 #define MSA64   INSN_MSA64
1240 #define WR_VD   INSN_WRITE_FPR_D    /* Reuse INSN_WRITE_FPR_D */
1241 #define RD_VD   WR_VD               /* Reuse WR_VD */
1242 #define RD_VT   INSN_READ_FPR_T     /* Reuse INSN_READ_FPR_T */
1243 #define RD_VS   INSN_READ_FPR_S     /* Reuse INSN_READ_FPR_S */
1244 #define RD_d    INSN2_READ_GPR_D    /* Reuse INSN2_READ_GPR_D */
1245
1246 #define RD_rd6  0
1247
1248 /* The order of overloaded instructions matters.  Label arguments and
1249    register arguments look the same. Instructions that can have either
1250    for arguments must apear in the correct order in this table for the
1251    assembler to pick the right one. In other words, entries with
1252    immediate operands must apear after the same instruction with
1253    registers.
1254
1255    Because of the lookup algorithm used, entries with the same opcode
1256    name must be contiguous.
1257
1258    Many instructions are short hand for other instructions (i.e., The
1259    jal <register> instruction is short for jalr <register>).  */
1260
1261 const struct mips_opcode mips_builtin_opcodes[] =
1262 {
1263 /* These instructions appear first so that the disassembler will find
1264    them first.  The assemblers uses a hash table based on the
1265    instruction name anyhow.  */
1266 /* name,    args,       match,      mask,       pinfo,                  membership */
1267 {"lwpc",    "s,+o2",    0xec080000, 0xfc180000, WR_d,                 0, I32R6},
1268 {"lwupc",   "s,+o2",    0xec100000, 0xfc180000, WR_d,                 0, I64R6},
1269 {"ldpc",    "s,+o1",    0xec180000, 0xfc1c0000, WR_d,                 0, I64R6},
1270 {"addiupc", "s,+o2",    0xec000000, 0xfc180000, WR_d,                 0, I32R6},
1271 {"auipc",   "s,u",      0xec1e0000, 0xfc1f0000, WR_d,                 0, I32R6},
1272 {"aluipc",  "s,u",      0xec1f0000, 0xfc1f0000, WR_d,                 0, I32R6},
1273 {"daui",    "s,t,u",    0x74000000, 0xfc000000, RD_s|WR_t,            0, I64R6},
1274 {"dahi",    "s,u",      0x04060000, 0xfc1f0000, RD_s,                 0, I64R6},
1275 {"dati",    "s,u",      0x041e0000, 0xfc1f0000, RD_s,                 0, I64R6},
1276 {"lsa",     "d,s,t",    0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1277 {"dlsa",    "d,s,t",    0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,       0, I64R6},
1278 {"clz",     "U,s",      0x00000050, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1279 {"clo",     "U,s",      0x00000051, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1280 {"dclz",    "U,s",      0x00000052, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1281 {"dclo",    "U,s",      0x00000053, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1282 {"sdbbp",   "B",        0x0000000e, 0xfc00003f, TRAP,                 0, I32R6},
1283 {"mul",     "d,s,t",    0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1284 {"muh",     "d,s,t",    0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1285 {"mulu",    "d,s,t",    0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1286 {"muhu",    "d,s,t",    0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1287 {"div",     "d,s,t",    0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1288 {"mod",     "d,s,t",    0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1289 {"divu",    "d,s,t",    0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1290 {"modu",    "d,s,t",    0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1291 {"dmul",    "d,s,t",    0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1292 {"dmuh",    "d,s,t",    0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1293 {"dmulu",   "d,s,t",    0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1294 {"dmuhu",   "d,s,t",    0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1295 {"ddiv",    "d,s,t",    0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1296 {"dmod",    "d,s,t",    0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1297 {"ddivu",   "d,s,t",    0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1298 {"dmodu",   "d,s,t",    0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1299 {"ll",      "t,+o(b)",  0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1300 {"sc",      "t,+o(b)",  0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1301 {"lld",     "t,+o(b)",  0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1302 {"scd",     "t,+o(b)",  0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1303 {"pref",    "h,+o(b)",  0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},
1304 {"cache",   "k,+o(b)",  0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},
1305 {"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1306 {"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1307 {"maddf.s", "D,S,T",    0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1308 {"maddf.d", "D,S,T",    0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1309 {"msubf.s", "D,S,T",    0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1310 {"msubf.d", "D,S,T",    0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1311 {"max.s",   "D,S,T",    0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1312 {"max.d",   "D,S,T",    0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1313 {"maxa.s",  "D,S,T",    0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1314 {"maxa.d",  "D,S,T",    0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1315 {"rint.s",  "D,S",      0x4600001a, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1316 {"rint.d",  "D,S",      0x4620001a, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1317 {"class.s", "D,S",      0x4600001b, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1318 {"class.d", "D,S",      0x4620001b, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1319 {"min.s",   "D,S,T",    0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1320 {"min.d",   "D,S,T",    0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1321 {"mina.s",  "D,S,T",    0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1322 {"mina.d",  "D,S,T",    0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1323 {"sel.s",   "D,S,T",    0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1324 {"sel.d",   "D,S,T",    0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1325 {"seleqz.s", "D,S,T",   0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1326 {"seleqz.d", "D,S,T",   0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1327 {"selnez.s", "D,S,T",   0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1328 {"selnez.d", "D,S,T",   0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1329 {"align",   "d,v,t",    0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1330 {"dalign",  "d,v,t",    0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t,       0, I64R6},
1331 {"bitswap", "d,w",      0x7c000020, 0xffe007ff, WR_d|RD_t,            0, I32R6},
1332 {"dbitswap","d,w",      0x7c000024, 0xffe007ff, WR_d|RD_t,            0, I64R6},
1333 {"balc",    "+p",       0xe8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1334 {"bc",      "+p",       0xc8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1335 {"jic",     "t,o",      0xd8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1336 {"beqzc",   "s,+p",     0xd8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1337 {"jialc",   "t,o",      0xf8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1338 {"bnezc",   "s,+p",     0xf8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1339 {"beqzalc", "s,t,p",    0x20000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1340 {"bovc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1341 {"beqc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1342 {"bnezalc", "s,t,p",    0x60000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1343 {"bnvc",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1344 {"bnec",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1345 {"blezc",   "s,t,p",    0x58000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1346 {"bgezc",   "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1347 {"bgec",    "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1348 {"bgtzc",   "s,t,p",    0x5c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1349 {"bltzc",   "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1350 {"bltc",    "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1351 {"blezalc", "s,t,p",    0x18000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1352 {"bgezalc", "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1353 {"bgeuc",   "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1354 {"bgtzalc", "s,t,p",    0x1c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1355 {"bltzalc", "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1356 {"bltuc",   "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1357 {"nal",     "p",        0x04100000, 0xffff0000, WR_31,                0, I32R6},
1358 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,            0, I32R6},
1359 {"bc1eqz",  "T,p",      0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1360 {"bc1nez",  "T,p",      0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1361 {"bc2eqz",  "E,p",      0x49200000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1362 {"bc2nez",  "E,p",      0x49a00000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1363 {"cmp.af.s",   "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1364 {"cmp.un.s",   "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1365 {"cmp.eq.s",   "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1366 {"cmp.ueq.s",  "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1367 {"cmp.lt.s",   "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1368 {"cmp.ult.s",  "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1369 {"cmp.le.s",   "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1370 {"cmp.ule.s",  "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1371 {"cmp.saf.s",  "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1372 {"cmp.sun.s",  "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1373 {"cmp.seq.s",  "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1374 {"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1375 {"cmp.slt.s",  "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1376 {"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1377 {"cmp.sle.s",  "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1378 {"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1379 {"cmp.or.s",   "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1380 {"cmp.une.s",  "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1381 {"cmp.ne.s",   "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1382 {"cmp.sor.s",  "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1383 {"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1384 {"cmp.sne.s",  "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1385 {"cmp.af.d",   "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1386 {"cmp.un.d",   "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1387 {"cmp.eq.d",   "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1388 {"cmp.ueq.d",  "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1389 {"cmp.lt.d",   "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1390 {"cmp.ult.d",  "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1391 {"cmp.le.d",   "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1392 {"cmp.ule.d",  "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1393 {"cmp.saf.d",  "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1394 {"cmp.sun.d",  "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1395 {"cmp.seq.d",  "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1396 {"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1397 {"cmp.slt.d",  "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1398 {"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1399 {"cmp.sle.d",  "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1400 {"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1401 {"cmp.or.d",   "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1402 {"cmp.une.d",  "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1403 {"cmp.ne.d",   "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1404 {"cmp.sor.d",  "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1405 {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1406 {"cmp.sne.d",  "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1407
1408 /* MSA */
1409 {"sll.b",   "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1410 {"sll.h",   "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1411 {"sll.w",   "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1412 {"sll.d",   "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1413 {"slli.b",  "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1414 {"slli.h",  "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1415 {"slli.w",  "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1416 {"slli.d",  "+d,+e,'",  0x78000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1417 {"sra.b",   "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1418 {"sra.h",   "+d,+e,+f", 0x78a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1419 {"sra.w",   "+d,+e,+f", 0x78c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1420 {"sra.d",   "+d,+e,+f", 0x78e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1421 {"srai.b",  "+d,+e,+7", 0x78f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1422 {"srai.h",  "+d,+e,+8", 0x78e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1423 {"srai.w",  "+d,+e,+9", 0x78c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1424 {"srai.d",  "+d,+e,'",  0x78800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1425 {"srl.b",   "+d,+e,+f", 0x7900000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1426 {"srl.h",   "+d,+e,+f", 0x7920000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1427 {"srl.w",   "+d,+e,+f", 0x7940000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1428 {"srl.d",   "+d,+e,+f", 0x7960000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1429 {"srli.b",  "+d,+e,+7", 0x79700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1430 {"srli.h",  "+d,+e,+8", 0x79600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1431 {"srli.w",  "+d,+e,+9", 0x79400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1432 {"srli.d",  "+d,+e,'",  0x79000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1433 {"bclr.b",  "+d,+e,+f", 0x7980000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1434 {"bclr.h",  "+d,+e,+f", 0x79a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1435 {"bclr.w",  "+d,+e,+f", 0x79c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1436 {"bclr.d",  "+d,+e,+f", 0x79e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1437 {"bclri.b", "+d,+e,+7", 0x79f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1438 {"bclri.h", "+d,+e,+8", 0x79e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1439 {"bclri.w", "+d,+e,+9", 0x79c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1440 {"bclri.d", "+d,+e,'",  0x79800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1441 {"bset.b",  "+d,+e,+f", 0x7a00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1442 {"bset.h",  "+d,+e,+f", 0x7a20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1443 {"bset.w",  "+d,+e,+f", 0x7a40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1444 {"bset.d",  "+d,+e,+f", 0x7a60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1445 {"bseti.b", "+d,+e,+7", 0x7a700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1446 {"bseti.h", "+d,+e,+8", 0x7a600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1447 {"bseti.w", "+d,+e,+9", 0x7a400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1448 {"bseti.d", "+d,+e,'",  0x7a000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1449 {"bneg.b",  "+d,+e,+f", 0x7a80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1450 {"bneg.h",  "+d,+e,+f", 0x7aa0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1451 {"bneg.w",  "+d,+e,+f", 0x7ac0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1452 {"bneg.d",  "+d,+e,+f", 0x7ae0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1453 {"bnegi.b", "+d,+e,+7", 0x7af00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1454 {"bnegi.h", "+d,+e,+8", 0x7ae00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1455 {"bnegi.w", "+d,+e,+9", 0x7ac00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1456 {"bnegi.d", "+d,+e,'",  0x7a800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1457 {"binsl.b", "+d,+e,+f", 0x7b00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1458 {"binsl.h", "+d,+e,+f", 0x7b20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1459 {"binsl.w", "+d,+e,+f", 0x7b40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1460 {"binsl.d", "+d,+e,+f", 0x7b60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1461 {"binsli.b", "+d,+e,+7", 0x7b700009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1462 {"binsli.h", "+d,+e,+8", 0x7b600009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1463 {"binsli.w", "+d,+e,+9", 0x7b400009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1464 {"binsli.d", "+d,+e,'",  0x7b000009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1465 {"binsr.b", "+d,+e,+f", 0x7b80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1466 {"binsr.h", "+d,+e,+f", 0x7ba0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1467 {"binsr.w", "+d,+e,+f", 0x7bc0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1468 {"binsr.d", "+d,+e,+f", 0x7be0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1469 {"binsri.b", "+d,+e,+7", 0x7bf00009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1470 {"binsri.h", "+d,+e,+8", 0x7be00009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1471 {"binsri.w", "+d,+e,+9", 0x7bc00009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1472 {"binsri.d", "+d,+e,'",  0x7b800009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1473 {"addv.b",  "+d,+e,+f", 0x7800000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1474 {"addv.h",  "+d,+e,+f", 0x7820000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1475 {"addv.w",  "+d,+e,+f", 0x7840000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1476 {"addv.d",  "+d,+e,+f", 0x7860000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1477 {"addvi.b", "+d,+e,k",  0x78000006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1478 {"addvi.h", "+d,+e,k",  0x78200006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1479 {"addvi.w", "+d,+e,k",  0x78400006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1480 {"addvi.d", "+d,+e,k",  0x78600006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1481 {"subv.b",  "+d,+e,+f", 0x7880000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1482 {"subv.h",  "+d,+e,+f", 0x78a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1483 {"subv.w",  "+d,+e,+f", 0x78c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1484 {"subv.d",  "+d,+e,+f", 0x78e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1485 {"subvi.b", "+d,+e,k",  0x78800006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1486 {"subvi.h", "+d,+e,k",  0x78a00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1487 {"subvi.w", "+d,+e,k",  0x78c00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1488 {"subvi.d", "+d,+e,k",  0x78e00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1489 {"max_s.b", "+d,+e,+f", 0x7900000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1490 {"max_s.h", "+d,+e,+f", 0x7920000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1491 {"max_s.w", "+d,+e,+f", 0x7940000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1492 {"max_s.d", "+d,+e,+f", 0x7960000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1493 {"maxi_s.b", "+d,+e,+5", 0x79000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1494 {"maxi_s.h", "+d,+e,+5", 0x79200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1495 {"maxi_s.w", "+d,+e,+5", 0x79400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1496 {"maxi_s.d", "+d,+e,+5", 0x79600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1497 {"max_u.b", "+d,+e,+f", 0x7980000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1498 {"max_u.h", "+d,+e,+f", 0x79a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1499 {"max_u.w", "+d,+e,+f", 0x79c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1500 {"max_u.d", "+d,+e,+f", 0x79e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1501 {"maxi_u.b", "+d,+e,k",  0x79800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1502 {"maxi_u.h", "+d,+e,k",  0x79a00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1503 {"maxi_u.w", "+d,+e,k",  0x79c00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1504 {"maxi_u.d", "+d,+e,k",  0x79e00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1505 {"min_s.b", "+d,+e,+f", 0x7a00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1506 {"min_s.h", "+d,+e,+f", 0x7a20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1507 {"min_s.w", "+d,+e,+f", 0x7a40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1508 {"min_s.d", "+d,+e,+f", 0x7a60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1509 {"mini_s.b", "+d,+e,+5", 0x7a000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1510 {"mini_s.h", "+d,+e,+5", 0x7a200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1511 {"mini_s.w", "+d,+e,+5", 0x7a400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1512 {"mini_s.d", "+d,+e,+5", 0x7a600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1513 {"min_u.b", "+d,+e,+f", 0x7a80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1514 {"min_u.h", "+d,+e,+f", 0x7aa0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1515 {"min_u.w", "+d,+e,+f", 0x7ac0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1516 {"min_u.d", "+d,+e,+f", 0x7ae0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1517 {"mini_u.b", "+d,+e,k",  0x7a800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1518 {"mini_u.h", "+d,+e,k",  0x7aa00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1519 {"mini_u.w", "+d,+e,k",  0x7ac00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1520 {"mini_u.d", "+d,+e,k",  0x7ae00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1521 {"max_a.b", "+d,+e,+f", 0x7b00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1522 {"max_a.h", "+d,+e,+f", 0x7b20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1523 {"max_a.w", "+d,+e,+f", 0x7b40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1524 {"max_a.d", "+d,+e,+f", 0x7b60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1525 {"min_a.b", "+d,+e,+f", 0x7b80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1526 {"min_a.h", "+d,+e,+f", 0x7ba0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1527 {"min_a.w", "+d,+e,+f", 0x7bc0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1528 {"min_a.d", "+d,+e,+f", 0x7be0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1529 {"ceq.b",   "+d,+e,+f", 0x7800000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1530 {"ceq.h",   "+d,+e,+f", 0x7820000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1531 {"ceq.w",   "+d,+e,+f", 0x7840000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1532 {"ceq.d",   "+d,+e,+f", 0x7860000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1533 {"ceqi.b",  "+d,+e,+5", 0x78000007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1534 {"ceqi.h",  "+d,+e,+5", 0x78200007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1535 {"ceqi.w",  "+d,+e,+5", 0x78400007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1536 {"ceqi.d",  "+d,+e,+5", 0x78600007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1537 {"clt_s.b", "+d,+e,+f", 0x7900000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1538 {"clt_s.h", "+d,+e,+f", 0x7920000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1539 {"clt_s.w", "+d,+e,+f", 0x7940000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1540 {"clt_s.d", "+d,+e,+f", 0x7960000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1541 {"clti_s.b", "+d,+e,+5", 0x79000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1542 {"clti_s.h", "+d,+e,+5", 0x79200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1543 {"clti_s.w", "+d,+e,+5", 0x79400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1544 {"clti_s.d", "+d,+e,+5", 0x79600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1545 {"clt_u.b", "+d,+e,+f", 0x7980000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1546 {"clt_u.h", "+d,+e,+f", 0x79a0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1547 {"clt_u.w", "+d,+e,+f", 0x79c0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1548 {"clt_u.d", "+d,+e,+f", 0x79e0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1549 {"clti_u.b", "+d,+e,k",  0x79800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1550 {"clti_u.h", "+d,+e,k",  0x79a00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1551 {"clti_u.w", "+d,+e,k",  0x79c00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1552 {"clti_u.d", "+d,+e,k",  0x79e00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1553 {"cle_s.b", "+d,+e,+f", 0x7a00000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1554 {"cle_s.h", "+d,+e,+f", 0x7a20000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1555 {"cle_s.w", "+d,+e,+f", 0x7a40000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1556 {"cle_s.d", "+d,+e,+f", 0x7a60000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1557 {"clei_s.b", "+d,+e,+5", 0x7a000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1558 {"clei_s.h", "+d,+e,+5", 0x7a200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1559 {"clei_s.w", "+d,+e,+5", 0x7a400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1560 {"clei_s.d", "+d,+e,+5", 0x7a600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1561 {"cle_u.b", "+d,+e,+f", 0x7a80000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1562 {"cle_u.h", "+d,+e,+f", 0x7aa0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1563 {"cle_u.w", "+d,+e,+f", 0x7ac0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1564 {"cle_u.d", "+d,+e,+f", 0x7ae0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1565 {"clei_u.b", "+d,+e,k",  0x7a800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1566 {"clei_u.h", "+d,+e,k",  0x7aa00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1567 {"clei_u.w", "+d,+e,k",  0x7ac00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1568 {"clei_u.d", "+d,+e,k",  0x7ae00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1569 {"ld.b",    "+d,+^(d)", 0x78000020, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1570 {"ld.h",    "+d,+#(d)", 0x78000021, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1571 {"ld.w",    "+d,+$(d)", 0x78000022, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1572 {"ld.d",    "+d,+%(d)", 0x78000023, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1573 {"st.b",    "+d,+^(d)", 0x78000024, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1574 {"st.h",    "+d,+#(d)", 0x78000025, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1575 {"st.w",    "+d,+$(d)", 0x78000026, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1576 {"st.d",    "+d,+%(d)", 0x78000027, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1577 {"sat_s.b", "+d,+e,+7", 0x7870000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1578 {"sat_s.h", "+d,+e,+8", 0x7860000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1579 {"sat_s.w", "+d,+e,+9", 0x7840000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1580 {"sat_s.d", "+d,+e,'",  0x7800000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1581 {"sat_u.b", "+d,+e,+7", 0x78f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1582 {"sat_u.h", "+d,+e,+8", 0x78e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1583 {"sat_u.w", "+d,+e,+9", 0x78c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1584 {"sat_u.d", "+d,+e,'",  0x7880000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1585 {"add_a.b", "+d,+e,+f", 0x78000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1586 {"add_a.h", "+d,+e,+f", 0x78200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1587 {"add_a.w", "+d,+e,+f", 0x78400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1588 {"add_a.d", "+d,+e,+f", 0x78600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1589 {"adds_a.b", "+d,+e,+f", 0x78800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1590 {"adds_a.h", "+d,+e,+f", 0x78a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1591 {"adds_a.w", "+d,+e,+f", 0x78c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1592 {"adds_a.d", "+d,+e,+f", 0x78e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1593 {"adds_s.b", "+d,+e,+f", 0x79000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1594 {"adds_s.h", "+d,+e,+f", 0x79200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1595 {"adds_s.w", "+d,+e,+f", 0x79400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1596 {"adds_s.d", "+d,+e,+f", 0x79600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1597 {"adds_u.b", "+d,+e,+f", 0x79800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1598 {"adds_u.h", "+d,+e,+f", 0x79a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1599 {"adds_u.w", "+d,+e,+f", 0x79c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1600 {"adds_u.d", "+d,+e,+f", 0x79e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1601 {"ave_s.b", "+d,+e,+f", 0x7a000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1602 {"ave_s.h", "+d,+e,+f", 0x7a200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1603 {"ave_s.w", "+d,+e,+f", 0x7a400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1604 {"ave_s.d", "+d,+e,+f", 0x7a600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1605 {"ave_u.b", "+d,+e,+f", 0x7a800010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1606 {"ave_u.h", "+d,+e,+f", 0x7aa00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1607 {"ave_u.w", "+d,+e,+f", 0x7ac00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1608 {"ave_u.d", "+d,+e,+f", 0x7ae00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1609 {"aver_s.b", "+d,+e,+f", 0x7b000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1610 {"aver_s.h", "+d,+e,+f", 0x7b200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1611 {"aver_s.w", "+d,+e,+f", 0x7b400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1612 {"aver_s.d", "+d,+e,+f", 0x7b600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1613 {"aver_u.b", "+d,+e,+f", 0x7b800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1614 {"aver_u.h", "+d,+e,+f", 0x7ba00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1615 {"aver_u.w", "+d,+e,+f", 0x7bc00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1616 {"aver_u.d", "+d,+e,+f", 0x7be00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1617 {"subs_s.b", "+d,+e,+f", 0x78000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1618 {"subs_s.h", "+d,+e,+f", 0x78200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1619 {"subs_s.w", "+d,+e,+f", 0x78400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1620 {"subs_s.d", "+d,+e,+f", 0x78600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1621 {"subs_u.b", "+d,+e,+f", 0x78800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1622 {"subs_u.h", "+d,+e,+f", 0x78a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1623 {"subs_u.w", "+d,+e,+f", 0x78c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1624 {"subs_u.d", "+d,+e,+f", 0x78e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1625 {"subsus_u.b", "+d,+e,+f", 0x79000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1626 {"subsus_u.h", "+d,+e,+f", 0x79200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1627 {"subsus_u.w", "+d,+e,+f", 0x79400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1628 {"subsus_u.d", "+d,+e,+f", 0x79600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1629 {"subsuu_s.b", "+d,+e,+f", 0x79800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1630 {"subsuu_s.h", "+d,+e,+f", 0x79a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1631 {"subsuu_s.w", "+d,+e,+f", 0x79c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1632 {"subsuu_s.d", "+d,+e,+f", 0x79e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1633 {"asub_s.b", "+d,+e,+f", 0x7a000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1634 {"asub_s.h", "+d,+e,+f", 0x7a200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1635 {"asub_s.w", "+d,+e,+f", 0x7a400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1636 {"asub_s.d", "+d,+e,+f", 0x7a600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1637 {"asub_u.b", "+d,+e,+f", 0x7a800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1638 {"asub_u.h", "+d,+e,+f", 0x7aa00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1639 {"asub_u.w", "+d,+e,+f", 0x7ac00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1640 {"asub_u.d", "+d,+e,+f", 0x7ae00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1641 {"mulv.b",  "+d,+e,+f", 0x78000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1642 {"mulv.h",  "+d,+e,+f", 0x78200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1643 {"mulv.w",  "+d,+e,+f", 0x78400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1644 {"mulv.d",  "+d,+e,+f", 0x78600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1645 {"maddv.b", "+d,+e,+f", 0x78800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1646 {"maddv.h", "+d,+e,+f", 0x78a00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1647 {"maddv.w", "+d,+e,+f", 0x78c00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1648 {"maddv.d", "+d,+e,+f", 0x78e00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1649 {"msubv.b", "+d,+e,+f", 0x79000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1650 {"msubv.h", "+d,+e,+f", 0x79200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1651 {"msubv.w", "+d,+e,+f", 0x79400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1652 {"msubv.d", "+d,+e,+f", 0x79600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1653 {"div_s.b", "+d,+e,+f", 0x7a000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1654 {"div_s.h", "+d,+e,+f", 0x7a200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1655 {"div_s.w", "+d,+e,+f", 0x7a400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1656 {"div_s.d", "+d,+e,+f", 0x7a600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1657 {"div_u.b", "+d,+e,+f", 0x7a800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1658 {"div_u.h", "+d,+e,+f", 0x7aa00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1659 {"div_u.w", "+d,+e,+f", 0x7ac00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1660 {"div_u.d", "+d,+e,+f", 0x7ae00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1661 {"mod_s.b", "+d,+e,+f", 0x7b000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1662 {"mod_s.h", "+d,+e,+f", 0x7b200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1663 {"mod_s.w", "+d,+e,+f", 0x7b400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1664 {"mod_s.d", "+d,+e,+f", 0x7b600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1665 {"mod_u.b", "+d,+e,+f", 0x7b800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1666 {"mod_u.h", "+d,+e,+f", 0x7ba00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1667 {"mod_u.w", "+d,+e,+f", 0x7bc00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1668 {"mod_u.d", "+d,+e,+f", 0x7be00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1669 {"dotp_s.h", "+d,+e,+f", 0x78200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1670 {"dotp_s.w", "+d,+e,+f", 0x78400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1671 {"dotp_s.d", "+d,+e,+f", 0x78600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1672 {"dotp_u.h", "+d,+e,+f", 0x78a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1673 {"dotp_u.w", "+d,+e,+f", 0x78c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1674 {"dotp_u.d", "+d,+e,+f", 0x78e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1675 {"dpadd_s.h", "+d,+e,+f", 0x79200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1676 {"dpadd_s.w", "+d,+e,+f", 0x79400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1677 {"dpadd_s.d", "+d,+e,+f", 0x79600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1678 {"dpadd_u.h", "+d,+e,+f", 0x79a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1679 {"dpadd_u.w", "+d,+e,+f", 0x79c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1680 {"dpadd_u.d", "+d,+e,+f", 0x79e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1681 {"dpsub_s.h", "+d,+e,+f", 0x7a200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1682 {"dpsub_s.w", "+d,+e,+f", 0x7a400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1683 {"dpsub_s.d", "+d,+e,+f", 0x7a600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1684 {"dpsub_u.h", "+d,+e,+f", 0x7aa00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1685 {"dpsub_u.w", "+d,+e,+f", 0x7ac00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1686 {"dpsub_u.d", "+d,+e,+f", 0x7ae00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1687 {"sld.b",   "+d,+e[t]", 0x78000014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1688 {"sld.h",   "+d,+e[t]", 0x78200014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1689 {"sld.w",   "+d,+e[t]", 0x78400014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1690 {"sld.d",   "+d,+e[t]", 0x78600014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1691 {"sldi.b",  "+d,+e[+9]", 0x78000019, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1692 {"sldi.h",  "+d,+e[+8]", 0x78200019, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1693 {"sldi.w",  "+d,+e[+7]", 0x78300019, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1694 {"sldi.d",  "+d,+e[+6]", 0x78380019, 0xfffc003f, WR_VD|RD_VS,       0, MSA},
1695 {"splat.b", "+d,+e[t]", 0x78800014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1696 {"splat.h", "+d,+e[t]", 0x78a00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1697 {"splat.w", "+d,+e[t]", 0x78c00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1698 {"splat.d", "+d,+e[t]", 0x78e00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1699 {"splati.b", "+d,+e[+9]", 0x78400019, 0xffe0003f, WR_VD|RD_VS,      0, MSA},
1700 {"splati.h", "+d,+e[+8]", 0x78600019, 0xfff0003f, WR_VD|RD_VS,      0, MSA},
1701 {"splati.w", "+d,+e[+7]", 0x78700019, 0xfff8003f, WR_VD|RD_VS,      0, MSA},
1702 {"splati.d", "+d,+e[+6]", 0x78780019, 0xfffc003f, WR_VD|RD_VS,      0, MSA},
1703 {"pckev.b", "+d,+e,+f", 0x79000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1704 {"pckev.h", "+d,+e,+f", 0x79200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1705 {"pckev.w", "+d,+e,+f", 0x79400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1706 {"pckev.d", "+d,+e,+f", 0x79600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1707 {"pckod.b", "+d,+e,+f", 0x79800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1708 {"pckod.h", "+d,+e,+f", 0x79a00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1709 {"pckod.w", "+d,+e,+f", 0x79c00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1710 {"pckod.d", "+d,+e,+f", 0x79e00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1711 {"ilvl.b",  "+d,+e,+f", 0x7a000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1712 {"ilvl.h",  "+d,+e,+f", 0x7a200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1713 {"ilvl.w",  "+d,+e,+f", 0x7a400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1714 {"ilvl.d",  "+d,+e,+f", 0x7a600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1715 {"ilvr.b",  "+d,+e,+f", 0x7a800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1716 {"ilvr.h",  "+d,+e,+f", 0x7aa00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1717 {"ilvr.w",  "+d,+e,+f", 0x7ac00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1718 {"ilvr.d",  "+d,+e,+f", 0x7ae00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1719 {"ilvev.b", "+d,+e,+f", 0x7b000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1720 {"ilvev.h", "+d,+e,+f", 0x7b200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1721 {"ilvev.w", "+d,+e,+f", 0x7b400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1722 {"ilvev.d", "+d,+e,+f", 0x7b600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1723 {"ilvod.b", "+d,+e,+f", 0x7b800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1724 {"ilvod.h", "+d,+e,+f", 0x7ba00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1725 {"ilvod.w", "+d,+e,+f", 0x7bc00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1726 {"ilvod.d", "+d,+e,+f", 0x7be00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1727 {"vshf.b",  "+d,+e,+f", 0x78000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1728 {"vshf.h",  "+d,+e,+f", 0x78200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1729 {"vshf.w",  "+d,+e,+f", 0x78400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1730 {"vshf.d",  "+d,+e,+f", 0x78600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1731 {"srar.b",  "+d,+e,+f", 0x78800015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1732 {"srar.h",  "+d,+e,+f", 0x78a00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1733 {"srar.w",  "+d,+e,+f", 0x78c00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1734 {"srar.d",  "+d,+e,+f", 0x78e00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1735 {"srari.b", "+d,+e,+7", 0x7970000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1736 {"srari.h", "+d,+e,+8", 0x7960000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1737 {"srari.w", "+d,+e,+9", 0x7940000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1738 {"srari.d", "+d,+e,'",  0x7900000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1739 {"srlr.b",  "+d,+e,+f", 0x79000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1740 {"srlr.h",  "+d,+e,+f", 0x79200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1741 {"srlr.w",  "+d,+e,+f", 0x79400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1742 {"srlr.d",  "+d,+e,+f", 0x79600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1743 {"srlri.b", "+d,+e,+7", 0x79f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1744 {"srlri.h", "+d,+e,+8", 0x79e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1745 {"srlri.w", "+d,+e,+9", 0x79c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1746 {"srlri.d", "+d,+e,'",  0x7980000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1747 {"hadd_s.h", "+d,+e,+f", 0x7a200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1748 {"hadd_s.w", "+d,+e,+f", 0x7a400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1749 {"hadd_s.d", "+d,+e,+f", 0x7a600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1750 {"hadd_u.h", "+d,+e,+f", 0x7aa00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1751 {"hadd_u.w", "+d,+e,+f", 0x7ac00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1752 {"hadd_u.d", "+d,+e,+f", 0x7ae00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1753 {"hsub_s.h", "+d,+e,+f", 0x7b200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1754 {"hsub_s.w", "+d,+e,+f", 0x7b400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1755 {"hsub_s.d", "+d,+e,+f", 0x7b600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1756 {"hsub_u.h", "+d,+e,+f", 0x7ba00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1757 {"hsub_u.w", "+d,+e,+f", 0x7bc00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1758 {"hsub_u.d", "+d,+e,+f", 0x7be00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1759 {"and.v",   "+d,+e,+f", 0x7800001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1760 {"andi.b",  "+d,+e,5",  0x78000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1761 {"or.v",    "+d,+e,+f", 0x7820001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1762 {"ori.b",   "+d,+e,5",  0x79000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1763 {"nor.v",   "+d,+e,+f", 0x7840001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1764 {"nori.b",  "+d,+e,5",  0x7a000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1765 {"xor.v",   "+d,+e,+f", 0x7860001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1766 {"xori.b",  "+d,+e,5",  0x7b000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1767 {"bmnz.v",  "+d,+e,+f", 0x7880001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1768 {"bmnzi.b", "+d,+e,5",  0x78000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1769 {"bmz.v",   "+d,+e,+f", 0x78a0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1770 {"bmzi.b",  "+d,+e,5",  0x79000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1771 {"bsel.v",  "+d,+e,+f", 0x78c0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1772 {"bseli.b", "+d,+e,5",  0x7a000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1773 {"shf.b",   "+d,+e,5",  0x78000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1774 {"shf.h",   "+d,+e,5",  0x79000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1775 {"shf.w",   "+d,+e,5",  0x7a000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1776 {"bnz.v",    "+f,p",    0x45e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1777 {"bz.v",    "+f,p",     0x45600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1778 {"fill.b",  "+d,d",     0x7b00001e, 0xffff003f, WR_VD,           RD_d, MSA},
1779 {"fill.h",  "+d,d",     0x7b01001e, 0xffff003f, WR_VD,           RD_d, MSA},
1780 {"fill.w",  "+d,d",     0x7b02001e, 0xffff003f, WR_VD,           RD_d, MSA},
1781 {"fill.d",  "+d,d",     0x7b03001e, 0xffff003f, WR_VD,           RD_d, MSA64},
1782 {"pcnt.b",  "+d,+e",    0x7b04001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1783 {"pcnt.h",  "+d,+e",    0x7b05001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1784 {"pcnt.w",  "+d,+e",    0x7b06001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1785 {"pcnt.d",  "+d,+e",    0x7b07001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1786 {"nloc.b",  "+d,+e",    0x7b08001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1787 {"nloc.h",  "+d,+e",    0x7b09001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1788 {"nloc.w",  "+d,+e",    0x7b0a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1789 {"nloc.d",  "+d,+e",    0x7b0b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1790 {"nlzc.b",  "+d,+e",    0x7b0c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1791 {"nlzc.h",  "+d,+e",    0x7b0d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1792 {"nlzc.w",  "+d,+e",    0x7b0e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1793 {"nlzc.d",  "+d,+e",    0x7b0f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1794 {"copy_s.b", "+i,+e[+9]", 0x78800019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1795 {"copy_s.h", "+i,+e[+8]", 0x78a00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1796 {"copy_s.w", "+i,+e[+7]", 0x78b00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1797 {"copy_s.d", "+i,+e[+6]", 0x78b80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1798 {"copy_u.b", "+i,+e[+9]", 0x78c00019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1799 {"copy_u.h", "+i,+e[+8]", 0x78e00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1800 {"copy_u.w", "+i,+e[+7]", 0x78f00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1801 {"copy_u.d", "+i,+e[+6]", 0x78f80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1802 {"insert.b", "+d[+9],d", 0x79000019, 0xffe0003f, WR_VD|RD_VD,    RD_d, MSA},
1803 {"insert.h", "+d[+8],d", 0x79200019, 0xfff0003f, WR_VD|RD_VD,    RD_d, MSA},
1804 {"insert.w", "+d[+7],d", 0x79300019, 0xfff8003f, WR_VD|RD_VD,    RD_d, MSA},
1805 {"insert.d", "+d[+6],d", 0x79380019, 0xfffc003f, WR_VD|RD_VD,    RD_d, MSA64},
1806 {"insve.b", "+d[+9],+e[+~]", 0x79400019, 0xffe0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1807 {"insve.h", "+d[+8],+e[+~]", 0x79600019, 0xfff0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1808 {"insve.w", "+d[+7],+e[+~]", 0x79700019, 0xfff8003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1809 {"insve.d", "+d[+6],+e[+~]", 0x79780019, 0xfffc003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1810 {"bnz.b",    "+f,p",    0x47800000, 0xffe00000, CBD|RD_VT,          0, MSA},
1811 {"bnz.h",    "+f,p",    0x47a00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1812 {"bnz.w",    "+f,p",    0x47c00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1813 {"bnz.d",    "+f,p",    0x47e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1814 {"bz.b",    "+f,p",     0x47000000, 0xffe00000, CBD|RD_VT,          0, MSA},
1815 {"bz.h",    "+f,p",     0x47200000, 0xffe00000, CBD|RD_VT,          0, MSA},
1816 {"bz.w",    "+f,p",     0x47400000, 0xffe00000, CBD|RD_VT,          0, MSA},
1817 {"bz.d",    "+f,p",     0x47600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1818 {"ldi.b",   "+d,+0",    0x7b000007, 0xffe0003f, WR_VD,              0, MSA},
1819 {"ldi.h",   "+d,+0",    0x7b200007, 0xffe0003f, WR_VD,              0, MSA},
1820 {"ldi.w",   "+d,+0",    0x7b400007, 0xffe0003f, WR_VD,              0, MSA},
1821 {"ldi.d",   "+d,+0",    0x7b600007, 0xffe0003f, WR_VD,              0, MSA},
1822 {"fcaf.w",  "+d,+e,+f", 0x7800001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1823 {"fcaf.d",  "+d,+e,+f", 0x7820001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1824 {"fcun.w",  "+d,+e,+f", 0x7840001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1825 {"fcun.d",  "+d,+e,+f", 0x7860001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1826 {"fceq.w",  "+d,+e,+f", 0x7880001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1827 {"fceq.d",  "+d,+e,+f", 0x78a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1828 {"fcueq.w", "+d,+e,+f", 0x78c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1829 {"fcueq.d", "+d,+e,+f", 0x78e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1830 {"fclt.w",  "+d,+e,+f", 0x7900001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1831 {"fclt.d",  "+d,+e,+f", 0x7920001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1832 {"fcult.w", "+d,+e,+f", 0x7940001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1833 {"fcult.d", "+d,+e,+f", 0x7960001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1834 {"fcle.w",  "+d,+e,+f", 0x7980001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1835 {"fcle.d",  "+d,+e,+f", 0x79a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1836 {"fcule.w", "+d,+e,+f", 0x79c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1837 {"fcule.d", "+d,+e,+f", 0x79e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1838 {"fsaf.w",  "+d,+e,+f", 0x7a00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1839 {"fsaf.d",  "+d,+e,+f", 0x7a20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1840 {"fsun.w",  "+d,+e,+f", 0x7a40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1841 {"fsun.d",  "+d,+e,+f", 0x7a60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1842 {"fseq.w",  "+d,+e,+f", 0x7a80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1843 {"fseq.d",  "+d,+e,+f", 0x7aa0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1844 {"fsueq.w", "+d,+e,+f", 0x7ac0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1845 {"fsueq.d", "+d,+e,+f", 0x7ae0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1846 {"fslt.w",  "+d,+e,+f", 0x7b00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1847 {"fslt.d",  "+d,+e,+f", 0x7b20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1848 {"fsult.w", "+d,+e,+f", 0x7b40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1849 {"fsult.d", "+d,+e,+f", 0x7b60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1850 {"fsle.w",  "+d,+e,+f", 0x7b80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1851 {"fsle.d",  "+d,+e,+f", 0x7ba0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1852 {"fsule.w", "+d,+e,+f", 0x7bc0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1853 {"fsule.d", "+d,+e,+f", 0x7be0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1854 {"fadd.w",  "+d,+e,+f", 0x7800001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1855 {"fadd.d",  "+d,+e,+f", 0x7820001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1856 {"fsub.w",  "+d,+e,+f", 0x7840001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1857 {"fsub.d",  "+d,+e,+f", 0x7860001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1858 {"fmul.w",  "+d,+e,+f", 0x7880001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1859 {"fmul.d",  "+d,+e,+f", 0x78a0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1860 {"fdiv.w",  "+d,+e,+f", 0x78c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1861 {"fdiv.d",  "+d,+e,+f", 0x78e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1862 {"fmadd.w", "+d,+e,+f", 0x7900001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1863 {"fmadd.d", "+d,+e,+f", 0x7920001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1864 {"fmsub.w", "+d,+e,+f", 0x7940001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1865 {"fmsub.d", "+d,+e,+f", 0x7960001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1866 {"fexp2.w", "+d,+e,+f", 0x79c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1867 {"fexp2.d", "+d,+e,+f", 0x79e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1868 {"fexdo.h", "+d,+e,+f", 0x7a00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1869 {"fexdo.w", "+d,+e,+f", 0x7a20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1870 {"ftq.h",   "+d,+e,+f", 0x7a80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1871 {"ftq.w",   "+d,+e,+f", 0x7aa0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1872 {"fmin.w",  "+d,+e,+f", 0x7b00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1873 {"fmin.d",  "+d,+e,+f", 0x7b20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1874 {"fmin_a.w", "+d,+e,+f", 0x7b40001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1875 {"fmin_a.d", "+d,+e,+f", 0x7b60001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1876 {"fmax.w",  "+d,+e,+f", 0x7b80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1877 {"fmax.d",  "+d,+e,+f", 0x7ba0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1878 {"fmax_a.w", "+d,+e,+f", 0x7bc0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1879 {"fmax_a.d", "+d,+e,+f", 0x7be0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1880 {"fcor.w",  "+d,+e,+f", 0x7840001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1881 {"fcor.d",  "+d,+e,+f", 0x7860001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1882 {"fcune.w", "+d,+e,+f", 0x7880001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1883 {"fcune.d", "+d,+e,+f", 0x78a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1884 {"fcne.w",  "+d,+e,+f", 0x78c0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1885 {"fcne.d",  "+d,+e,+f", 0x78e0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1886 {"mul_q.h", "+d,+e,+f", 0x7900001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1887 {"mul_q.w", "+d,+e,+f", 0x7920001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1888 {"madd_q.h", "+d,+e,+f", 0x7940001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1889 {"madd_q.w", "+d,+e,+f", 0x7960001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1890 {"msub_q.h", "+d,+e,+f", 0x7980001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1891 {"msub_q.w", "+d,+e,+f", 0x79a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1892 {"fsor.w",  "+d,+e,+f", 0x7a40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1893 {"fsor.d",  "+d,+e,+f", 0x7a60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1894 {"fsune.w", "+d,+e,+f", 0x7a80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1895 {"fsune.d", "+d,+e,+f", 0x7aa0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1896 {"fsne.w",  "+d,+e,+f", 0x7ac0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1897 {"fsne.d",  "+d,+e,+f", 0x7ae0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1898 {"mulr_q.h", "+d,+e,+f", 0x7b00001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1899 {"mulr_q.w", "+d,+e,+f", 0x7b20001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1900 {"maddr_q.h", "+d,+e,+f", 0x7b40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1901 {"maddr_q.w", "+d,+e,+f", 0x7b60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1902 {"msubr_q.h", "+d,+e,+f", 0x7b80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1903 {"msubr_q.w", "+d,+e,+f", 0x7ba0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1904 {"fclass.w", "+d,+e",    0x7b20001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1905 {"fclass.d", "+d,+e",    0x7b21001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1906 {"fsqrt.w", "+d,+e",    0x7b26001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1907 {"fsqrt.d", "+d,+e",    0x7b27001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1908 {"frsqrt.w", "+d,+e",    0x7b28001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1909 {"frsqrt.d", "+d,+e",    0x7b29001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1910 {"frcp.w",  "+d,+e",    0x7b2a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1911 {"frcp.d",  "+d,+e",    0x7b2b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1912 {"frint.w", "+d,+e",    0x7b2c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1913 {"frint.d", "+d,+e",    0x7b2d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1914 {"flog2.w", "+d,+e",    0x7b2e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1915 {"flog2.d", "+d,+e",    0x7b2f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1916 {"fexupl.w", "+d,+e",    0x7b30001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1917 {"fexupl.d", "+d,+e",    0x7b31001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1918 {"fexupr.w", "+d,+e",    0x7b32001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1919 {"fexupr.d", "+d,+e",    0x7b33001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1920 {"ffql.w",  "+d,+e",    0x7b34001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1921 {"ffql.d",  "+d,+e",    0x7b35001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1922 {"ffqr.w",  "+d,+e",    0x7b36001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1923 {"ffqr.d",  "+d,+e",    0x7b37001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1924 {"ftint_s.w", "+d,+e",   0x7b38001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1925 {"ftint_s.d", "+d,+e",   0x7b39001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1926 {"ftint_u.w", "+d,+e",   0x7b3a001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1927 {"ftint_u.d", "+d,+e",   0x7b3b001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1928 {"ffint_s.w", "+d,+e",   0x7b3c001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1929 {"ffint_s.d", "+d,+e",   0x7b3d001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1930 {"ffint_u.w", "+d,+e",   0x7b3e001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1931 {"ffint_u.d", "+d,+e",   0x7b3f001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1932 {"ftrunc_s.w", "+d,+e",  0x7b40001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1933 {"ftrunc_s.d", "+d,+e",  0x7b41001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1934 {"ftrunc_u.w", "+d,+e",  0x7b42001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1935 {"ftrunc_u.d", "+d,+e",  0x7b43001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1936 {"ctcmsa",  "+h,d",     0x783e0019, 0xffff003f, COD,             RD_d, MSA},
1937 {"cfcmsa",  "+i,+g",    0x787e0019, 0xffff003f, COD,                0, MSA},
1938 {"move.v",  "+d,+e",    0x78be0019, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1939 {"lsa",     "d,v,t,+@", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA},
1940 {"dlsa",    "d,v,t,+@", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA64},
1941
1942 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1943 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1944 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1945 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1946 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1947 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1948 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1949 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1950 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1951 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1952 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1953 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1954 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1955 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1956 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1957
1958 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1959 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1960 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1961 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1962 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1963 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1964 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1965 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1966 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1967 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1968 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1969 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1970 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1971 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1972 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1973 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1974 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1975 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1976 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1977 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1978 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1979 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1980 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1981 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1982 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1983 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1984 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1985 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1986 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1987 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1988 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1989 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1990 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1991 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1992 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1993 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1994 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1995 /* b is at the top of the table.  */
1996 /* bal is at the top of the table.  */
1997 /* bc0[tf]l? are at the bottom of the table.  */
1998 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1999 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2000 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2001 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2002 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2003 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2004 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2005 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2006 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2007 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2008 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2009 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2010 /* bc2* are at the bottom of the table.  */
2011 /* bc3* are at the bottom of the table.  */
2012 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2013 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2014 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2015 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
2016 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2017 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
2018 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
2019 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
2020 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
2021 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
2022 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
2023 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
2024 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
2025 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
2026 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2027 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2028 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2029 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2030 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
2031 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
2032 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
2033 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
2034 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
2035 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
2036 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
2037 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
2038 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2039 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2040 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
2041 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
2042 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
2043 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
2044 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
2045 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
2046 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
2047 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
2048 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2049 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2050 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
2051 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
2052 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
2053 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
2054 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
2055 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
2056 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
2057 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
2058 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2059 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2060 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2061 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2062 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2063 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2064 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2065 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
2066 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2067 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
2068 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
2069 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
2070 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
2071 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2072 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2073 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2074 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2075 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2076 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2077 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2078 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2079 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2080 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2081 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2082 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2083 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2084 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2085 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2086 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2087 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2088 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2089 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2090 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2091 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2092 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2093 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2094 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2095 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2096 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2097 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2098 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2099 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2100 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2101 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2102 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2103 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2104 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2105 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2106 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2107 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2108 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2109 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2110 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2111 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2112 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2113 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2114 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2115 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2116 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2117 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2118 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2119 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2120 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2121 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2122 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2123 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2124 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2125 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2126 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2127 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2128 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2129 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2130 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2131 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2132 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2133 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2134 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2135 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2136 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2137 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2138 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2139 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2140 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2141 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2142 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2143 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2144 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2145 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2146 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2147 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2148 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2149 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2150 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2151 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2152 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2153 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2154 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2155 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2156 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2157 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2158 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2159 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2160 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2161 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2162 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2163 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2164 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2165 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2166 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2167 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2168 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2169 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2170 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2171 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2172 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2173 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2174 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2175 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2176 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2177 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2178 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2179 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2180 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2181 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2182 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2183 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2184 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2185 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2186 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2187 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2188 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2189 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2190 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2191 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2192 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2193 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2194 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2195 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2196 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2197 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2198 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2199 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2200 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2201 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2202 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2203 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2204 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2205 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2206 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2207 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2208 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2209 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2210 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2211 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2212 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2213 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2214 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2215 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2216 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2217 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2218 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2219 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2220 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2221 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2222 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2223 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2224 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2225 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2226 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2227 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2228 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2229 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2230 /* CW4010 instructions which are aliases for the cache instruction.  */
2231 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
2232 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
2233 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
2234 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
2235 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
2236 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
2237 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2238 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2239 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2240 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2241 {"mfhc0",   "t,G,H",    0x40400000, 0xffe007f8, LCD|WR_t|RD_C0,       0, I33},
2242 {"mthc0",   "t,G,H",    0x40c00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I33},
2243 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2244 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2245 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2246 /* cfc2 is at the bottom of the table.  */
2247 /* cfc3 is at the bottom of the table.  */
2248 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2249 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2250 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2251 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2252 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2253 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2254 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2255 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2256 /* ctc2 is at the bottom of the table.  */
2257 /* ctc3 is at the bottom of the table.  */
2258 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2259 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2260 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
2261 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2262 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2263 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2264 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2265 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2266 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2267 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2268 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2269 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2270 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2271 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2272 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2273 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2274 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
2275 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2276 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
2277 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2278 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
2279 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2280 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2281 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2282 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
2283 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
2284 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2285 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2286 /* dctr and dctw are used on the r5000.  */
2287 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
2288 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
2289 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
2290 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
2291 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2292 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2293 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2294 /* For ddiv, see the comments about div.  */
2295 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2296 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
2297 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
2298 /* For ddivu, see the comments about div.  */
2299 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2300 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
2301 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
2302 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2303 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2304 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
2305 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2306 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2307 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2308 /* The MIPS assembler treats the div opcode with two operands as
2309    though the first operand appeared twice (the first operand is both
2310    a source and a destination).  To get the div machine instruction,
2311    you must use an explicit destination of $0.  */
2312 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2313 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2314 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
2315 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
2316 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2317 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2318 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2319 /* For divu, see the comments about div.  */
2320 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2321 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2322 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
2323 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
2324 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
2325 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
2326 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
2327 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
2328 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
2329 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2330 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2331 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2332 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2333 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2334 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2335 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2336 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2337 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
2338 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
2339 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2340 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2341 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
2342 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2343 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
2344 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2345 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2346 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2347 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2348 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2349 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2350 /* dmfc2 is at the bottom of the table.  */
2351 /* dmtc2 is at the bottom of the table.  */
2352 /* dmfc3 is at the bottom of the table.  */
2353 /* dmtc3 is at the bottom of the table.  */
2354 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
2355 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
2356 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
2357 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
2358 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
2359 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
2360 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2361 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2362 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
2363 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
2364 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2365 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
2366 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
2367 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2368 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
2369 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
2370 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
2371 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
2372 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
2373 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
2374 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
2375 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2376 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
2377 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2378 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
2379 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
2380 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
2381 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
2382 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
2383 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
2384 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2385 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2386 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2387 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2388 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
2389 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
2390 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2391 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2392 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2393 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
2394 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
2395 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2396 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2397 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2398 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
2399 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
2400 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2401 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2402 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
2403 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2404 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
2405 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
2406 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2407 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2408 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2409 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
2410 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2411 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
2412 {"eretnc",  "",         0x42000058, 0xffffffff, 0,                    0, I33},
2413 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
2414 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2415 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2416 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2417 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2418 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2419 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2420 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
2421 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2422 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
2423 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
2424    the same hazard barrier effect.  */
2425 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
2426 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
2427 /* SVR4 PIC code requires special handling for j, so it must be a
2428    macro.  */
2429 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
2430 /* This form of j is used by the disassembler and internally by the
2431    assembler, but will never match user input (because the line above
2432    will match first).  */
2433 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
2434 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
2435 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
2436 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
2437    with the same hazard barrier effect.  */
2438 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
2439 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
2440 /* SVR4 PIC code requires special handling for jal, so it must be a
2441    macro.  */
2442 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
2443 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
2444 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
2445 /* This form of jal is used by the disassembler and internally by the
2446    assembler, but will never match user input (because the line above
2447    will match first).  */
2448 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
2449 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
2450 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
2451 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2452 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
2453 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2454 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
2455 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
2456 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
2457 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
2458 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
2459 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2460 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2461 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2462 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2463 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
2464 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
2465 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
2466 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2467 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
2468 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2469 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
2470 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2471 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
2472 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2473 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
2474 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2475 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2476 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
2477 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2478 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
2479 /* li is at the start of the table.  */
2480 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
2481 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
2482 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
2483 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
2484 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
2485 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
2486 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2487 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
2488 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
2489 {"aui",     "s,t,u",    0x3c000000, 0xfc000000, RD_s|WR_t,            0, I32R6},
2490 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
2491 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2492 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
2493 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2494 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
2495 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2496 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2497 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2498 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2499 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
2500 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2501 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2502 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
2503 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2504 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
2505 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2506 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
2507 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2508 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
2509 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2510 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
2511 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2512 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
2513 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
2514 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2515 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
2516 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2517 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
2518 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2519 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2520 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2521 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2522 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2523 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2524 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2525 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2526 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2527 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2528 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2529 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2530 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2531 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2532 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
2533 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
2534 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
2535 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2536 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2537 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2538 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2539 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2540 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
2541 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2542 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2543 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2544 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2545 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2546 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
2547 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2548 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2549 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2550 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2551 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2552 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2553 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2554 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2555 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2556 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2557 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2558 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2559 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2560 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2561 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2562 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
2563 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2564 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2565 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2566 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2567 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2568 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2569 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2570 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2571 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
2572 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2573 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2574 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2575 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2576 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2577 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2578 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2579 /* mfc2 is at the bottom of the table.  */
2580 /* mfhc2 is at the bottom of the table.  */
2581 /* mfc3 is at the bottom of the table.  */
2582 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
2583 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
2584 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
2585 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
2586 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
2587 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
2588 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2589 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2590 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2591 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2592 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2593 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2594 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2595 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2596 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2597 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2598 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2599 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2600 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2601 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2602 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2603 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2604 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2605 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2606 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2607 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2608 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2609 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2610 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2611 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2612 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2613 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2614 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2615 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2616 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2617 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2618 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2619 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2620 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2621 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2622 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2623 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2624 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2625 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2626 /* move is at the top of the table.  */
2627 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2628 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2629 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2630 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2631 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2632 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2633 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2634 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2635 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2636 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2637 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2638 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2639 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
2640 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2641 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2642 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2643 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2644 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2645 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2646 /* mtc2 is at the bottom of the table.  */
2647 /* mthc2 is at the bottom of the table.  */
2648 /* mtc3 is at the bottom of the table.  */
2649 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
2650 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
2651 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
2652 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
2653 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
2654 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
2655 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2656 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2657 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2658 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2659 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2660 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2661 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2662 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2663 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
2664 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2665 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2666 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2667 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2668 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2669 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2670 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2671 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2672 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
2673 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2674 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2675 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2676 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2677 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2678 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2679 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2680 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2681 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
2682 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
2683 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
2684 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
2685 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2686 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2687 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2688 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2689 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2690 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2691 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2692 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2693 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2694 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2695 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2696 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2697 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
2698 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
2699 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
2700 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
2701 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2702 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2703 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2704 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2705 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2706 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2707 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2708 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2709 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2710 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2711 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2712 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2713 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2714 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2715 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2716 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2717 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2718 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2719 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
2720 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2721 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2722 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2723 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2724 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
2725 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
2726 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2727 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2728 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2729 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2730 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2731 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2732 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2733 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2734 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2735 /* nop is at the start of the table.  */
2736 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2737 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
2738 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2739 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2740 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2741 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2742 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2743 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2744 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2745 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2746 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2747 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2748 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2749 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2750 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2751 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2752 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2753 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2754 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2755 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2756 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2757 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2758 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2759 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2760 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2761 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2762 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2763 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2764 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2765 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2766 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2767   /* pref and prefx are at the start of the table.  */
2768 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2769 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2770 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2771 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2772 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2773 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2774 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2775 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2776 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2777 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2778 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2779 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2780 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2781 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2782 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2783 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2784 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2785 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2786 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2787 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2788 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2789 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2790 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2791 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2792 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2793 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2794 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2795 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2796 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2797 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2798 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2799 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2800 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2801 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2802 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2803 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2804 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2805 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2806 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2807 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2808 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2809 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2810 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2811 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2812 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2813 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2814 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2815 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2816 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2817 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2818 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2819 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2820 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2821 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2822 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2823 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2824 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2825 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2826 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2827 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2828 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2829 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2830 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2831 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2832 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2833 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2834 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2835 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2836 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2837 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2838 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2839 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2840 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2841 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2842 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2843 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2844 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2845 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2846 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2847 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2848 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2849 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2850 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2851 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2852 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2853 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2854 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2855 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2856 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2857 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2858 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2859 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2860 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2861 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2862 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2863 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2864 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2865 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2866 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2867 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2868 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2869 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2870 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2871 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2872 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2873 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2874 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2875 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2876 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2877 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2878 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2879 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2880 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2881 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2882 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2883 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2884 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2885 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2886 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2887 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2888 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2889 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2890 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2891 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2892 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2893 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2894 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2895 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2896 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2897 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2898 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2899 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2900 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2901 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2902 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2903 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2904 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2905 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2906 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2907 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2908 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2909 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2910 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2911 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2912 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2913 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2914 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2915 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2916 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2917 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2918 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2919 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2920 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2921 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2922 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2923 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2924 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2925 /* ssnop is at the start of the table.  */
2926 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2927 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2928 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2929 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2930 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2931 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2932 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2933 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2934 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2935 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2936 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2937 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2938 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2939 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2940 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2941 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2942 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2943 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2944 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2945 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2946 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2947 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2948 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2949 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2950 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2951 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2952 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2953 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2954 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2955 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2956 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2957 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2958 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2959 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2960 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2961 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2962 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2963 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2964 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2965 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2966 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2967 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2968 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2969 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2970 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2971 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2972 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2973 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2974 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2975 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2976 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2977 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2978 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2979 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2980 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2981 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2982 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2983 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2984 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2985 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2986 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2987 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2988 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2989 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2990 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2991 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2992 {"tlbinv",  "",         0x42000003, 0xffffffff, INSN_TLB,             0, I32  },
2993 {"tlbinvf", "",         0x42000004, 0xffffffff, INSN_TLB,             0, I32  },
2994 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2995 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2996 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2997 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2998 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
2999 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
3000 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
3001 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3002 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3003 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
3004 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
3005 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
3006 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3007 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3008 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
3009 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
3010 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
3011 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
3012 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3013 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3014 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
3015 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3016 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3017 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
3018 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
3019 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
3020 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
3021 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
3022 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
3023 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
3024 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
3025 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
3026 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
3027 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
3028 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
3029 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
3030 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
3031 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
3032 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
3033 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
3034 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
3035 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
3036 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
3037 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
3038 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
3039 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
3040 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
3041 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
3042 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
3043 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
3044 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
3045 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
3046 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3047 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
3048 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3049 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
3050 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
3051 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
3052 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
3053
3054 /* User Defined Instruction.  */
3055 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3056 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3057 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3058 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3059 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3060 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3061 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3062 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3063 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3064 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3065 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3066 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3067 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3068 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3069 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3070 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3071 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3072 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3073 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3074 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3075 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3076 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3077 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3078 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3079 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3080 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3081 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3082 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3083 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3084 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3085 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3086 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3087 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3088 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3089 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3090 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3091 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3092 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3093 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3094 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3095 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3096 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3097 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3098 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3099 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3100 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3101 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3102 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3103 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3104 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3105 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3106 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3107 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3108 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3109 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3110 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3111 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3112 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3113 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3114 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3115 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3116 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3117 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3118 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3119
3120 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
3121    instructions so they are here for the latters to take precedence.  */
3122 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3123 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3124 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3125 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3126 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3127 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3128 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3129 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3130 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3131 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3132 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
3133 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
3134 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
3135 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
3136 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3137 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
3138 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
3139 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
3140 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
3141 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
3142 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
3143 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3144 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3145 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3146
3147 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
3148    instructions, so they are here for the latters to take precedence.  */
3149 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3150 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3151 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3152 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3153 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3154 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3155 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
3156 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
3157 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3158 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
3159 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
3160 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
3161
3162 /* No hazard protection on coprocessor instructions--they shouldn't
3163    change the state of the processor and if they do it's up to the
3164    user to put in nops as necessary.  These are at the end so that the
3165    disassembler recognizes more specific versions first.  */
3166 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
3167 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
3168 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
3169 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
3170 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
3171 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
3172 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
3173 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
3174   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
3175      4010 any more, so move this insn out of the way.  If the object
3176      format gave us more info, we could do this right.  */
3177 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
3178 /* MIPS DSP ASE */
3179 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3180 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3181 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3182 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3183 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3184 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3185 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3186 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3187 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3188 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3189 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3190 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3191 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3192 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3193 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3194 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3195 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3196 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3197 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
3198 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
3199 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3200 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3201 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3202 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3203 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3204 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3205 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3206 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3207 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3208 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3209 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3210 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3211 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3212 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3213 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3214 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3215 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3216 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3217 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3218 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3219 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3220 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
3221 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
3222 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3223 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3224 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3225 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3226 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3227 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3228 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3229 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3230 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3231 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3232 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3233 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3234 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3235 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3236 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3237 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3238 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
3239 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3240 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3241 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3242 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3243 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
3244 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3245 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3246 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3247 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3248 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3249 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3250 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3251 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3252 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3253 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3254 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3255 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3256 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3257 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3258 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3259 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3260 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
3261 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
3262 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
3263 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
3264 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3265 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3266 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3267 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3268 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3269 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3270 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3271 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3272 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3273 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3274 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
3275 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3276 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
3277 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3278 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3279 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3280 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3281 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3282 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3283 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3284 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3285 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3286 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3287 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3288 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3289 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3290 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3291 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3292 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3293 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3294 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
3295 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3296 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3297 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3298 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3299 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3300 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3301 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3302 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3303 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
3304 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
3305 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3306 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
3307 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3308 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3309 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3310 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3311 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3312 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3313 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3314 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3315 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3316 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3317 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3318 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3319 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3320 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3321 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3322 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3323 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3324 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3325 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3326 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3327 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3328 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3329 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3330 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3331 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3332 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3333 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3334 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3335 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3336 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3337 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3338 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3339 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3340 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3341 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3342 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
3343 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3344 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
3345 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3346 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3347 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
3348 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
3349 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
3350 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
3351 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
3352 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
3353 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
3354 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
3355 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
3356 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
3357 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3358 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3359 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3360 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3361 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3362 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
3363 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
3364 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3365 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3366 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3367 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3368 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3369 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3370 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3371 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3372 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3373 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3374 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3375 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3376 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3377 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3378 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3379 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3380 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3381 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3382 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3383 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3384 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3385 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3386 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3387 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3388 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3389 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3390 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3391 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3392 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3393 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3394 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3395 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3396 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3397 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3398 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3399 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3400 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3401 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3402 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3403 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3404 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3405 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3406 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3407 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3408 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3409 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3410 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3411 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
3412 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
3413 /* MIPS DSP ASE Rev2 */
3414 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
3415 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3416 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3417 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3418 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3419 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3420 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
3421 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
3422 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3423 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3424 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3425 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3426 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3427 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3428 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3429 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3430 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3431 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3432 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3433 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
3434 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
3435 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
3436 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3437 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3438 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3439 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3440 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3441 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
3442 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3443 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3444 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3445 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3446 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3447 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3448 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3449 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3450 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3451 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3452 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3453 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3454 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3455 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3456 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3457 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3458 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3459 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3460 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3461 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
3462 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3463 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3464 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3465 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3466 /* ST Microelectronics Loongson-2E and -2F.  */
3467 {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3468 {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3469 {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3470 {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3471 {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3472 {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3473 {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3474 {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3475 {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3476 {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3477 {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3478 {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3479 {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3480 {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3481 {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3482 {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3483 {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3484 {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3485 {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3486 {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3487 {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3488 {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3489 {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3490 {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3491 };
3492
3493 #define MIPS_NUM_OPCODES \
3494         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
3495 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
3496
3497 /* const removed from the following to allow for dynamic extensions to the
3498  * built-in instruction set. */
3499 struct mips_opcode *mips_opcodes =
3500   (struct mips_opcode *) mips_builtin_opcodes;
3501 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
3502 #undef MIPS_NUM_OPCODES
3503
3504 /* Mips instructions are at maximum this many bytes long.  */
3505 #define INSNLEN 4
3506
3507 \f
3508 /* FIXME: These should be shared with gdb somehow.  */
3509
3510 struct mips_cp0sel_name
3511 {
3512   unsigned int cp0reg;
3513   unsigned int sel;
3514   const char * const name;
3515 };
3516
3517 #if 0
3518 /* The mips16 registers.  */
3519 static const unsigned int mips16_to_32_reg_map[] =
3520 {
3521   16, 17, 2, 3, 4, 5, 6, 7
3522 };
3523
3524 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
3525 #endif
3526
3527 static const char * const mips_gpr_names_numeric[32] =
3528 {
3529   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3530   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3531   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3532   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3533 };
3534
3535 static const char * const mips_gpr_names_oldabi[32] =
3536 {
3537   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3538   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
3539   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3540   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3541 };
3542
3543 static const char * const mips_gpr_names_newabi[32] =
3544 {
3545   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3546   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
3547   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3548   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3549 };
3550
3551 static const char * const mips_fpr_names_numeric[32] =
3552 {
3553   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
3554   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
3555   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
3556   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
3557 };
3558
3559 static const char * const mips_fpr_names_32[32] =
3560 {
3561   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
3562   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
3563   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
3564   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
3565 };
3566
3567 static const char * const mips_fpr_names_n32[32] =
3568 {
3569   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
3570   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3571   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
3572   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
3573 };
3574
3575 static const char * const mips_fpr_names_64[32] =
3576 {
3577   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
3578   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3579   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
3580   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
3581 };
3582
3583 static const char * const mips_wr_names[32] = {
3584   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",
3585   "w8",  "w9",  "w10", "w11", "w12", "w13", "w14", "w15",
3586   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3587   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "w31"
3588 };
3589
3590 static const char * const mips_cp0_names_numeric[32] =
3591 {
3592   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3593   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3594   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3595   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3596 };
3597
3598 static const char * const mips_cp0_names_mips3264[32] =
3599 {
3600   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3601   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3602   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3603   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3604   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3605   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3606   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3607   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3608 };
3609
3610 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3611 {
3612   {  4, 1, "c0_contextconfig"   },
3613   {  0, 1, "c0_mvpcontrol"      },
3614   {  0, 2, "c0_mvpconf0"        },
3615   {  0, 3, "c0_mvpconf1"        },
3616   {  1, 1, "c0_vpecontrol"      },
3617   {  1, 2, "c0_vpeconf0"        },
3618   {  1, 3, "c0_vpeconf1"        },
3619   {  1, 4, "c0_yqmask"          },
3620   {  1, 5, "c0_vpeschedule"     },
3621   {  1, 6, "c0_vpeschefback"    },
3622   {  2, 1, "c0_tcstatus"        },
3623   {  2, 2, "c0_tcbind"          },
3624   {  2, 3, "c0_tcrestart"       },
3625   {  2, 4, "c0_tchalt"          },
3626   {  2, 5, "c0_tccontext"       },
3627   {  2, 6, "c0_tcschedule"      },
3628   {  2, 7, "c0_tcschefback"     },
3629   {  5, 1, "c0_pagegrain"       },
3630   {  6, 1, "c0_srsconf0"        },
3631   {  6, 2, "c0_srsconf1"        },
3632   {  6, 3, "c0_srsconf2"        },
3633   {  6, 4, "c0_srsconf3"        },
3634   {  6, 5, "c0_srsconf4"        },
3635   { 12, 1, "c0_intctl"          },
3636   { 12, 2, "c0_srsctl"          },
3637   { 12, 3, "c0_srsmap"          },
3638   { 15, 1, "c0_ebase"           },
3639   { 16, 1, "c0_config1"         },
3640   { 16, 2, "c0_config2"         },
3641   { 16, 3, "c0_config3"         },
3642   { 18, 1, "c0_watchlo,1"       },
3643   { 18, 2, "c0_watchlo,2"       },
3644   { 18, 3, "c0_watchlo,3"       },
3645   { 18, 4, "c0_watchlo,4"       },
3646   { 18, 5, "c0_watchlo,5"       },
3647   { 18, 6, "c0_watchlo,6"       },
3648   { 18, 7, "c0_watchlo,7"       },
3649   { 19, 1, "c0_watchhi,1"       },
3650   { 19, 2, "c0_watchhi,2"       },
3651   { 19, 3, "c0_watchhi,3"       },
3652   { 19, 4, "c0_watchhi,4"       },
3653   { 19, 5, "c0_watchhi,5"       },
3654   { 19, 6, "c0_watchhi,6"       },
3655   { 19, 7, "c0_watchhi,7"       },
3656   { 23, 1, "c0_tracecontrol"    },
3657   { 23, 2, "c0_tracecontrol2"   },
3658   { 23, 3, "c0_usertracedata"   },
3659   { 23, 4, "c0_tracebpc"        },
3660   { 25, 1, "c0_perfcnt,1"       },
3661   { 25, 2, "c0_perfcnt,2"       },
3662   { 25, 3, "c0_perfcnt,3"       },
3663   { 25, 4, "c0_perfcnt,4"       },
3664   { 25, 5, "c0_perfcnt,5"       },
3665   { 25, 6, "c0_perfcnt,6"       },
3666   { 25, 7, "c0_perfcnt,7"       },
3667   { 27, 1, "c0_cacheerr,1"      },
3668   { 27, 2, "c0_cacheerr,2"      },
3669   { 27, 3, "c0_cacheerr,3"      },
3670   { 28, 1, "c0_datalo"          },
3671   { 28, 2, "c0_taglo1"          },
3672   { 28, 3, "c0_datalo1"         },
3673   { 28, 4, "c0_taglo2"          },
3674   { 28, 5, "c0_datalo2"         },
3675   { 28, 6, "c0_taglo3"          },
3676   { 28, 7, "c0_datalo3"         },
3677   { 29, 1, "c0_datahi"          },
3678   { 29, 2, "c0_taghi1"          },
3679   { 29, 3, "c0_datahi1"         },
3680   { 29, 4, "c0_taghi2"          },
3681   { 29, 5, "c0_datahi2"         },
3682   { 29, 6, "c0_taghi3"          },
3683   { 29, 7, "c0_datahi3"         },
3684 };
3685
3686 static const char * const mips_cp0_names_mips3264r2[32] =
3687 {
3688   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3689   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
3690   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3691   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3692   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3693   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3694   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3695   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3696 };
3697
3698 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
3699 {
3700   {  4, 1, "c0_contextconfig"   },
3701   {  5, 1, "c0_pagegrain"       },
3702   { 12, 1, "c0_intctl"          },
3703   { 12, 2, "c0_srsctl"          },
3704   { 12, 3, "c0_srsmap"          },
3705   { 15, 1, "c0_ebase"           },
3706   { 16, 1, "c0_config1"         },
3707   { 16, 2, "c0_config2"         },
3708   { 16, 3, "c0_config3"         },
3709   { 18, 1, "c0_watchlo,1"       },
3710   { 18, 2, "c0_watchlo,2"       },
3711   { 18, 3, "c0_watchlo,3"       },
3712   { 18, 4, "c0_watchlo,4"       },
3713   { 18, 5, "c0_watchlo,5"       },
3714   { 18, 6, "c0_watchlo,6"       },
3715   { 18, 7, "c0_watchlo,7"       },
3716   { 19, 1, "c0_watchhi,1"       },
3717   { 19, 2, "c0_watchhi,2"       },
3718   { 19, 3, "c0_watchhi,3"       },
3719   { 19, 4, "c0_watchhi,4"       },
3720   { 19, 5, "c0_watchhi,5"       },
3721   { 19, 6, "c0_watchhi,6"       },
3722   { 19, 7, "c0_watchhi,7"       },
3723   { 23, 1, "c0_tracecontrol"    },
3724   { 23, 2, "c0_tracecontrol2"   },
3725   { 23, 3, "c0_usertracedata"   },
3726   { 23, 4, "c0_tracebpc"        },
3727   { 25, 1, "c0_perfcnt,1"       },
3728   { 25, 2, "c0_perfcnt,2"       },
3729   { 25, 3, "c0_perfcnt,3"       },
3730   { 25, 4, "c0_perfcnt,4"       },
3731   { 25, 5, "c0_perfcnt,5"       },
3732   { 25, 6, "c0_perfcnt,6"       },
3733   { 25, 7, "c0_perfcnt,7"       },
3734   { 27, 1, "c0_cacheerr,1"      },
3735   { 27, 2, "c0_cacheerr,2"      },
3736   { 27, 3, "c0_cacheerr,3"      },
3737   { 28, 1, "c0_datalo"          },
3738   { 28, 2, "c0_taglo1"          },
3739   { 28, 3, "c0_datalo1"         },
3740   { 28, 4, "c0_taglo2"          },
3741   { 28, 5, "c0_datalo2"         },
3742   { 28, 6, "c0_taglo3"          },
3743   { 28, 7, "c0_datalo3"         },
3744   { 29, 1, "c0_datahi"          },
3745   { 29, 2, "c0_taghi1"          },
3746   { 29, 3, "c0_datahi1"         },
3747   { 29, 4, "c0_taghi2"          },
3748   { 29, 5, "c0_datahi2"         },
3749   { 29, 6, "c0_taghi3"          },
3750   { 29, 7, "c0_datahi3"         },
3751 };
3752
3753 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
3754 static const char * const mips_cp0_names_sb1[32] =
3755 {
3756   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3757   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3758   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3759   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3760   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3761   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3762   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
3763   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
3764 };
3765
3766 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3767 {
3768   { 16, 1, "c0_config1"         },
3769   { 18, 1, "c0_watchlo,1"       },
3770   { 19, 1, "c0_watchhi,1"       },
3771   { 22, 0, "c0_perftrace"       },
3772   { 23, 3, "c0_edebug"          },
3773   { 25, 1, "c0_perfcnt,1"       },
3774   { 25, 2, "c0_perfcnt,2"       },
3775   { 25, 3, "c0_perfcnt,3"       },
3776   { 25, 4, "c0_perfcnt,4"       },
3777   { 25, 5, "c0_perfcnt,5"       },
3778   { 25, 6, "c0_perfcnt,6"       },
3779   { 25, 7, "c0_perfcnt,7"       },
3780   { 26, 1, "c0_buserr_pa"       },
3781   { 27, 1, "c0_cacheerr_d"      },
3782   { 27, 3, "c0_cacheerr_d_pa"   },
3783   { 28, 1, "c0_datalo_i"        },
3784   { 28, 2, "c0_taglo_d"         },
3785   { 28, 3, "c0_datalo_d"        },
3786   { 29, 1, "c0_datahi_i"        },
3787   { 29, 2, "c0_taghi_d"         },
3788   { 29, 3, "c0_datahi_d"        },
3789 };
3790
3791 static const char * const mips_hwr_names_numeric[32] =
3792 {
3793   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3794   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3795   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3796   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3797 };
3798
3799 static const char * const mips_hwr_names_mips3264r2[32] =
3800 {
3801   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3802   "$4",          "$5",            "$6",           "$7",
3803   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3804   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3805   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3806 };
3807
3808 static const char * const mips_msa_control_names_mips3264r2[32] = {
3809   "MSAIR", "MSACSR", "$2", "$3",  "$4",   "$5",   "$6",   "$7",
3810   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3811   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3812   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3813 };
3814
3815 struct mips_abi_choice
3816 {
3817   const char *name;
3818   const char * const *gpr_names;
3819   const char * const *fpr_names;
3820 };
3821
3822 static struct mips_abi_choice mips_abi_choices[] =
3823 {
3824   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3825   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3826   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3827   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3828 };
3829
3830 struct mips_arch_choice
3831 {
3832   const char *name;
3833   int bfd_mach_valid;
3834   unsigned long bfd_mach;
3835   int processor;
3836   int isa;
3837   const char * const *cp0_names;
3838   const struct mips_cp0sel_name *cp0sel_names;
3839   unsigned int cp0sel_names_len;
3840   const char * const *hwr_names;
3841 };
3842
3843 #define bfd_mach_mips3000              3000
3844 #define bfd_mach_mips3900              3900
3845 #define bfd_mach_mips4000              4000
3846 #define bfd_mach_mips4010              4010
3847 #define bfd_mach_mips4100              4100
3848 #define bfd_mach_mips4111              4111
3849 #define bfd_mach_mips4120              4120
3850 #define bfd_mach_mips4300              4300
3851 #define bfd_mach_mips4400              4400
3852 #define bfd_mach_mips4600              4600
3853 #define bfd_mach_mips4650              4650
3854 #define bfd_mach_mips5000              5000
3855 #define bfd_mach_mips5400              5400
3856 #define bfd_mach_mips5500              5500
3857 #define bfd_mach_mips6000              6000
3858 #define bfd_mach_mips7000              7000
3859 #define bfd_mach_mips8000              8000
3860 #define bfd_mach_mips9000              9000
3861 #define bfd_mach_mips10000             10000
3862 #define bfd_mach_mips12000             12000
3863 #define bfd_mach_mips16                16
3864 #define bfd_mach_mips5                 5
3865 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3866 #define bfd_mach_mipsisa32             32
3867 #define bfd_mach_mipsisa32r2           33
3868 #define bfd_mach_mipsisa64             64
3869 #define bfd_mach_mipsisa64r2           65
3870
3871 static const struct mips_arch_choice mips_arch_choices[] =
3872 {
3873   { "numeric",  0, 0, 0, 0,
3874     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3875
3876   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3877     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3878   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3879     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3880   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3881     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3882   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3883     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3884   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3885     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3886   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3887     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3888   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3889     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3890   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3891     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3892   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3893     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3894   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3895     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3896   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3897     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3898   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3899     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3900   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3901     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3902   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3903     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3904   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3905     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3906   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3907     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3908   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3909     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3910   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3911     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3912   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3913     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3914   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3915     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3916   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3917     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3918
3919   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3920      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3921      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3922      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3923      page 1.  */
3924   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3925     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3926     mips_cp0_names_mips3264,
3927     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3928     mips_hwr_names_numeric },
3929
3930   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3931     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3932      | INSN_MIPS3D | INSN_MT | INSN_MSA),
3933     mips_cp0_names_mips3264r2,
3934     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3935     mips_hwr_names_mips3264r2 },
3936
3937   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3938   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3939     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3940     mips_cp0_names_mips3264,
3941     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3942     mips_hwr_names_numeric },
3943
3944   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3945     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3946      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3947     mips_cp0_names_mips3264r2,
3948     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3949     mips_hwr_names_mips3264r2 },
3950
3951   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3952     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3953     mips_cp0_names_sb1,
3954     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3955     mips_hwr_names_numeric },
3956
3957   /* This entry, mips16, is here only for ISA/processor selection; do
3958      not print its name.  */
3959   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3960     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3961 };
3962
3963 /* ISA and processor type to disassemble for, and register names to use.
3964    set_default_mips_dis_options and parse_mips_dis_options fill in these
3965    values.  */
3966 static int mips_processor;
3967 static int mips_isa;
3968 static const char * const *mips_gpr_names;
3969 static const char * const *mips_fpr_names;
3970 static const char * const *mips_cp0_names;
3971 static const struct mips_cp0sel_name *mips_cp0sel_names;
3972 static int mips_cp0sel_names_len;
3973 static const char * const *mips_hwr_names;
3974
3975 /* Other options */
3976 static int no_aliases;  /* If set disassemble as most general inst.  */
3977 \f
3978 static const struct mips_abi_choice *
3979 choose_abi_by_name (const char *name, unsigned int namelen)
3980 {
3981   const struct mips_abi_choice *c;
3982   unsigned int i;
3983
3984   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3985     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3986         && strlen (mips_abi_choices[i].name) == namelen)
3987       c = &mips_abi_choices[i];
3988
3989   return c;
3990 }
3991
3992 static const struct mips_arch_choice *
3993 choose_arch_by_name (const char *name, unsigned int namelen)
3994 {
3995   const struct mips_arch_choice *c = NULL;
3996   unsigned int i;
3997
3998   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3999     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
4000         && strlen (mips_arch_choices[i].name) == namelen)
4001       c = &mips_arch_choices[i];
4002
4003   return c;
4004 }
4005
4006 static const struct mips_arch_choice *
4007 choose_arch_by_number (unsigned long mach)
4008 {
4009   static unsigned long hint_bfd_mach;
4010   static const struct mips_arch_choice *hint_arch_choice;
4011   const struct mips_arch_choice *c;
4012   unsigned int i;
4013
4014   /* We optimize this because even if the user specifies no
4015      flags, this will be done for every instruction!  */
4016   if (hint_bfd_mach == mach
4017       && hint_arch_choice != NULL
4018       && hint_arch_choice->bfd_mach == hint_bfd_mach)
4019     return hint_arch_choice;
4020
4021   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
4022     {
4023       if (mips_arch_choices[i].bfd_mach_valid
4024           && mips_arch_choices[i].bfd_mach == mach)
4025         {
4026           c = &mips_arch_choices[i];
4027           hint_bfd_mach = mach;
4028           hint_arch_choice = c;
4029         }
4030     }
4031   return c;
4032 }
4033
4034 static void
4035 set_default_mips_dis_options (struct disassemble_info *info)
4036 {
4037   const struct mips_arch_choice *chosen_arch;
4038
4039   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
4040      and numeric FPR, CP0 register, and HWR names.  */
4041   mips_isa = ISA_MIPS3;
4042   mips_processor =  CPU_R3000;
4043   mips_gpr_names = mips_gpr_names_oldabi;
4044   mips_fpr_names = mips_fpr_names_numeric;
4045   mips_cp0_names = mips_cp0_names_numeric;
4046   mips_cp0sel_names = NULL;
4047   mips_cp0sel_names_len = 0;
4048   mips_hwr_names = mips_hwr_names_numeric;
4049   no_aliases = 0;
4050
4051   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
4052 #if 0
4053   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
4054     {
4055       Elf_Internal_Ehdr *header;
4056
4057       header = elf_elfheader (info->section->owner);
4058       if (is_newabi (header))
4059         mips_gpr_names = mips_gpr_names_newabi;
4060     }
4061 #endif
4062
4063   /* Set ISA, architecture, and cp0 register names as best we can.  */
4064 #if !defined(SYMTAB_AVAILABLE) && 0
4065   /* This is running out on a target machine, not in a host tool.
4066      FIXME: Where does mips_target_info come from?  */
4067   target_processor = mips_target_info.processor;
4068   mips_isa = mips_target_info.isa;
4069 #else
4070   chosen_arch = choose_arch_by_number (info->mach);
4071   if (chosen_arch != NULL)
4072     {
4073       mips_processor = chosen_arch->processor;
4074       mips_isa = chosen_arch->isa;
4075       mips_cp0_names = chosen_arch->cp0_names;
4076       mips_cp0sel_names = chosen_arch->cp0sel_names;
4077       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4078       mips_hwr_names = chosen_arch->hwr_names;
4079     }
4080 #endif
4081 }
4082
4083 static void
4084 parse_mips_dis_option (const char *option, unsigned int len)
4085 {
4086   unsigned int i, optionlen, vallen;
4087   const char *val;
4088   const struct mips_abi_choice *chosen_abi;
4089   const struct mips_arch_choice *chosen_arch;
4090
4091   /* Look for the = that delimits the end of the option name.  */
4092   for (i = 0; i < len; i++)
4093     {
4094       if (option[i] == '=')
4095         break;
4096     }
4097   if (i == 0)           /* Invalid option: no name before '='.  */
4098     return;
4099   if (i == len)         /* Invalid option: no '='.  */
4100     return;
4101   if (i == (len - 1))   /* Invalid option: no value after '='.  */
4102     return;
4103
4104   optionlen = i;
4105   val = option + (optionlen + 1);
4106   vallen = len - (optionlen + 1);
4107
4108   if (strncmp("gpr-names", option, optionlen) == 0
4109       && strlen("gpr-names") == optionlen)
4110     {
4111       chosen_abi = choose_abi_by_name (val, vallen);
4112       if (chosen_abi != NULL)
4113         mips_gpr_names = chosen_abi->gpr_names;
4114       return;
4115     }
4116
4117   if (strncmp("fpr-names", option, optionlen) == 0
4118       && strlen("fpr-names") == optionlen)
4119     {
4120       chosen_abi = choose_abi_by_name (val, vallen);
4121       if (chosen_abi != NULL)
4122         mips_fpr_names = chosen_abi->fpr_names;
4123       return;
4124     }
4125
4126   if (strncmp("cp0-names", option, optionlen) == 0
4127       && strlen("cp0-names") == optionlen)
4128     {
4129       chosen_arch = choose_arch_by_name (val, vallen);
4130       if (chosen_arch != NULL)
4131         {
4132           mips_cp0_names = chosen_arch->cp0_names;
4133           mips_cp0sel_names = chosen_arch->cp0sel_names;
4134           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4135         }
4136       return;
4137     }
4138
4139   if (strncmp("hwr-names", option, optionlen) == 0
4140       && strlen("hwr-names") == optionlen)
4141     {
4142       chosen_arch = choose_arch_by_name (val, vallen);
4143       if (chosen_arch != NULL)
4144         mips_hwr_names = chosen_arch->hwr_names;
4145       return;
4146     }
4147
4148   if (strncmp("reg-names", option, optionlen) == 0
4149       && strlen("reg-names") == optionlen)
4150     {
4151       /* We check both ABI and ARCH here unconditionally, so
4152          that "numeric" will do the desirable thing: select
4153          numeric register names for all registers.  Other than
4154          that, a given name probably won't match both.  */
4155       chosen_abi = choose_abi_by_name (val, vallen);
4156       if (chosen_abi != NULL)
4157         {
4158           mips_gpr_names = chosen_abi->gpr_names;
4159           mips_fpr_names = chosen_abi->fpr_names;
4160         }
4161       chosen_arch = choose_arch_by_name (val, vallen);
4162       if (chosen_arch != NULL)
4163         {
4164           mips_cp0_names = chosen_arch->cp0_names;
4165           mips_cp0sel_names = chosen_arch->cp0sel_names;
4166           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4167           mips_hwr_names = chosen_arch->hwr_names;
4168         }
4169       return;
4170     }
4171
4172   /* Invalid option.  */
4173 }
4174
4175 static void
4176 parse_mips_dis_options (const char *options)
4177 {
4178   const char *option_end;
4179
4180   if (options == NULL)
4181     return;
4182
4183   while (*options != '\0')
4184     {
4185       /* Skip empty options.  */
4186       if (*options == ',')
4187         {
4188           options++;
4189           continue;
4190         }
4191
4192       /* We know that *options is neither NUL or a comma.  */
4193       option_end = options + 1;
4194       while (*option_end != ',' && *option_end != '\0')
4195         option_end++;
4196
4197       parse_mips_dis_option (options, option_end - options);
4198
4199       /* Go on to the next one.  If option_end points to a comma, it
4200          will be skipped above.  */
4201       options = option_end;
4202     }
4203 }
4204
4205 static const struct mips_cp0sel_name *
4206 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
4207                          unsigned int len,
4208                          unsigned int cp0reg,
4209                          unsigned int sel)
4210 {
4211   unsigned int i;
4212
4213   for (i = 0; i < len; i++)
4214     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
4215       return &names[i];
4216   return NULL;
4217 }
4218 \f
4219 /* Print insn arguments for 32/64-bit code.  */
4220
4221 static void
4222 print_insn_args (const char *d,
4223                  register unsigned long int l,
4224                  bfd_vma pc,
4225                  struct disassemble_info *info,
4226                  const struct mips_opcode *opp)
4227 {
4228   int op, delta;
4229   unsigned int lsb, msb, msbd;
4230
4231   lsb = 0;
4232
4233   for (; *d != '\0'; d++)
4234     {
4235       switch (*d)
4236         {
4237         case ',':
4238         case '(':
4239         case ')':
4240         case '[':
4241         case ']':
4242           (*info->fprintf_func) (info->stream, "%c", *d);
4243           break;
4244
4245         case '+':
4246           /* Extension character; switch for second char.  */
4247           d++;
4248           switch (*d)
4249             {
4250             case '\0':
4251               /* xgettext:c-format */
4252               (*info->fprintf_func) (info->stream,
4253                                      _("# internal error, incomplete extension sequence (+)"));
4254               return;
4255
4256             case 'A':
4257               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
4258               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4259               break;
4260
4261             case 'B':
4262               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
4263               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4264               break;
4265
4266             case '1':
4267               (*info->fprintf_func) (info->stream, "0x%lx",
4268                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
4269               break;
4270
4271             case '2':
4272               (*info->fprintf_func) (info->stream, "0x%lx",
4273                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
4274               break;
4275
4276             case '3':
4277               (*info->fprintf_func) (info->stream, "0x%lx",
4278                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
4279               break;
4280
4281             case '4':
4282               (*info->fprintf_func) (info->stream, "0x%lx",
4283                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
4284               break;
4285
4286         case '5': /* 5-bit signed immediate in bit 16 */
4287             delta = ((l >> OP_SH_RT) & OP_MASK_RT);
4288             if (delta & 0x10) { /* test sign bit */
4289                 delta |= ~OP_MASK_RT;
4290             }
4291             (*info->fprintf_func) (info->stream, "%d", delta);
4292             break;
4293
4294         case '6':
4295             (*info->fprintf_func) (info->stream, "0x%lx",
4296                     (l >> OP_SH_2BIT) & OP_MASK_2BIT);
4297             break;
4298
4299         case '7':
4300             (*info->fprintf_func) (info->stream, "0x%lx",
4301                     (l >> OP_SH_3BIT) & OP_MASK_3BIT);
4302             break;
4303
4304         case '8':
4305             (*info->fprintf_func) (info->stream, "0x%lx",
4306                     (l >> OP_SH_4BIT) & OP_MASK_4BIT);
4307             break;
4308
4309         case '9':
4310             (*info->fprintf_func) (info->stream, "0x%lx",
4311                     (l >> OP_SH_5BIT) & OP_MASK_5BIT);
4312             break;
4313
4314         case ':':
4315             (*info->fprintf_func) (info->stream, "0x%lx",
4316                     (l >> OP_SH_1BIT) & OP_MASK_1BIT);
4317             break;
4318
4319         case '!': /* 10-bit pc-relative target in bit 11 */
4320             delta = ((l >> OP_SH_10BIT) & OP_MASK_10BIT);
4321             if (delta & 0x200) { /* test sign bit */
4322                 delta |= ~OP_MASK_10BIT;
4323             }
4324             info->target = (delta << 2) + pc + INSNLEN;
4325             (*info->print_address_func) (info->target, info);
4326             break;
4327
4328         case '~':
4329             (*info->fprintf_func) (info->stream, "0");
4330             break;
4331
4332         case '@':
4333             (*info->fprintf_func) (info->stream, "0x%lx",
4334                     ((l >> OP_SH_1_TO_4) & OP_MASK_1_TO_4)+1);
4335             break;
4336
4337         case '^': /* 10-bit signed immediate << 0 in bit 16 */
4338             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4339             if (delta & 0x200) { /* test sign bit */
4340                 delta |= ~OP_MASK_IMM10;
4341             }
4342             (*info->fprintf_func) (info->stream, "%d", delta);
4343             break;
4344
4345         case '#': /* 10-bit signed immediate << 1 in bit 16 */
4346             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4347             if (delta & 0x200) { /* test sign bit */
4348                 delta |= ~OP_MASK_IMM10;
4349             }
4350             (*info->fprintf_func) (info->stream, "%d", delta << 1);
4351             break;
4352
4353         case '$': /* 10-bit signed immediate << 2 in bit 16 */
4354             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4355             if (delta & 0x200) { /* test sign bit */
4356                 delta |= ~OP_MASK_IMM10;
4357             }
4358             (*info->fprintf_func) (info->stream, "%d", delta << 2);
4359             break;
4360
4361         case '%': /* 10-bit signed immediate << 3 in bit 16 */
4362             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4363             if (delta & 0x200) { /* test sign bit */
4364                 delta |= ~OP_MASK_IMM10;
4365             }
4366             (*info->fprintf_func) (info->stream, "%d", delta << 3);
4367             break;
4368
4369             case 'C':
4370             case 'H':
4371               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
4372               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4373               break;
4374
4375             case 'D':
4376               {
4377                 const struct mips_cp0sel_name *n;
4378                 unsigned int cp0reg, sel;
4379
4380                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
4381                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4382
4383                 /* CP0 register including 'sel' code for mtcN (et al.), to be
4384                    printed textually if known.  If not known, print both
4385                    CP0 register name and sel numerically since CP0 register
4386                    with sel 0 may have a name unrelated to register being
4387                    printed.  */
4388                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4389                                             mips_cp0sel_names_len, cp0reg, sel);
4390                 if (n != NULL)
4391                   (*info->fprintf_func) (info->stream, "%s", n->name);
4392                 else
4393                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4394                 break;
4395               }
4396
4397             case 'E':
4398               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
4399               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4400               break;
4401
4402             case 'F':
4403               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
4404               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4405               break;
4406
4407             case 'G':
4408               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
4409               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4410               break;
4411
4412             case 'o':
4413                 switch (*(d+1)) {
4414                 case '1':
4415                     d++;
4416                     delta = l & ((1 << 18) - 1);
4417                     if (delta & 0x20000) {
4418                         delta |= ~0x1ffff;
4419                     }
4420                     break;
4421                 case '2':
4422                     d++;
4423                     delta = l & ((1 << 19) - 1);
4424                     if (delta & 0x40000) {
4425                         delta |= ~0x3ffff;
4426                     }
4427                     break;
4428                 default:
4429                     delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
4430                     if (delta & 0x8000) {
4431                         delta |= ~0xffff;
4432                     }
4433                 }
4434
4435                 (*info->fprintf_func) (info->stream, "%d", delta);
4436                 break;
4437
4438             case 'p':
4439                 /* Sign extend the displacement with 26 bits.  */
4440                 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
4441                 if (delta & 0x2000000) {
4442                     delta |= ~0x3FFFFFF;
4443                 }
4444                 info->target = (delta << 2) + pc + INSNLEN;
4445                 (*info->print_address_func) (info->target, info);
4446                 break;
4447
4448             case 't': /* Coprocessor 0 reg name */
4449               (*info->fprintf_func) (info->stream, "%s",
4450                                      mips_cp0_names[(l >> OP_SH_RT) &
4451                                                      OP_MASK_RT]);
4452               break;
4453
4454             case 'T': /* Coprocessor 0 reg name */
4455               {
4456                 const struct mips_cp0sel_name *n;
4457                 unsigned int cp0reg, sel;
4458
4459                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
4460                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4461
4462                 /* CP0 register including 'sel' code for mftc0, to be
4463                    printed textually if known.  If not known, print both
4464                    CP0 register name and sel numerically since CP0 register
4465                    with sel 0 may have a name unrelated to register being
4466                    printed.  */
4467                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4468                                             mips_cp0sel_names_len, cp0reg, sel);
4469                 if (n != NULL)
4470                   (*info->fprintf_func) (info->stream, "%s", n->name);
4471                 else
4472                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4473                 break;
4474               }
4475
4476         case 'd':
4477             (*info->fprintf_func) (info->stream, "%s",
4478                     mips_wr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4479             break;
4480
4481         case 'e':
4482             (*info->fprintf_func) (info->stream, "%s",
4483                     mips_wr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4484             break;
4485
4486         case 'f':
4487             (*info->fprintf_func) (info->stream, "%s",
4488                     mips_wr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4489             break;
4490
4491         case 'g':
4492             (*info->fprintf_func) (info->stream, "%s",
4493                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR11)
4494                                                       & OP_MASK_MSACR11]);
4495             break;
4496
4497         case 'h':
4498             (*info->fprintf_func) (info->stream, "%s",
4499                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR6)
4500                                                       & OP_MASK_MSACR6]);
4501             break;
4502
4503         case 'i':
4504             (*info->fprintf_func) (info->stream, "%s",
4505                     mips_gpr_names[(l >> OP_SH_GPR) & OP_MASK_GPR]);
4506             break;
4507
4508             default:
4509               /* xgettext:c-format */
4510               (*info->fprintf_func) (info->stream,
4511                                      _("# internal error, undefined extension sequence (+%c)"),
4512                                      *d);
4513               return;
4514             }
4515           break;
4516
4517         case '2':
4518           (*info->fprintf_func) (info->stream, "0x%lx",
4519                                  (l >> OP_SH_BP) & OP_MASK_BP);
4520           break;
4521
4522         case '3':
4523           (*info->fprintf_func) (info->stream, "0x%lx",
4524                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
4525           break;
4526
4527         case '4':
4528           (*info->fprintf_func) (info->stream, "0x%lx",
4529                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
4530           break;
4531
4532         case '5':
4533           (*info->fprintf_func) (info->stream, "0x%lx",
4534                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
4535           break;
4536
4537         case '6':
4538           (*info->fprintf_func) (info->stream, "0x%lx",
4539                                  (l >> OP_SH_RS) & OP_MASK_RS);
4540           break;
4541
4542         case '7':
4543           (*info->fprintf_func) (info->stream, "$ac%ld",
4544                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
4545           break;
4546
4547         case '8':
4548           (*info->fprintf_func) (info->stream, "0x%lx",
4549                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
4550           break;
4551
4552         case '9':
4553           (*info->fprintf_func) (info->stream, "$ac%ld",
4554                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
4555           break;
4556
4557         case '0': /* dsp 6-bit signed immediate in bit 20 */
4558           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
4559           if (delta & 0x20) /* test sign bit */
4560             delta |= ~OP_MASK_DSPSFT;
4561           (*info->fprintf_func) (info->stream, "%d", delta);
4562           break;
4563
4564         case ':': /* dsp 7-bit signed immediate in bit 19 */
4565           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
4566           if (delta & 0x40) /* test sign bit */
4567             delta |= ~OP_MASK_DSPSFT_7;
4568           (*info->fprintf_func) (info->stream, "%d", delta);
4569           break;
4570
4571         case '\'':
4572           (*info->fprintf_func) (info->stream, "0x%lx",
4573                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
4574           break;
4575
4576         case '@': /* dsp 10-bit signed immediate in bit 16 */
4577           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4578           if (delta & 0x200) /* test sign bit */
4579             delta |= ~OP_MASK_IMM10;
4580           (*info->fprintf_func) (info->stream, "%d", delta);
4581           break;
4582
4583         case '!':
4584           (*info->fprintf_func) (info->stream, "%ld",
4585                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
4586           break;
4587
4588         case '$':
4589           (*info->fprintf_func) (info->stream, "%ld",
4590                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
4591           break;
4592
4593         case '*':
4594           (*info->fprintf_func) (info->stream, "$ac%ld",
4595                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
4596           break;
4597
4598         case '&':
4599           (*info->fprintf_func) (info->stream, "$ac%ld",
4600                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
4601           break;
4602
4603         case 'g':
4604           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
4605           (*info->fprintf_func) (info->stream, "$%ld",
4606                                  (l >> OP_SH_RD) & OP_MASK_RD);
4607           break;
4608
4609         case 's':
4610         case 'b':
4611         case 'r':
4612         case 'v':
4613           (*info->fprintf_func) (info->stream, "%s",
4614                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
4615           break;
4616
4617         case 't':
4618         case 'w':
4619           (*info->fprintf_func) (info->stream, "%s",
4620                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4621           break;
4622
4623         case 'i':
4624         case 'u':
4625           (*info->fprintf_func) (info->stream, "0x%lx",
4626                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
4627           break;
4628
4629         case 'j': /* Same as i, but sign-extended.  */
4630         case 'o':
4631             delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4632
4633           if (delta & 0x8000)
4634             delta |= ~0xffff;
4635           (*info->fprintf_func) (info->stream, "%d",
4636                                  delta);
4637           break;
4638
4639         case 'h':
4640           (*info->fprintf_func) (info->stream, "0x%x",
4641                                  (unsigned int) ((l >> OP_SH_PREFX)
4642                                                  & OP_MASK_PREFX));
4643           break;
4644
4645         case 'k':
4646           (*info->fprintf_func) (info->stream, "0x%x",
4647                                  (unsigned int) ((l >> OP_SH_CACHE)
4648                                                  & OP_MASK_CACHE));
4649           break;
4650
4651         case 'a':
4652           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
4653                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
4654           /* For gdb disassembler, force odd address on jalx.  */
4655           if (info->flavour == bfd_target_unknown_flavour
4656               && strcmp (opp->name, "jalx") == 0)
4657             info->target |= 1;
4658           (*info->print_address_func) (info->target, info);
4659           break;
4660
4661         case 'p':
4662           /* Sign extend the displacement.  */
4663           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4664           if (delta & 0x8000)
4665             delta |= ~0xffff;
4666           info->target = (delta << 2) + pc + INSNLEN;
4667           (*info->print_address_func) (info->target, info);
4668           break;
4669
4670         case 'd':
4671           (*info->fprintf_func) (info->stream, "%s",
4672                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4673           break;
4674
4675         case 'U':
4676           {
4677             /* First check for both rd and rt being equal.  */
4678             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
4679             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
4680               (*info->fprintf_func) (info->stream, "%s",
4681                                      mips_gpr_names[reg]);
4682             else
4683               {
4684                 /* If one is zero use the other.  */
4685                 if (reg == 0)
4686                   (*info->fprintf_func) (info->stream, "%s",
4687                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4688                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
4689                   (*info->fprintf_func) (info->stream, "%s",
4690                                          mips_gpr_names[reg]);
4691                 else /* Bogus, result depends on processor.  */
4692                   (*info->fprintf_func) (info->stream, "%s or %s",
4693                                          mips_gpr_names[reg],
4694                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4695               }
4696           }
4697           break;
4698
4699         case 'z':
4700           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4701           break;
4702
4703         case '<':
4704           (*info->fprintf_func) (info->stream, "0x%lx",
4705                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
4706           break;
4707
4708         case 'c':
4709           (*info->fprintf_func) (info->stream, "0x%lx",
4710                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
4711           break;
4712
4713         case 'q':
4714           (*info->fprintf_func) (info->stream, "0x%lx",
4715                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
4716           break;
4717
4718         case 'C':
4719           (*info->fprintf_func) (info->stream, "0x%lx",
4720                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
4721           break;
4722
4723         case 'B':
4724           (*info->fprintf_func) (info->stream, "0x%lx",
4725
4726                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
4727           break;
4728
4729         case 'J':
4730           (*info->fprintf_func) (info->stream, "0x%lx",
4731                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
4732           break;
4733
4734         case 'S':
4735         case 'V':
4736           (*info->fprintf_func) (info->stream, "%s",
4737                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4738           break;
4739
4740         case 'T':
4741         case 'W':
4742           (*info->fprintf_func) (info->stream, "%s",
4743                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4744           break;
4745
4746         case 'D':
4747           (*info->fprintf_func) (info->stream, "%s",
4748                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4749           break;
4750
4751         case 'R':
4752           (*info->fprintf_func) (info->stream, "%s",
4753                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
4754           break;
4755
4756         case 'E':
4757           /* Coprocessor register for lwcN instructions, et al.
4758
4759              Note that there is no load/store cp0 instructions, and
4760              that FPU (cp1) instructions disassemble this field using
4761              'T' format.  Therefore, until we gain understanding of
4762              cp2 register names, we can simply print the register
4763              numbers.  */
4764           (*info->fprintf_func) (info->stream, "$%ld",
4765                                  (l >> OP_SH_RT) & OP_MASK_RT);
4766           break;
4767
4768         case 'G':
4769           /* Coprocessor register for mtcN instructions, et al.  Note
4770              that FPU (cp1) instructions disassemble this field using
4771              'S' format.  Therefore, we only need to worry about cp0,
4772              cp2, and cp3.  */
4773           op = (l >> OP_SH_OP) & OP_MASK_OP;
4774           if (op == OP_OP_COP0)
4775             (*info->fprintf_func) (info->stream, "%s",
4776                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4777           else
4778             (*info->fprintf_func) (info->stream, "$%ld",
4779                                    (l >> OP_SH_RD) & OP_MASK_RD);
4780           break;
4781
4782         case 'K':
4783           (*info->fprintf_func) (info->stream, "%s",
4784                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4785           break;
4786
4787         case 'N':
4788           (*info->fprintf_func) (info->stream,
4789                                  ((opp->pinfo & (FP_D | FP_S)) != 0
4790                                   ? "$fcc%ld" : "$cc%ld"),
4791                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
4792           break;
4793
4794         case 'M':
4795           (*info->fprintf_func) (info->stream, "$fcc%ld",
4796                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
4797           break;
4798
4799         case 'P':
4800           (*info->fprintf_func) (info->stream, "%ld",
4801                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
4802           break;
4803
4804         case 'e':
4805           (*info->fprintf_func) (info->stream, "%ld",
4806                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
4807           break;
4808
4809         case '%':
4810           (*info->fprintf_func) (info->stream, "%ld",
4811                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
4812           break;
4813
4814         case 'H':
4815           (*info->fprintf_func) (info->stream, "%ld",
4816                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
4817           break;
4818
4819         case 'O':
4820           (*info->fprintf_func) (info->stream, "%ld",
4821                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
4822           break;
4823
4824         case 'Q':
4825           {
4826             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
4827
4828             if ((vsel & 0x10) == 0)
4829               {
4830                 int fmt;
4831
4832                 vsel &= 0x0f;
4833                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
4834                   if ((vsel & 1) == 0)
4835                     break;
4836                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
4837                                        (l >> OP_SH_FT) & OP_MASK_FT,
4838                                        vsel >> 1);
4839               }
4840             else if ((vsel & 0x08) == 0)
4841               {
4842                 (*info->fprintf_func) (info->stream, "$v%ld",
4843                                        (l >> OP_SH_FT) & OP_MASK_FT);
4844               }
4845             else
4846               {
4847                 (*info->fprintf_func) (info->stream, "0x%lx",
4848                                        (l >> OP_SH_FT) & OP_MASK_FT);
4849               }
4850           }
4851           break;
4852
4853         case 'X':
4854           (*info->fprintf_func) (info->stream, "$v%ld",
4855                                  (l >> OP_SH_FD) & OP_MASK_FD);
4856           break;
4857
4858         case 'Y':
4859           (*info->fprintf_func) (info->stream, "$v%ld",
4860                                  (l >> OP_SH_FS) & OP_MASK_FS);
4861           break;
4862
4863         case 'Z':
4864           (*info->fprintf_func) (info->stream, "$v%ld",
4865                                  (l >> OP_SH_FT) & OP_MASK_FT);
4866           break;
4867
4868         default:
4869           /* xgettext:c-format */
4870           (*info->fprintf_func) (info->stream,
4871                                  _("# internal error, undefined modifier(%c)"),
4872                                  *d);
4873           return;
4874         }
4875     }
4876 }
4877 \f
4878 /* Check if the object uses NewABI conventions.  */
4879 #if 0
4880 static int
4881 is_newabi (header)
4882      Elf_Internal_Ehdr *header;
4883 {
4884   /* There are no old-style ABIs which use 64-bit ELF.  */
4885   if (header->e_ident[EI_CLASS] == ELFCLASS64)
4886     return 1;
4887
4888   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
4889   if ((header->e_flags & EF_MIPS_ABI2) != 0)
4890     return 1;
4891
4892   return 0;
4893 }
4894 #endif
4895 \f
4896 /* Print the mips instruction at address MEMADDR in debugged memory,
4897    on using INFO.  Returns length of the instruction, in bytes, which is
4898    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
4899    this is little-endian code.  */
4900
4901 static int
4902 print_insn_mips (bfd_vma memaddr,
4903                  unsigned long int word,
4904                  struct disassemble_info *info)
4905 {
4906   const struct mips_opcode *op;
4907   static bfd_boolean init = 0;
4908   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4909
4910   /* Build a hash table to shorten the search time.  */
4911   if (! init)
4912     {
4913       unsigned int i;
4914
4915       for (i = 0; i <= OP_MASK_OP; i++)
4916         {
4917           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4918             {
4919               if (op->pinfo == INSN_MACRO
4920                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4921                 continue;
4922               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4923                 {
4924                   mips_hash[i] = op;
4925                   break;
4926                 }
4927             }
4928         }
4929
4930       init = 1;
4931     }
4932
4933   info->bytes_per_chunk = INSNLEN;
4934   info->display_endian = info->endian;
4935   info->insn_info_valid = 1;
4936   info->branch_delay_insns = 0;
4937   info->data_size = 0;
4938   info->insn_type = dis_nonbranch;
4939   info->target = 0;
4940   info->target2 = 0;
4941
4942   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4943   if (op != NULL)
4944     {
4945       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4946         {
4947           if (op->pinfo != INSN_MACRO
4948               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4949               && (word & op->mask) == op->match)
4950             {
4951               const char *d;
4952
4953               /* We always allow to disassemble the jalx instruction.  */
4954               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4955                   && strcmp (op->name, "jalx"))
4956                 continue;
4957
4958               if (strcmp(op->name, "bovc") == 0
4959                   || strcmp(op->name, "bnvc") == 0) {
4960                   if (((word >> OP_SH_RS) & OP_MASK_RS) <
4961                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4962                       continue;
4963                   }
4964               }
4965               if (strcmp(op->name, "bgezc") == 0
4966                   || strcmp(op->name, "bltzc") == 0
4967                   || strcmp(op->name, "bgezalc") == 0
4968                   || strcmp(op->name, "bltzalc") == 0) {
4969                   if (((word >> OP_SH_RS) & OP_MASK_RS) !=
4970                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4971                       continue;
4972                   }
4973               }
4974
4975               /* Figure out instruction type and branch delay information.  */
4976               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4977                 {
4978                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4979                     info->insn_type = dis_jsr;
4980                   else
4981                     info->insn_type = dis_branch;
4982                   info->branch_delay_insns = 1;
4983                 }
4984               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4985                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4986                 {
4987                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4988                     info->insn_type = dis_condjsr;
4989                   else
4990                     info->insn_type = dis_condbranch;
4991                   info->branch_delay_insns = 1;
4992                 }
4993               else if ((op->pinfo & (INSN_STORE_MEMORY
4994                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4995                 info->insn_type = dis_dref;
4996
4997               (*info->fprintf_func) (info->stream, "%s", op->name);
4998
4999               d = op->args;
5000               if (d != NULL && *d != '\0')
5001                 {
5002                   (*info->fprintf_func) (info->stream, "\t");
5003                   print_insn_args (d, word, memaddr, info, op);
5004                 }
5005
5006               return INSNLEN;
5007             }
5008         }
5009     }
5010
5011   /* Handle undefined instructions.  */
5012   info->insn_type = dis_noninsn;
5013   (*info->fprintf_func) (info->stream, "0x%lx", word);
5014   return INSNLEN;
5015 }
5016 \f
5017 /* In an environment where we do not know the symbol type of the
5018    instruction we are forced to assume that the low order bit of the
5019    instructions' address may mark it as a mips16 instruction.  If we
5020    are single stepping, or the pc is within the disassembled function,
5021    this works.  Otherwise, we need a clue.  Sometimes.  */
5022
5023 static int
5024 _print_insn_mips (bfd_vma memaddr,
5025                   struct disassemble_info *info,
5026                   enum bfd_endian endianness)
5027 {
5028   bfd_byte buffer[INSNLEN];
5029   int status;
5030
5031   set_default_mips_dis_options (info);
5032   parse_mips_dis_options (info->disassembler_options);
5033
5034 #if 0
5035 #if 1
5036   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
5037   /* Only a few tools will work this way.  */
5038   if (memaddr & 0x01)
5039     return print_insn_mips16 (memaddr, info);
5040 #endif
5041
5042 #if SYMTAB_AVAILABLE
5043   if (info->mach == bfd_mach_mips16
5044       || (info->flavour == bfd_target_elf_flavour
5045           && info->symbols != NULL
5046           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
5047               == STO_MIPS16)))
5048     return print_insn_mips16 (memaddr, info);
5049 #endif
5050 #endif
5051
5052   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
5053   if (status == 0)
5054     {
5055       unsigned long insn;
5056
5057       if (endianness == BFD_ENDIAN_BIG)
5058         insn = (unsigned long) bfd_getb32 (buffer);
5059       else
5060         insn = (unsigned long) bfd_getl32 (buffer);
5061
5062       return print_insn_mips (memaddr, insn, info);
5063     }
5064   else
5065     {
5066       (*info->memory_error_func) (status, memaddr, info);
5067       return -1;
5068     }
5069 }
5070
5071 int
5072 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
5073 {
5074   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
5075 }
5076
5077 int
5078 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
5079 {
5080   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
5081 }
5082 \f
5083 /* Disassemble mips16 instructions.  */
5084 #if 0
5085 static int
5086 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
5087 {
5088   int status;
5089   bfd_byte buffer[2];
5090   int length;
5091   int insn;
5092   bfd_boolean use_extend;
5093   int extend = 0;
5094   const struct mips_opcode *op, *opend;
5095
5096   info->bytes_per_chunk = 2;
5097   info->display_endian = info->endian;
5098   info->insn_info_valid = 1;
5099   info->branch_delay_insns = 0;
5100   info->data_size = 0;
5101   info->insn_type = dis_nonbranch;
5102   info->target = 0;
5103   info->target2 = 0;
5104
5105   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5106   if (status != 0)
5107     {
5108       (*info->memory_error_func) (status, memaddr, info);
5109       return -1;
5110     }
5111
5112   length = 2;
5113
5114   if (info->endian == BFD_ENDIAN_BIG)
5115     insn = bfd_getb16 (buffer);
5116   else
5117     insn = bfd_getl16 (buffer);
5118
5119   /* Handle the extend opcode specially.  */
5120   use_extend = FALSE;
5121   if ((insn & 0xf800) == 0xf000)
5122     {
5123       use_extend = TRUE;
5124       extend = insn & 0x7ff;
5125
5126       memaddr += 2;
5127
5128       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5129       if (status != 0)
5130         {
5131           (*info->fprintf_func) (info->stream, "extend 0x%x",
5132                                  (unsigned int) extend);
5133           (*info->memory_error_func) (status, memaddr, info);
5134           return -1;
5135         }
5136
5137       if (info->endian == BFD_ENDIAN_BIG)
5138         insn = bfd_getb16 (buffer);
5139       else
5140         insn = bfd_getl16 (buffer);
5141
5142       /* Check for an extend opcode followed by an extend opcode.  */
5143       if ((insn & 0xf800) == 0xf000)
5144         {
5145           (*info->fprintf_func) (info->stream, "extend 0x%x",
5146                                  (unsigned int) extend);
5147           info->insn_type = dis_noninsn;
5148           return length;
5149         }
5150
5151       length += 2;
5152     }
5153
5154   /* FIXME: Should probably use a hash table on the major opcode here.  */
5155
5156   opend = mips16_opcodes + bfd_mips16_num_opcodes;
5157   for (op = mips16_opcodes; op < opend; op++)
5158     {
5159       if (op->pinfo != INSN_MACRO
5160           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
5161           && (insn & op->mask) == op->match)
5162         {
5163           const char *s;
5164
5165           if (strchr (op->args, 'a') != NULL)
5166             {
5167               if (use_extend)
5168                 {
5169                   (*info->fprintf_func) (info->stream, "extend 0x%x",
5170                                          (unsigned int) extend);
5171                   info->insn_type = dis_noninsn;
5172                   return length - 2;
5173                 }
5174
5175               use_extend = FALSE;
5176
5177               memaddr += 2;
5178
5179               status = (*info->read_memory_func) (memaddr, buffer, 2,
5180                                                   info);
5181               if (status == 0)
5182                 {
5183                   use_extend = TRUE;
5184                   if (info->endian == BFD_ENDIAN_BIG)
5185                     extend = bfd_getb16 (buffer);
5186                   else
5187                     extend = bfd_getl16 (buffer);
5188                   length += 2;
5189                 }
5190             }
5191
5192           (*info->fprintf_func) (info->stream, "%s", op->name);
5193           if (op->args[0] != '\0')
5194             (*info->fprintf_func) (info->stream, "\t");
5195
5196           for (s = op->args; *s != '\0'; s++)
5197             {
5198               if (*s == ','
5199                   && s[1] == 'w'
5200                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
5201                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
5202                 {
5203                   /* Skip the register and the comma.  */
5204                   ++s;
5205                   continue;
5206                 }
5207               if (*s == ','
5208                   && s[1] == 'v'
5209                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
5210                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
5211                 {
5212                   /* Skip the register and the comma.  */
5213                   ++s;
5214                   continue;
5215                 }
5216               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
5217                                      info);
5218             }
5219
5220           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
5221             {
5222               info->branch_delay_insns = 1;
5223               if (info->insn_type != dis_jsr)
5224                 info->insn_type = dis_branch;
5225             }
5226
5227           return length;
5228         }
5229     }
5230
5231   if (use_extend)
5232     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
5233   (*info->fprintf_func) (info->stream, "0x%x", insn);
5234   info->insn_type = dis_noninsn;
5235
5236   return length;
5237 }
5238
5239 /* Disassemble an operand for a mips16 instruction.  */
5240
5241 static void
5242 print_mips16_insn_arg (char type,
5243                        const struct mips_opcode *op,
5244                        int l,
5245                        bfd_boolean use_extend,
5246                        int extend,
5247                        bfd_vma memaddr,
5248                        struct disassemble_info *info)
5249 {
5250   switch (type)
5251     {
5252     case ',':
5253     case '(':
5254     case ')':
5255       (*info->fprintf_func) (info->stream, "%c", type);
5256       break;
5257
5258     case 'y':
5259     case 'w':
5260       (*info->fprintf_func) (info->stream, "%s",
5261                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
5262                                                & MIPS16OP_MASK_RY)));
5263       break;
5264
5265     case 'x':
5266     case 'v':
5267       (*info->fprintf_func) (info->stream, "%s",
5268                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
5269                                                & MIPS16OP_MASK_RX)));
5270       break;
5271
5272     case 'z':
5273       (*info->fprintf_func) (info->stream, "%s",
5274                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
5275                                                & MIPS16OP_MASK_RZ)));
5276       break;
5277
5278     case 'Z':
5279       (*info->fprintf_func) (info->stream, "%s",
5280                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
5281                                                & MIPS16OP_MASK_MOVE32Z)));
5282       break;
5283
5284     case '0':
5285       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
5286       break;
5287
5288     case 'S':
5289       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
5290       break;
5291
5292     case 'P':
5293       (*info->fprintf_func) (info->stream, "$pc");
5294       break;
5295
5296     case 'R':
5297       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
5298       break;
5299
5300     case 'X':
5301       (*info->fprintf_func) (info->stream, "%s",
5302                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
5303                                             & MIPS16OP_MASK_REGR32)]);
5304       break;
5305
5306     case 'Y':
5307       (*info->fprintf_func) (info->stream, "%s",
5308                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
5309       break;
5310
5311     case '<':
5312     case '>':
5313     case '[':
5314     case ']':
5315     case '4':
5316     case '5':
5317     case 'H':
5318     case 'W':
5319     case 'D':
5320     case 'j':
5321     case '6':
5322     case '8':
5323     case 'V':
5324     case 'C':
5325     case 'U':
5326     case 'k':
5327     case 'K':
5328     case 'p':
5329     case 'q':
5330     case 'A':
5331     case 'B':
5332     case 'E':
5333       {
5334         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
5335
5336         shift = 0;
5337         signedp = 0;
5338         extbits = 16;
5339         pcrel = 0;
5340         extu = 0;
5341         branch = 0;
5342         switch (type)
5343           {
5344           case '<':
5345             nbits = 3;
5346             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5347             extbits = 5;
5348             extu = 1;
5349             break;
5350           case '>':
5351             nbits = 3;
5352             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5353             extbits = 5;
5354             extu = 1;
5355             break;
5356           case '[':
5357             nbits = 3;
5358             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5359             extbits = 6;
5360             extu = 1;
5361             break;
5362           case ']':
5363             nbits = 3;
5364             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5365             extbits = 6;
5366             extu = 1;
5367             break;
5368           case '4':
5369             nbits = 4;
5370             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
5371             signedp = 1;
5372             extbits = 15;
5373             break;
5374           case '5':
5375             nbits = 5;
5376             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5377             info->insn_type = dis_dref;
5378             info->data_size = 1;
5379             break;
5380           case 'H':
5381             nbits = 5;
5382             shift = 1;
5383             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5384             info->insn_type = dis_dref;
5385             info->data_size = 2;
5386             break;
5387           case 'W':
5388             nbits = 5;
5389             shift = 2;
5390             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5391             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
5392                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
5393               {
5394                 info->insn_type = dis_dref;
5395                 info->data_size = 4;
5396               }
5397             break;
5398           case 'D':
5399             nbits = 5;
5400             shift = 3;
5401             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5402             info->insn_type = dis_dref;
5403             info->data_size = 8;
5404             break;
5405           case 'j':
5406             nbits = 5;
5407             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5408             signedp = 1;
5409             break;
5410           case '6':
5411             nbits = 6;
5412             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5413             break;
5414           case '8':
5415             nbits = 8;
5416             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5417             break;
5418           case 'V':
5419             nbits = 8;
5420             shift = 2;
5421             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5422             /* FIXME: This might be lw, or it might be addiu to $sp or
5423                $pc.  We assume it's load.  */
5424             info->insn_type = dis_dref;
5425             info->data_size = 4;
5426             break;
5427           case 'C':
5428             nbits = 8;
5429             shift = 3;
5430             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5431             info->insn_type = dis_dref;
5432             info->data_size = 8;
5433             break;
5434           case 'U':
5435             nbits = 8;
5436             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5437             extu = 1;
5438             break;
5439           case 'k':
5440             nbits = 8;
5441             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5442             signedp = 1;
5443             break;
5444           case 'K':
5445             nbits = 8;
5446             shift = 3;
5447             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5448             signedp = 1;
5449             break;
5450           case 'p':
5451             nbits = 8;
5452             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5453             signedp = 1;
5454             pcrel = 1;
5455             branch = 1;
5456             info->insn_type = dis_condbranch;
5457             break;
5458           case 'q':
5459             nbits = 11;
5460             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
5461             signedp = 1;
5462             pcrel = 1;
5463             branch = 1;
5464             info->insn_type = dis_branch;
5465             break;
5466           case 'A':
5467             nbits = 8;
5468             shift = 2;
5469             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5470             pcrel = 1;
5471             /* FIXME: This can be lw or la.  We assume it is lw.  */
5472             info->insn_type = dis_dref;
5473             info->data_size = 4;
5474             break;
5475           case 'B':
5476             nbits = 5;
5477             shift = 3;
5478             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5479             pcrel = 1;
5480             info->insn_type = dis_dref;
5481             info->data_size = 8;
5482             break;
5483           case 'E':
5484             nbits = 5;
5485             shift = 2;
5486             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5487             pcrel = 1;
5488             break;
5489           default:
5490             abort ();
5491           }
5492
5493         if (! use_extend)
5494           {
5495             if (signedp && immed >= (1 << (nbits - 1)))
5496               immed -= 1 << nbits;
5497             immed <<= shift;
5498             if ((type == '<' || type == '>' || type == '[' || type == ']')
5499                 && immed == 0)
5500               immed = 8;
5501           }
5502         else
5503           {
5504             if (extbits == 16)
5505               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
5506             else if (extbits == 15)
5507               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
5508             else
5509               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
5510             immed &= (1 << extbits) - 1;
5511             if (! extu && immed >= (1 << (extbits - 1)))
5512               immed -= 1 << extbits;
5513           }
5514
5515         if (! pcrel)
5516           (*info->fprintf_func) (info->stream, "%d", immed);
5517         else
5518           {
5519             bfd_vma baseaddr;
5520
5521             if (branch)
5522               {
5523                 immed *= 2;
5524                 baseaddr = memaddr + 2;
5525               }
5526             else if (use_extend)
5527               baseaddr = memaddr - 2;
5528             else
5529               {
5530                 int status;
5531                 bfd_byte buffer[2];
5532
5533                 baseaddr = memaddr;
5534
5535                 /* If this instruction is in the delay slot of a jr
5536                    instruction, the base address is the address of the
5537                    jr instruction.  If it is in the delay slot of jalr
5538                    instruction, the base address is the address of the
5539                    jalr instruction.  This test is unreliable: we have
5540                    no way of knowing whether the previous word is
5541                    instruction or data.  */
5542                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
5543                                                     info);
5544                 if (status == 0
5545                     && (((info->endian == BFD_ENDIAN_BIG
5546                           ? bfd_getb16 (buffer)
5547                           : bfd_getl16 (buffer))
5548                          & 0xf800) == 0x1800))
5549                   baseaddr = memaddr - 4;
5550                 else
5551                   {
5552                     status = (*info->read_memory_func) (memaddr - 2, buffer,
5553                                                         2, info);
5554                     if (status == 0
5555                         && (((info->endian == BFD_ENDIAN_BIG
5556                               ? bfd_getb16 (buffer)
5557                               : bfd_getl16 (buffer))
5558                              & 0xf81f) == 0xe800))
5559                       baseaddr = memaddr - 2;
5560                   }
5561               }
5562             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
5563             if (pcrel && branch
5564                 && info->flavour == bfd_target_unknown_flavour)
5565               /* For gdb disassembler, maintain odd address.  */
5566               info->target |= 1;
5567             (*info->print_address_func) (info->target, info);
5568           }
5569       }
5570       break;
5571
5572     case 'a':
5573       {
5574         int jalx = l & 0x400;
5575
5576         if (! use_extend)
5577           extend = 0;
5578         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
5579         if (!jalx && info->flavour == bfd_target_unknown_flavour)
5580           /* For gdb disassembler, maintain odd address.  */
5581           l |= 1;
5582       }
5583       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
5584       (*info->print_address_func) (info->target, info);
5585       info->insn_type = dis_jsr;
5586       info->branch_delay_insns = 1;
5587       break;
5588
5589     case 'l':
5590     case 'L':
5591       {
5592         int need_comma, amask, smask;
5593
5594         need_comma = 0;
5595
5596         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5597
5598         amask = (l >> 3) & 7;
5599
5600         if (amask > 0 && amask < 5)
5601           {
5602             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5603             if (amask > 1)
5604               (*info->fprintf_func) (info->stream, "-%s",
5605                                      mips_gpr_names[amask + 3]);
5606             need_comma = 1;
5607           }
5608
5609         smask = (l >> 1) & 3;
5610         if (smask == 3)
5611           {
5612             (*info->fprintf_func) (info->stream, "%s??",
5613                                    need_comma ? "," : "");
5614             need_comma = 1;
5615           }
5616         else if (smask > 0)
5617           {
5618             (*info->fprintf_func) (info->stream, "%s%s",
5619                                    need_comma ? "," : "",
5620                                    mips_gpr_names[16]);
5621             if (smask > 1)
5622               (*info->fprintf_func) (info->stream, "-%s",
5623                                      mips_gpr_names[smask + 15]);
5624             need_comma = 1;
5625           }
5626
5627         if (l & 1)
5628           {
5629             (*info->fprintf_func) (info->stream, "%s%s",
5630                                    need_comma ? "," : "",
5631                                    mips_gpr_names[31]);
5632             need_comma = 1;
5633           }
5634
5635         if (amask == 5 || amask == 6)
5636           {
5637             (*info->fprintf_func) (info->stream, "%s$f0",
5638                                    need_comma ? "," : "");
5639             if (amask == 6)
5640               (*info->fprintf_func) (info->stream, "-$f1");
5641           }
5642       }
5643       break;
5644
5645     case 'm':
5646     case 'M':
5647       /* MIPS16e save/restore.  */
5648       {
5649       int need_comma = 0;
5650       int amask, args, statics;
5651       int nsreg, smask;
5652       int framesz;
5653       int i, j;
5654
5655       l = l & 0x7f;
5656       if (use_extend)
5657         l |= extend << 16;
5658
5659       amask = (l >> 16) & 0xf;
5660       if (amask == MIPS16_ALL_ARGS)
5661         {
5662           args = 4;
5663           statics = 0;
5664         }
5665       else if (amask == MIPS16_ALL_STATICS)
5666         {
5667           args = 0;
5668           statics = 4;
5669         }
5670       else
5671         {
5672           args = amask >> 2;
5673           statics = amask & 3;
5674         }
5675
5676       if (args > 0) {
5677           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5678           if (args > 1)
5679             (*info->fprintf_func) (info->stream, "-%s",
5680                                    mips_gpr_names[4 + args - 1]);
5681           need_comma = 1;
5682       }
5683
5684       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
5685       if (framesz == 0 && !use_extend)
5686         framesz = 128;
5687
5688       (*info->fprintf_func) (info->stream, "%s%d",
5689                              need_comma ? "," : "",
5690                              framesz);
5691
5692       if (l & 0x40)                   /* $ra */
5693         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
5694
5695       nsreg = (l >> 24) & 0x7;
5696       smask = 0;
5697       if (l & 0x20)                   /* $s0 */
5698         smask |= 1 << 0;
5699       if (l & 0x10)                   /* $s1 */
5700         smask |= 1 << 1;
5701       if (nsreg > 0)                  /* $s2-$s8 */
5702         smask |= ((1 << nsreg) - 1) << 2;
5703
5704       /* Find first set static reg bit.  */
5705       for (i = 0; i < 9; i++)
5706         {
5707           if (smask & (1 << i))
5708             {
5709               (*info->fprintf_func) (info->stream, ",%s",
5710                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
5711               /* Skip over string of set bits.  */
5712               for (j = i; smask & (2 << j); j++)
5713                 continue;
5714               if (j > i)
5715                 (*info->fprintf_func) (info->stream, "-%s",
5716                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
5717               i = j + 1;
5718             }
5719         }
5720
5721       /* Statics $ax - $a3.  */
5722       if (statics == 1)
5723         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
5724       else if (statics > 0)
5725         (*info->fprintf_func) (info->stream, ",%s-%s",
5726                                mips_gpr_names[7 - statics + 1],
5727                                mips_gpr_names[7]);
5728       }
5729       break;
5730
5731     default:
5732       /* xgettext:c-format */
5733       (*info->fprintf_func)
5734         (info->stream,
5735          _("# internal disassembler error, unrecognised modifier (%c)"),
5736          type);
5737       abort ();
5738     }
5739 }
5740
5741 void
5742 print_mips_disassembler_options (FILE *stream)
5743 {
5744   unsigned int i;
5745
5746   fprintf (stream, _("\n\
5747 The following MIPS specific disassembler options are supported for use\n\
5748 with the -M switch (multiple options should be separated by commas):\n"));
5749
5750   fprintf (stream, _("\n\
5751   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
5752                            Default: based on binary being disassembled.\n"));
5753
5754   fprintf (stream, _("\n\
5755   fpr-names=ABI            Print FPR names according to specified ABI.\n\
5756                            Default: numeric.\n"));
5757
5758   fprintf (stream, _("\n\
5759   cp0-names=ARCH           Print CP0 register names according to\n\
5760                            specified architecture.\n\
5761                            Default: based on binary being disassembled.\n"));
5762
5763   fprintf (stream, _("\n\
5764   hwr-names=ARCH           Print HWR names according to specified\n\
5765                            architecture.\n\
5766                            Default: based on binary being disassembled.\n"));
5767
5768   fprintf (stream, _("\n\
5769   reg-names=ABI            Print GPR and FPR names according to\n\
5770                            specified ABI.\n"));
5771
5772   fprintf (stream, _("\n\
5773   reg-names=ARCH           Print CP0 register and HWR names according to\n\
5774                            specified architecture.\n"));
5775
5776   fprintf (stream, _("\n\
5777   For the options above, the following values are supported for \"ABI\":\n\
5778    "));
5779   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
5780     fprintf (stream, " %s", mips_abi_choices[i].name);
5781   fprintf (stream, _("\n"));
5782
5783   fprintf (stream, _("\n\
5784   For the options above, The following values are supported for \"ARCH\":\n\
5785    "));
5786   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
5787     if (*mips_arch_choices[i].name != '\0')
5788       fprintf (stream, " %s", mips_arch_choices[i].name);
5789   fprintf (stream, _("\n"));
5790
5791   fprintf (stream, _("\n"));
5792 }
5793 #endif