kernel/sound/soc/codecs/wm8990.c

   1 /*
   2  * wm8990.c  --  WM8990 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008 Wolfson Microelectronics PLC.
   5  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/initval.h>
  27 #include <sound/tlv.h>
  28 #include <asm/div64.h>
  29
  30 #include "wm8990.h"
  31
  32 /* codec private data */
  33 struct wm8990_priv {
  34         struct regmap *regmap;
  35         unsigned int sysclk;
  36         unsigned int pcmclk;
  37 };
  38
  39 static bool wm8990_volatile_register(struct device *dev, unsigned int reg)
  40 {
  41         switch (reg) {
  42         case WM8990_RESET:
  43                 return 1;
  44         default:
  45                 return 0;
  46         }
  47 }
  48
  49 static const struct reg_default wm8990_reg_defaults[] = {
  50         {  1, 0x0000 },     /* R1  - Power Management (1) */
  51         {  2, 0x6000 },     /* R2  - Power Management (2) */
  52         {  3, 0x0000 },     /* R3  - Power Management (3) */
  53         {  4, 0x4050 },     /* R4  - Audio Interface (1) */
  54         {  5, 0x4000 },     /* R5  - Audio Interface (2) */
  55         {  6, 0x01C8 },     /* R6  - Clocking (1) */
  56         {  7, 0x0000 },     /* R7  - Clocking (2) */
  57         {  8, 0x0040 },     /* R8  - Audio Interface (3) */
  58         {  9, 0x0040 },     /* R9  - Audio Interface (4) */
  59         { 10, 0x0004 },     /* R10 - DAC CTRL */
  60         { 11, 0x00C0 },     /* R11 - Left DAC Digital Volume */
  61         { 12, 0x00C0 },     /* R12 - Right DAC Digital Volume */
  62         { 13, 0x0000 },     /* R13 - Digital Side Tone */
  63         { 14, 0x0100 },     /* R14 - ADC CTRL */
  64         { 15, 0x00C0 },     /* R15 - Left ADC Digital Volume */
  65         { 16, 0x00C0 },     /* R16 - Right ADC Digital Volume */
  66
  67         { 18, 0x0000 },     /* R18 - GPIO CTRL 1 */
  68         { 19, 0x1000 },     /* R19 - GPIO1 & GPIO2 */
  69         { 20, 0x1010 },     /* R20 - GPIO3 & GPIO4 */
  70         { 21, 0x1010 },     /* R21 - GPIO5 & GPIO6 */
  71         { 22, 0x8000 },     /* R22 - GPIOCTRL 2 */
  72         { 23, 0x0800 },     /* R23 - GPIO_POL */
  73         { 24, 0x008B },     /* R24 - Left Line Input 1&2 Volume */
  74         { 25, 0x008B },     /* R25 - Left Line Input 3&4 Volume */
  75         { 26, 0x008B },     /* R26 - Right Line Input 1&2 Volume */
  76         { 27, 0x008B },     /* R27 - Right Line Input 3&4 Volume */
  77         { 28, 0x0000 },     /* R28 - Left Output Volume */
  78         { 29, 0x0000 },     /* R29 - Right Output Volume */
  79         { 30, 0x0066 },     /* R30 - Line Outputs Volume */
  80         { 31, 0x0022 },     /* R31 - Out3/4 Volume */
  81         { 32, 0x0079 },     /* R32 - Left OPGA Volume */
  82         { 33, 0x0079 },     /* R33 - Right OPGA Volume */
  83         { 34, 0x0003 },     /* R34 - Speaker Volume */
  84         { 35, 0x0003 },     /* R35 - ClassD1 */
  85
  86         { 37, 0x0100 },     /* R37 - ClassD3 */
  87         { 38, 0x0079 },     /* R38 - ClassD4 */
  88         { 39, 0x0000 },     /* R39 - Input Mixer1 */
  89         { 40, 0x0000 },     /* R40 - Input Mixer2 */
  90         { 41, 0x0000 },     /* R41 - Input Mixer3 */
  91         { 42, 0x0000 },     /* R42 - Input Mixer4 */
  92         { 43, 0x0000 },     /* R43 - Input Mixer5 */
  93         { 44, 0x0000 },     /* R44 - Input Mixer6 */
  94         { 45, 0x0000 },     /* R45 - Output Mixer1 */
  95         { 46, 0x0000 },     /* R46 - Output Mixer2 */
  96         { 47, 0x0000 },     /* R47 - Output Mixer3 */
  97         { 48, 0x0000 },     /* R48 - Output Mixer4 */
  98         { 49, 0x0000 },     /* R49 - Output Mixer5 */
  99         { 50, 0x0000 },     /* R50 - Output Mixer6 */
 100         { 51, 0x0180 },     /* R51 - Out3/4 Mixer */
 101         { 52, 0x0000 },     /* R52 - Line Mixer1 */
 102         { 53, 0x0000 },     /* R53 - Line Mixer2 */
 103         { 54, 0x0000 },     /* R54 - Speaker Mixer */
 104         { 55, 0x0000 },     /* R55 - Additional Control */
 105         { 56, 0x0000 },     /* R56 - AntiPOP1 */
 106         { 57, 0x0000 },     /* R57 - AntiPOP2 */
 107         { 58, 0x0000 },     /* R58 - MICBIAS */
 108
 109         { 60, 0x0008 },     /* R60 - PLL1 */
 110         { 61, 0x0031 },     /* R61 - PLL2 */
 111         { 62, 0x0026 },     /* R62 - PLL3 */
 112 };
 113
 114 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
 115
 116 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
 117
 118 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
 119
 120 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
 121
 122 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
 123
 124 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
 125
 126 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
 127
 128 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
 129
 130 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
 131
 132 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 133         struct snd_ctl_elem_value *ucontrol)
 134 {
 135         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 136         struct soc_mixer_control *mc =
 137                 (struct soc_mixer_control *)kcontrol->private_value;
 138         int reg = mc->reg;
 139         int ret;
 140         u16 val;
 141
 142         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 143         if (ret < 0)
 144                 return ret;
 145
 146         /* now hit the volume update bits (always bit 8) */
 147         val = snd_soc_read(codec, reg);
 148         return snd_soc_write(codec, reg, val | 0x0100);
 149 }
 150
 151 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
 152         tlv_array) \
 153         SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
 154                 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
 155
 156
 157 static const char *wm8990_digital_sidetone[] =
 158         {"None", "Left ADC", "Right ADC", "Reserved"};
 159
 160 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
 161                             WM8990_DIGITAL_SIDE_TONE,
 162                             WM8990_ADC_TO_DACL_SHIFT,
 163                             wm8990_digital_sidetone);
 164
 165 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
 166                             WM8990_DIGITAL_SIDE_TONE,
 167                             WM8990_ADC_TO_DACR_SHIFT,
 168                             wm8990_digital_sidetone);
 169
 170 static const char *wm8990_adcmode[] =
 171         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
 172
 173 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
 174                             WM8990_ADC_CTRL,
 175                             WM8990_ADC_HPF_CUT_SHIFT,
 176                             wm8990_adcmode);
 177
 178 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
 179 /* INMIXL */
 180 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
 181 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
 182 /* INMIXR */
 183 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
 184 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
 185
 186 /* LOMIX */
 187 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
 188         WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
 189 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
 190         WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
 191 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
 192         WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
 193 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
 194         WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
 195 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
 196         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
 197 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
 198         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
 199
 200 /* ROMIX */
 201 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
 202         WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
 203 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
 204         WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
 205 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
 206         WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
 207 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
 208         WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
 209 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
 210         WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
 211 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
 212         WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
 213
 214 /* LOUT */
 215 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
 216         WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
 217 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
 218
 219 /* ROUT */
 220 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
 221         WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
 222 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
 223
 224 /* LOPGA */
 225 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
 226         WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
 227 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
 228         WM8990_LOPGAZC_BIT, 1, 0),
 229
 230 /* ROPGA */
 231 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
 232         WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
 233 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
 234         WM8990_ROPGAZC_BIT, 1, 0),
 235
 236 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 237         WM8990_LONMUTE_BIT, 1, 0),
 238 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 239         WM8990_LOPMUTE_BIT, 1, 0),
 240 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
 241         WM8990_LOATTN_BIT, 1, 0),
 242 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 243         WM8990_RONMUTE_BIT, 1, 0),
 244 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 245         WM8990_ROPMUTE_BIT, 1, 0),
 246 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
 247         WM8990_ROATTN_BIT, 1, 0),
 248
 249 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
 250         WM8990_OUT3MUTE_BIT, 1, 0),
 251 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
 252         WM8990_OUT3ATTN_BIT, 1, 0),
 253
 254 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
 255         WM8990_OUT4MUTE_BIT, 1, 0),
 256 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
 257         WM8990_OUT4ATTN_BIT, 1, 0),
 258
 259 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
 260         WM8990_CDMODE_BIT, 1, 0),
 261
 262 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
 263         WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
 264 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
 265         WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
 266 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
 267         WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
 268 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
 269         WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
 270 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
 271         WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
 272
 273 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
 274         WM8990_LEFT_DAC_DIGITAL_VOLUME,
 275         WM8990_DACL_VOL_SHIFT,
 276         WM8990_DACL_VOL_MASK,
 277         0,
 278         out_dac_tlv),
 279
 280 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
 281         WM8990_RIGHT_DAC_DIGITAL_VOLUME,
 282         WM8990_DACR_VOL_SHIFT,
 283         WM8990_DACR_VOL_MASK,
 284         0,
 285         out_dac_tlv),
 286
 287 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
 288 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
 289
 290 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
 291         WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
 292         out_sidetone_tlv),
 293 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
 294         WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
 295         out_sidetone_tlv),
 296
 297 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
 298         WM8990_ADC_HPF_ENA_BIT, 1, 0),
 299
 300 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
 301
 302 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
 303         WM8990_LEFT_ADC_DIGITAL_VOLUME,
 304         WM8990_ADCL_VOL_SHIFT,
 305         WM8990_ADCL_VOL_MASK,
 306         0,
 307         in_adc_tlv),
 308
 309 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
 310         WM8990_RIGHT_ADC_DIGITAL_VOLUME,
 311         WM8990_ADCR_VOL_SHIFT,
 312         WM8990_ADCR_VOL_MASK,
 313         0,
 314         in_adc_tlv),
 315
 316 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
 317         WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 318         WM8990_LIN12VOL_SHIFT,
 319         WM8990_LIN12VOL_MASK,
 320         0,
 321         in_pga_tlv),
 322
 323 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 324         WM8990_LI12ZC_BIT, 1, 0),
 325
 326 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 327         WM8990_LI12MUTE_BIT, 1, 0),
 328
 329 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
 330         WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 331         WM8990_LIN34VOL_SHIFT,
 332         WM8990_LIN34VOL_MASK,
 333         0,
 334         in_pga_tlv),
 335
 336 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 337         WM8990_LI34ZC_BIT, 1, 0),
 338
 339 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 340         WM8990_LI34MUTE_BIT, 1, 0),
 341
 342 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
 343         WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 344         WM8990_RIN12VOL_SHIFT,
 345         WM8990_RIN12VOL_MASK,
 346         0,
 347         in_pga_tlv),
 348
 349 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 350         WM8990_RI12ZC_BIT, 1, 0),
 351
 352 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 353         WM8990_RI12MUTE_BIT, 1, 0),
 354
 355 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
 356         WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 357         WM8990_RIN34VOL_SHIFT,
 358         WM8990_RIN34VOL_MASK,
 359         0,
 360         in_pga_tlv),
 361
 362 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 363         WM8990_RI34ZC_BIT, 1, 0),
 364
 365 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 366         WM8990_RI34MUTE_BIT, 1, 0),
 367
 368 };
 369
 370 /*
 371  * _DAPM_ Controls
 372  */
 373
 374 static int outmixer_event(struct snd_soc_dapm_widget *w,
 375         struct snd_kcontrol *kcontrol, int event)
 376 {
 377         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 378         u32 reg_shift = kcontrol->private_value & 0xfff;
 379         int ret = 0;
 380         u16 reg;
 381
 382         switch (reg_shift) {
 383         case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
 384                 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER1);
 385                 if (reg & WM8990_LDLO) {
 386                         printk(KERN_WARNING
 387                         "Cannot set as Output Mixer 1 LDLO Set\n");
 388                         ret = -1;
 389                 }
 390                 break;
 391         case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
 392                 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER2);
 393                 if (reg & WM8990_RDRO) {
 394                         printk(KERN_WARNING
 395                         "Cannot set as Output Mixer 2 RDRO Set\n");
 396                         ret = -1;
 397                 }
 398                 break;
 399         case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
 400                 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
 401                 if (reg & WM8990_LDSPK) {
 402                         printk(KERN_WARNING
 403                         "Cannot set as Speaker Mixer LDSPK Set\n");
 404                         ret = -1;
 405                 }
 406                 break;
 407         case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
 408                 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
 409                 if (reg & WM8990_RDSPK) {
 410                         printk(KERN_WARNING
 411                         "Cannot set as Speaker Mixer RDSPK Set\n");
 412                         ret = -1;
 413                 }
 414                 break;
 415         }
 416
 417         return ret;
 418 }
 419
 420 /* INMIX dB values */
 421 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
 422
 423 /* Left In PGA Connections */
 424 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
 425 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
 426 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
 427 };
 428
 429 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
 430 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
 431 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
 432 };
 433
 434 /* Right In PGA Connections */
 435 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
 436 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
 437 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
 438 };
 439
 440 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
 441 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
 442 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
 443 };
 444
 445 /* INMIXL */
 446 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
 447 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
 448         WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
 449 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
 450         7, 0, in_mix_tlv),
 451 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
 452         1, 0),
 453 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
 454         1, 0),
 455 };
 456
 457 /* INMIXR */
 458 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
 459 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
 460         WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
 461 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
 462         7, 0, in_mix_tlv),
 463 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
 464         1, 0),
 465 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
 466         1, 0),
 467 };
 468
 469 /* AINLMUX */
 470 static const char *wm8990_ainlmux[] =
 471         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
 472
 473 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
 474                             WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
 475                             wm8990_ainlmux);
 476
 477 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
 478 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
 479
 480 /* DIFFINL */
 481
 482 /* AINRMUX */
 483 static const char *wm8990_ainrmux[] =
 484         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
 485
 486 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
 487                             WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
 488                             wm8990_ainrmux);
 489
 490 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
 491 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
 492
 493 /* RXVOICE */
 494 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
 495 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
 496                         WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
 497 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
 498                         WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
 499 };
 500
 501 /* LOMIX */
 502 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
 503 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
 504         WM8990_LRBLO_BIT, 1, 0),
 505 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
 506         WM8990_LLBLO_BIT, 1, 0),
 507 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
 508         WM8990_LRI3LO_BIT, 1, 0),
 509 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
 510         WM8990_LLI3LO_BIT, 1, 0),
 511 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
 512         WM8990_LR12LO_BIT, 1, 0),
 513 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
 514         WM8990_LL12LO_BIT, 1, 0),
 515 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
 516         WM8990_LDLO_BIT, 1, 0),
 517 };
 518
 519 /* ROMIX */
 520 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
 521 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
 522         WM8990_RLBRO_BIT, 1, 0),
 523 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
 524         WM8990_RRBRO_BIT, 1, 0),
 525 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
 526         WM8990_RLI3RO_BIT, 1, 0),
 527 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
 528         WM8990_RRI3RO_BIT, 1, 0),
 529 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
 530         WM8990_RL12RO_BIT, 1, 0),
 531 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
 532         WM8990_RR12RO_BIT, 1, 0),
 533 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
 534         WM8990_RDRO_BIT, 1, 0),
 535 };
 536
 537 /* LONMIX */
 538 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
 539 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
 540         WM8990_LLOPGALON_BIT, 1, 0),
 541 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
 542         WM8990_LROPGALON_BIT, 1, 0),
 543 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
 544         WM8990_LOPLON_BIT, 1, 0),
 545 };
 546
 547 /* LOPMIX */
 548 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
 549 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
 550         WM8990_LR12LOP_BIT, 1, 0),
 551 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
 552         WM8990_LL12LOP_BIT, 1, 0),
 553 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
 554         WM8990_LLOPGALOP_BIT, 1, 0),
 555 };
 556
 557 /* RONMIX */
 558 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
 559 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
 560         WM8990_RROPGARON_BIT, 1, 0),
 561 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
 562         WM8990_RLOPGARON_BIT, 1, 0),
 563 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
 564         WM8990_ROPRON_BIT, 1, 0),
 565 };
 566
 567 /* ROPMIX */
 568 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
 569 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
 570         WM8990_RL12ROP_BIT, 1, 0),
 571 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
 572         WM8990_RR12ROP_BIT, 1, 0),
 573 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
 574         WM8990_RROPGAROP_BIT, 1, 0),
 575 };
 576
 577 /* OUT3MIX */
 578 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
 579 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
 580         WM8990_LI4O3_BIT, 1, 0),
 581 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
 582         WM8990_LPGAO3_BIT, 1, 0),
 583 };
 584
 585 /* OUT4MIX */
 586 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
 587 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
 588         WM8990_RPGAO4_BIT, 1, 0),
 589 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
 590         WM8990_RI4O4_BIT, 1, 0),
 591 };
 592
 593 /* SPKMIX */
 594 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
 595 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
 596         WM8990_LI2SPK_BIT, 1, 0),
 597 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
 598         WM8990_LB2SPK_BIT, 1, 0),
 599 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
 600         WM8990_LOPGASPK_BIT, 1, 0),
 601 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
 602         WM8990_LDSPK_BIT, 1, 0),
 603 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
 604         WM8990_RDSPK_BIT, 1, 0),
 605 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
 606         WM8990_ROPGASPK_BIT, 1, 0),
 607 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
 608         WM8990_RL12ROP_BIT, 1, 0),
 609 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
 610         WM8990_RI2SPK_BIT, 1, 0),
 611 };
 612
 613 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
 614 /* Input Side */
 615 /* Input Lines */
 616 SND_SOC_DAPM_INPUT("LIN1"),
 617 SND_SOC_DAPM_INPUT("LIN2"),
 618 SND_SOC_DAPM_INPUT("LIN3"),
 619 SND_SOC_DAPM_INPUT("LIN4/RXN"),
 620 SND_SOC_DAPM_INPUT("RIN3"),
 621 SND_SOC_DAPM_INPUT("RIN4/RXP"),
 622 SND_SOC_DAPM_INPUT("RIN1"),
 623 SND_SOC_DAPM_INPUT("RIN2"),
 624 SND_SOC_DAPM_INPUT("Internal ADC Source"),
 625
 626 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
 627                     NULL, 0),
 628 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
 629                     NULL, 0),
 630
 631 /* DACs */
 632 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
 633         WM8990_ADCL_ENA_BIT, 0),
 634 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
 635         WM8990_ADCR_ENA_BIT, 0),
 636
 637 /* Input PGAs */
 638 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
 639         0, &wm8990_dapm_lin12_pga_controls[0],
 640         ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
 641 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
 642         0, &wm8990_dapm_lin34_pga_controls[0],
 643         ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
 644 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
 645         0, &wm8990_dapm_rin12_pga_controls[0],
 646         ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
 647 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
 648         0, &wm8990_dapm_rin34_pga_controls[0],
 649         ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
 650
 651 /* INMIXL */
 652 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
 653         &wm8990_dapm_inmixl_controls[0],
 654         ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
 655
 656 /* AINLMUX */
 657 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
 658
 659 /* INMIXR */
 660 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
 661         &wm8990_dapm_inmixr_controls[0],
 662         ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
 663
 664 /* AINRMUX */
 665 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
 666
 667 /* Output Side */
 668 /* DACs */
 669 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
 670         WM8990_DACL_ENA_BIT, 0),
 671 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
 672         WM8990_DACR_ENA_BIT, 0),
 673
 674 /* LOMIX */
 675 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
 676         0, &wm8990_dapm_lomix_controls[0],
 677         ARRAY_SIZE(wm8990_dapm_lomix_controls),
 678         outmixer_event, SND_SOC_DAPM_PRE_REG),
 679
 680 /* LONMIX */
 681 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
 682         &wm8990_dapm_lonmix_controls[0],
 683         ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
 684
 685 /* LOPMIX */
 686 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
 687         &wm8990_dapm_lopmix_controls[0],
 688         ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
 689
 690 /* OUT3MIX */
 691 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
 692         &wm8990_dapm_out3mix_controls[0],
 693         ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
 694
 695 /* SPKMIX */
 696 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
 697         &wm8990_dapm_spkmix_controls[0],
 698         ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
 699         SND_SOC_DAPM_PRE_REG),
 700
 701 /* OUT4MIX */
 702 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
 703         &wm8990_dapm_out4mix_controls[0],
 704         ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
 705
 706 /* ROPMIX */
 707 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
 708         &wm8990_dapm_ropmix_controls[0],
 709         ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
 710
 711 /* RONMIX */
 712 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
 713         &wm8990_dapm_ronmix_controls[0],
 714         ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
 715
 716 /* ROMIX */
 717 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
 718         0, &wm8990_dapm_romix_controls[0],
 719         ARRAY_SIZE(wm8990_dapm_romix_controls),
 720         outmixer_event, SND_SOC_DAPM_PRE_REG),
 721
 722 /* LOUT PGA */
 723 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
 724         NULL, 0),
 725
 726 /* ROUT PGA */
 727 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
 728         NULL, 0),
 729
 730 /* LOPGA */
 731 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
 732         NULL, 0),
 733
 734 /* ROPGA */
 735 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
 736         NULL, 0),
 737
 738 /* MICBIAS */
 739 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
 740                     WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
 741
 742 SND_SOC_DAPM_OUTPUT("LON"),
 743 SND_SOC_DAPM_OUTPUT("LOP"),
 744 SND_SOC_DAPM_OUTPUT("OUT3"),
 745 SND_SOC_DAPM_OUTPUT("LOUT"),
 746 SND_SOC_DAPM_OUTPUT("SPKN"),
 747 SND_SOC_DAPM_OUTPUT("SPKP"),
 748 SND_SOC_DAPM_OUTPUT("ROUT"),
 749 SND_SOC_DAPM_OUTPUT("OUT4"),
 750 SND_SOC_DAPM_OUTPUT("ROP"),
 751 SND_SOC_DAPM_OUTPUT("RON"),
 752
 753 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
 754 };
 755
 756 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
 757         /* Make DACs turn on when playing even if not mixed into any outputs */
 758         {"Internal DAC Sink", NULL, "Left DAC"},
 759         {"Internal DAC Sink", NULL, "Right DAC"},
 760
 761         /* Make ADCs turn on when recording even if not mixed from any inputs */
 762         {"Left ADC", NULL, "Internal ADC Source"},
 763         {"Right ADC", NULL, "Internal ADC Source"},
 764
 765         {"AINLMUX", NULL, "INL"},
 766         {"INMIXL", NULL, "INL"},
 767         {"AINRMUX", NULL, "INR"},
 768         {"INMIXR", NULL, "INR"},
 769
 770         /* Input Side */
 771         /* LIN12 PGA */
 772         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
 773         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
 774         /* LIN34 PGA */
 775         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
 776         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
 777         /* INMIXL */
 778         {"INMIXL", "Record Left Volume", "LOMIX"},
 779         {"INMIXL", "LIN2 Volume", "LIN2"},
 780         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
 781         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
 782         /* AINLMUX */
 783         {"AINLMUX", "INMIXL Mix", "INMIXL"},
 784         {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
 785         {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
 786         {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
 787         {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
 788         /* ADC */
 789         {"Left ADC", NULL, "AINLMUX"},
 790
 791         /* RIN12 PGA */
 792         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
 793         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
 794         /* RIN34 PGA */
 795         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
 796         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
 797         /* INMIXL */
 798         {"INMIXR", "Record Right Volume", "ROMIX"},
 799         {"INMIXR", "RIN2 Volume", "RIN2"},
 800         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
 801         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
 802         /* AINRMUX */
 803         {"AINRMUX", "INMIXR Mix", "INMIXR"},
 804         {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
 805         {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
 806         {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
 807         {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
 808         /* ADC */
 809         {"Right ADC", NULL, "AINRMUX"},
 810
 811         /* LOMIX */
 812         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
 813         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
 814         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 815         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 816         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
 817         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
 818         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
 819
 820         /* ROMIX */
 821         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
 822         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
 823         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 824         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 825         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
 826         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
 827         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
 828
 829         /* SPKMIX */
 830         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
 831         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
 832         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
 833         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
 834         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
 835         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
 836         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
 837         {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
 838
 839         /* LONMIX */
 840         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
 841         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
 842         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
 843
 844         /* LOPMIX */
 845         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 846         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 847         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
 848
 849         /* OUT3MIX */
 850         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
 851         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
 852
 853         /* OUT4MIX */
 854         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
 855         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
 856
 857         /* RONMIX */
 858         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
 859         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
 860         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
 861
 862         /* ROPMIX */
 863         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 864         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 865         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
 866
 867         /* Out Mixer PGAs */
 868         {"LOPGA", NULL, "LOMIX"},
 869         {"ROPGA", NULL, "ROMIX"},
 870
 871         {"LOUT PGA", NULL, "LOMIX"},
 872         {"ROUT PGA", NULL, "ROMIX"},
 873
 874         /* Output Pins */
 875         {"LON", NULL, "LONMIX"},
 876         {"LOP", NULL, "LOPMIX"},
 877         {"OUT3", NULL, "OUT3MIX"},
 878         {"LOUT", NULL, "LOUT PGA"},
 879         {"SPKN", NULL, "SPKMIX"},
 880         {"ROUT", NULL, "ROUT PGA"},
 881         {"OUT4", NULL, "OUT4MIX"},
 882         {"ROP", NULL, "ROPMIX"},
 883         {"RON", NULL, "RONMIX"},
 884 };
 885
 886 /* PLL divisors */
 887 struct _pll_div {
 888         u32 div2;
 889         u32 n;
 890         u32 k;
 891 };
 892
 893 /* The size in bits of the pll divide multiplied by 10
 894  * to allow rounding later */
 895 #define FIXED_PLL_SIZE ((1 << 16) * 10)
 896
 897 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
 898         unsigned int source)
 899 {
 900         u64 Kpart;
 901         unsigned int K, Ndiv, Nmod;
 902
 903
 904         Ndiv = target / source;
 905         if (Ndiv < 6) {
 906                 source >>= 1;
 907                 pll_div->div2 = 1;
 908                 Ndiv = target / source;
 909         } else
 910                 pll_div->div2 = 0;
 911
 912         if ((Ndiv < 6) || (Ndiv > 12))
 913                 printk(KERN_WARNING
 914                 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
 915
 916         pll_div->n = Ndiv;
 917         Nmod = target % source;
 918         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 919
 920         do_div(Kpart, source);
 921
 922         K = Kpart & 0xFFFFFFFF;
 923
 924         /* Check if we need to round */
 925         if ((K % 10) >= 5)
 926                 K += 5;
 927
 928         /* Move down to proper range now rounding is done */
 929         K /= 10;
 930
 931         pll_div->k = K;
 932 }
 933
 934 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 935                 int source, unsigned int freq_in, unsigned int freq_out)
 936 {
 937         struct snd_soc_codec *codec = codec_dai->codec;
 938         struct _pll_div pll_div;
 939
 940         if (freq_in && freq_out) {
 941                 pll_factors(&pll_div, freq_out * 4, freq_in);
 942
 943                 /* Turn on PLL */
 944                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
 945                                     WM8990_PLL_ENA, WM8990_PLL_ENA);
 946
 947                 /* sysclk comes from PLL */
 948                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
 949                                     WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
 950
 951                 /* set up N , fractional mode and pre-divisor if necessary */
 952                 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
 953                         (pll_div.div2?WM8990_PRESCALE:0));
 954                 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
 955                 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
 956         } else {
 957                 /* Turn off PLL */
 958                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
 959                                     WM8990_PLL_ENA, 0);
 960         }
 961         return 0;
 962 }
 963
 964 /*
 965  * Clock after PLL and dividers
 966  */
 967 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 968                 int clk_id, unsigned int freq, int dir)
 969 {
 970         struct snd_soc_codec *codec = codec_dai->codec;
 971         struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
 972
 973         wm8990->sysclk = freq;
 974         return 0;
 975 }
 976
 977 /*
 978  * Set's ADC and Voice DAC format.
 979  */
 980 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
 981                 unsigned int fmt)
 982 {
 983         struct snd_soc_codec *codec = codec_dai->codec;
 984         u16 audio1, audio3;
 985
 986         audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
 987         audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
 988
 989         /* set master/slave audio interface */
 990         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 991         case SND_SOC_DAIFMT_CBS_CFS:
 992                 audio3 &= ~WM8990_AIF_MSTR1;
 993                 break;
 994         case SND_SOC_DAIFMT_CBM_CFM:
 995                 audio3 |= WM8990_AIF_MSTR1;
 996                 break;
 997         default:
 998                 return -EINVAL;
 999         }
1000
1001         audio1 &= ~WM8990_AIF_FMT_MASK;
1002
1003         /* interface format */
1004         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1005         case SND_SOC_DAIFMT_I2S:
1006                 audio1 |= WM8990_AIF_TMF_I2S;
1007                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1008                 break;
1009         case SND_SOC_DAIFMT_RIGHT_J:
1010                 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1011                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1012                 break;
1013         case SND_SOC_DAIFMT_LEFT_J:
1014                 audio1 |= WM8990_AIF_TMF_LEFTJ;
1015                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1016                 break;
1017         case SND_SOC_DAIFMT_DSP_A:
1018                 audio1 |= WM8990_AIF_TMF_DSP;
1019                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1020                 break;
1021         case SND_SOC_DAIFMT_DSP_B:
1022                 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1023                 break;
1024         default:
1025                 return -EINVAL;
1026         }
1027
1028         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1029         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1030         return 0;
1031 }
1032
1033 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1034                 int div_id, int div)
1035 {
1036         struct snd_soc_codec *codec = codec_dai->codec;
1037
1038         switch (div_id) {
1039         case WM8990_MCLK_DIV:
1040                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1041                                     WM8990_MCLK_DIV_MASK, div);
1042                 break;
1043         case WM8990_DACCLK_DIV:
1044                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1045                                     WM8990_DAC_CLKDIV_MASK, div);
1046                 break;
1047         case WM8990_ADCCLK_DIV:
1048                 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1049                                     WM8990_ADC_CLKDIV_MASK, div);
1050                 break;
1051         case WM8990_BCLK_DIV:
1052                 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
1053                                     WM8990_BCLK_DIV_MASK, div);
1054                 break;
1055         default:
1056                 return -EINVAL;
1057         }
1058
1059         return 0;
1060 }
1061
1062 /*
1063  * Set PCM DAI bit size and sample rate.
1064  */
1065 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1066                             struct snd_pcm_hw_params *params,
1067                             struct snd_soc_dai *dai)
1068 {
1069         struct snd_soc_codec *codec = dai->codec;
1070         u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1071
1072         audio1 &= ~WM8990_AIF_WL_MASK;
1073         /* bit size */
1074         switch (params_width(params)) {
1075         case 16:
1076                 break;
1077         case 20:
1078                 audio1 |= WM8990_AIF_WL_20BITS;
1079                 break;
1080         case 24:
1081                 audio1 |= WM8990_AIF_WL_24BITS;
1082                 break;
1083         case 32:
1084                 audio1 |= WM8990_AIF_WL_32BITS;
1085                 break;
1086         }
1087
1088         snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1089         return 0;
1090 }
1091
1092 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1093 {
1094         struct snd_soc_codec *codec = dai->codec;
1095         u16 val;
1096
1097         val  = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1098
1099         if (mute)
1100                 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1101         else
1102                 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1103
1104         return 0;
1105 }
1106
1107 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1108         enum snd_soc_bias_level level)
1109 {
1110         struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1111         int ret;
1112
1113         switch (level) {
1114         case SND_SOC_BIAS_ON:
1115                 break;
1116
1117         case SND_SOC_BIAS_PREPARE:
1118                 /* VMID=2*50k */
1119                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1120                                     WM8990_VMID_MODE_MASK, 0x2);
1121                 break;
1122
1123         case SND_SOC_BIAS_STANDBY:
1124                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1125                         ret = regcache_sync(wm8990->regmap);
1126                         if (ret < 0) {
1127                                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1128                                 return ret;
1129                         }
1130
1131                         /* Enable all output discharge bits */
1132                         snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1133                                 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1134                                 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1135                                 WM8990_DIS_ROUT);
1136
1137                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1138                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1139                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1140                                      WM8990_VMIDTOG);
1141
1142                         /* Delay to allow output caps to discharge */
1143                         msleep(300);
1144
1145                         /* Disable VMIDTOG */
1146                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1147                                      WM8990_BUFDCOPEN | WM8990_POBCTRL);
1148
1149                         /* disable all output discharge bits */
1150                         snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1151
1152                         /* Enable outputs */
1153                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1154
1155                         msleep(50);
1156
1157                         /* Enable VMID at 2x50k */
1158                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1159
1160                         msleep(100);
1161
1162                         /* Enable VREF */
1163                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1164
1165                         msleep(600);
1166
1167                         /* Enable BUFIOEN */
1168                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1169                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1170                                      WM8990_BUFIOEN);
1171
1172                         /* Disable outputs */
1173                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1174
1175                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1176                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1177
1178                         /* Enable workaround for ADC clocking issue. */
1179                         snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1180                         snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1181                         snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1182                 }
1183
1184                 /* VMID=2*250k */
1185                 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1186                                     WM8990_VMID_MODE_MASK, 0x4);
1187                 break;
1188
1189         case SND_SOC_BIAS_OFF:
1190                 /* Enable POBCTRL and SOFT_ST */
1191                 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1192                         WM8990_POBCTRL | WM8990_BUFIOEN);
1193
1194                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1195                 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1196                         WM8990_BUFDCOPEN | WM8990_POBCTRL |
1197                         WM8990_BUFIOEN);
1198
1199                 /* mute DAC */
1200                 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1201                                     WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1202
1203                 /* Enable any disabled outputs */
1204                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1205
1206                 /* Disable VMID */
1207                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1208
1209                 msleep(300);
1210
1211                 /* Enable all output discharge bits */
1212                 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1213                         WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1214                         WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1215                         WM8990_DIS_ROUT);
1216
1217                 /* Disable VREF */
1218                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1219
1220                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1221                 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1222
1223                 regcache_mark_dirty(wm8990->regmap);
1224                 break;
1225         }
1226
1227         return 0;
1228 }
1229
1230 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1231         SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1232         SNDRV_PCM_RATE_48000)
1233
1234 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1235         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1236
1237 /*
1238  * The WM8990 supports 2 different and mutually exclusive DAI
1239  * configurations.
1240  *
1241  * 1. ADC/DAC on Primary Interface
1242  * 2. ADC on Primary Interface/DAC on secondary
1243  */
1244 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1245         .hw_params      = wm8990_hw_params,
1246         .digital_mute   = wm8990_mute,
1247         .set_fmt        = wm8990_set_dai_fmt,
1248         .set_clkdiv     = wm8990_set_dai_clkdiv,
1249         .set_pll        = wm8990_set_dai_pll,
1250         .set_sysclk     = wm8990_set_dai_sysclk,
1251 };
1252
1253 static struct snd_soc_dai_driver wm8990_dai = {
1254 /* ADC/DAC on primary */
1255         .name = "wm8990-hifi",
1256         .playback = {
1257                 .stream_name = "Playback",
1258                 .channels_min = 1,
1259                 .channels_max = 2,
1260                 .rates = WM8990_RATES,
1261                 .formats = WM8990_FORMATS,},
1262         .capture = {
1263                 .stream_name = "Capture",
1264                 .channels_min = 1,
1265                 .channels_max = 2,
1266                 .rates = WM8990_RATES,
1267                 .formats = WM8990_FORMATS,},
1268         .ops = &wm8990_dai_ops,
1269 };
1270
1271 /*
1272  * initialise the WM8990 driver
1273  * register the mixer and dsp interfaces with the kernel
1274  */
1275 static int wm8990_probe(struct snd_soc_codec *codec)
1276 {
1277         wm8990_reset(codec);
1278
1279         /* charge output caps */
1280         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1281
1282         snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1283                             WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1284
1285         snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1286                             WM8990_GPIO1_SEL_MASK, 1);
1287
1288         snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1289                             WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1290
1291         snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1292         snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1293
1294         return 0;
1295 }
1296
1297 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1298         .probe =        wm8990_probe,
1299         .set_bias_level = wm8990_set_bias_level,
1300         .suspend_bias_off = true,
1301
1302         .controls =     wm8990_snd_controls,
1303         .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1304         .dapm_widgets = wm8990_dapm_widgets,
1305         .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1306         .dapm_routes =  wm8990_dapm_routes,
1307         .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
1308 };
1309
1310 static const struct regmap_config wm8990_regmap = {
1311         .reg_bits = 8,
1312         .val_bits = 16,
1313
1314         .max_register = WM8990_PLL3,
1315         .volatile_reg = wm8990_volatile_register,
1316         .reg_defaults = wm8990_reg_defaults,
1317         .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults),
1318         .cache_type = REGCACHE_RBTREE,
1319 };
1320
1321 static int wm8990_i2c_probe(struct i2c_client *i2c,
1322                             const struct i2c_device_id *id)
1323 {
1324         struct wm8990_priv *wm8990;
1325         int ret;
1326
1327         wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1328                               GFP_KERNEL);
1329         if (wm8990 == NULL)
1330                 return -ENOMEM;
1331
1332         i2c_set_clientdata(i2c, wm8990);
1333
1334         ret = snd_soc_register_codec(&i2c->dev,
1335                         &soc_codec_dev_wm8990, &wm8990_dai, 1);
1336
1337         return ret;
1338 }
1339
1340 static int wm8990_i2c_remove(struct i2c_client *client)
1341 {
1342         snd_soc_unregister_codec(&client->dev);
1343
1344         return 0;
1345 }
1346
1347 static const struct i2c_device_id wm8990_i2c_id[] = {
1348         { "wm8990", 0 },
1349         { }
1350 };
1351 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1352
1353 static struct i2c_driver wm8990_i2c_driver = {
1354         .driver = {
1355                 .name = "wm8990",
1356         },
1357         .probe =    wm8990_i2c_probe,
1358         .remove =   wm8990_i2c_remove,
1359         .id_table = wm8990_i2c_id,
1360 };
1361
1362 module_i2c_driver(wm8990_i2c_driver);
1363
1364 MODULE_DESCRIPTION("ASoC WM8990 driver");
1365 MODULE_AUTHOR("Liam Girdwood");
1366 MODULE_LICENSE("GPL");