kernel/sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008-12 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/slab.h>
  29 #include <linux/of_device.h>
  30
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/soc.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <asm/div64.h>
  38
  39 #include "wm8580.h"
  40
  41 /* WM8580 register space */
  42 #define WM8580_PLLA1                         0x00
  43 #define WM8580_PLLA2                         0x01
  44 #define WM8580_PLLA3                         0x02
  45 #define WM8580_PLLA4                         0x03
  46 #define WM8580_PLLB1                         0x04
  47 #define WM8580_PLLB2                         0x05
  48 #define WM8580_PLLB3                         0x06
  49 #define WM8580_PLLB4                         0x07
  50 #define WM8580_CLKSEL                        0x08
  51 #define WM8580_PAIF1                         0x09
  52 #define WM8580_PAIF2                         0x0A
  53 #define WM8580_SAIF1                         0x0B
  54 #define WM8580_PAIF3                         0x0C
  55 #define WM8580_PAIF4                         0x0D
  56 #define WM8580_SAIF2                         0x0E
  57 #define WM8580_DAC_CONTROL1                  0x0F
  58 #define WM8580_DAC_CONTROL2                  0x10
  59 #define WM8580_DAC_CONTROL3                  0x11
  60 #define WM8580_DAC_CONTROL4                  0x12
  61 #define WM8580_DAC_CONTROL5                  0x13
  62 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  63 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  64 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  65 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  66 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  67 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  68 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  69 #define WM8580_ADC_CONTROL1                  0x1D
  70 #define WM8580_SPDTXCHAN0                    0x1E
  71 #define WM8580_SPDTXCHAN1                    0x1F
  72 #define WM8580_SPDTXCHAN2                    0x20
  73 #define WM8580_SPDTXCHAN3                    0x21
  74 #define WM8580_SPDTXCHAN4                    0x22
  75 #define WM8580_SPDTXCHAN5                    0x23
  76 #define WM8580_SPDMODE                       0x24
  77 #define WM8580_INTMASK                       0x25
  78 #define WM8580_GPO1                          0x26
  79 #define WM8580_GPO2                          0x27
  80 #define WM8580_GPO3                          0x28
  81 #define WM8580_GPO4                          0x29
  82 #define WM8580_GPO5                          0x2A
  83 #define WM8580_INTSTAT                       0x2B
  84 #define WM8580_SPDRXCHAN1                    0x2C
  85 #define WM8580_SPDRXCHAN2                    0x2D
  86 #define WM8580_SPDRXCHAN3                    0x2E
  87 #define WM8580_SPDRXCHAN4                    0x2F
  88 #define WM8580_SPDRXCHAN5                    0x30
  89 #define WM8580_SPDSTAT                       0x31
  90 #define WM8580_PWRDN1                        0x32
  91 #define WM8580_PWRDN2                        0x33
  92 #define WM8580_READBACK                      0x34
  93 #define WM8580_RESET                         0x35
  94
  95 #define WM8580_MAX_REGISTER                  0x35
  96
  97 #define WM8580_DACOSR 0x40
  98
  99 /* PLLB4 (register 7h) */
 100 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 103 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 104
 105 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 109
 110 /* CLKSEL (register 8h) */
 111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 114
 115 /* AIF control 1 (registers 9h-bh) */
 116 #define WM8580_AIF_RATE_MASK       0x7
 117 #define WM8580_AIF_BCLKSEL_MASK   0x18
 118
 119 #define WM8580_AIF_MS             0x20
 120
 121 #define WM8580_AIF_CLKSRC_MASK    0xc0
 122 #define WM8580_AIF_CLKSRC_PLLA    0x40
 123 #define WM8580_AIF_CLKSRC_PLLB    0x40
 124 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 125
 126 /* AIF control 2 (registers ch-eh) */
 127 #define WM8580_AIF_FMT_MASK    0x03
 128 #define WM8580_AIF_FMT_RIGHTJ  0x00
 129 #define WM8580_AIF_FMT_LEFTJ   0x01
 130 #define WM8580_AIF_FMT_I2S     0x02
 131 #define WM8580_AIF_FMT_DSP     0x03
 132
 133 #define WM8580_AIF_LENGTH_MASK   0x0c
 134 #define WM8580_AIF_LENGTH_16     0x00
 135 #define WM8580_AIF_LENGTH_20     0x04
 136 #define WM8580_AIF_LENGTH_24     0x08
 137 #define WM8580_AIF_LENGTH_32     0x0c
 138
 139 #define WM8580_AIF_LRP         0x10
 140 #define WM8580_AIF_BCP         0x20
 141
 142 /* Powerdown Register 1 (register 32h) */
 143 #define WM8580_PWRDN1_PWDN     0x001
 144 #define WM8580_PWRDN1_ALLDACPD 0x040
 145
 146 /* Powerdown Register 2 (register 33h) */
 147 #define WM8580_PWRDN2_OSSCPD   0x001
 148 #define WM8580_PWRDN2_PLLAPD   0x002
 149 #define WM8580_PWRDN2_PLLBPD   0x004
 150 #define WM8580_PWRDN2_SPDIFPD  0x008
 151 #define WM8580_PWRDN2_SPDIFTXD 0x010
 152 #define WM8580_PWRDN2_SPDIFRXD 0x020
 153
 154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 155
 156 /*
 157  * wm8580 register cache
 158  * We can't read the WM8580 register space when we
 159  * are using 2 wire for device control, so we cache them instead.
 160  */
 161 static const struct reg_default wm8580_reg_defaults[] = {
 162         {  0, 0x0121 },
 163         {  1, 0x017e },
 164         {  2, 0x007d },
 165         {  3, 0x0014 },
 166         {  4, 0x0121 },
 167         {  5, 0x017e },
 168         {  6, 0x007d },
 169         {  7, 0x0194 },
 170         {  8, 0x0010 },
 171         {  9, 0x0002 },
 172         { 10, 0x0002 },
 173         { 11, 0x00c2 },
 174         { 12, 0x0182 },
 175         { 13, 0x0082 },
 176         { 14, 0x000a },
 177         { 15, 0x0024 },
 178         { 16, 0x0009 },
 179         { 17, 0x0000 },
 180         { 18, 0x00ff },
 181         { 19, 0x0000 },
 182         { 20, 0x00ff },
 183         { 21, 0x00ff },
 184         { 22, 0x00ff },
 185         { 23, 0x00ff },
 186         { 24, 0x00ff },
 187         { 25, 0x00ff },
 188         { 26, 0x00ff },
 189         { 27, 0x00ff },
 190         { 28, 0x01f0 },
 191         { 29, 0x0040 },
 192         { 30, 0x0000 },
 193         { 31, 0x0000 },
 194         { 32, 0x0000 },
 195         { 33, 0x0000 },
 196         { 34, 0x0031 },
 197         { 35, 0x000b },
 198         { 36, 0x0039 },
 199         { 37, 0x0000 },
 200         { 38, 0x0010 },
 201         { 39, 0x0032 },
 202         { 40, 0x0054 },
 203         { 41, 0x0076 },
 204         { 42, 0x0098 },
 205         { 43, 0x0000 },
 206         { 44, 0x0000 },
 207         { 45, 0x0000 },
 208         { 46, 0x0000 },
 209         { 47, 0x0000 },
 210         { 48, 0x0000 },
 211         { 49, 0x0000 },
 212         { 50, 0x005e },
 213         { 51, 0x003e },
 214         { 52, 0x0000 },
 215 };
 216
 217 static bool wm8580_volatile(struct device *dev, unsigned int reg)
 218 {
 219         switch (reg) {
 220         case WM8580_RESET:
 221                 return true;
 222         default:
 223                 return false;
 224         }
 225 }
 226
 227 struct pll_state {
 228         unsigned int in;
 229         unsigned int out;
 230 };
 231
 232 #define WM8580_NUM_SUPPLIES 3
 233 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 234         "AVDD",
 235         "DVDD",
 236         "PVDD",
 237 };
 238
 239 /* codec private data */
 240 struct wm8580_priv {
 241         struct regmap *regmap;
 242         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 243         struct pll_state a;
 244         struct pll_state b;
 245         int sysclk[2];
 246 };
 247
 248 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 249
 250 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 251                          struct snd_ctl_elem_value *ucontrol)
 252 {
 253         struct soc_mixer_control *mc =
 254                 (struct soc_mixer_control *)kcontrol->private_value;
 255         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 256         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 257         unsigned int reg = mc->reg;
 258         unsigned int reg2 = mc->rreg;
 259         int ret;
 260
 261         /* Clear the register cache VU so we write without VU set */
 262         regcache_cache_only(wm8580->regmap, true);
 263         regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
 264         regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
 265         regcache_cache_only(wm8580->regmap, false);
 266
 267         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 268         if (ret < 0)
 269                 return ret;
 270
 271         /* Now write again with the volume update bit set */
 272         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 273         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 274
 275         return 0;
 276 }
 277
 278 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 279 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
 280                      WM8580_DIGITAL_ATTENUATION_DACL1,
 281                      WM8580_DIGITAL_ATTENUATION_DACR1,
 282                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 283 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
 284                      WM8580_DIGITAL_ATTENUATION_DACL2,
 285                      WM8580_DIGITAL_ATTENUATION_DACR2,
 286                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 287 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
 288                      WM8580_DIGITAL_ATTENUATION_DACL3,
 289                      WM8580_DIGITAL_ATTENUATION_DACR3,
 290                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 291
 292 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 293 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 294 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 295
 296 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 297 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 298 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 299
 300 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 301 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
 302 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
 303 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
 304
 305 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
 306 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 307 };
 308
 309 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 310 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 311 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 312 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 313
 314 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 315 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 316 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 317 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 318 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 319 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 320
 321 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 322
 323 SND_SOC_DAPM_INPUT("AINL"),
 324 SND_SOC_DAPM_INPUT("AINR"),
 325 };
 326
 327 static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
 328         { "VOUT1L", NULL, "DAC1" },
 329         { "VOUT1R", NULL, "DAC1" },
 330
 331         { "VOUT2L", NULL, "DAC2" },
 332         { "VOUT2R", NULL, "DAC2" },
 333
 334         { "VOUT3L", NULL, "DAC3" },
 335         { "VOUT3R", NULL, "DAC3" },
 336
 337         { "ADC", NULL, "AINL" },
 338         { "ADC", NULL, "AINR" },
 339 };
 340
 341 /* PLL divisors */
 342 struct _pll_div {
 343         u32 prescale:1;
 344         u32 postscale:1;
 345         u32 freqmode:2;
 346         u32 n:4;
 347         u32 k:24;
 348 };
 349
 350 /* The size in bits of the pll divide */
 351 #define FIXED_PLL_SIZE (1 << 22)
 352
 353 /* PLL rate to output rate divisions */
 354 static struct {
 355         unsigned int div;
 356         unsigned int freqmode;
 357         unsigned int postscale;
 358 } post_table[] = {
 359         {  2,  0, 0 },
 360         {  4,  0, 1 },
 361         {  4,  1, 0 },
 362         {  8,  1, 1 },
 363         {  8,  2, 0 },
 364         { 16,  2, 1 },
 365         { 12,  3, 0 },
 366         { 24,  3, 1 }
 367 };
 368
 369 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 370                        unsigned int source)
 371 {
 372         u64 Kpart;
 373         unsigned int K, Ndiv, Nmod;
 374         int i;
 375
 376         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 377
 378         /* Scale the output frequency up; the PLL should run in the
 379          * region of 90-100MHz.
 380          */
 381         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 382                 if (target * post_table[i].div >=  90000000 &&
 383                     target * post_table[i].div <= 100000000) {
 384                         pll_div->freqmode = post_table[i].freqmode;
 385                         pll_div->postscale = post_table[i].postscale;
 386                         target *= post_table[i].div;
 387                         break;
 388                 }
 389         }
 390
 391         if (i == ARRAY_SIZE(post_table)) {
 392                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 393                        "%u\n", target);
 394                 return -EINVAL;
 395         }
 396
 397         Ndiv = target / source;
 398
 399         if (Ndiv < 5) {
 400                 source /= 2;
 401                 pll_div->prescale = 1;
 402                 Ndiv = target / source;
 403         } else
 404                 pll_div->prescale = 0;
 405
 406         if ((Ndiv < 5) || (Ndiv > 13)) {
 407                 printk(KERN_ERR
 408                         "WM8580 N=%u outside supported range\n", Ndiv);
 409                 return -EINVAL;
 410         }
 411
 412         pll_div->n = Ndiv;
 413         Nmod = target % source;
 414         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 415
 416         do_div(Kpart, source);
 417
 418         K = Kpart & 0xFFFFFFFF;
 419
 420         pll_div->k = K;
 421
 422         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 423                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 424                  pll_div->postscale);
 425
 426         return 0;
 427 }
 428
 429 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 430                 int source, unsigned int freq_in, unsigned int freq_out)
 431 {
 432         int offset;
 433         struct snd_soc_codec *codec = codec_dai->codec;
 434         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 435         struct pll_state *state;
 436         struct _pll_div pll_div;
 437         unsigned int reg;
 438         unsigned int pwr_mask;
 439         int ret;
 440
 441         /* GCC isn't able to work out the ifs below for initialising/using
 442          * pll_div so suppress warnings.
 443          */
 444         memset(&pll_div, 0, sizeof(pll_div));
 445
 446         switch (pll_id) {
 447         case WM8580_PLLA:
 448                 state = &wm8580->a;
 449                 offset = 0;
 450                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 451                 break;
 452         case WM8580_PLLB:
 453                 state = &wm8580->b;
 454                 offset = 4;
 455                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 456                 break;
 457         default:
 458                 return -ENODEV;
 459         }
 460
 461         if (freq_in && freq_out) {
 462                 ret = pll_factors(&pll_div, freq_out, freq_in);
 463                 if (ret != 0)
 464                         return ret;
 465         }
 466
 467         state->in = freq_in;
 468         state->out = freq_out;
 469
 470         /* Always disable the PLL - it is not safe to leave it running
 471          * while reprogramming it.
 472          */
 473         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
 474
 475         if (!freq_in || !freq_out)
 476                 return 0;
 477
 478         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 479         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 480         snd_soc_write(codec, WM8580_PLLA3 + offset,
 481                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 482
 483         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 484         reg &= ~0x1b;
 485         reg |= pll_div.prescale | pll_div.postscale << 1 |
 486                 pll_div.freqmode << 3;
 487
 488         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 489
 490         /* All done, turn it on */
 491         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
 492
 493         return 0;
 494 }
 495
 496 static const int wm8580_sysclk_ratios[] = {
 497         128, 192, 256, 384, 512, 768, 1152,
 498 };
 499
 500 /*
 501  * Set PCM DAI bit size and sample rate.
 502  */
 503 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 504                                  struct snd_pcm_hw_params *params,
 505                                  struct snd_soc_dai *dai)
 506 {
 507         struct snd_soc_codec *codec = dai->codec;
 508         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 509         u16 paifa = 0;
 510         u16 paifb = 0;
 511         int i, ratio, osr;
 512
 513         /* bit size */
 514         switch (params_width(params)) {
 515         case 16:
 516                 paifa |= 0x8;
 517                 break;
 518         case 20:
 519                 paifa |= 0x0;
 520                 paifb |= WM8580_AIF_LENGTH_20;
 521                 break;
 522         case 24:
 523                 paifa |= 0x0;
 524                 paifb |= WM8580_AIF_LENGTH_24;
 525                 break;
 526         case 32:
 527                 paifa |= 0x0;
 528                 paifb |= WM8580_AIF_LENGTH_32;
 529                 break;
 530         default:
 531                 return -EINVAL;
 532         }
 533
 534         /* Look up the SYSCLK ratio; accept only exact matches */
 535         ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
 536         for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
 537                 if (ratio == wm8580_sysclk_ratios[i])
 538                         break;
 539         if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
 540                 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
 541                         wm8580->sysclk[dai->driver->id], params_rate(params));
 542                 return -EINVAL;
 543         }
 544         paifa |= i;
 545         dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
 546                 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
 547
 548         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 549                 switch (ratio) {
 550                 case 128:
 551                 case 192:
 552                         osr = WM8580_DACOSR;
 553                         dev_dbg(codec->dev, "Selecting 64x OSR\n");
 554                         break;
 555                 default:
 556                         osr = 0;
 557                         dev_dbg(codec->dev, "Selecting 128x OSR\n");
 558                         break;
 559                 }
 560
 561                 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
 562         }
 563
 564         snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
 565                             WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
 566                             paifa);
 567         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 568                             WM8580_AIF_LENGTH_MASK, paifb);
 569         return 0;
 570 }
 571
 572 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 573                                       unsigned int fmt)
 574 {
 575         struct snd_soc_codec *codec = codec_dai->codec;
 576         unsigned int aifa;
 577         unsigned int aifb;
 578         int can_invert_lrclk;
 579
 580         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 581         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 582
 583         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 584
 585         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 586         case SND_SOC_DAIFMT_CBS_CFS:
 587                 aifa &= ~WM8580_AIF_MS;
 588                 break;
 589         case SND_SOC_DAIFMT_CBM_CFM:
 590                 aifa |= WM8580_AIF_MS;
 591                 break;
 592         default:
 593                 return -EINVAL;
 594         }
 595
 596         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 597         case SND_SOC_DAIFMT_I2S:
 598                 can_invert_lrclk = 1;
 599                 aifb |= WM8580_AIF_FMT_I2S;
 600                 break;
 601         case SND_SOC_DAIFMT_RIGHT_J:
 602                 can_invert_lrclk = 1;
 603                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 604                 break;
 605         case SND_SOC_DAIFMT_LEFT_J:
 606                 can_invert_lrclk = 1;
 607                 aifb |= WM8580_AIF_FMT_LEFTJ;
 608                 break;
 609         case SND_SOC_DAIFMT_DSP_A:
 610                 can_invert_lrclk = 0;
 611                 aifb |= WM8580_AIF_FMT_DSP;
 612                 break;
 613         case SND_SOC_DAIFMT_DSP_B:
 614                 can_invert_lrclk = 0;
 615                 aifb |= WM8580_AIF_FMT_DSP;
 616                 aifb |= WM8580_AIF_LRP;
 617                 break;
 618         default:
 619                 return -EINVAL;
 620         }
 621
 622         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 623         case SND_SOC_DAIFMT_NB_NF:
 624                 break;
 625
 626         case SND_SOC_DAIFMT_IB_IF:
 627                 if (!can_invert_lrclk)
 628                         return -EINVAL;
 629                 aifb |= WM8580_AIF_BCP;
 630                 aifb |= WM8580_AIF_LRP;
 631                 break;
 632
 633         case SND_SOC_DAIFMT_IB_NF:
 634                 aifb |= WM8580_AIF_BCP;
 635                 break;
 636
 637         case SND_SOC_DAIFMT_NB_IF:
 638                 if (!can_invert_lrclk)
 639                         return -EINVAL;
 640                 aifb |= WM8580_AIF_LRP;
 641                 break;
 642
 643         default:
 644                 return -EINVAL;
 645         }
 646
 647         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 648         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 649
 650         return 0;
 651 }
 652
 653 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 654                                  int div_id, int div)
 655 {
 656         struct snd_soc_codec *codec = codec_dai->codec;
 657         unsigned int reg;
 658
 659         switch (div_id) {
 660         case WM8580_MCLK:
 661                 reg = snd_soc_read(codec, WM8580_PLLB4);
 662                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 663
 664                 switch (div) {
 665                 case WM8580_CLKSRC_MCLK:
 666                         /* Input */
 667                         break;
 668
 669                 case WM8580_CLKSRC_PLLA:
 670                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 671                         break;
 672                 case WM8580_CLKSRC_PLLB:
 673                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 674                         break;
 675
 676                 case WM8580_CLKSRC_OSC:
 677                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 678                         break;
 679
 680                 default:
 681                         return -EINVAL;
 682                 }
 683                 snd_soc_write(codec, WM8580_PLLB4, reg);
 684                 break;
 685
 686         case WM8580_CLKOUTSRC:
 687                 reg = snd_soc_read(codec, WM8580_PLLB4);
 688                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 689
 690                 switch (div) {
 691                 case WM8580_CLKSRC_NONE:
 692                         break;
 693
 694                 case WM8580_CLKSRC_PLLA:
 695                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 696                         break;
 697
 698                 case WM8580_CLKSRC_PLLB:
 699                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 700                         break;
 701
 702                 case WM8580_CLKSRC_OSC:
 703                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 704                         break;
 705
 706                 default:
 707                         return -EINVAL;
 708                 }
 709                 snd_soc_write(codec, WM8580_PLLB4, reg);
 710                 break;
 711
 712         default:
 713                 return -EINVAL;
 714         }
 715
 716         return 0;
 717 }
 718
 719 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 720                              unsigned int freq, int dir)
 721 {
 722         struct snd_soc_codec *codec = dai->codec;
 723         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 724         int ret, sel, sel_mask, sel_shift;
 725
 726         switch (dai->driver->id) {
 727         case WM8580_DAI_PAIFRX:
 728                 sel_mask = 0x3;
 729                 sel_shift = 0;
 730                 break;
 731
 732         case WM8580_DAI_PAIFTX:
 733                 sel_mask = 0xc;
 734                 sel_shift = 2;
 735                 break;
 736
 737         default:
 738                 WARN(1, "Unknown DAI driver ID\n");
 739                 return -EINVAL;
 740         }
 741
 742         switch (clk_id) {
 743         case WM8580_CLKSRC_ADCMCLK:
 744                 if (dai->driver->id != WM8580_DAI_PAIFTX)
 745                         return -EINVAL;
 746                 sel = 0 << sel_shift;
 747                 break;
 748         case WM8580_CLKSRC_PLLA:
 749                 sel = 1 << sel_shift;
 750                 break;
 751         case WM8580_CLKSRC_PLLB:
 752                 sel = 2 << sel_shift;
 753                 break;
 754         case WM8580_CLKSRC_MCLK:
 755                 sel = 3 << sel_shift;
 756                 break;
 757         default:
 758                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
 759                 return -EINVAL;
 760         }
 761
 762         /* We really should validate PLL settings but not yet */
 763         wm8580->sysclk[dai->driver->id] = freq;
 764
 765         ret = snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
 766         if (ret < 0)
 767                 return ret;
 768
 769         return 0;
 770 }
 771
 772 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 773 {
 774         struct snd_soc_codec *codec = codec_dai->codec;
 775         unsigned int reg;
 776
 777         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 778
 779         if (mute)
 780                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 781         else
 782                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 783
 784         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 785
 786         return 0;
 787 }
 788
 789 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 790         enum snd_soc_bias_level level)
 791 {
 792         switch (level) {
 793         case SND_SOC_BIAS_ON:
 794         case SND_SOC_BIAS_PREPARE:
 795                 break;
 796
 797         case SND_SOC_BIAS_STANDBY:
 798                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 799                         /* Power up and get individual control of the DACs */
 800                         snd_soc_update_bits(codec, WM8580_PWRDN1,
 801                                             WM8580_PWRDN1_PWDN |
 802                                             WM8580_PWRDN1_ALLDACPD, 0);
 803
 804                         /* Make VMID high impedance */
 805                         snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
 806                                             0x100, 0);
 807                 }
 808                 break;
 809
 810         case SND_SOC_BIAS_OFF:
 811                 snd_soc_update_bits(codec, WM8580_PWRDN1,
 812                                     WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
 813                 break;
 814         }
 815         codec->dapm.bias_level = level;
 816         return 0;
 817 }
 818
 819 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 820                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 821
 822 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 823         .set_sysclk     = wm8580_set_sysclk,
 824         .hw_params      = wm8580_paif_hw_params,
 825         .set_fmt        = wm8580_set_paif_dai_fmt,
 826         .set_clkdiv     = wm8580_set_dai_clkdiv,
 827         .set_pll        = wm8580_set_dai_pll,
 828         .digital_mute   = wm8580_digital_mute,
 829 };
 830
 831 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 832         .set_sysclk     = wm8580_set_sysclk,
 833         .hw_params      = wm8580_paif_hw_params,
 834         .set_fmt        = wm8580_set_paif_dai_fmt,
 835         .set_clkdiv     = wm8580_set_dai_clkdiv,
 836         .set_pll        = wm8580_set_dai_pll,
 837 };
 838
 839 static struct snd_soc_dai_driver wm8580_dai[] = {
 840         {
 841                 .name = "wm8580-hifi-playback",
 842                 .id     = WM8580_DAI_PAIFRX,
 843                 .playback = {
 844                         .stream_name = "Playback",
 845                         .channels_min = 1,
 846                         .channels_max = 6,
 847                         .rates = SNDRV_PCM_RATE_8000_192000,
 848                         .formats = WM8580_FORMATS,
 849                 },
 850                 .ops = &wm8580_dai_ops_playback,
 851         },
 852         {
 853                 .name = "wm8580-hifi-capture",
 854                 .id     =       WM8580_DAI_PAIFTX,
 855                 .capture = {
 856                         .stream_name = "Capture",
 857                         .channels_min = 2,
 858                         .channels_max = 2,
 859                         .rates = SNDRV_PCM_RATE_8000_192000,
 860                         .formats = WM8580_FORMATS,
 861                 },
 862                 .ops = &wm8580_dai_ops_capture,
 863         },
 864 };
 865
 866 static int wm8580_probe(struct snd_soc_codec *codec)
 867 {
 868         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 869         int ret = 0;
 870
 871         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 872                                     wm8580->supplies);
 873         if (ret != 0) {
 874                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 875                 goto err_regulator_get;
 876         }
 877
 878         /* Get the codec into a known state */
 879         ret = snd_soc_write(codec, WM8580_RESET, 0);
 880         if (ret != 0) {
 881                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 882                 goto err_regulator_enable;
 883         }
 884
 885         return 0;
 886
 887 err_regulator_enable:
 888         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 889 err_regulator_get:
 890         return ret;
 891 }
 892
 893 /* power down chip */
 894 static int wm8580_remove(struct snd_soc_codec *codec)
 895 {
 896         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 897
 898         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 899
 900         return 0;
 901 }
 902
 903 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 904         .probe =        wm8580_probe,
 905         .remove =       wm8580_remove,
 906         .set_bias_level = wm8580_set_bias_level,
 907
 908         .controls = wm8580_snd_controls,
 909         .num_controls = ARRAY_SIZE(wm8580_snd_controls),
 910         .dapm_widgets = wm8580_dapm_widgets,
 911         .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
 912         .dapm_routes = wm8580_dapm_routes,
 913         .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
 914 };
 915
 916 static const struct of_device_id wm8580_of_match[] = {
 917         { .compatible = "wlf,wm8580" },
 918         { },
 919 };
 920
 921 static const struct regmap_config wm8580_regmap = {
 922         .reg_bits = 7,
 923         .val_bits = 9,
 924         .max_register = WM8580_MAX_REGISTER,
 925
 926         .reg_defaults = wm8580_reg_defaults,
 927         .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
 928         .cache_type = REGCACHE_RBTREE,
 929
 930         .volatile_reg = wm8580_volatile,
 931 };
 932
 933 #if IS_ENABLED(CONFIG_I2C)
 934 static int wm8580_i2c_probe(struct i2c_client *i2c,
 935                             const struct i2c_device_id *id)
 936 {
 937         struct wm8580_priv *wm8580;
 938         int ret, i;
 939
 940         wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
 941                               GFP_KERNEL);
 942         if (wm8580 == NULL)
 943                 return -ENOMEM;
 944
 945         wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
 946         if (IS_ERR(wm8580->regmap))
 947                 return PTR_ERR(wm8580->regmap);
 948
 949         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 950                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 951
 952         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
 953                                       wm8580->supplies);
 954         if (ret != 0) {
 955                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
 956                 return ret;
 957         }
 958
 959         i2c_set_clientdata(i2c, wm8580);
 960
 961         ret =  snd_soc_register_codec(&i2c->dev,
 962                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 963
 964         return ret;
 965 }
 966
 967 static int wm8580_i2c_remove(struct i2c_client *client)
 968 {
 969         snd_soc_unregister_codec(&client->dev);
 970         return 0;
 971 }
 972
 973 static const struct i2c_device_id wm8580_i2c_id[] = {
 974         { "wm8580", 0 },
 975         { }
 976 };
 977 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 978
 979 static struct i2c_driver wm8580_i2c_driver = {
 980         .driver = {
 981                 .name = "wm8580",
 982                 .owner = THIS_MODULE,
 983                 .of_match_table = wm8580_of_match,
 984         },
 985         .probe =    wm8580_i2c_probe,
 986         .remove =   wm8580_i2c_remove,
 987         .id_table = wm8580_i2c_id,
 988 };
 989 #endif
 990
 991 static int __init wm8580_modinit(void)
 992 {
 993         int ret = 0;
 994
 995 #if IS_ENABLED(CONFIG_I2C)
 996         ret = i2c_add_driver(&wm8580_i2c_driver);
 997         if (ret != 0) {
 998                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 999         }
1000 #endif
1001
1002         return ret;
1003 }
1004 module_init(wm8580_modinit);
1005
1006 static void __exit wm8580_exit(void)
1007 {
1008 #if IS_ENABLED(CONFIG_I2C)
1009         i2c_del_driver(&wm8580_i2c_driver);
1010 #endif
1011 }
1012 module_exit(wm8580_exit);
1013
1014 MODULE_DESCRIPTION("ASoC WM8580 driver");
1015 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1016 MODULE_LICENSE("GPL");