kernel/sound/pci/pcxhr/pcxhr.c

   1 /*
   2  * Driver for Digigram pcxhr compatible soundcards
   3  *
   4  * main file with alsa callbacks
   5  *
   6  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  */
  22
  23
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/slab.h>
  27 #include <linux/pci.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/delay.h>
  30 #include <linux/module.h>
  31 #include <linux/mutex.h>
  32
  33 #include <sound/core.h>
  34 #include <sound/initval.h>
  35 #include <sound/info.h>
  36 #include <sound/control.h>
  37 #include <sound/pcm.h>
  38 #include <sound/pcm_params.h>
  39 #include "pcxhr.h"
  40 #include "pcxhr_mixer.h"
  41 #include "pcxhr_hwdep.h"
  42 #include "pcxhr_core.h"
  43 #include "pcxhr_mix22.h"
  44
  45 #define DRIVER_NAME "pcxhr"
  46
  47 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
  48               "Marc Titinger <titinger@digigram.com>");
  49 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
  50 MODULE_LICENSE("GPL");
  51 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  55 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  56 static bool mono[SNDRV_CARDS];                          /* capture  mono only */
  57
  58 module_param_array(index, int, NULL, 0444);
  59 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
  60 module_param_array(id, charp, NULL, 0444);
  61 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
  62 module_param_array(enable, bool, NULL, 0444);
  63 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
  64 module_param_array(mono, bool, NULL, 0444);
  65 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
  66
  67 enum {
  68         PCI_ID_VX882HR,
  69         PCI_ID_PCX882HR,
  70         PCI_ID_VX881HR,
  71         PCI_ID_PCX881HR,
  72         PCI_ID_VX882E,
  73         PCI_ID_PCX882E,
  74         PCI_ID_VX881E,
  75         PCI_ID_PCX881E,
  76         PCI_ID_VX1222HR,
  77         PCI_ID_PCX1222HR,
  78         PCI_ID_VX1221HR,
  79         PCI_ID_PCX1221HR,
  80         PCI_ID_VX1222E,
  81         PCI_ID_PCX1222E,
  82         PCI_ID_VX1221E,
  83         PCI_ID_PCX1221E,
  84         PCI_ID_VX222HR,
  85         PCI_ID_VX222E,
  86         PCI_ID_PCX22HR,
  87         PCI_ID_PCX22E,
  88         PCI_ID_VX222HRMIC,
  89         PCI_ID_VX222E_MIC,
  90         PCI_ID_PCX924HR,
  91         PCI_ID_PCX924E,
  92         PCI_ID_PCX924HRMIC,
  93         PCI_ID_PCX924E_MIC,
  94         PCI_ID_VX442HR,
  95         PCI_ID_PCX442HR,
  96         PCI_ID_VX442E,
  97         PCI_ID_PCX442E,
  98         PCI_ID_VX822HR,
  99         PCI_ID_PCX822HR,
 100         PCI_ID_VX822E,
 101         PCI_ID_PCX822E,
 102         PCI_ID_LAST
 103 };
 104
 105 static const struct pci_device_id pcxhr_ids[] = {
 106         { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
 107         { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
 108         { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
 109         { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
 110         { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
 111         { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
 112         { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
 113         { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
 114         { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
 115         { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
 116         { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
 117         { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
 118         { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
 119         { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
 120         { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
 121         { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
 122         { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
 123         { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
 124         { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
 125         { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
 126         { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
 127         { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
 128         { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
 129         { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
 130         { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
 131         { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
 132         { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, },
 133         { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, },
 134         { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, },
 135         { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, },
 136         { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, },
 137         { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, },
 138         { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, },
 139         { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, },
 140         { 0, }
 141 };
 142
 143 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
 144
 145 struct board_parameters {
 146         char* board_name;
 147         short playback_chips;
 148         short capture_chips;
 149         short fw_file_set;
 150         short firmware_num;
 151 };
 152 static struct board_parameters pcxhr_board_params[] = {
 153 [PCI_ID_VX882HR] =      { "VX882HR",      4, 4, 0, 41 },
 154 [PCI_ID_PCX882HR] =     { "PCX882HR",     4, 4, 0, 41 },
 155 [PCI_ID_VX881HR] =      { "VX881HR",      4, 4, 0, 41 },
 156 [PCI_ID_PCX881HR] =     { "PCX881HR",     4, 4, 0, 41 },
 157 [PCI_ID_VX882E] =       { "VX882e",       4, 4, 1, 41 },
 158 [PCI_ID_PCX882E] =      { "PCX882e",      4, 4, 1, 41 },
 159 [PCI_ID_VX881E] =       { "VX881e",       4, 4, 1, 41 },
 160 [PCI_ID_PCX881E] =      { "PCX881e",      4, 4, 1, 41 },
 161 [PCI_ID_VX1222HR] =     { "VX1222HR",     6, 1, 2, 42 },
 162 [PCI_ID_PCX1222HR] =    { "PCX1222HR",    6, 1, 2, 42 },
 163 [PCI_ID_VX1221HR] =     { "VX1221HR",     6, 1, 2, 42 },
 164 [PCI_ID_PCX1221HR] =    { "PCX1221HR",    6, 1, 2, 42 },
 165 [PCI_ID_VX1222E] =      { "VX1222e",      6, 1, 3, 42 },
 166 [PCI_ID_PCX1222E] =     { "PCX1222e",     6, 1, 3, 42 },
 167 [PCI_ID_VX1221E] =      { "VX1221e",      6, 1, 3, 42 },
 168 [PCI_ID_PCX1221E] =     { "PCX1221e",     6, 1, 3, 42 },
 169 [PCI_ID_VX222HR] =      { "VX222HR",      1, 1, 4, 44 },
 170 [PCI_ID_VX222E] =       { "VX222e",       1, 1, 4, 44 },
 171 [PCI_ID_PCX22HR] =      { "PCX22HR",      1, 0, 4, 44 },
 172 [PCI_ID_PCX22E] =       { "PCX22e",       1, 0, 4, 44 },
 173 [PCI_ID_VX222HRMIC] =   { "VX222HR-Mic",  1, 1, 5, 44 },
 174 [PCI_ID_VX222E_MIC] =   { "VX222e-Mic",   1, 1, 5, 44 },
 175 [PCI_ID_PCX924HR] =     { "PCX924HR",     1, 1, 5, 44 },
 176 [PCI_ID_PCX924E] =      { "PCX924e",      1, 1, 5, 44 },
 177 [PCI_ID_PCX924HRMIC] =  { "PCX924HR-Mic", 1, 1, 5, 44 },
 178 [PCI_ID_PCX924E_MIC] =  { "PCX924e-Mic",  1, 1, 5, 44 },
 179 [PCI_ID_VX442HR] =      { "VX442HR",      2, 2, 0, 41 },
 180 [PCI_ID_PCX442HR] =     { "PCX442HR",     2, 2, 0, 41 },
 181 [PCI_ID_VX442E] =       { "VX442e",       2, 2, 1, 41 },
 182 [PCI_ID_PCX442E] =      { "PCX442e",      2, 2, 1, 41 },
 183 [PCI_ID_VX822HR] =      { "VX822HR",      4, 1, 2, 42 },
 184 [PCI_ID_PCX822HR] =     { "PCX822HR",     4, 1, 2, 42 },
 185 [PCI_ID_VX822E] =       { "VX822e",       4, 1, 3, 42 },
 186 [PCI_ID_PCX822E] =      { "PCX822e",      4, 1, 3, 42 },
 187 };
 188
 189 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
 190 /* VX222HR, VX222e, PCX22HR and PCX22e */
 191 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
 192 /* some boards do not support 192kHz on digital AES input plugs */
 193 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
 194                                       (x->fw_file_set == 0)   || \
 195                                       (x->fw_file_set == 2))
 196
 197 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
 198                                    unsigned int* realfreq)
 199 {
 200         unsigned int reg;
 201
 202         if (freq < 6900 || freq > 110000)
 203                 return -EINVAL;
 204         reg = (28224000 * 2) / freq;
 205         reg = (reg - 1) / 2;
 206         if (reg < 0x200)
 207                 *pllreg = reg + 0x800;
 208         else if (reg < 0x400)
 209                 *pllreg = reg & 0x1ff;
 210         else if (reg < 0x800) {
 211                 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
 212                 reg &= ~1;
 213         } else {
 214                 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
 215                 reg &= ~3;
 216         }
 217         if (realfreq)
 218                 *realfreq = (28224000 / (reg + 1));
 219         return 0;
 220 }
 221
 222
 223 #define PCXHR_FREQ_REG_MASK             0x1f
 224 #define PCXHR_FREQ_QUARTZ_48000         0x00
 225 #define PCXHR_FREQ_QUARTZ_24000         0x01
 226 #define PCXHR_FREQ_QUARTZ_12000         0x09
 227 #define PCXHR_FREQ_QUARTZ_32000         0x08
 228 #define PCXHR_FREQ_QUARTZ_16000         0x04
 229 #define PCXHR_FREQ_QUARTZ_8000          0x0c
 230 #define PCXHR_FREQ_QUARTZ_44100         0x02
 231 #define PCXHR_FREQ_QUARTZ_22050         0x0a
 232 #define PCXHR_FREQ_QUARTZ_11025         0x06
 233 #define PCXHR_FREQ_PLL                  0x05
 234 #define PCXHR_FREQ_QUARTZ_192000        0x10
 235 #define PCXHR_FREQ_QUARTZ_96000         0x18
 236 #define PCXHR_FREQ_QUARTZ_176400        0x14
 237 #define PCXHR_FREQ_QUARTZ_88200         0x1c
 238 #define PCXHR_FREQ_QUARTZ_128000        0x12
 239 #define PCXHR_FREQ_QUARTZ_64000         0x1a
 240
 241 #define PCXHR_FREQ_WORD_CLOCK           0x0f
 242 #define PCXHR_FREQ_SYNC_AES             0x0e
 243 #define PCXHR_FREQ_AES_1                0x07
 244 #define PCXHR_FREQ_AES_2                0x0b
 245 #define PCXHR_FREQ_AES_3                0x03
 246 #define PCXHR_FREQ_AES_4                0x0d
 247
 248 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
 249                                unsigned int *reg, unsigned int *freq)
 250 {
 251         unsigned int val, realfreq, pllreg;
 252         struct pcxhr_rmh rmh;
 253         int err;
 254
 255         realfreq = rate;
 256         switch (mgr->use_clock_type) {
 257         case PCXHR_CLOCK_TYPE_INTERNAL :        /* clock by quartz or pll */
 258                 switch (rate) {
 259                 case 48000 :    val = PCXHR_FREQ_QUARTZ_48000;  break;
 260                 case 24000 :    val = PCXHR_FREQ_QUARTZ_24000;  break;
 261                 case 12000 :    val = PCXHR_FREQ_QUARTZ_12000;  break;
 262                 case 32000 :    val = PCXHR_FREQ_QUARTZ_32000;  break;
 263                 case 16000 :    val = PCXHR_FREQ_QUARTZ_16000;  break;
 264                 case 8000 :     val = PCXHR_FREQ_QUARTZ_8000;   break;
 265                 case 44100 :    val = PCXHR_FREQ_QUARTZ_44100;  break;
 266                 case 22050 :    val = PCXHR_FREQ_QUARTZ_22050;  break;
 267                 case 11025 :    val = PCXHR_FREQ_QUARTZ_11025;  break;
 268                 case 192000 :   val = PCXHR_FREQ_QUARTZ_192000; break;
 269                 case 96000 :    val = PCXHR_FREQ_QUARTZ_96000;  break;
 270                 case 176400 :   val = PCXHR_FREQ_QUARTZ_176400; break;
 271                 case 88200 :    val = PCXHR_FREQ_QUARTZ_88200;  break;
 272                 case 128000 :   val = PCXHR_FREQ_QUARTZ_128000; break;
 273                 case 64000 :    val = PCXHR_FREQ_QUARTZ_64000;  break;
 274                 default :
 275                         val = PCXHR_FREQ_PLL;
 276                         /* get the value for the pll register */
 277                         err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
 278                         if (err)
 279                                 return err;
 280                         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
 281                         rmh.cmd[0] |= IO_NUM_REG_GENCLK;
 282                         rmh.cmd[1]  = pllreg & MASK_DSP_WORD;
 283                         rmh.cmd[2]  = pllreg >> 24;
 284                         rmh.cmd_len = 3;
 285                         err = pcxhr_send_msg(mgr, &rmh);
 286                         if (err < 0) {
 287                                 dev_err(&mgr->pci->dev,
 288                                            "error CMD_ACCESS_IO_WRITE "
 289                                            "for PLL register : %x!\n", err);
 290                                 return err;
 291                         }
 292                 }
 293                 break;
 294         case PCXHR_CLOCK_TYPE_WORD_CLOCK:
 295                 val = PCXHR_FREQ_WORD_CLOCK;
 296                 break;
 297         case PCXHR_CLOCK_TYPE_AES_SYNC:
 298                 val = PCXHR_FREQ_SYNC_AES;
 299                 break;
 300         case PCXHR_CLOCK_TYPE_AES_1:
 301                 val = PCXHR_FREQ_AES_1;
 302                 break;
 303         case PCXHR_CLOCK_TYPE_AES_2:
 304                 val = PCXHR_FREQ_AES_2;
 305                 break;
 306         case PCXHR_CLOCK_TYPE_AES_3:
 307                 val = PCXHR_FREQ_AES_3;
 308                 break;
 309         case PCXHR_CLOCK_TYPE_AES_4:
 310                 val = PCXHR_FREQ_AES_4;
 311                 break;
 312         default:
 313                 return -EINVAL;
 314         }
 315         *reg = val;
 316         *freq = realfreq;
 317         return 0;
 318 }
 319
 320
 321 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
 322                                unsigned int rate,
 323                                int *changed)
 324 {
 325         unsigned int val, realfreq, speed;
 326         struct pcxhr_rmh rmh;
 327         int err;
 328
 329         err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
 330         if (err)
 331                 return err;
 332
 333         /* codec speed modes */
 334         if (rate < 55000)
 335                 speed = 0;      /* single speed */
 336         else if (rate < 100000)
 337                 speed = 1;      /* dual speed */
 338         else
 339                 speed = 2;      /* quad speed */
 340         if (mgr->codec_speed != speed) {
 341                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
 342                 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
 343                 if (DSP_EXT_CMD_SET(mgr)) {
 344                         rmh.cmd[1]  = 1;
 345                         rmh.cmd_len = 2;
 346                 }
 347                 err = pcxhr_send_msg(mgr, &rmh);
 348                 if (err)
 349                         return err;
 350
 351                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
 352                 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
 353                 rmh.cmd[1] = speed;
 354                 rmh.cmd_len = 2;
 355                 err = pcxhr_send_msg(mgr, &rmh);
 356                 if (err)
 357                         return err;
 358         }
 359         /* set the new frequency */
 360         dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
 361         err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
 362                                           val, changed);
 363         if (err)
 364                 return err;
 365
 366         mgr->sample_rate_real = realfreq;
 367         mgr->cur_clock_type = mgr->use_clock_type;
 368
 369         /* unmute after codec speed modes */
 370         if (mgr->codec_speed != speed) {
 371                 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
 372                 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
 373                 if (DSP_EXT_CMD_SET(mgr)) {
 374                         rmh.cmd[1]  = 1;
 375                         rmh.cmd_len = 2;
 376                 }
 377                 err = pcxhr_send_msg(mgr, &rmh);
 378                 if (err)
 379                         return err;
 380                 mgr->codec_speed = speed;       /* save new codec speed */
 381         }
 382
 383         dev_dbg(&mgr->pci->dev, "pcxhr_sub_set_clock to %dHz (realfreq=%d)\n",
 384                     rate, realfreq);
 385         return 0;
 386 }
 387
 388 #define PCXHR_MODIFY_CLOCK_S_BIT        0x04
 389
 390 #define PCXHR_IRQ_TIMER_FREQ            92000
 391 #define PCXHR_IRQ_TIMER_PERIOD          48
 392
 393 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
 394 {
 395         struct pcxhr_rmh rmh;
 396         int err, changed;
 397
 398         if (rate == 0)
 399                 return 0; /* nothing to do */
 400
 401         if (mgr->is_hr_stereo)
 402                 err = hr222_sub_set_clock(mgr, rate, &changed);
 403         else
 404                 err = pcxhr_sub_set_clock(mgr, rate, &changed);
 405
 406         if (err)
 407                 return err;
 408
 409         if (changed) {
 410                 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
 411                 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos  */
 412                 if (rate < PCXHR_IRQ_TIMER_FREQ)
 413                         rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
 414                 else
 415                         rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
 416                 rmh.cmd[2] = rate;
 417                 rmh.cmd_len = 3;
 418                 err = pcxhr_send_msg(mgr, &rmh);
 419                 if (err)
 420                         return err;
 421         }
 422         return 0;
 423 }
 424
 425
 426 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
 427                                         enum pcxhr_clock_type clock_type,
 428                                         int *sample_rate)
 429 {
 430         struct pcxhr_rmh rmh;
 431         unsigned char reg;
 432         int err, rate;
 433
 434         switch (clock_type) {
 435         case PCXHR_CLOCK_TYPE_WORD_CLOCK:
 436                 reg = REG_STATUS_WORD_CLOCK;
 437                 break;
 438         case PCXHR_CLOCK_TYPE_AES_SYNC:
 439                 reg = REG_STATUS_AES_SYNC;
 440                 break;
 441         case PCXHR_CLOCK_TYPE_AES_1:
 442                 reg = REG_STATUS_AES_1;
 443                 break;
 444         case PCXHR_CLOCK_TYPE_AES_2:
 445                 reg = REG_STATUS_AES_2;
 446                 break;
 447         case PCXHR_CLOCK_TYPE_AES_3:
 448                 reg = REG_STATUS_AES_3;
 449                 break;
 450         case PCXHR_CLOCK_TYPE_AES_4:
 451                 reg = REG_STATUS_AES_4;
 452                 break;
 453         default:
 454                 return -EINVAL;
 455         }
 456         pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
 457         rmh.cmd_len = 2;
 458         rmh.cmd[0] |= IO_NUM_REG_STATUS;
 459         if (mgr->last_reg_stat != reg) {
 460                 rmh.cmd[1]  = reg;
 461                 err = pcxhr_send_msg(mgr, &rmh);
 462                 if (err)
 463                         return err;
 464                 udelay(100);    /* wait minimum 2 sample_frames at 32kHz ! */
 465                 mgr->last_reg_stat = reg;
 466         }
 467         rmh.cmd[1]  = REG_STATUS_CURRENT;
 468         err = pcxhr_send_msg(mgr, &rmh);
 469         if (err)
 470                 return err;
 471         switch (rmh.stat[1] & 0x0f) {
 472         case REG_STATUS_SYNC_32000 :    rate = 32000; break;
 473         case REG_STATUS_SYNC_44100 :    rate = 44100; break;
 474         case REG_STATUS_SYNC_48000 :    rate = 48000; break;
 475         case REG_STATUS_SYNC_64000 :    rate = 64000; break;
 476         case REG_STATUS_SYNC_88200 :    rate = 88200; break;
 477         case REG_STATUS_SYNC_96000 :    rate = 96000; break;
 478         case REG_STATUS_SYNC_128000 :   rate = 128000; break;
 479         case REG_STATUS_SYNC_176400 :   rate = 176400; break;
 480         case REG_STATUS_SYNC_192000 :   rate = 192000; break;
 481         default: rate = 0;
 482         }
 483         dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
 484         *sample_rate = rate;
 485         return 0;
 486 }
 487
 488
 489 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
 490                              enum pcxhr_clock_type clock_type,
 491                              int *sample_rate)
 492 {
 493         if (mgr->is_hr_stereo)
 494                 return hr222_get_external_clock(mgr, clock_type,
 495                                                 sample_rate);
 496         else
 497                 return pcxhr_sub_get_external_clock(mgr, clock_type,
 498                                                     sample_rate);
 499 }
 500
 501 /*
 502  *  start or stop playback/capture substream
 503  */
 504 static int pcxhr_set_stream_state(struct snd_pcxhr *chip,
 505                                   struct pcxhr_stream *stream)
 506 {
 507         int err;
 508         struct pcxhr_rmh rmh;
 509         int stream_mask, start;
 510
 511         if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
 512                 start = 1;
 513         else {
 514                 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
 515                         dev_err(chip->card->dev,
 516                                 "pcxhr_set_stream_state CANNOT be stopped\n");
 517                         return -EINVAL;
 518                 }
 519                 start = 0;
 520         }
 521         if (!stream->substream)
 522                 return -EINVAL;
 523
 524         stream->timer_abs_periods = 0;
 525         stream->timer_period_frag = 0;  /* reset theoretical stream pos */
 526         stream->timer_buf_periods = 0;
 527         stream->timer_is_synced = 0;
 528
 529         stream_mask =
 530           stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
 531
 532         pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
 533         pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
 534                                   stream->pipe->first_audio, 0, stream_mask);
 535
 536         chip = snd_pcm_substream_chip(stream->substream);
 537
 538         err = pcxhr_send_msg(chip->mgr, &rmh);
 539         if (err)
 540                 dev_err(chip->card->dev,
 541                         "ERROR pcxhr_set_stream_state err=%x;\n", err);
 542         stream->status =
 543           start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
 544         return err;
 545 }
 546
 547 #define HEADER_FMT_BASE_LIN             0xfed00000
 548 #define HEADER_FMT_BASE_FLOAT           0xfad00000
 549 #define HEADER_FMT_INTEL                0x00008000
 550 #define HEADER_FMT_24BITS               0x00004000
 551 #define HEADER_FMT_16BITS               0x00002000
 552 #define HEADER_FMT_UPTO11               0x00000200
 553 #define HEADER_FMT_UPTO32               0x00000100
 554 #define HEADER_FMT_MONO                 0x00000080
 555
 556 static int pcxhr_set_format(struct pcxhr_stream *stream)
 557 {
 558         int err, is_capture, sample_rate, stream_num;
 559         struct snd_pcxhr *chip;
 560         struct pcxhr_rmh rmh;
 561         unsigned int header;
 562
 563         chip = snd_pcm_substream_chip(stream->substream);
 564         switch (stream->format) {
 565         case SNDRV_PCM_FORMAT_U8:
 566                 header = HEADER_FMT_BASE_LIN;
 567                 break;
 568         case SNDRV_PCM_FORMAT_S16_LE:
 569                 header = HEADER_FMT_BASE_LIN |
 570                          HEADER_FMT_16BITS | HEADER_FMT_INTEL;
 571                 break;
 572         case SNDRV_PCM_FORMAT_S16_BE:
 573                 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
 574                 break;
 575         case SNDRV_PCM_FORMAT_S24_3LE:
 576                 header = HEADER_FMT_BASE_LIN |
 577                          HEADER_FMT_24BITS | HEADER_FMT_INTEL;
 578                 break;
 579         case SNDRV_PCM_FORMAT_S24_3BE:
 580                 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
 581                 break;
 582         case SNDRV_PCM_FORMAT_FLOAT_LE:
 583                 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
 584                 break;
 585         default:
 586                 dev_err(chip->card->dev,
 587                         "error pcxhr_set_format() : unknown format\n");
 588                 return -EINVAL;
 589         }
 590
 591         sample_rate = chip->mgr->sample_rate;
 592         if (sample_rate <= 32000 && sample_rate !=0) {
 593                 if (sample_rate <= 11025)
 594                         header |= HEADER_FMT_UPTO11;
 595                 else
 596                         header |= HEADER_FMT_UPTO32;
 597         }
 598         if (stream->channels == 1)
 599                 header |= HEADER_FMT_MONO;
 600
 601         is_capture = stream->pipe->is_capture;
 602         stream_num = is_capture ? 0 : stream->substream->number;
 603
 604         pcxhr_init_rmh(&rmh, is_capture ?
 605                        CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
 606         pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
 607                                   stream_num, 0);
 608         if (is_capture) {
 609                 /* bug with old dsp versions: */
 610                 /* bit 12 also sets the format of the playback stream */
 611                 if (DSP_EXT_CMD_SET(chip->mgr))
 612                         rmh.cmd[0] |= 1<<10;
 613                 else
 614                         rmh.cmd[0] |= 1<<12;
 615         }
 616         rmh.cmd[1] = 0;
 617         rmh.cmd_len = 2;
 618         if (DSP_EXT_CMD_SET(chip->mgr)) {
 619                 /* add channels and set bit 19 if channels>2 */
 620                 rmh.cmd[1] = stream->channels;
 621                 if (!is_capture) {
 622                         /* playback : add channel mask to command */
 623                         rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
 624                         rmh.cmd_len = 3;
 625                 }
 626         }
 627         rmh.cmd[rmh.cmd_len++] = header >> 8;
 628         rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
 629         err = pcxhr_send_msg(chip->mgr, &rmh);
 630         if (err)
 631                 dev_err(chip->card->dev,
 632                         "ERROR pcxhr_set_format err=%x;\n", err);
 633         return err;
 634 }
 635
 636 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
 637 {
 638         int err, is_capture, stream_num;
 639         struct pcxhr_rmh rmh;
 640         struct snd_pcm_substream *subs = stream->substream;
 641         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
 642
 643         is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
 644         stream_num = is_capture ? 0 : subs->number;
 645
 646         dev_dbg(chip->card->dev,
 647                 "pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
 648                 is_capture ? 'c' : 'p',
 649                 chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
 650                 subs->runtime->dma_bytes, subs->number);
 651
 652         pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
 653         pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
 654                                   stream_num, 0);
 655
 656         /* max buffer size is 2 MByte */
 657         snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
 658         /* size in bits */
 659         rmh.cmd[1] = subs->runtime->dma_bytes * 8;
 660         /* most significant byte */
 661         rmh.cmd[2] = subs->runtime->dma_addr >> 24;
 662         /* this is a circular buffer */
 663         rmh.cmd[2] |= 1<<19;
 664         /* least 3 significant bytes */
 665         rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
 666         rmh.cmd_len = 4;
 667         err = pcxhr_send_msg(chip->mgr, &rmh);
 668         if (err)
 669                 dev_err(chip->card->dev,
 670                            "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
 671         return err;
 672 }
 673
 674
 675 #if 0
 676 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
 677                                    snd_pcm_uframes_t *sample_count)
 678 {
 679         struct pcxhr_rmh rmh;
 680         int err;
 681         pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
 682         pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
 683         pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
 684                                   1<<stream->pipe->first_audio);
 685         err = pcxhr_send_msg(chip->mgr, &rmh);
 686         if (err == 0) {
 687                 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
 688                 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
 689         }
 690         dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
 691         return err;
 692 }
 693 #endif
 694
 695 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
 696                                                   struct pcxhr_pipe **pipe)
 697 {
 698         if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
 699                 *pipe = stream->pipe;
 700                 return 1;
 701         }
 702         return 0;
 703 }
 704
 705 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
 706 {
 707         int i, j, err;
 708         struct pcxhr_pipe *pipe;
 709         struct snd_pcxhr *chip;
 710         int capture_mask = 0;
 711         int playback_mask = 0;
 712
 713 #ifdef CONFIG_SND_DEBUG_VERBOSE
 714         ktime_t start_time, stop_time, diff_time;
 715
 716         start_time = ktime_get();
 717 #endif
 718         mutex_lock(&mgr->setup_mutex);
 719
 720         /* check the pipes concerned and build pipe_array */
 721         for (i = 0; i < mgr->num_cards; i++) {
 722                 chip = mgr->chip[i];
 723                 for (j = 0; j < chip->nb_streams_capt; j++) {
 724                         if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
 725                                 capture_mask |= (1 << pipe->first_audio);
 726                 }
 727                 for (j = 0; j < chip->nb_streams_play; j++) {
 728                         if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
 729                                 playback_mask |= (1 << pipe->first_audio);
 730                                 break;  /* add only once, as all playback
 731                                          * streams of one chip use the same pipe
 732                                          */
 733                         }
 734                 }
 735         }
 736         if (capture_mask == 0 && playback_mask == 0) {
 737                 mutex_unlock(&mgr->setup_mutex);
 738                 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : no pipes\n");
 739                 return;
 740         }
 741
 742         dev_dbg(&mgr->pci->dev, "pcxhr_start_linked_stream : "
 743                     "playback_mask=%x capture_mask=%x\n",
 744                     playback_mask, capture_mask);
 745
 746         /* synchronous stop of all the pipes concerned */
 747         err = pcxhr_set_pipe_state(mgr,  playback_mask, capture_mask, 0);
 748         if (err) {
 749                 mutex_unlock(&mgr->setup_mutex);
 750                 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
 751                            "error stop pipes (P%x C%x)\n",
 752                            playback_mask, capture_mask);
 753                 return;
 754         }
 755
 756         /* the dsp lost format and buffer info with the stop pipe */
 757         for (i = 0; i < mgr->num_cards; i++) {
 758                 struct pcxhr_stream *stream;
 759                 chip = mgr->chip[i];
 760                 for (j = 0; j < chip->nb_streams_capt; j++) {
 761                         stream = &chip->capture_stream[j];
 762                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
 763                                 err = pcxhr_set_format(stream);
 764                                 err = pcxhr_update_r_buffer(stream);
 765                         }
 766                 }
 767                 for (j = 0; j < chip->nb_streams_play; j++) {
 768                         stream = &chip->playback_stream[j];
 769                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
 770                                 err = pcxhr_set_format(stream);
 771                                 err = pcxhr_update_r_buffer(stream);
 772                         }
 773                 }
 774         }
 775         /* start all the streams */
 776         for (i = 0; i < mgr->num_cards; i++) {
 777                 struct pcxhr_stream *stream;
 778                 chip = mgr->chip[i];
 779                 for (j = 0; j < chip->nb_streams_capt; j++) {
 780                         stream = &chip->capture_stream[j];
 781                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
 782                                 err = pcxhr_set_stream_state(chip, stream);
 783                 }
 784                 for (j = 0; j < chip->nb_streams_play; j++) {
 785                         stream = &chip->playback_stream[j];
 786                         if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
 787                                 err = pcxhr_set_stream_state(chip, stream);
 788                 }
 789         }
 790
 791         /* synchronous start of all the pipes concerned */
 792         err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
 793         if (err) {
 794                 mutex_unlock(&mgr->setup_mutex);
 795                 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
 796                            "error start pipes (P%x C%x)\n",
 797                            playback_mask, capture_mask);
 798                 return;
 799         }
 800
 801         /* put the streams into the running state now
 802          * (increment pointer by interrupt)
 803          */
 804         mutex_lock(&mgr->lock);
 805         for ( i =0; i < mgr->num_cards; i++) {
 806                 struct pcxhr_stream *stream;
 807                 chip = mgr->chip[i];
 808                 for(j = 0; j < chip->nb_streams_capt; j++) {
 809                         stream = &chip->capture_stream[j];
 810                         if(stream->status == PCXHR_STREAM_STATUS_STARTED)
 811                                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
 812                 }
 813                 for (j = 0; j < chip->nb_streams_play; j++) {
 814                         stream = &chip->playback_stream[j];
 815                         if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
 816                                 /* playback will already have advanced ! */
 817                                 stream->timer_period_frag += mgr->granularity;
 818                                 stream->status = PCXHR_STREAM_STATUS_RUNNING;
 819                         }
 820                 }
 821         }
 822         mutex_unlock(&mgr->lock);
 823
 824         mutex_unlock(&mgr->setup_mutex);
 825
 826 #ifdef CONFIG_SND_DEBUG_VERBOSE
 827         stop_time = ktime_get();
 828         diff_time = ktime_sub(stop_time, start_time);
 829         dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
 830                     (long)(ktime_to_ns(diff_time)), err);
 831 #endif
 832 }
 833
 834
 835 /*
 836  *  trigger callback
 837  */
 838 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
 839 {
 840         struct pcxhr_stream *stream;
 841         struct snd_pcm_substream *s;
 842         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
 843
 844         switch (cmd) {
 845         case SNDRV_PCM_TRIGGER_START:
 846                 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n");
 847                 if (snd_pcm_stream_linked(subs)) {
 848                         snd_pcm_group_for_each_entry(s, subs) {
 849                                 if (snd_pcm_substream_chip(s) != chip)
 850                                         continue;
 851                                 stream = s->runtime->private_data;
 852                                 stream->status =
 853                                         PCXHR_STREAM_STATUS_SCHEDULE_RUN;
 854                                 snd_pcm_trigger_done(s, subs);
 855                         }
 856                         pcxhr_start_linked_stream(chip->mgr);
 857                 } else {
 858                         stream = subs->runtime->private_data;
 859                         dev_dbg(chip->card->dev, "Only one Substream %c %d\n",
 860                                     stream->pipe->is_capture ? 'C' : 'P',
 861                                     stream->pipe->first_audio);
 862                         if (pcxhr_set_format(stream))
 863                                 return -EINVAL;
 864                         if (pcxhr_update_r_buffer(stream))
 865                                 return -EINVAL;
 866
 867                         stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
 868                         if (pcxhr_set_stream_state(chip, stream))
 869                                 return -EINVAL;
 870                         stream->status = PCXHR_STREAM_STATUS_RUNNING;
 871                 }
 872                 break;
 873         case SNDRV_PCM_TRIGGER_STOP:
 874                 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n");
 875                 snd_pcm_group_for_each_entry(s, subs) {
 876                         stream = s->runtime->private_data;
 877                         stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
 878                         if (pcxhr_set_stream_state(chip, stream))
 879                                 return -EINVAL;
 880                         snd_pcm_trigger_done(s, subs);
 881                 }
 882                 break;
 883         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 884         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 885                 /* TODO */
 886         default:
 887                 return -EINVAL;
 888         }
 889         return 0;
 890 }
 891
 892
 893 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
 894 {
 895         struct pcxhr_rmh rmh;
 896         int err;
 897
 898         pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
 899         if (start) {
 900                 /* last dsp time invalid */
 901                 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
 902                 rmh.cmd[0] |= mgr->granularity;
 903         }
 904         err = pcxhr_send_msg(mgr, &rmh);
 905         if (err < 0)
 906                 dev_err(&mgr->pci->dev, "error pcxhr_hardware_timer err(%x)\n",
 907                            err);
 908         return err;
 909 }
 910
 911 /*
 912  *  prepare callback for all pcms
 913  */
 914 static int pcxhr_prepare(struct snd_pcm_substream *subs)
 915 {
 916         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
 917         struct pcxhr_mgr *mgr = chip->mgr;
 918         int err = 0;
 919
 920         dev_dbg(chip->card->dev,
 921                 "pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
 922                     subs->runtime->period_size, subs->runtime->periods,
 923                     subs->runtime->buffer_size);
 924
 925         mutex_lock(&mgr->setup_mutex);
 926
 927         do {
 928                 /* only the first stream can choose the sample rate */
 929                 /* set the clock only once (first stream) */
 930                 if (mgr->sample_rate != subs->runtime->rate) {
 931                         err = pcxhr_set_clock(mgr, subs->runtime->rate);
 932                         if (err)
 933                                 break;
 934                         if (mgr->sample_rate == 0)
 935                                 /* start the DSP-timer */
 936                                 err = pcxhr_hardware_timer(mgr, 1);
 937                         mgr->sample_rate = subs->runtime->rate;
 938                 }
 939         } while(0);     /* do only once (so we can use break instead of goto) */
 940
 941         mutex_unlock(&mgr->setup_mutex);
 942
 943         return err;
 944 }
 945
 946
 947 /*
 948  *  HW_PARAMS callback for all pcms
 949  */
 950 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
 951                            struct snd_pcm_hw_params *hw)
 952 {
 953         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
 954         struct pcxhr_mgr *mgr = chip->mgr;
 955         struct pcxhr_stream *stream = subs->runtime->private_data;
 956         snd_pcm_format_t format;
 957         int err;
 958         int channels;
 959
 960         /* set up channels */
 961         channels = params_channels(hw);
 962
 963         /*  set up format for the stream */
 964         format = params_format(hw);
 965
 966         mutex_lock(&mgr->setup_mutex);
 967
 968         stream->channels = channels;
 969         stream->format = format;
 970
 971         /* allocate buffer */
 972         err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
 973
 974         mutex_unlock(&mgr->setup_mutex);
 975
 976         return err;
 977 }
 978
 979 static int pcxhr_hw_free(struct snd_pcm_substream *subs)
 980 {
 981         snd_pcm_lib_free_pages(subs);
 982         return 0;
 983 }
 984
 985
 986 /*
 987  *  CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
 988  */
 989 static struct snd_pcm_hardware pcxhr_caps =
 990 {
 991         .info             = (SNDRV_PCM_INFO_MMAP |
 992                              SNDRV_PCM_INFO_INTERLEAVED |
 993                              SNDRV_PCM_INFO_MMAP_VALID |
 994                              SNDRV_PCM_INFO_SYNC_START),
 995         .formats          = (SNDRV_PCM_FMTBIT_U8 |
 996                              SNDRV_PCM_FMTBIT_S16_LE |
 997                              SNDRV_PCM_FMTBIT_S16_BE |
 998                              SNDRV_PCM_FMTBIT_S24_3LE |
 999                              SNDRV_PCM_FMTBIT_S24_3BE |
1000                              SNDRV_PCM_FMTBIT_FLOAT_LE),
1001         .rates            = (SNDRV_PCM_RATE_CONTINUOUS |
1002                              SNDRV_PCM_RATE_8000_192000),
1003         .rate_min         = 8000,
1004         .rate_max         = 192000,
1005         .channels_min     = 1,
1006         .channels_max     = 2,
1007         .buffer_bytes_max = (32*1024),
1008         /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
1009         .period_bytes_min = (2*PCXHR_GRANULARITY),
1010         .period_bytes_max = (16*1024),
1011         .periods_min      = 2,
1012         .periods_max      = (32*1024/PCXHR_GRANULARITY),
1013 };
1014
1015
1016 static int pcxhr_open(struct snd_pcm_substream *subs)
1017 {
1018         struct snd_pcxhr       *chip = snd_pcm_substream_chip(subs);
1019         struct pcxhr_mgr       *mgr = chip->mgr;
1020         struct snd_pcm_runtime *runtime = subs->runtime;
1021         struct pcxhr_stream    *stream;
1022         int err;
1023
1024         mutex_lock(&mgr->setup_mutex);
1025
1026         /* copy the struct snd_pcm_hardware struct */
1027         runtime->hw = pcxhr_caps;
1028
1029         if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
1030                 dev_dbg(chip->card->dev, "pcxhr_open playback chip%d subs%d\n",
1031                             chip->chip_idx, subs->number);
1032                 stream = &chip->playback_stream[subs->number];
1033         } else {
1034                 dev_dbg(chip->card->dev, "pcxhr_open capture chip%d subs%d\n",
1035                             chip->chip_idx, subs->number);
1036                 if (mgr->mono_capture)
1037                         runtime->hw.channels_max = 1;
1038                 else
1039                         runtime->hw.channels_min = 2;
1040                 stream = &chip->capture_stream[subs->number];
1041         }
1042         if (stream->status != PCXHR_STREAM_STATUS_FREE){
1043                 /* streams in use */
1044                 dev_err(chip->card->dev, "pcxhr_open chip%d subs%d in use\n",
1045                            chip->chip_idx, subs->number);
1046                 mutex_unlock(&mgr->setup_mutex);
1047                 return -EBUSY;
1048         }
1049
1050         /* float format support is in some cases buggy on stereo cards */
1051         if (mgr->is_hr_stereo)
1052                 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1053
1054         /* buffer-size should better be multiple of period-size */
1055         err = snd_pcm_hw_constraint_integer(runtime,
1056                                             SNDRV_PCM_HW_PARAM_PERIODS);
1057         if (err < 0) {
1058                 mutex_unlock(&mgr->setup_mutex);
1059                 return err;
1060         }
1061
1062         /* if a sample rate is already used or fixed by external clock,
1063          * the stream cannot change
1064          */
1065         if (mgr->sample_rate)
1066                 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1067         else {
1068                 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1069                         int external_rate;
1070                         if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1071                                                      &external_rate) ||
1072                             external_rate == 0) {
1073                                 /* cannot detect the external clock rate */
1074                                 mutex_unlock(&mgr->setup_mutex);
1075                                 return -EBUSY;
1076                         }
1077                         runtime->hw.rate_min = external_rate;
1078                         runtime->hw.rate_max = external_rate;
1079                 }
1080         }
1081
1082         stream->status      = PCXHR_STREAM_STATUS_OPEN;
1083         stream->substream   = subs;
1084         stream->channels    = 0; /* not configured yet */
1085
1086         runtime->private_data = stream;
1087
1088         /* better get a divisor of granularity values (96 or 192) */
1089         snd_pcm_hw_constraint_step(runtime, 0,
1090                                    SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1091         snd_pcm_hw_constraint_step(runtime, 0,
1092                                    SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1093         snd_pcm_set_sync(subs);
1094
1095         mgr->ref_count_rate++;
1096
1097         mutex_unlock(&mgr->setup_mutex);
1098         return 0;
1099 }
1100
1101
1102 static int pcxhr_close(struct snd_pcm_substream *subs)
1103 {
1104         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1105         struct pcxhr_mgr *mgr = chip->mgr;
1106         struct pcxhr_stream *stream = subs->runtime->private_data;
1107
1108         mutex_lock(&mgr->setup_mutex);
1109
1110         dev_dbg(chip->card->dev, "pcxhr_close chip%d subs%d\n",
1111                     chip->chip_idx, subs->number);
1112
1113         /* sample rate released */
1114         if (--mgr->ref_count_rate == 0) {
1115                 mgr->sample_rate = 0;   /* the sample rate is no more locked */
1116                 pcxhr_hardware_timer(mgr, 0);   /* stop the DSP-timer */
1117         }
1118
1119         stream->status    = PCXHR_STREAM_STATUS_FREE;
1120         stream->substream = NULL;
1121
1122         mutex_unlock(&mgr->setup_mutex);
1123
1124         return 0;
1125 }
1126
1127
1128 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1129 {
1130         u_int32_t timer_period_frag;
1131         int timer_buf_periods;
1132         struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1133         struct snd_pcm_runtime *runtime = subs->runtime;
1134         struct pcxhr_stream *stream  = runtime->private_data;
1135
1136         mutex_lock(&chip->mgr->lock);
1137
1138         /* get the period fragment and the nb of periods in the buffer */
1139         timer_period_frag = stream->timer_period_frag;
1140         timer_buf_periods = stream->timer_buf_periods;
1141
1142         mutex_unlock(&chip->mgr->lock);
1143
1144         return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1145                                    timer_period_frag);
1146 }
1147
1148
1149 static struct snd_pcm_ops pcxhr_ops = {
1150         .open      = pcxhr_open,
1151         .close     = pcxhr_close,
1152         .ioctl     = snd_pcm_lib_ioctl,
1153         .prepare   = pcxhr_prepare,
1154         .hw_params = pcxhr_hw_params,
1155         .hw_free   = pcxhr_hw_free,
1156         .trigger   = pcxhr_trigger,
1157         .pointer   = pcxhr_stream_pointer,
1158 };
1159
1160 /*
1161  */
1162 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1163 {
1164         int err;
1165         struct snd_pcm *pcm;
1166         char name[32];
1167
1168         sprintf(name, "pcxhr %d", chip->chip_idx);
1169         if ((err = snd_pcm_new(chip->card, name, 0,
1170                                chip->nb_streams_play,
1171                                chip->nb_streams_capt, &pcm)) < 0) {
1172                 dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1173                 return err;
1174         }
1175         pcm->private_data = chip;
1176
1177         if (chip->nb_streams_play)
1178                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1179         if (chip->nb_streams_capt)
1180                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1181
1182         pcm->info_flags = 0;
1183         pcm->nonatomic = true;
1184         strcpy(pcm->name, name);
1185
1186         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1187                                               snd_dma_pci_data(chip->mgr->pci),
1188                                               32*1024, 32*1024);
1189         chip->pcm = pcm;
1190         return 0;
1191 }
1192
1193 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1194 {
1195         kfree(chip);
1196         return 0;
1197 }
1198
1199 static int pcxhr_chip_dev_free(struct snd_device *device)
1200 {
1201         struct snd_pcxhr *chip = device->device_data;
1202         return pcxhr_chip_free(chip);
1203 }
1204
1205
1206 /*
1207  */
1208 static int pcxhr_create(struct pcxhr_mgr *mgr,
1209                         struct snd_card *card, int idx)
1210 {
1211         int err;
1212         struct snd_pcxhr *chip;
1213         static struct snd_device_ops ops = {
1214                 .dev_free = pcxhr_chip_dev_free,
1215         };
1216
1217         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1218         if (! chip) {
1219                 dev_err(card->dev, "cannot allocate chip\n");
1220                 return -ENOMEM;
1221         }
1222
1223         chip->card = card;
1224         chip->chip_idx = idx;
1225         chip->mgr = mgr;
1226
1227         if (idx < mgr->playback_chips)
1228                 /* stereo or mono streams */
1229                 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1230
1231         if (idx < mgr->capture_chips) {
1232                 if (mgr->mono_capture)
1233                         chip->nb_streams_capt = 2;      /* 2 mono streams */
1234                 else
1235                         chip->nb_streams_capt = 1;      /* or 1 stereo stream */
1236         }
1237
1238         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1239                 pcxhr_chip_free(chip);
1240                 return err;
1241         }
1242
1243         mgr->chip[idx] = chip;
1244
1245         return 0;
1246 }
1247
1248 /* proc interface */
1249 static void pcxhr_proc_info(struct snd_info_entry *entry,
1250                             struct snd_info_buffer *buffer)
1251 {
1252         struct snd_pcxhr *chip = entry->private_data;
1253         struct pcxhr_mgr *mgr = chip->mgr;
1254
1255         snd_iprintf(buffer, "\n%s\n", mgr->longname);
1256
1257         /* stats available when embedded DSP is running */
1258         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1259                 struct pcxhr_rmh rmh;
1260                 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1261                 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1262                 short ver_build = mgr->dsp_version & 0xff;
1263                 snd_iprintf(buffer, "module version %s\n",
1264                             PCXHR_DRIVER_VERSION_STRING);
1265                 snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1266                             ver_maj, ver_min, ver_build);
1267                 if (mgr->board_has_analog)
1268                         snd_iprintf(buffer, "analog io available\n");
1269                 else
1270                         snd_iprintf(buffer, "digital only board\n");
1271
1272                 /* calc cpu load of the dsp */
1273                 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1274                 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1275                         int cur = rmh.stat[0];
1276                         int ref = rmh.stat[1];
1277                         if (ref > 0) {
1278                                 if (mgr->sample_rate_real != 0 &&
1279                                     mgr->sample_rate_real != 48000) {
1280                                         ref = (ref * 48000) /
1281                                           mgr->sample_rate_real;
1282                                         if (mgr->sample_rate_real >=
1283                                             PCXHR_IRQ_TIMER_FREQ)
1284                                                 ref *= 2;
1285                                 }
1286                                 cur = 100 - (100 * cur) / ref;
1287                                 snd_iprintf(buffer, "cpu load    %d%%\n", cur);
1288                                 snd_iprintf(buffer, "buffer pool %d/%d\n",
1289                                             rmh.stat[2], rmh.stat[3]);
1290                         }
1291                 }
1292                 snd_iprintf(buffer, "dma granularity : %d\n",
1293                             mgr->granularity);
1294                 snd_iprintf(buffer, "dsp time errors : %d\n",
1295                             mgr->dsp_time_err);
1296                 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1297                             mgr->async_err_pipe_xrun);
1298                 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1299                             mgr->async_err_stream_xrun);
1300                 snd_iprintf(buffer, "dsp async last other error : %x\n",
1301                             mgr->async_err_other_last);
1302                 /* debug zone dsp */
1303                 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1304                 rmh.cmd_len = 1;
1305                 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1306                 rmh.dsp_stat = 0;
1307                 rmh.cmd_idx = CMD_LAST_INDEX;
1308                 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1309                         int i;
1310                         if (rmh.stat_len > 8)
1311                                 rmh.stat_len = 8;
1312                         for (i = 0; i < rmh.stat_len; i++)
1313                                 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1314                                             i,  rmh.stat[i]);
1315                 }
1316         } else
1317                 snd_iprintf(buffer, "no firmware loaded\n");
1318         snd_iprintf(buffer, "\n");
1319 }
1320 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1321                             struct snd_info_buffer *buffer)
1322 {
1323         struct snd_pcxhr *chip = entry->private_data;
1324         struct pcxhr_mgr *mgr = chip->mgr;
1325         static const char *textsHR22[3] = {
1326                 "Internal", "AES Sync", "AES 1"
1327         };
1328         static const char *textsPCXHR[7] = {
1329                 "Internal", "Word", "AES Sync",
1330                 "AES 1", "AES 2", "AES 3", "AES 4"
1331         };
1332         const char **texts;
1333         int max_clock;
1334         if (mgr->is_hr_stereo) {
1335                 texts = textsHR22;
1336                 max_clock = HR22_CLOCK_TYPE_MAX;
1337         } else {
1338                 texts = textsPCXHR;
1339                 max_clock = PCXHR_CLOCK_TYPE_MAX;
1340         }
1341
1342         snd_iprintf(buffer, "\n%s\n", mgr->longname);
1343         snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1344                     texts[mgr->cur_clock_type]);
1345         snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1346                     mgr->sample_rate_real);
1347         /* commands available when embedded DSP is running */
1348         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1349                 int i, err, sample_rate;
1350                 for (i = 1; i <= max_clock; i++) {
1351                         err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1352                         if (err)
1353                                 break;
1354                         snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1355                                     texts[i], sample_rate);
1356                 }
1357         } else
1358                 snd_iprintf(buffer, "no firmware loaded\n");
1359         snd_iprintf(buffer, "\n");
1360 }
1361
1362 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1363                                  struct snd_info_buffer *buffer)
1364 {
1365         struct snd_pcxhr *chip = entry->private_data;
1366         struct pcxhr_mgr *mgr = chip->mgr;
1367         /* commands available when embedded DSP is running */
1368         if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1369                 /* gpio ports on stereo boards only available */
1370                 int value = 0;
1371                 hr222_read_gpio(mgr, 1, &value);        /* GPI */
1372                 snd_iprintf(buffer, "GPI: 0x%x\n", value);
1373                 hr222_read_gpio(mgr, 0, &value);        /* GP0 */
1374                 snd_iprintf(buffer, "GPO: 0x%x\n", value);
1375         } else
1376                 snd_iprintf(buffer, "no firmware loaded\n");
1377         snd_iprintf(buffer, "\n");
1378 }
1379 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1380                                  struct snd_info_buffer *buffer)
1381 {
1382         struct snd_pcxhr *chip = entry->private_data;
1383         struct pcxhr_mgr *mgr = chip->mgr;
1384         char line[64];
1385         int value;
1386         /* commands available when embedded DSP is running */
1387         if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1388                 return;
1389         while (!snd_info_get_line(buffer, line, sizeof(line))) {
1390                 if (sscanf(line, "GPO: 0x%x", &value) != 1)
1391                         continue;
1392                 hr222_write_gpo(mgr, value);    /* GP0 */
1393         }
1394 }
1395
1396 /* Access to the results of the CMD_GET_TIME_CODE RMH */
1397 #define TIME_CODE_VALID_MASK    0x00800000
1398 #define TIME_CODE_NEW_MASK      0x00400000
1399 #define TIME_CODE_BACK_MASK     0x00200000
1400 #define TIME_CODE_WAIT_MASK     0x00100000
1401
1402 /* Values for the CMD_MANAGE_SIGNAL RMH */
1403 #define MANAGE_SIGNAL_TIME_CODE 0x01
1404 #define MANAGE_SIGNAL_MIDI      0x02
1405
1406 /* linear time code read proc*/
1407 static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1408                            struct snd_info_buffer *buffer)
1409 {
1410         struct snd_pcxhr *chip = entry->private_data;
1411         struct pcxhr_mgr *mgr = chip->mgr;
1412         struct pcxhr_rmh rmh;
1413         unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1414         int err;
1415         /* commands available when embedded DSP is running */
1416         if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1417                 snd_iprintf(buffer, "no firmware loaded\n");
1418                 return;
1419         }
1420         if (!mgr->capture_ltc) {
1421                 pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL);
1422                 rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1423                 err = pcxhr_send_msg(mgr, &rmh);
1424                 if (err) {
1425                         snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1426                         return;
1427                 }
1428                 if (mgr->is_hr_stereo)
1429                         hr222_manage_timecode(mgr, 1);
1430                 else
1431                         pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1432                                                     REG_CONT_VALSMPTE, NULL);
1433                 mgr->capture_ltc = 1;
1434         }
1435         pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE);
1436         err = pcxhr_send_msg(mgr, &rmh);
1437         if (err) {
1438                 snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1439                 return ;
1440         }
1441         ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1442         ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1443         ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1444         ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1445
1446         snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1447                             ltcHrs, ltcMin, ltcSec, ltcFrm);
1448         snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1449                             rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1450         /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1451                             rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1452         if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1453                 snd_iprintf(buffer, "warning: linear timecode not valid\n");
1454         }
1455 }
1456
1457 static void pcxhr_proc_init(struct snd_pcxhr *chip)
1458 {
1459         struct snd_info_entry *entry;
1460
1461         if (! snd_card_proc_new(chip->card, "info", &entry))
1462                 snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1463         if (! snd_card_proc_new(chip->card, "sync", &entry))
1464                 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1465         /* gpio available on stereo sound cards only */
1466         if (chip->mgr->is_hr_stereo &&
1467             !snd_card_proc_new(chip->card, "gpio", &entry)) {
1468                 snd_info_set_text_ops(entry, chip, pcxhr_proc_gpio_read);
1469                 entry->c.text.write = pcxhr_proc_gpo_write;
1470                 entry->mode |= S_IWUSR;
1471         }
1472         if (!snd_card_proc_new(chip->card, "ltc", &entry))
1473                 snd_info_set_text_ops(entry, chip, pcxhr_proc_ltc);
1474 }
1475 /* end of proc interface */
1476
1477 /*
1478  * release all the cards assigned to a manager instance
1479  */
1480 static int pcxhr_free(struct pcxhr_mgr *mgr)
1481 {
1482         unsigned int i;
1483
1484         for (i = 0; i < mgr->num_cards; i++) {
1485                 if (mgr->chip[i])
1486                         snd_card_free(mgr->chip[i]->card);
1487         }
1488
1489         /* reset board if some firmware was loaded */
1490         if(mgr->dsp_loaded) {
1491                 pcxhr_reset_board(mgr);
1492                 dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1493         }
1494
1495         /* release irq  */
1496         if (mgr->irq >= 0)
1497                 free_irq(mgr->irq, mgr);
1498
1499         pci_release_regions(mgr->pci);
1500
1501         /* free hostport purgebuffer */
1502         if (mgr->hostport.area) {
1503                 snd_dma_free_pages(&mgr->hostport);
1504                 mgr->hostport.area = NULL;
1505         }
1506
1507         kfree(mgr->prmh);
1508
1509         pci_disable_device(mgr->pci);
1510         kfree(mgr);
1511         return 0;
1512 }
1513
1514 /*
1515  *    probe function - creates the card manager
1516  */
1517 static int pcxhr_probe(struct pci_dev *pci,
1518                        const struct pci_device_id *pci_id)
1519 {
1520         static int dev;
1521         struct pcxhr_mgr *mgr;
1522         unsigned int i;
1523         int err;
1524         size_t size;
1525         char *card_name;
1526
1527         if (dev >= SNDRV_CARDS)
1528                 return -ENODEV;
1529         if (! enable[dev]) {
1530                 dev++;
1531                 return -ENOENT;
1532         }
1533
1534         /* enable PCI device */
1535         if ((err = pci_enable_device(pci)) < 0)
1536                 return err;
1537         pci_set_master(pci);
1538
1539         /* check if we can restrict PCI DMA transfers to 32 bits */
1540         if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) < 0) {
1541                 dev_err(&pci->dev,
1542                         "architecture does not support 32bit PCI busmaster DMA\n");
1543                 pci_disable_device(pci);
1544                 return -ENXIO;
1545         }
1546
1547         /* alloc card manager */
1548         mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1549         if (! mgr) {
1550                 pci_disable_device(pci);
1551                 return -ENOMEM;
1552         }
1553
1554         if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1555                 kfree(mgr);
1556                 pci_disable_device(pci);
1557                 return -ENODEV;
1558         }
1559         card_name =
1560                 pcxhr_board_params[pci_id->driver_data].board_name;
1561         mgr->playback_chips =
1562                 pcxhr_board_params[pci_id->driver_data].playback_chips;
1563         mgr->capture_chips  =
1564                 pcxhr_board_params[pci_id->driver_data].capture_chips;
1565         mgr->fw_file_set =
1566                 pcxhr_board_params[pci_id->driver_data].fw_file_set;
1567         mgr->firmware_num  =
1568                 pcxhr_board_params[pci_id->driver_data].firmware_num;
1569         mgr->mono_capture = mono[dev];
1570         mgr->is_hr_stereo = (mgr->playback_chips == 1);
1571         mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1572         mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1573
1574         if (mgr->is_hr_stereo)
1575                 mgr->granularity = PCXHR_GRANULARITY_HR22;
1576         else
1577                 mgr->granularity = PCXHR_GRANULARITY;
1578
1579         /* resource assignment */
1580         if ((err = pci_request_regions(pci, card_name)) < 0) {
1581                 kfree(mgr);
1582                 pci_disable_device(pci);
1583                 return err;
1584         }
1585         for (i = 0; i < 3; i++)
1586                 mgr->port[i] = pci_resource_start(pci, i);
1587
1588         mgr->pci = pci;
1589         mgr->irq = -1;
1590
1591         if (request_threaded_irq(pci->irq, pcxhr_interrupt,
1592                                  pcxhr_threaded_irq, IRQF_SHARED,
1593                                  KBUILD_MODNAME, mgr)) {
1594                 dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1595                 pcxhr_free(mgr);
1596                 return -EBUSY;
1597         }
1598         mgr->irq = pci->irq;
1599
1600         sprintf(mgr->shortname, "Digigram %s", card_name);
1601         sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i",
1602                 mgr->shortname,
1603                 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1604
1605         /* ISR lock  */
1606         mutex_init(&mgr->lock);
1607         mutex_init(&mgr->msg_lock);
1608
1609         /* init setup mutex*/
1610         mutex_init(&mgr->setup_mutex);
1611
1612         mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1613                             sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1614                                            PCXHR_SIZE_MAX_STATUS),
1615                             GFP_KERNEL);
1616         if (! mgr->prmh) {
1617                 pcxhr_free(mgr);
1618                 return -ENOMEM;
1619         }
1620
1621         for (i=0; i < PCXHR_MAX_CARDS; i++) {
1622                 struct snd_card *card;
1623                 char tmpid[16];
1624                 int idx;
1625
1626                 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1627                         break;
1628                 mgr->num_cards++;
1629
1630                 if (index[dev] < 0)
1631                         idx = index[dev];
1632                 else
1633                         idx = index[dev] + i;
1634
1635                 snprintf(tmpid, sizeof(tmpid), "%s-%d",
1636                          id[dev] ? id[dev] : card_name, i);
1637                 err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE,
1638                                    0, &card);
1639
1640                 if (err < 0) {
1641                         dev_err(&pci->dev, "cannot allocate the card %d\n", i);
1642                         pcxhr_free(mgr);
1643                         return err;
1644                 }
1645
1646                 strcpy(card->driver, DRIVER_NAME);
1647                 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1648                 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1649
1650                 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1651                         snd_card_free(card);
1652                         pcxhr_free(mgr);
1653                         return err;
1654                 }
1655
1656                 if (i == 0)
1657                         /* init proc interface only for chip0 */
1658                         pcxhr_proc_init(mgr->chip[i]);
1659
1660                 if ((err = snd_card_register(card)) < 0) {
1661                         pcxhr_free(mgr);
1662                         return err;
1663                 }
1664         }
1665
1666         /* create hostport purgebuffer */
1667         size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1668         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1669                                 size, &mgr->hostport) < 0) {
1670                 pcxhr_free(mgr);
1671                 return -ENOMEM;
1672         }
1673         /* init purgebuffer */
1674         memset(mgr->hostport.area, 0, size);
1675
1676         /* create a DSP loader */
1677         err = pcxhr_setup_firmware(mgr);
1678         if (err < 0) {
1679                 pcxhr_free(mgr);
1680                 return err;
1681         }
1682
1683         pci_set_drvdata(pci, mgr);
1684         dev++;
1685         return 0;
1686 }
1687
1688 static void pcxhr_remove(struct pci_dev *pci)
1689 {
1690         pcxhr_free(pci_get_drvdata(pci));
1691 }
1692
1693 static struct pci_driver pcxhr_driver = {
1694         .name = KBUILD_MODNAME,
1695         .id_table = pcxhr_ids,
1696         .probe = pcxhr_probe,
1697         .remove = pcxhr_remove,
1698 };
1699
1700 module_pci_driver(pcxhr_driver);