kernel/sound/pci/oxygen/oxygen_lib.c

   1 /*
   2  * C-Media CMI8788 driver - main driver module
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  *  This driver is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License, version 2.
   9  *
  10  *  This driver is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this driver; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mutex.h>
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <sound/ac97_codec.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/core.h>
  29 #include <sound/info.h>
  30 #include <sound/mpu401.h>
  31 #include <sound/pcm.h>
  32 #include "oxygen.h"
  33 #include "cm9780.h"
  34
  35 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  36 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  37 MODULE_LICENSE("GPL v2");
  38
  39 #define DRIVER "oxygen"
  40
  41 static inline int oxygen_uart_input_ready(struct oxygen *chip)
  42 {
  43         return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
  44 }
  45
  46 static void oxygen_read_uart(struct oxygen *chip)
  47 {
  48         if (unlikely(!oxygen_uart_input_ready(chip))) {
  49                 /* no data, but read it anyway to clear the interrupt */
  50                 oxygen_read8(chip, OXYGEN_MPU401);
  51                 return;
  52         }
  53         do {
  54                 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
  55                 if (data == MPU401_ACK)
  56                         continue;
  57                 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
  58                         chip->uart_input_count = 0;
  59                 chip->uart_input[chip->uart_input_count++] = data;
  60         } while (oxygen_uart_input_ready(chip));
  61         if (chip->model.uart_input)
  62                 chip->model.uart_input(chip);
  63 }
  64
  65 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  66 {
  67         struct oxygen *chip = dev_id;
  68         unsigned int status, clear, elapsed_streams, i;
  69
  70         status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  71         if (!status)
  72                 return IRQ_NONE;
  73
  74         spin_lock(&chip->reg_lock);
  75
  76         clear = status & (OXYGEN_CHANNEL_A |
  77                           OXYGEN_CHANNEL_B |
  78                           OXYGEN_CHANNEL_C |
  79                           OXYGEN_CHANNEL_SPDIF |
  80                           OXYGEN_CHANNEL_MULTICH |
  81                           OXYGEN_CHANNEL_AC97 |
  82                           OXYGEN_INT_SPDIF_IN_DETECT |
  83                           OXYGEN_INT_GPIO |
  84                           OXYGEN_INT_AC97);
  85         if (clear) {
  86                 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  87                         chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  88                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  89                                chip->interrupt_mask & ~clear);
  90                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  91                                chip->interrupt_mask);
  92         }
  93
  94         elapsed_streams = status & chip->pcm_running;
  95
  96         spin_unlock(&chip->reg_lock);
  97
  98         for (i = 0; i < PCM_COUNT; ++i)
  99                 if ((elapsed_streams & (1 << i)) && chip->streams[i])
 100                         snd_pcm_period_elapsed(chip->streams[i]);
 101
 102         if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
 103                 spin_lock(&chip->reg_lock);
 104                 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 105                 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
 106                          OXYGEN_SPDIF_RATE_INT)) {
 107                         /* write the interrupt bit(s) to clear */
 108                         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
 109                         schedule_work(&chip->spdif_input_bits_work);
 110                 }
 111                 spin_unlock(&chip->reg_lock);
 112         }
 113
 114         if (status & OXYGEN_INT_GPIO)
 115                 schedule_work(&chip->gpio_work);
 116
 117         if (status & OXYGEN_INT_MIDI) {
 118                 if (chip->midi)
 119                         snd_mpu401_uart_interrupt(0, chip->midi->private_data);
 120                 else
 121                         oxygen_read_uart(chip);
 122         }
 123
 124         if (status & OXYGEN_INT_AC97)
 125                 wake_up(&chip->ac97_waitqueue);
 126
 127         return IRQ_HANDLED;
 128 }
 129
 130 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
 131 {
 132         struct oxygen *chip = container_of(work, struct oxygen,
 133                                            spdif_input_bits_work);
 134         u32 reg;
 135
 136         /*
 137          * This function gets called when there is new activity on the SPDIF
 138          * input, or when we lose lock on the input signal, or when the rate
 139          * changes.
 140          */
 141         msleep(1);
 142         spin_lock_irq(&chip->reg_lock);
 143         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 144         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 145                     OXYGEN_SPDIF_LOCK_STATUS))
 146             == OXYGEN_SPDIF_SENSE_STATUS) {
 147                 /*
 148                  * If we detect activity on the SPDIF input but cannot lock to
 149                  * a signal, the clock bit is likely to be wrong.
 150                  */
 151                 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
 152                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 153                 spin_unlock_irq(&chip->reg_lock);
 154                 msleep(1);
 155                 spin_lock_irq(&chip->reg_lock);
 156                 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 157                 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 158                             OXYGEN_SPDIF_LOCK_STATUS))
 159                     == OXYGEN_SPDIF_SENSE_STATUS) {
 160                         /* nothing detected with either clock; give up */
 161                         if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
 162                             == OXYGEN_SPDIF_IN_CLOCK_192) {
 163                                 /*
 164                                  * Reset clock to <= 96 kHz because this is
 165                                  * more likely to be received next time.
 166                                  */
 167                                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
 168                                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
 169                                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 170                         }
 171                 }
 172         }
 173         spin_unlock_irq(&chip->reg_lock);
 174
 175         if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
 176                 spin_lock_irq(&chip->reg_lock);
 177                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 178                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
 179                                chip->interrupt_mask);
 180                 spin_unlock_irq(&chip->reg_lock);
 181
 182                 /*
 183                  * We don't actually know that any channel status bits have
 184                  * changed, but let's send a notification just to be sure.
 185                  */
 186                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
 187                                &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
 188         }
 189 }
 190
 191 static void oxygen_gpio_changed(struct work_struct *work)
 192 {
 193         struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
 194
 195         if (chip->model.gpio_changed)
 196                 chip->model.gpio_changed(chip);
 197 }
 198
 199 #ifdef CONFIG_PROC_FS
 200 static void oxygen_proc_read(struct snd_info_entry *entry,
 201                              struct snd_info_buffer *buffer)
 202 {
 203         struct oxygen *chip = entry->private_data;
 204         int i, j;
 205
 206         switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
 207         case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
 208         case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
 209         case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
 210         default:                     i = '?'; break;
 211         }
 212         snd_iprintf(buffer, "CMI878%c:\n", i);
 213         for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
 214                 snd_iprintf(buffer, "%02x:", i);
 215                 for (j = 0; j < 0x10; ++j)
 216                         snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
 217                 snd_iprintf(buffer, "\n");
 218         }
 219         if (mutex_lock_interruptible(&chip->mutex) < 0)
 220                 return;
 221         if (chip->has_ac97_0) {
 222                 snd_iprintf(buffer, "\nAC97:\n");
 223                 for (i = 0; i < 0x80; i += 0x10) {
 224                         snd_iprintf(buffer, "%02x:", i);
 225                         for (j = 0; j < 0x10; j += 2)
 226                                 snd_iprintf(buffer, " %04x",
 227                                             oxygen_read_ac97(chip, 0, i + j));
 228                         snd_iprintf(buffer, "\n");
 229                 }
 230         }
 231         if (chip->has_ac97_1) {
 232                 snd_iprintf(buffer, "\nAC97 2:\n");
 233                 for (i = 0; i < 0x80; i += 0x10) {
 234                         snd_iprintf(buffer, "%02x:", i);
 235                         for (j = 0; j < 0x10; j += 2)
 236                                 snd_iprintf(buffer, " %04x",
 237                                             oxygen_read_ac97(chip, 1, i + j));
 238                         snd_iprintf(buffer, "\n");
 239                 }
 240         }
 241         mutex_unlock(&chip->mutex);
 242         if (chip->model.dump_registers)
 243                 chip->model.dump_registers(chip, buffer);
 244 }
 245
 246 static void oxygen_proc_init(struct oxygen *chip)
 247 {
 248         struct snd_info_entry *entry;
 249
 250         if (!snd_card_proc_new(chip->card, "oxygen", &entry))
 251                 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
 252 }
 253 #else
 254 #define oxygen_proc_init(chip)
 255 #endif
 256
 257 static const struct pci_device_id *
 258 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
 259 {
 260         u16 subdevice;
 261
 262         /*
 263          * Make sure the EEPROM pins are available, i.e., not used for SPI.
 264          * (This function is called before we initialize or use SPI.)
 265          */
 266         oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
 267                            OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 268         /*
 269          * Read the subsystem device ID directly from the EEPROM, because the
 270          * chip didn't if the first EEPROM word was overwritten.
 271          */
 272         subdevice = oxygen_read_eeprom(chip, 2);
 273         /* use default ID if EEPROM is missing */
 274         if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
 275                 subdevice = 0x8788;
 276         /*
 277          * We use only the subsystem device ID for searching because it is
 278          * unique even without the subsystem vendor ID, which may have been
 279          * overwritten in the EEPROM.
 280          */
 281         for (; ids->vendor; ++ids)
 282                 if (ids->subdevice == subdevice &&
 283                     ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
 284                         return ids;
 285         return NULL;
 286 }
 287
 288 static void oxygen_restore_eeprom(struct oxygen *chip,
 289                                   const struct pci_device_id *id)
 290 {
 291         u16 eeprom_id;
 292
 293         eeprom_id = oxygen_read_eeprom(chip, 0);
 294         if (eeprom_id != OXYGEN_EEPROM_ID &&
 295             (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
 296                 /*
 297                  * This function gets called only when a known card model has
 298                  * been detected, i.e., we know there is a valid subsystem
 299                  * product ID at index 2 in the EEPROM.  Therefore, we have
 300                  * been able to deduce the correct subsystem vendor ID, and
 301                  * this is enough information to restore the original EEPROM
 302                  * contents.
 303                  */
 304                 oxygen_write_eeprom(chip, 1, id->subvendor);
 305                 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
 306
 307                 oxygen_set_bits8(chip, OXYGEN_MISC,
 308                                  OXYGEN_MISC_WRITE_PCI_SUBID);
 309                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
 310                                       id->subvendor);
 311                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
 312                                       id->subdevice);
 313                 oxygen_clear_bits8(chip, OXYGEN_MISC,
 314                                    OXYGEN_MISC_WRITE_PCI_SUBID);
 315
 316                 dev_info(chip->card->dev, "EEPROM ID restored\n");
 317         }
 318 }
 319
 320 static void configure_pcie_bridge(struct pci_dev *pci)
 321 {
 322         enum { PEX811X, PI7C9X110, XIO2001 };
 323         static const struct pci_device_id bridge_ids[] = {
 324                 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
 325                 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
 326                 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
 327                 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
 328                 { }
 329         };
 330         struct pci_dev *bridge;
 331         const struct pci_device_id *id;
 332         u32 tmp;
 333
 334         if (!pci->bus || !pci->bus->self)
 335                 return;
 336         bridge = pci->bus->self;
 337
 338         id = pci_match_id(bridge_ids, bridge);
 339         if (!id)
 340                 return;
 341
 342         switch (id->driver_data) {
 343         case PEX811X:   /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
 344                 pci_read_config_dword(bridge, 0x48, &tmp);
 345                 tmp |= 1;       /* enable blind prefetching */
 346                 tmp |= 1 << 11; /* enable beacon generation */
 347                 pci_write_config_dword(bridge, 0x48, tmp);
 348
 349                 pci_write_config_dword(bridge, 0x84, 0x0c);
 350                 pci_read_config_dword(bridge, 0x88, &tmp);
 351                 tmp &= ~(7 << 27);
 352                 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
 353                 pci_write_config_dword(bridge, 0x88, tmp);
 354                 break;
 355
 356         case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
 357                 pci_read_config_dword(bridge, 0x40, &tmp);
 358                 tmp |= 1;       /* park the PCI arbiter to the sound chip */
 359                 pci_write_config_dword(bridge, 0x40, tmp);
 360                 break;
 361
 362         case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
 363                 pci_read_config_dword(bridge, 0xe8, &tmp);
 364                 tmp &= ~0xf;    /* request length limit: 64 bytes */
 365                 tmp &= ~(0xf << 8);
 366                 tmp |= 1 << 8;  /* request count limit: one buffer */
 367                 pci_write_config_dword(bridge, 0xe8, tmp);
 368                 break;
 369         }
 370 }
 371
 372 static void oxygen_init(struct oxygen *chip)
 373 {
 374         unsigned int i;
 375
 376         chip->dac_routing = 1;
 377         for (i = 0; i < 8; ++i)
 378                 chip->dac_volume[i] = chip->model.dac_volume_min;
 379         chip->dac_mute = 1;
 380         chip->spdif_playback_enable = 1;
 381         chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
 382                 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
 383         chip->spdif_pcm_bits = chip->spdif_bits;
 384
 385         if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
 386                 oxygen_set_bits8(chip, OXYGEN_MISC,
 387                                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
 388
 389         i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
 390         chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
 391         chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
 392
 393         oxygen_write8_masked(chip, OXYGEN_FUNCTION,
 394                              OXYGEN_FUNCTION_RESET_CODEC |
 395                              chip->model.function_flags,
 396                              OXYGEN_FUNCTION_RESET_CODEC |
 397                              OXYGEN_FUNCTION_2WIRE_SPI_MASK |
 398                              OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 399         oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
 400         oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
 401         oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
 402                       OXYGEN_PLAY_CHANNELS_2 |
 403                       OXYGEN_DMA_A_BURST_8 |
 404                       OXYGEN_DMA_MULTICH_BURST_8);
 405         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 406         oxygen_write8_masked(chip, OXYGEN_MISC,
 407                              chip->model.misc_flags,
 408                              OXYGEN_MISC_WRITE_PCI_SUBID |
 409                              OXYGEN_MISC_REC_C_FROM_SPDIF |
 410                              OXYGEN_MISC_REC_B_FROM_AC97 |
 411                              OXYGEN_MISC_REC_A_FROM_MULTICH |
 412                              OXYGEN_MISC_MIDI);
 413         oxygen_write8(chip, OXYGEN_REC_FORMAT,
 414                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
 415                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
 416                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
 417         oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
 418                       (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
 419                       (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
 420         oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
 421         oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
 422                        OXYGEN_RATE_48000 |
 423                        chip->model.dac_i2s_format |
 424                        OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
 425                        OXYGEN_I2S_BITS_16 |
 426                        OXYGEN_I2S_MASTER |
 427                        OXYGEN_I2S_BCLK_64);
 428         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
 429                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 430                                OXYGEN_RATE_48000 |
 431                                chip->model.adc_i2s_format |
 432                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 433                                OXYGEN_I2S_BITS_16 |
 434                                OXYGEN_I2S_MASTER |
 435                                OXYGEN_I2S_BCLK_64);
 436         else
 437                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 438                                OXYGEN_I2S_MASTER |
 439                                OXYGEN_I2S_MUTE_MCLK);
 440         if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
 441                                          CAPTURE_2_FROM_I2S_2))
 442                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 443                                OXYGEN_RATE_48000 |
 444                                chip->model.adc_i2s_format |
 445                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 446                                OXYGEN_I2S_BITS_16 |
 447                                OXYGEN_I2S_MASTER |
 448                                OXYGEN_I2S_BCLK_64);
 449         else
 450                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 451                                OXYGEN_I2S_MASTER |
 452                                OXYGEN_I2S_MUTE_MCLK);
 453         if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
 454                 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 455                                OXYGEN_RATE_48000 |
 456                                chip->model.adc_i2s_format |
 457                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 458                                OXYGEN_I2S_BITS_16 |
 459                                OXYGEN_I2S_MASTER |
 460                                OXYGEN_I2S_BCLK_64);
 461         else
 462                 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 463                                OXYGEN_I2S_MASTER |
 464                                OXYGEN_I2S_MUTE_MCLK);
 465         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 466                             OXYGEN_SPDIF_OUT_ENABLE |
 467                             OXYGEN_SPDIF_LOOPBACK);
 468         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 469                 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
 470                                       OXYGEN_SPDIF_SENSE_MASK |
 471                                       OXYGEN_SPDIF_LOCK_MASK |
 472                                       OXYGEN_SPDIF_RATE_MASK |
 473                                       OXYGEN_SPDIF_LOCK_PAR |
 474                                       OXYGEN_SPDIF_IN_CLOCK_96,
 475                                       OXYGEN_SPDIF_SENSE_MASK |
 476                                       OXYGEN_SPDIF_LOCK_MASK |
 477                                       OXYGEN_SPDIF_RATE_MASK |
 478                                       OXYGEN_SPDIF_SENSE_PAR |
 479                                       OXYGEN_SPDIF_LOCK_PAR |
 480                                       OXYGEN_SPDIF_IN_CLOCK_MASK);
 481         else
 482                 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 483                                     OXYGEN_SPDIF_SENSE_MASK |
 484                                     OXYGEN_SPDIF_LOCK_MASK |
 485                                     OXYGEN_SPDIF_RATE_MASK);
 486         oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
 487         oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
 488                        OXYGEN_2WIRE_LENGTH_8 |
 489                        OXYGEN_2WIRE_INTERRUPT_MASK |
 490                        OXYGEN_2WIRE_SPEED_STANDARD);
 491         oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
 492         oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
 493         oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
 494         oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
 495                        OXYGEN_PLAY_MULTICH_I2S_DAC |
 496                        OXYGEN_PLAY_SPDIF_SPDIF |
 497                        (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
 498                        (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
 499                        (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
 500                        (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
 501         oxygen_write8(chip, OXYGEN_REC_ROUTING,
 502                       OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
 503                       OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
 504                       OXYGEN_REC_C_ROUTE_SPDIF);
 505         oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
 506         oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
 507                       (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
 508                       (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
 509                       (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
 510                       (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
 511
 512         if (chip->has_ac97_0 | chip->has_ac97_1)
 513                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
 514                               OXYGEN_AC97_INT_READ_DONE |
 515                               OXYGEN_AC97_INT_WRITE_DONE);
 516         else
 517                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
 518         oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
 519         oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
 520         if (!(chip->has_ac97_0 | chip->has_ac97_1))
 521                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 522                                   OXYGEN_AC97_CLOCK_DISABLE);
 523         if (!chip->has_ac97_0) {
 524                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 525                                   OXYGEN_AC97_NO_CODEC_0);
 526         } else {
 527                 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
 528                 msleep(1);
 529                 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
 530                                      CM9780_GPIO0IO | CM9780_GPIO1IO);
 531                 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
 532                                      CM9780_BSTSEL | CM9780_STRO_MIC |
 533                                      CM9780_MIX2FR | CM9780_PCBSW);
 534                 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
 535                                      CM9780_RSOE | CM9780_CBOE |
 536                                      CM9780_SSOE | CM9780_FROE |
 537                                      CM9780_MIC2MIC | CM9780_LI2LI);
 538                 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
 539                 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
 540                 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
 541                 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
 542                 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
 543                 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
 544                 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
 545                 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
 546                 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
 547                 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
 548                 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
 549                                        CM9780_GPO0);
 550                 /* power down unused ADCs and DACs */
 551                 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
 552                                      AC97_PD_PR0 | AC97_PD_PR1);
 553                 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
 554                                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
 555         }
 556         if (chip->has_ac97_1) {
 557                 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
 558                                   OXYGEN_AC97_CODEC1_SLOT3 |
 559                                   OXYGEN_AC97_CODEC1_SLOT4);
 560                 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
 561                 msleep(1);
 562                 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
 563                 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
 564                 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
 565                 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
 566                 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
 567                 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
 568                 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
 569                 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
 570                 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
 571                 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
 572                 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
 573                 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
 574         }
 575 }
 576
 577 static void oxygen_shutdown(struct oxygen *chip)
 578 {
 579         spin_lock_irq(&chip->reg_lock);
 580         chip->interrupt_mask = 0;
 581         chip->pcm_running = 0;
 582         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 583         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 584         spin_unlock_irq(&chip->reg_lock);
 585 }
 586
 587 static void oxygen_card_free(struct snd_card *card)
 588 {
 589         struct oxygen *chip = card->private_data;
 590
 591         oxygen_shutdown(chip);
 592         if (chip->irq >= 0)
 593                 free_irq(chip->irq, chip);
 594         flush_work(&chip->spdif_input_bits_work);
 595         flush_work(&chip->gpio_work);
 596         chip->model.cleanup(chip);
 597         kfree(chip->model_data);
 598         mutex_destroy(&chip->mutex);
 599         pci_release_regions(chip->pci);
 600         pci_disable_device(chip->pci);
 601 }
 602
 603 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
 604                      struct module *owner,
 605                      const struct pci_device_id *ids,
 606                      int (*get_model)(struct oxygen *chip,
 607                                       const struct pci_device_id *id
 608                                      )
 609                     )
 610 {
 611         struct snd_card *card;
 612         struct oxygen *chip;
 613         const struct pci_device_id *pci_id;
 614         int err;
 615
 616         err = snd_card_new(&pci->dev, index, id, owner,
 617                            sizeof(*chip), &card);
 618         if (err < 0)
 619                 return err;
 620
 621         chip = card->private_data;
 622         chip->card = card;
 623         chip->pci = pci;
 624         chip->irq = -1;
 625         spin_lock_init(&chip->reg_lock);
 626         mutex_init(&chip->mutex);
 627         INIT_WORK(&chip->spdif_input_bits_work,
 628                   oxygen_spdif_input_bits_changed);
 629         INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
 630         init_waitqueue_head(&chip->ac97_waitqueue);
 631
 632         err = pci_enable_device(pci);
 633         if (err < 0)
 634                 goto err_card;
 635
 636         err = pci_request_regions(pci, DRIVER);
 637         if (err < 0) {
 638                 dev_err(card->dev, "cannot reserve PCI resources\n");
 639                 goto err_pci_enable;
 640         }
 641
 642         if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
 643             pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
 644                 dev_err(card->dev, "invalid PCI I/O range\n");
 645                 err = -ENXIO;
 646                 goto err_pci_regions;
 647         }
 648         chip->addr = pci_resource_start(pci, 0);
 649
 650         pci_id = oxygen_search_pci_id(chip, ids);
 651         if (!pci_id) {
 652                 err = -ENODEV;
 653                 goto err_pci_regions;
 654         }
 655         oxygen_restore_eeprom(chip, pci_id);
 656         err = get_model(chip, pci_id);
 657         if (err < 0)
 658                 goto err_pci_regions;
 659
 660         if (chip->model.model_data_size) {
 661                 chip->model_data = kzalloc(chip->model.model_data_size,
 662                                            GFP_KERNEL);
 663                 if (!chip->model_data) {
 664                         err = -ENOMEM;
 665                         goto err_pci_regions;
 666                 }
 667         }
 668
 669         pci_set_master(pci);
 670         card->private_free = oxygen_card_free;
 671
 672         configure_pcie_bridge(pci);
 673         oxygen_init(chip);
 674         chip->model.init(chip);
 675
 676         err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
 677                           KBUILD_MODNAME, chip);
 678         if (err < 0) {
 679                 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
 680                 goto err_card;
 681         }
 682         chip->irq = pci->irq;
 683
 684         strcpy(card->driver, chip->model.chip);
 685         strcpy(card->shortname, chip->model.shortname);
 686         sprintf(card->longname, "%s at %#lx, irq %i",
 687                 chip->model.longname, chip->addr, chip->irq);
 688         strcpy(card->mixername, chip->model.chip);
 689         snd_component_add(card, chip->model.chip);
 690
 691         err = oxygen_pcm_init(chip);
 692         if (err < 0)
 693                 goto err_card;
 694
 695         err = oxygen_mixer_init(chip);
 696         if (err < 0)
 697                 goto err_card;
 698
 699         if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
 700                 unsigned int info_flags =
 701                                 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
 702                 if (chip->model.device_config & MIDI_OUTPUT)
 703                         info_flags |= MPU401_INFO_OUTPUT;
 704                 if (chip->model.device_config & MIDI_INPUT)
 705                         info_flags |= MPU401_INFO_INPUT;
 706                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
 707                                           chip->addr + OXYGEN_MPU401,
 708                                           info_flags, -1, &chip->midi);
 709                 if (err < 0)
 710                         goto err_card;
 711         }
 712
 713         oxygen_proc_init(chip);
 714
 715         spin_lock_irq(&chip->reg_lock);
 716         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 717                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 718         if (chip->has_ac97_0 | chip->has_ac97_1)
 719                 chip->interrupt_mask |= OXYGEN_INT_AC97;
 720         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 721         spin_unlock_irq(&chip->reg_lock);
 722
 723         err = snd_card_register(card);
 724         if (err < 0)
 725                 goto err_card;
 726
 727         pci_set_drvdata(pci, card);
 728         return 0;
 729
 730 err_pci_regions:
 731         pci_release_regions(pci);
 732 err_pci_enable:
 733         pci_disable_device(pci);
 734 err_card:
 735         snd_card_free(card);
 736         return err;
 737 }
 738 EXPORT_SYMBOL(oxygen_pci_probe);
 739
 740 void oxygen_pci_remove(struct pci_dev *pci)
 741 {
 742         snd_card_free(pci_get_drvdata(pci));
 743 }
 744 EXPORT_SYMBOL(oxygen_pci_remove);
 745
 746 #ifdef CONFIG_PM_SLEEP
 747 static int oxygen_pci_suspend(struct device *dev)
 748 {
 749         struct snd_card *card = dev_get_drvdata(dev);
 750         struct oxygen *chip = card->private_data;
 751         unsigned int i, saved_interrupt_mask;
 752
 753         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 754
 755         for (i = 0; i < PCM_COUNT; ++i)
 756                 snd_pcm_suspend(chip->streams[i]);
 757
 758         if (chip->model.suspend)
 759                 chip->model.suspend(chip);
 760
 761         spin_lock_irq(&chip->reg_lock);
 762         saved_interrupt_mask = chip->interrupt_mask;
 763         chip->interrupt_mask = 0;
 764         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 765         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 766         spin_unlock_irq(&chip->reg_lock);
 767
 768         synchronize_irq(chip->irq);
 769         flush_work(&chip->spdif_input_bits_work);
 770         flush_work(&chip->gpio_work);
 771         chip->interrupt_mask = saved_interrupt_mask;
 772         return 0;
 773 }
 774
 775 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
 776         0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
 777         0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
 778 };
 779 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
 780         { 0x18284fa2, 0x03060000 },
 781         { 0x00007fa6, 0x00200000 }
 782 };
 783
 784 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
 785 {
 786         return bitmap[bit / 32] & (1 << (bit & 31));
 787 }
 788
 789 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
 790 {
 791         unsigned int i;
 792
 793         oxygen_write_ac97(chip, codec, AC97_RESET, 0);
 794         msleep(1);
 795         for (i = 1; i < 0x40; ++i)
 796                 if (is_bit_set(ac97_registers_to_restore[codec], i))
 797                         oxygen_write_ac97(chip, codec, i * 2,
 798                                           chip->saved_ac97_registers[codec][i]);
 799 }
 800
 801 static int oxygen_pci_resume(struct device *dev)
 802 {
 803         struct snd_card *card = dev_get_drvdata(dev);
 804         struct oxygen *chip = card->private_data;
 805         unsigned int i;
 806
 807         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 808         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 809         for (i = 0; i < OXYGEN_IO_SIZE; ++i)
 810                 if (is_bit_set(registers_to_restore, i))
 811                         oxygen_write8(chip, i, chip->saved_registers._8[i]);
 812         if (chip->has_ac97_0)
 813                 oxygen_restore_ac97(chip, 0);
 814         if (chip->has_ac97_1)
 815                 oxygen_restore_ac97(chip, 1);
 816
 817         if (chip->model.resume)
 818                 chip->model.resume(chip);
 819
 820         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 821
 822         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 823         return 0;
 824 }
 825
 826 SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
 827 EXPORT_SYMBOL(oxygen_pci_pm);
 828 #endif /* CONFIG_PM_SLEEP */
 829
 830 void oxygen_pci_shutdown(struct pci_dev *pci)
 831 {
 832         struct snd_card *card = pci_get_drvdata(pci);
 833         struct oxygen *chip = card->private_data;
 834
 835         oxygen_shutdown(chip);
 836         chip->model.cleanup(chip);
 837 }
 838 EXPORT_SYMBOL(oxygen_pci_shutdown);