kernel/sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/jack.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/tlv.h>
  40 #include <sound/hdaudio.h>
  41 #include <sound/hda_i915.h>
  42 #include "hda_codec.h"
  43 #include "hda_local.h"
  44 #include "hda_jack.h"
  45
  46 static bool static_hdmi_pcm;
  47 module_param(static_hdmi_pcm, bool, 0644);
  48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  49
  50 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  51 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  53 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  54 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  55 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  56                                 || is_skylake(codec) || is_broxton(codec) \
  57                                 || is_kabylake(codec))
  58
  59 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  60 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  61 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  62
  63 struct hdmi_spec_per_cvt {
  64         hda_nid_t cvt_nid;
  65         int assigned;
  66         unsigned int channels_min;
  67         unsigned int channels_max;
  68         u32 rates;
  69         u64 formats;
  70         unsigned int maxbps;
  71 };
  72
  73 /* max. connections to a widget */
  74 #define HDA_MAX_CONNECTIONS     32
  75
  76 struct hdmi_spec_per_pin {
  77         hda_nid_t pin_nid;
  78         int num_mux_nids;
  79         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  80         int mux_idx;
  81         hda_nid_t cvt_nid;
  82
  83         struct hda_codec *codec;
  84         struct hdmi_eld sink_eld;
  85         struct mutex lock;
  86         struct delayed_work work;
  87         struct snd_kcontrol *eld_ctl;
  88         int repoll_count;
  89         bool setup; /* the stream has been set up by prepare callback */
  90         int channels; /* current number of channels */
  91         bool non_pcm;
  92         bool chmap_set;         /* channel-map override by ALSA API? */
  93         unsigned char chmap[8]; /* ALSA API channel-map */
  94 #ifdef CONFIG_SND_PROC_FS
  95         struct snd_info_entry *proc_entry;
  96 #endif
  97 };
  98
  99 struct cea_channel_speaker_allocation;
 100
 101 /* operations used by generic code that can be overridden by patches */
 102 struct hdmi_ops {
 103         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 104                            unsigned char *buf, int *eld_size);
 105
 106         /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
 107         int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 108                                     int asp_slot);
 109         int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                                     int asp_slot, int channel);
 111
 112         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 113                                     int ca, int active_channels, int conn_type);
 114
 115         /* enable/disable HBR (HD passthrough) */
 116         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 117
 118         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 119                             hda_nid_t pin_nid, u32 stream_tag, int format);
 120
 121         /* Helpers for producing the channel map TLVs. These can be overridden
 122          * for devices that have non-standard mapping requirements. */
 123         int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
 124                                                  int channels);
 125         void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
 126                                        unsigned int *chmap, int channels);
 127
 128         /* check that the user-given chmap is supported */
 129         int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
 130 };
 131
 132 struct hdmi_spec {
 133         int num_cvts;
 134         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 135         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 136
 137         int num_pins;
 138         struct snd_array pins; /* struct hdmi_spec_per_pin */
 139         struct hda_pcm *pcm_rec[16];
 140         unsigned int channels_max; /* max over all cvts */
 141
 142         struct hdmi_eld temp_eld;
 143         struct hdmi_ops ops;
 144
 145         bool dyn_pin_out;
 146
 147         /*
 148          * Non-generic VIA/NVIDIA specific
 149          */
 150         struct hda_multi_out multiout;
 151         struct hda_pcm_stream pcm_playback;
 152
 153         /* i915/powerwell (Haswell+/Valleyview+) specific */
 154         struct i915_audio_component_audio_ops i915_audio_ops;
 155 };
 156
 157
 158 struct hdmi_audio_infoframe {
 159         u8 type; /* 0x84 */
 160         u8 ver;  /* 0x01 */
 161         u8 len;  /* 0x0a */
 162
 163         u8 checksum;
 164
 165         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 166         u8 SS01_SF24;
 167         u8 CXT04;
 168         u8 CA;
 169         u8 LFEPBL01_LSV36_DM_INH7;
 170 };
 171
 172 struct dp_audio_infoframe {
 173         u8 type; /* 0x84 */
 174         u8 len;  /* 0x1b */
 175         u8 ver;  /* 0x11 << 2 */
 176
 177         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 178         u8 SS01_SF24;
 179         u8 CXT04;
 180         u8 CA;
 181         u8 LFEPBL01_LSV36_DM_INH7;
 182 };
 183
 184 union audio_infoframe {
 185         struct hdmi_audio_infoframe hdmi;
 186         struct dp_audio_infoframe dp;
 187         u8 bytes[0];
 188 };
 189
 190 /*
 191  * CEA speaker placement:
 192  *
 193  *        FLH       FCH        FRH
 194  *  FLW    FL  FLC   FC   FRC   FR   FRW
 195  *
 196  *                                  LFE
 197  *                     TC
 198  *
 199  *          RL  RLC   RC   RRC   RR
 200  *
 201  * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
 202  * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
 203  */
 204 enum cea_speaker_placement {
 205         FL  = (1 <<  0),        /* Front Left           */
 206         FC  = (1 <<  1),        /* Front Center         */
 207         FR  = (1 <<  2),        /* Front Right          */
 208         FLC = (1 <<  3),        /* Front Left Center    */
 209         FRC = (1 <<  4),        /* Front Right Center   */
 210         RL  = (1 <<  5),        /* Rear Left            */
 211         RC  = (1 <<  6),        /* Rear Center          */
 212         RR  = (1 <<  7),        /* Rear Right           */
 213         RLC = (1 <<  8),        /* Rear Left Center     */
 214         RRC = (1 <<  9),        /* Rear Right Center    */
 215         LFE = (1 << 10),        /* Low Frequency Effect */
 216         FLW = (1 << 11),        /* Front Left Wide      */
 217         FRW = (1 << 12),        /* Front Right Wide     */
 218         FLH = (1 << 13),        /* Front Left High      */
 219         FCH = (1 << 14),        /* Front Center High    */
 220         FRH = (1 << 15),        /* Front Right High     */
 221         TC  = (1 << 16),        /* Top Center           */
 222 };
 223
 224 /*
 225  * ELD SA bits in the CEA Speaker Allocation data block
 226  */
 227 static int eld_speaker_allocation_bits[] = {
 228         [0] = FL | FR,
 229         [1] = LFE,
 230         [2] = FC,
 231         [3] = RL | RR,
 232         [4] = RC,
 233         [5] = FLC | FRC,
 234         [6] = RLC | RRC,
 235         /* the following are not defined in ELD yet */
 236         [7] = FLW | FRW,
 237         [8] = FLH | FRH,
 238         [9] = TC,
 239         [10] = FCH,
 240 };
 241
 242 struct cea_channel_speaker_allocation {
 243         int ca_index;
 244         int speakers[8];
 245
 246         /* derived values, just for convenience */
 247         int channels;
 248         int spk_mask;
 249 };
 250
 251 /*
 252  * ALSA sequence is:
 253  *
 254  *       surround40   surround41   surround50   surround51   surround71
 255  * ch0   front left   =            =            =            =
 256  * ch1   front right  =            =            =            =
 257  * ch2   rear left    =            =            =            =
 258  * ch3   rear right   =            =            =            =
 259  * ch4                LFE          center       center       center
 260  * ch5                                          LFE          LFE
 261  * ch6                                                       side left
 262  * ch7                                                       side right
 263  *
 264  * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
 265  */
 266 static int hdmi_channel_mapping[0x32][8] = {
 267         /* stereo */
 268         [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 269         /* 2.1 */
 270         [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 271         /* Dolby Surround */
 272         [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
 273         /* surround40 */
 274         [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
 275         /* 4ch */
 276         [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
 277         /* surround41 */
 278         [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
 279         /* surround50 */
 280         [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
 281         /* surround51 */
 282         [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
 283         /* 7.1 */
 284         [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
 285 };
 286
 287 /*
 288  * This is an ordered list!
 289  *
 290  * The preceding ones have better chances to be selected by
 291  * hdmi_channel_allocation().
 292  */
 293 static struct cea_channel_speaker_allocation channel_allocations[] = {
 294 /*                        channel:   7     6    5    4    3     2    1    0  */
 295 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
 296                                  /* 2.1 */
 297 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
 298                                  /* Dolby Surround */
 299 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
 300                                  /* surround40 */
 301 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
 302                                  /* surround41 */
 303 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
 304                                  /* surround50 */
 305 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 306                                  /* surround51 */
 307 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 308                                  /* 6.1 */
 309 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 310                                  /* surround71 */
 311 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 312
 313 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
 314 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
 315 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
 316 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
 317 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 318 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 319 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 320 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 321 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 322 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 323 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 324 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 325 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 326 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 327 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 328 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 329 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 330 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 331 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 332 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 333 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 334 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 335 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 336 { .ca_index = 0x20,  .speakers = {   0,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 337 { .ca_index = 0x21,  .speakers = {   0,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 338 { .ca_index = 0x22,  .speakers = {  TC,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 339 { .ca_index = 0x23,  .speakers = {  TC,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 340 { .ca_index = 0x24,  .speakers = { FRH,  FLH,  RR,  RL,   0,    0,  FR,  FL } },
 341 { .ca_index = 0x25,  .speakers = { FRH,  FLH,  RR,  RL,   0,  LFE,  FR,  FL } },
 342 { .ca_index = 0x26,  .speakers = { FRW,  FLW,  RR,  RL,   0,    0,  FR,  FL } },
 343 { .ca_index = 0x27,  .speakers = { FRW,  FLW,  RR,  RL,   0,  LFE,  FR,  FL } },
 344 { .ca_index = 0x28,  .speakers = {  TC,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 345 { .ca_index = 0x29,  .speakers = {  TC,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 346 { .ca_index = 0x2a,  .speakers = { FCH,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 347 { .ca_index = 0x2b,  .speakers = { FCH,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 348 { .ca_index = 0x2c,  .speakers = {  TC,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 349 { .ca_index = 0x2d,  .speakers = {  TC,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 350 { .ca_index = 0x2e,  .speakers = { FRH,  FLH,  RR,  RL,  FC,    0,  FR,  FL } },
 351 { .ca_index = 0x2f,  .speakers = { FRH,  FLH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 352 { .ca_index = 0x30,  .speakers = { FRW,  FLW,  RR,  RL,  FC,    0,  FR,  FL } },
 353 { .ca_index = 0x31,  .speakers = { FRW,  FLW,  RR,  RL,  FC,  LFE,  FR,  FL } },
 354 };
 355
 356
 357 /*
 358  * HDMI routines
 359  */
 360
 361 #define get_pin(spec, idx) \
 362         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 363 #define get_cvt(spec, idx) \
 364         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 365 #define get_pcm_rec(spec, idx)  ((spec)->pcm_rec[idx])
 366
 367 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
 368 {
 369         struct hdmi_spec *spec = codec->spec;
 370         int pin_idx;
 371
 372         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 373                 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
 374                         return pin_idx;
 375
 376         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 377         return -EINVAL;
 378 }
 379
 380 static int hinfo_to_pin_index(struct hda_codec *codec,
 381                               struct hda_pcm_stream *hinfo)
 382 {
 383         struct hdmi_spec *spec = codec->spec;
 384         int pin_idx;
 385
 386         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 387                 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
 388                         return pin_idx;
 389
 390         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 391         return -EINVAL;
 392 }
 393
 394 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 395 {
 396         struct hdmi_spec *spec = codec->spec;
 397         int cvt_idx;
 398
 399         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 400                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 401                         return cvt_idx;
 402
 403         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 404         return -EINVAL;
 405 }
 406
 407 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 408                         struct snd_ctl_elem_info *uinfo)
 409 {
 410         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 411         struct hdmi_spec *spec = codec->spec;
 412         struct hdmi_spec_per_pin *per_pin;
 413         struct hdmi_eld *eld;
 414         int pin_idx;
 415
 416         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 417
 418         pin_idx = kcontrol->private_value;
 419         per_pin = get_pin(spec, pin_idx);
 420         eld = &per_pin->sink_eld;
 421
 422         mutex_lock(&per_pin->lock);
 423         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 424         mutex_unlock(&per_pin->lock);
 425
 426         return 0;
 427 }
 428
 429 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 430                         struct snd_ctl_elem_value *ucontrol)
 431 {
 432         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 433         struct hdmi_spec *spec = codec->spec;
 434         struct hdmi_spec_per_pin *per_pin;
 435         struct hdmi_eld *eld;
 436         int pin_idx;
 437
 438         pin_idx = kcontrol->private_value;
 439         per_pin = get_pin(spec, pin_idx);
 440         eld = &per_pin->sink_eld;
 441
 442         mutex_lock(&per_pin->lock);
 443         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
 444             eld->eld_size > ELD_MAX_SIZE) {
 445                 mutex_unlock(&per_pin->lock);
 446                 snd_BUG();
 447                 return -EINVAL;
 448         }
 449
 450         memset(ucontrol->value.bytes.data, 0,
 451                ARRAY_SIZE(ucontrol->value.bytes.data));
 452         if (eld->eld_valid)
 453                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 454                        eld->eld_size);
 455         mutex_unlock(&per_pin->lock);
 456
 457         return 0;
 458 }
 459
 460 static struct snd_kcontrol_new eld_bytes_ctl = {
 461         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 462         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 463         .name = "ELD",
 464         .info = hdmi_eld_ctl_info,
 465         .get = hdmi_eld_ctl_get,
 466 };
 467
 468 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
 469                         int device)
 470 {
 471         struct snd_kcontrol *kctl;
 472         struct hdmi_spec *spec = codec->spec;
 473         int err;
 474
 475         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 476         if (!kctl)
 477                 return -ENOMEM;
 478         kctl->private_value = pin_idx;
 479         kctl->id.device = device;
 480
 481         err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
 482         if (err < 0)
 483                 return err;
 484
 485         get_pin(spec, pin_idx)->eld_ctl = kctl;
 486         return 0;
 487 }
 488
 489 #ifdef BE_PARANOID
 490 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 491                                 int *packet_index, int *byte_index)
 492 {
 493         int val;
 494
 495         val = snd_hda_codec_read(codec, pin_nid, 0,
 496                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 497
 498         *packet_index = val >> 5;
 499         *byte_index = val & 0x1f;
 500 }
 501 #endif
 502
 503 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 504                                 int packet_index, int byte_index)
 505 {
 506         int val;
 507
 508         val = (packet_index << 5) | (byte_index & 0x1f);
 509
 510         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 511 }
 512
 513 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 514                                 unsigned char val)
 515 {
 516         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 517 }
 518
 519 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 520 {
 521         struct hdmi_spec *spec = codec->spec;
 522         int pin_out;
 523
 524         /* Unmute */
 525         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 526                 snd_hda_codec_write(codec, pin_nid, 0,
 527                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 528
 529         if (spec->dyn_pin_out)
 530                 /* Disable pin out until stream is active */
 531                 pin_out = 0;
 532         else
 533                 /* Enable pin out: some machines with GM965 gets broken output
 534                  * when the pin is disabled or changed while using with HDMI
 535                  */
 536                 pin_out = PIN_OUT;
 537
 538         snd_hda_codec_write(codec, pin_nid, 0,
 539                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 540 }
 541
 542 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
 543 {
 544         return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
 545                                         AC_VERB_GET_CVT_CHAN_COUNT, 0);
 546 }
 547
 548 static void hdmi_set_channel_count(struct hda_codec *codec,
 549                                    hda_nid_t cvt_nid, int chs)
 550 {
 551         if (chs != hdmi_get_channel_count(codec, cvt_nid))
 552                 snd_hda_codec_write(codec, cvt_nid, 0,
 553                                     AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
 554 }
 555
 556 /*
 557  * ELD proc files
 558  */
 559
 560 #ifdef CONFIG_SND_PROC_FS
 561 static void print_eld_info(struct snd_info_entry *entry,
 562                            struct snd_info_buffer *buffer)
 563 {
 564         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 565
 566         mutex_lock(&per_pin->lock);
 567         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 568         mutex_unlock(&per_pin->lock);
 569 }
 570
 571 static void write_eld_info(struct snd_info_entry *entry,
 572                            struct snd_info_buffer *buffer)
 573 {
 574         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 575
 576         mutex_lock(&per_pin->lock);
 577         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 578         mutex_unlock(&per_pin->lock);
 579 }
 580
 581 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 582 {
 583         char name[32];
 584         struct hda_codec *codec = per_pin->codec;
 585         struct snd_info_entry *entry;
 586         int err;
 587
 588         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 589         err = snd_card_proc_new(codec->card, name, &entry);
 590         if (err < 0)
 591                 return err;
 592
 593         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 594         entry->c.text.write = write_eld_info;
 595         entry->mode |= S_IWUSR;
 596         per_pin->proc_entry = entry;
 597
 598         return 0;
 599 }
 600
 601 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 602 {
 603         if (!per_pin->codec->bus->shutdown) {
 604                 snd_info_free_entry(per_pin->proc_entry);
 605                 per_pin->proc_entry = NULL;
 606         }
 607 }
 608 #else
 609 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 610                                int index)
 611 {
 612         return 0;
 613 }
 614 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 615 {
 616 }
 617 #endif
 618
 619 /*
 620  * Channel mapping routines
 621  */
 622
 623 /*
 624  * Compute derived values in channel_allocations[].
 625  */
 626 static void init_channel_allocations(void)
 627 {
 628         int i, j;
 629         struct cea_channel_speaker_allocation *p;
 630
 631         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 632                 p = channel_allocations + i;
 633                 p->channels = 0;
 634                 p->spk_mask = 0;
 635                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 636                         if (p->speakers[j]) {
 637                                 p->channels++;
 638                                 p->spk_mask |= p->speakers[j];
 639                         }
 640         }
 641 }
 642
 643 static int get_channel_allocation_order(int ca)
 644 {
 645         int i;
 646
 647         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 648                 if (channel_allocations[i].ca_index == ca)
 649                         break;
 650         }
 651         return i;
 652 }
 653
 654 /*
 655  * The transformation takes two steps:
 656  *
 657  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 658  *            spk_mask => (channel_allocations[])         => ai->CA
 659  *
 660  * TODO: it could select the wrong CA from multiple candidates.
 661 */
 662 static int hdmi_channel_allocation(struct hda_codec *codec,
 663                                    struct hdmi_eld *eld, int channels)
 664 {
 665         int i;
 666         int ca = 0;
 667         int spk_mask = 0;
 668         char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
 669
 670         /*
 671          * CA defaults to 0 for basic stereo audio
 672          */
 673         if (channels <= 2)
 674                 return 0;
 675
 676         /*
 677          * expand ELD's speaker allocation mask
 678          *
 679          * ELD tells the speaker mask in a compact(paired) form,
 680          * expand ELD's notions to match the ones used by Audio InfoFrame.
 681          */
 682         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 683                 if (eld->info.spk_alloc & (1 << i))
 684                         spk_mask |= eld_speaker_allocation_bits[i];
 685         }
 686
 687         /* search for the first working match in the CA table */
 688         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 689                 if (channels == channel_allocations[i].channels &&
 690                     (spk_mask & channel_allocations[i].spk_mask) ==
 691                                 channel_allocations[i].spk_mask) {
 692                         ca = channel_allocations[i].ca_index;
 693                         break;
 694                 }
 695         }
 696
 697         if (!ca) {
 698                 /* if there was no match, select the regular ALSA channel
 699                  * allocation with the matching number of channels */
 700                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 701                         if (channels == channel_allocations[i].channels) {
 702                                 ca = channel_allocations[i].ca_index;
 703                                 break;
 704                         }
 705                 }
 706         }
 707
 708         snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
 709         codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
 710                     ca, channels, buf);
 711
 712         return ca;
 713 }
 714
 715 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
 716                                        hda_nid_t pin_nid)
 717 {
 718 #ifdef CONFIG_SND_DEBUG_VERBOSE
 719         struct hdmi_spec *spec = codec->spec;
 720         int i;
 721         int channel;
 722
 723         for (i = 0; i < 8; i++) {
 724                 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
 725                 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
 726                                                 channel, i);
 727         }
 728 #endif
 729 }
 730
 731 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
 732                                        hda_nid_t pin_nid,
 733                                        bool non_pcm,
 734                                        int ca)
 735 {
 736         struct hdmi_spec *spec = codec->spec;
 737         struct cea_channel_speaker_allocation *ch_alloc;
 738         int i;
 739         int err;
 740         int order;
 741         int non_pcm_mapping[8];
 742
 743         order = get_channel_allocation_order(ca);
 744         ch_alloc = &channel_allocations[order];
 745
 746         if (hdmi_channel_mapping[ca][1] == 0) {
 747                 int hdmi_slot = 0;
 748                 /* fill actual channel mappings in ALSA channel (i) order */
 749                 for (i = 0; i < ch_alloc->channels; i++) {
 750                         while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
 751                                 hdmi_slot++; /* skip zero slots */
 752
 753                         hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
 754                 }
 755                 /* fill the rest of the slots with ALSA channel 0xf */
 756                 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
 757                         if (!ch_alloc->speakers[7 - hdmi_slot])
 758                                 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
 759         }
 760
 761         if (non_pcm) {
 762                 for (i = 0; i < ch_alloc->channels; i++)
 763                         non_pcm_mapping[i] = (i << 4) | i;
 764                 for (; i < 8; i++)
 765                         non_pcm_mapping[i] = (0xf << 4) | i;
 766         }
 767
 768         for (i = 0; i < 8; i++) {
 769                 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
 770                 int hdmi_slot = slotsetup & 0x0f;
 771                 int channel = (slotsetup & 0xf0) >> 4;
 772                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
 773                 if (err) {
 774                         codec_dbg(codec, "HDMI: channel mapping failed\n");
 775                         break;
 776                 }
 777         }
 778 }
 779
 780 struct channel_map_table {
 781         unsigned char map;              /* ALSA API channel map position */
 782         int spk_mask;                   /* speaker position bit mask */
 783 };
 784
 785 static struct channel_map_table map_tables[] = {
 786         { SNDRV_CHMAP_FL,       FL },
 787         { SNDRV_CHMAP_FR,       FR },
 788         { SNDRV_CHMAP_RL,       RL },
 789         { SNDRV_CHMAP_RR,       RR },
 790         { SNDRV_CHMAP_LFE,      LFE },
 791         { SNDRV_CHMAP_FC,       FC },
 792         { SNDRV_CHMAP_RLC,      RLC },
 793         { SNDRV_CHMAP_RRC,      RRC },
 794         { SNDRV_CHMAP_RC,       RC },
 795         { SNDRV_CHMAP_FLC,      FLC },
 796         { SNDRV_CHMAP_FRC,      FRC },
 797         { SNDRV_CHMAP_TFL,      FLH },
 798         { SNDRV_CHMAP_TFR,      FRH },
 799         { SNDRV_CHMAP_FLW,      FLW },
 800         { SNDRV_CHMAP_FRW,      FRW },
 801         { SNDRV_CHMAP_TC,       TC },
 802         { SNDRV_CHMAP_TFC,      FCH },
 803         {} /* terminator */
 804 };
 805
 806 /* from ALSA API channel position to speaker bit mask */
 807 static int to_spk_mask(unsigned char c)
 808 {
 809         struct channel_map_table *t = map_tables;
 810         for (; t->map; t++) {
 811                 if (t->map == c)
 812                         return t->spk_mask;
 813         }
 814         return 0;
 815 }
 816
 817 /* from ALSA API channel position to CEA slot */
 818 static int to_cea_slot(int ordered_ca, unsigned char pos)
 819 {
 820         int mask = to_spk_mask(pos);
 821         int i;
 822
 823         if (mask) {
 824                 for (i = 0; i < 8; i++) {
 825                         if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
 826                                 return i;
 827                 }
 828         }
 829
 830         return -1;
 831 }
 832
 833 /* from speaker bit mask to ALSA API channel position */
 834 static int spk_to_chmap(int spk)
 835 {
 836         struct channel_map_table *t = map_tables;
 837         for (; t->map; t++) {
 838                 if (t->spk_mask == spk)
 839                         return t->map;
 840         }
 841         return 0;
 842 }
 843
 844 /* from CEA slot to ALSA API channel position */
 845 static int from_cea_slot(int ordered_ca, unsigned char slot)
 846 {
 847         int mask = channel_allocations[ordered_ca].speakers[7 - slot];
 848
 849         return spk_to_chmap(mask);
 850 }
 851
 852 /* get the CA index corresponding to the given ALSA API channel map */
 853 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
 854 {
 855         int i, spks = 0, spk_mask = 0;
 856
 857         for (i = 0; i < chs; i++) {
 858                 int mask = to_spk_mask(map[i]);
 859                 if (mask) {
 860                         spk_mask |= mask;
 861                         spks++;
 862                 }
 863         }
 864
 865         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 866                 if ((chs == channel_allocations[i].channels ||
 867                      spks == channel_allocations[i].channels) &&
 868                     (spk_mask & channel_allocations[i].spk_mask) ==
 869                                 channel_allocations[i].spk_mask)
 870                         return channel_allocations[i].ca_index;
 871         }
 872         return -1;
 873 }
 874
 875 /* set up the channel slots for the given ALSA API channel map */
 876 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
 877                                              hda_nid_t pin_nid,
 878                                              int chs, unsigned char *map,
 879                                              int ca)
 880 {
 881         struct hdmi_spec *spec = codec->spec;
 882         int ordered_ca = get_channel_allocation_order(ca);
 883         int alsa_pos, hdmi_slot;
 884         int assignments[8] = {[0 ... 7] = 0xf};
 885
 886         for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
 887
 888                 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
 889
 890                 if (hdmi_slot < 0)
 891                         continue; /* unassigned channel */
 892
 893                 assignments[hdmi_slot] = alsa_pos;
 894         }
 895
 896         for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
 897                 int err;
 898
 899                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
 900                                                      assignments[hdmi_slot]);
 901                 if (err)
 902                         return -EINVAL;
 903         }
 904         return 0;
 905 }
 906
 907 /* store ALSA API channel map from the current default map */
 908 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
 909 {
 910         int i;
 911         int ordered_ca = get_channel_allocation_order(ca);
 912         for (i = 0; i < 8; i++) {
 913                 if (i < channel_allocations[ordered_ca].channels)
 914                         map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
 915                 else
 916                         map[i] = 0;
 917         }
 918 }
 919
 920 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
 921                                        hda_nid_t pin_nid, bool non_pcm, int ca,
 922                                        int channels, unsigned char *map,
 923                                        bool chmap_set)
 924 {
 925         if (!non_pcm && chmap_set) {
 926                 hdmi_manual_setup_channel_mapping(codec, pin_nid,
 927                                                   channels, map, ca);
 928         } else {
 929                 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
 930                 hdmi_setup_fake_chmap(map, ca);
 931         }
 932
 933         hdmi_debug_channel_mapping(codec, pin_nid);
 934 }
 935
 936 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 937                                      int asp_slot, int channel)
 938 {
 939         return snd_hda_codec_write(codec, pin_nid, 0,
 940                                    AC_VERB_SET_HDMI_CHAN_SLOT,
 941                                    (channel << 4) | asp_slot);
 942 }
 943
 944 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 945                                      int asp_slot)
 946 {
 947         return (snd_hda_codec_read(codec, pin_nid, 0,
 948                                    AC_VERB_GET_HDMI_CHAN_SLOT,
 949                                    asp_slot) & 0xf0) >> 4;
 950 }
 951
 952 /*
 953  * Audio InfoFrame routines
 954  */
 955
 956 /*
 957  * Enable Audio InfoFrame Transmission
 958  */
 959 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 960                                        hda_nid_t pin_nid)
 961 {
 962         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 963         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 964                                                 AC_DIPXMIT_BEST);
 965 }
 966
 967 /*
 968  * Disable Audio InfoFrame Transmission
 969  */
 970 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 971                                       hda_nid_t pin_nid)
 972 {
 973         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 974         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 975                                                 AC_DIPXMIT_DISABLE);
 976 }
 977
 978 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 979 {
 980 #ifdef CONFIG_SND_DEBUG_VERBOSE
 981         int i;
 982         int size;
 983
 984         size = snd_hdmi_get_eld_size(codec, pin_nid);
 985         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 986
 987         for (i = 0; i < 8; i++) {
 988                 size = snd_hda_codec_read(codec, pin_nid, 0,
 989                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 990                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 991         }
 992 #endif
 993 }
 994
 995 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 996 {
 997 #ifdef BE_PARANOID
 998         int i, j;
 999         int size;
1000         int pi, bi;
1001         for (i = 0; i < 8; i++) {
1002                 size = snd_hda_codec_read(codec, pin_nid, 0,
1003                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
1004                 if (size == 0)
1005                         continue;
1006
1007                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1008                 for (j = 1; j < 1000; j++) {
1009                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
1010                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1011                         if (pi != i)
1012                                 codec_dbg(codec, "dip index %d: %d != %d\n",
1013                                                 bi, pi, i);
1014                         if (bi == 0) /* byte index wrapped around */
1015                                 break;
1016                 }
1017                 codec_dbg(codec,
1018                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1019                         i, size, j);
1020         }
1021 #endif
1022 }
1023
1024 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1025 {
1026         u8 *bytes = (u8 *)hdmi_ai;
1027         u8 sum = 0;
1028         int i;
1029
1030         hdmi_ai->checksum = 0;
1031
1032         for (i = 0; i < sizeof(*hdmi_ai); i++)
1033                 sum += bytes[i];
1034
1035         hdmi_ai->checksum = -sum;
1036 }
1037
1038 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1039                                       hda_nid_t pin_nid,
1040                                       u8 *dip, int size)
1041 {
1042         int i;
1043
1044         hdmi_debug_dip_size(codec, pin_nid);
1045         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1046
1047         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1048         for (i = 0; i < size; i++)
1049                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1050 }
1051
1052 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1053                                     u8 *dip, int size)
1054 {
1055         u8 val;
1056         int i;
1057
1058         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1059                                                             != AC_DIPXMIT_BEST)
1060                 return false;
1061
1062         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1063         for (i = 0; i < size; i++) {
1064                 val = snd_hda_codec_read(codec, pin_nid, 0,
1065                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
1066                 if (val != dip[i])
1067                         return false;
1068         }
1069
1070         return true;
1071 }
1072
1073 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1074                                      hda_nid_t pin_nid,
1075                                      int ca, int active_channels,
1076                                      int conn_type)
1077 {
1078         union audio_infoframe ai;
1079
1080         memset(&ai, 0, sizeof(ai));
1081         if (conn_type == 0) { /* HDMI */
1082                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1083
1084                 hdmi_ai->type           = 0x84;
1085                 hdmi_ai->ver            = 0x01;
1086                 hdmi_ai->len            = 0x0a;
1087                 hdmi_ai->CC02_CT47      = active_channels - 1;
1088                 hdmi_ai->CA             = ca;
1089                 hdmi_checksum_audio_infoframe(hdmi_ai);
1090         } else if (conn_type == 1) { /* DisplayPort */
1091                 struct dp_audio_infoframe *dp_ai = &ai.dp;
1092
1093                 dp_ai->type             = 0x84;
1094                 dp_ai->len              = 0x1b;
1095                 dp_ai->ver              = 0x11 << 2;
1096                 dp_ai->CC02_CT47        = active_channels - 1;
1097                 dp_ai->CA               = ca;
1098         } else {
1099                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1100                             pin_nid);
1101                 return;
1102         }
1103
1104         /*
1105          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1106          * sizeof(*dp_ai) to avoid partial match/update problems when
1107          * the user switches between HDMI/DP monitors.
1108          */
1109         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1110                                         sizeof(ai))) {
1111                 codec_dbg(codec,
1112                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1113                             pin_nid,
1114                             active_channels, ca);
1115                 hdmi_stop_infoframe_trans(codec, pin_nid);
1116                 hdmi_fill_audio_infoframe(codec, pin_nid,
1117                                             ai.bytes, sizeof(ai));
1118                 hdmi_start_infoframe_trans(codec, pin_nid);
1119         }
1120 }
1121
1122 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1123                                        struct hdmi_spec_per_pin *per_pin,
1124                                        bool non_pcm)
1125 {
1126         struct hdmi_spec *spec = codec->spec;
1127         hda_nid_t pin_nid = per_pin->pin_nid;
1128         int channels = per_pin->channels;
1129         int active_channels;
1130         struct hdmi_eld *eld;
1131         int ca, ordered_ca;
1132
1133         if (!channels)
1134                 return;
1135
1136         if (is_haswell_plus(codec))
1137                 snd_hda_codec_write(codec, pin_nid, 0,
1138                                             AC_VERB_SET_AMP_GAIN_MUTE,
1139                                             AMP_OUT_UNMUTE);
1140
1141         eld = &per_pin->sink_eld;
1142
1143         if (!non_pcm && per_pin->chmap_set)
1144                 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1145         else
1146                 ca = hdmi_channel_allocation(codec, eld, channels);
1147         if (ca < 0)
1148                 ca = 0;
1149
1150         ordered_ca = get_channel_allocation_order(ca);
1151         active_channels = channel_allocations[ordered_ca].channels;
1152
1153         hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1154
1155         /*
1156          * always configure channel mapping, it may have been changed by the
1157          * user in the meantime
1158          */
1159         hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1160                                    channels, per_pin->chmap,
1161                                    per_pin->chmap_set);
1162
1163         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1164                                       eld->info.conn_type);
1165
1166         per_pin->non_pcm = non_pcm;
1167 }
1168
1169 /*
1170  * Unsolicited events
1171  */
1172
1173 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1174
1175 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1176 {
1177         struct hdmi_spec *spec = codec->spec;
1178         int pin_idx = pin_nid_to_pin_index(codec, nid);
1179
1180         if (pin_idx < 0)
1181                 return;
1182         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1183                 snd_hda_jack_report_sync(codec);
1184 }
1185
1186 static void jack_callback(struct hda_codec *codec,
1187                           struct hda_jack_callback *jack)
1188 {
1189         check_presence_and_report(codec, jack->nid);
1190 }
1191
1192 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1193 {
1194         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1195         struct hda_jack_tbl *jack;
1196         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1197
1198         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1199         if (!jack)
1200                 return;
1201         jack->jack_dirty = 1;
1202
1203         codec_dbg(codec,
1204                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1205                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1206                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1207
1208         check_presence_and_report(codec, jack->nid);
1209 }
1210
1211 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1212 {
1213         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1214         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1215         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1216         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1217
1218         codec_info(codec,
1219                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1220                 codec->addr,
1221                 tag,
1222                 subtag,
1223                 cp_state,
1224                 cp_ready);
1225
1226         /* TODO */
1227         if (cp_state)
1228                 ;
1229         if (cp_ready)
1230                 ;
1231 }
1232
1233
1234 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1235 {
1236         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1237         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1238
1239         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1240                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1241                 return;
1242         }
1243
1244         if (subtag == 0)
1245                 hdmi_intrinsic_event(codec, res);
1246         else
1247                 hdmi_non_intrinsic_event(codec, res);
1248 }
1249
1250 static void haswell_verify_D0(struct hda_codec *codec,
1251                 hda_nid_t cvt_nid, hda_nid_t nid)
1252 {
1253         int pwr;
1254
1255         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1256          * thus pins could only choose converter 0 for use. Make sure the
1257          * converters are in correct power state */
1258         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1259                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1260
1261         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1262                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1263                                     AC_PWRST_D0);
1264                 msleep(40);
1265                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1266                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1267                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1268         }
1269 }
1270
1271 /*
1272  * Callbacks
1273  */
1274
1275 /* HBR should be Non-PCM, 8 channels */
1276 #define is_hbr_format(format) \
1277         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1278
1279 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1280                               bool hbr)
1281 {
1282         int pinctl, new_pinctl;
1283
1284         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1285                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1286                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1287
1288                 if (pinctl < 0)
1289                         return hbr ? -EINVAL : 0;
1290
1291                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1292                 if (hbr)
1293                         new_pinctl |= AC_PINCTL_EPT_HBR;
1294                 else
1295                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
1296
1297                 codec_dbg(codec,
1298                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1299                             pin_nid,
1300                             pinctl == new_pinctl ? "" : "new-",
1301                             new_pinctl);
1302
1303                 if (pinctl != new_pinctl)
1304                         snd_hda_codec_write(codec, pin_nid, 0,
1305                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1306                                             new_pinctl);
1307         } else if (hbr)
1308                 return -EINVAL;
1309
1310         return 0;
1311 }
1312
1313 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1314                               hda_nid_t pin_nid, u32 stream_tag, int format)
1315 {
1316         struct hdmi_spec *spec = codec->spec;
1317         int err;
1318
1319         if (is_haswell_plus(codec))
1320                 haswell_verify_D0(codec, cvt_nid, pin_nid);
1321
1322         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1323
1324         if (err) {
1325                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1326                 return err;
1327         }
1328
1329         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1330         return 0;
1331 }
1332
1333 static int hdmi_choose_cvt(struct hda_codec *codec,
1334                         int pin_idx, int *cvt_id, int *mux_id)
1335 {
1336         struct hdmi_spec *spec = codec->spec;
1337         struct hdmi_spec_per_pin *per_pin;
1338         struct hdmi_spec_per_cvt *per_cvt = NULL;
1339         int cvt_idx, mux_idx = 0;
1340
1341         per_pin = get_pin(spec, pin_idx);
1342
1343         /* Dynamically assign converter to stream */
1344         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1345                 per_cvt = get_cvt(spec, cvt_idx);
1346
1347                 /* Must not already be assigned */
1348                 if (per_cvt->assigned)
1349                         continue;
1350                 /* Must be in pin's mux's list of converters */
1351                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1352                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1353                                 break;
1354                 /* Not in mux list */
1355                 if (mux_idx == per_pin->num_mux_nids)
1356                         continue;
1357                 break;
1358         }
1359
1360         /* No free converters */
1361         if (cvt_idx == spec->num_cvts)
1362                 return -ENODEV;
1363
1364         per_pin->mux_idx = mux_idx;
1365
1366         if (cvt_id)
1367                 *cvt_id = cvt_idx;
1368         if (mux_id)
1369                 *mux_id = mux_idx;
1370
1371         return 0;
1372 }
1373
1374 /* Assure the pin select the right convetor */
1375 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1376                         struct hdmi_spec_per_pin *per_pin)
1377 {
1378         hda_nid_t pin_nid = per_pin->pin_nid;
1379         int mux_idx, curr;
1380
1381         mux_idx = per_pin->mux_idx;
1382         curr = snd_hda_codec_read(codec, pin_nid, 0,
1383                                           AC_VERB_GET_CONNECT_SEL, 0);
1384         if (curr != mux_idx)
1385                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1386                                             AC_VERB_SET_CONNECT_SEL,
1387                                             mux_idx);
1388 }
1389
1390 /* Intel HDMI workaround to fix audio routing issue:
1391  * For some Intel display codecs, pins share the same connection list.
1392  * So a conveter can be selected by multiple pins and playback on any of these
1393  * pins will generate sound on the external display, because audio flows from
1394  * the same converter to the display pipeline. Also muting one pin may make
1395  * other pins have no sound output.
1396  * So this function assures that an assigned converter for a pin is not selected
1397  * by any other pins.
1398  */
1399 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1400                         hda_nid_t pin_nid, int mux_idx)
1401 {
1402         struct hdmi_spec *spec = codec->spec;
1403         hda_nid_t nid;
1404         int cvt_idx, curr;
1405         struct hdmi_spec_per_cvt *per_cvt;
1406
1407         /* configure all pins, including "no physical connection" ones */
1408         for_each_hda_codec_node(nid, codec) {
1409                 unsigned int wid_caps = get_wcaps(codec, nid);
1410                 unsigned int wid_type = get_wcaps_type(wid_caps);
1411
1412                 if (wid_type != AC_WID_PIN)
1413                         continue;
1414
1415                 if (nid == pin_nid)
1416                         continue;
1417
1418                 curr = snd_hda_codec_read(codec, nid, 0,
1419                                           AC_VERB_GET_CONNECT_SEL, 0);
1420                 if (curr != mux_idx)
1421                         continue;
1422
1423                 /* choose an unassigned converter. The conveters in the
1424                  * connection list are in the same order as in the codec.
1425                  */
1426                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1427                         per_cvt = get_cvt(spec, cvt_idx);
1428                         if (!per_cvt->assigned) {
1429                                 codec_dbg(codec,
1430                                           "choose cvt %d for pin nid %d\n",
1431                                         cvt_idx, nid);
1432                                 snd_hda_codec_write_cache(codec, nid, 0,
1433                                             AC_VERB_SET_CONNECT_SEL,
1434                                             cvt_idx);
1435                                 break;
1436                         }
1437                 }
1438         }
1439 }
1440
1441 /*
1442  * HDA PCM callbacks
1443  */
1444 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1445                          struct hda_codec *codec,
1446                          struct snd_pcm_substream *substream)
1447 {
1448         struct hdmi_spec *spec = codec->spec;
1449         struct snd_pcm_runtime *runtime = substream->runtime;
1450         int pin_idx, cvt_idx, mux_idx = 0;
1451         struct hdmi_spec_per_pin *per_pin;
1452         struct hdmi_eld *eld;
1453         struct hdmi_spec_per_cvt *per_cvt = NULL;
1454         int err;
1455
1456         /* Validate hinfo */
1457         pin_idx = hinfo_to_pin_index(codec, hinfo);
1458         if (snd_BUG_ON(pin_idx < 0))
1459                 return -EINVAL;
1460         per_pin = get_pin(spec, pin_idx);
1461         eld = &per_pin->sink_eld;
1462
1463         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1464         if (err < 0)
1465                 return err;
1466
1467         per_cvt = get_cvt(spec, cvt_idx);
1468         /* Claim converter */
1469         per_cvt->assigned = 1;
1470         per_pin->cvt_nid = per_cvt->cvt_nid;
1471         hinfo->nid = per_cvt->cvt_nid;
1472
1473         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1474                             AC_VERB_SET_CONNECT_SEL,
1475                             mux_idx);
1476
1477         /* configure unused pins to choose other converters */
1478         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1479                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1480
1481         snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1482
1483         /* Initially set the converter's capabilities */
1484         hinfo->channels_min = per_cvt->channels_min;
1485         hinfo->channels_max = per_cvt->channels_max;
1486         hinfo->rates = per_cvt->rates;
1487         hinfo->formats = per_cvt->formats;
1488         hinfo->maxbps = per_cvt->maxbps;
1489
1490         /* Restrict capabilities by ELD if this isn't disabled */
1491         if (!static_hdmi_pcm && eld->eld_valid) {
1492                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1493                 if (hinfo->channels_min > hinfo->channels_max ||
1494                     !hinfo->rates || !hinfo->formats) {
1495                         per_cvt->assigned = 0;
1496                         hinfo->nid = 0;
1497                         snd_hda_spdif_ctls_unassign(codec, pin_idx);
1498                         return -ENODEV;
1499                 }
1500         }
1501
1502         /* Store the updated parameters */
1503         runtime->hw.channels_min = hinfo->channels_min;
1504         runtime->hw.channels_max = hinfo->channels_max;
1505         runtime->hw.formats = hinfo->formats;
1506         runtime->hw.rates = hinfo->rates;
1507
1508         snd_pcm_hw_constraint_step(substream->runtime, 0,
1509                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1510         return 0;
1511 }
1512
1513 /*
1514  * HDA/HDMI auto parsing
1515  */
1516 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1517 {
1518         struct hdmi_spec *spec = codec->spec;
1519         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1520         hda_nid_t pin_nid = per_pin->pin_nid;
1521
1522         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1523                 codec_warn(codec,
1524                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1525                            pin_nid, get_wcaps(codec, pin_nid));
1526                 return -EINVAL;
1527         }
1528
1529         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1530                                                         per_pin->mux_nids,
1531                                                         HDA_MAX_CONNECTIONS);
1532
1533         return 0;
1534 }
1535
1536 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1537 {
1538         struct hda_jack_tbl *jack;
1539         struct hda_codec *codec = per_pin->codec;
1540         struct hdmi_spec *spec = codec->spec;
1541         struct hdmi_eld *eld = &spec->temp_eld;
1542         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1543         hda_nid_t pin_nid = per_pin->pin_nid;
1544         /*
1545          * Always execute a GetPinSense verb here, even when called from
1546          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1547          * response's PD bit is not the real PD value, but indicates that
1548          * the real PD value changed. An older version of the HD-audio
1549          * specification worked this way. Hence, we just ignore the data in
1550          * the unsolicited response to avoid custom WARs.
1551          */
1552         int present;
1553         bool update_eld = false;
1554         bool eld_changed = false;
1555         bool ret;
1556
1557         snd_hda_power_up_pm(codec);
1558         present = snd_hda_pin_sense(codec, pin_nid);
1559
1560         mutex_lock(&per_pin->lock);
1561         pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1562         if (pin_eld->monitor_present)
1563                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1564         else
1565                 eld->eld_valid = false;
1566
1567         codec_dbg(codec,
1568                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1569                 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1570
1571         if (eld->eld_valid) {
1572                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1573                                                      &eld->eld_size) < 0)
1574                         eld->eld_valid = false;
1575                 else {
1576                         memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1577                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1578                                                     eld->eld_size) < 0)
1579                                 eld->eld_valid = false;
1580                 }
1581
1582                 if (eld->eld_valid) {
1583                         snd_hdmi_show_eld(codec, &eld->info);
1584                         update_eld = true;
1585                 }
1586                 else if (repoll) {
1587                         schedule_delayed_work(&per_pin->work,
1588                                               msecs_to_jiffies(300));
1589                         goto unlock;
1590                 }
1591         }
1592
1593         if (pin_eld->eld_valid != eld->eld_valid)
1594                 eld_changed = true;
1595
1596         if (pin_eld->eld_valid && !eld->eld_valid)
1597                 update_eld = true;
1598
1599         if (update_eld) {
1600                 bool old_eld_valid = pin_eld->eld_valid;
1601                 pin_eld->eld_valid = eld->eld_valid;
1602                 if (pin_eld->eld_size != eld->eld_size ||
1603                               memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1604                                      eld->eld_size) != 0) {
1605                         memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1606                                eld->eld_size);
1607                         eld_changed = true;
1608                 }
1609                 pin_eld->eld_size = eld->eld_size;
1610                 pin_eld->info = eld->info;
1611
1612                 /*
1613                  * Re-setup pin and infoframe. This is needed e.g. when
1614                  * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1615                  * - transcoder can change during stream playback on Haswell
1616                  *   and this can make HW reset converter selection on a pin.
1617                  */
1618                 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1619                         if (is_haswell_plus(codec) ||
1620                                 is_valleyview_plus(codec)) {
1621                                 intel_verify_pin_cvt_connect(codec, per_pin);
1622                                 intel_not_share_assigned_cvt(codec, pin_nid,
1623                                                         per_pin->mux_idx);
1624                         }
1625
1626                         hdmi_setup_audio_infoframe(codec, per_pin,
1627                                                    per_pin->non_pcm);
1628                 }
1629         }
1630
1631         if (eld_changed)
1632                 snd_ctl_notify(codec->card,
1633                                SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1634                                &per_pin->eld_ctl->id);
1635  unlock:
1636         ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1637
1638         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1639         if (jack)
1640                 jack->block_report = !ret;
1641
1642         mutex_unlock(&per_pin->lock);
1643         snd_hda_power_down_pm(codec);
1644         return ret;
1645 }
1646
1647 static void hdmi_repoll_eld(struct work_struct *work)
1648 {
1649         struct hdmi_spec_per_pin *per_pin =
1650         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1651
1652         if (per_pin->repoll_count++ > 6)
1653                 per_pin->repoll_count = 0;
1654
1655         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1656                 snd_hda_jack_report_sync(per_pin->codec);
1657 }
1658
1659 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1660                                              hda_nid_t nid);
1661
1662 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1663 {
1664         struct hdmi_spec *spec = codec->spec;
1665         unsigned int caps, config;
1666         int pin_idx;
1667         struct hdmi_spec_per_pin *per_pin;
1668         int err;
1669
1670         caps = snd_hda_query_pin_caps(codec, pin_nid);
1671         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1672                 return 0;
1673
1674         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1675         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1676                 return 0;
1677
1678         if (is_haswell_plus(codec))
1679                 intel_haswell_fixup_connect_list(codec, pin_nid);
1680
1681         pin_idx = spec->num_pins;
1682         per_pin = snd_array_new(&spec->pins);
1683         if (!per_pin)
1684                 return -ENOMEM;
1685
1686         per_pin->pin_nid = pin_nid;
1687         per_pin->non_pcm = false;
1688
1689         err = hdmi_read_pin_conn(codec, pin_idx);
1690         if (err < 0)
1691                 return err;
1692
1693         spec->num_pins++;
1694
1695         return 0;
1696 }
1697
1698 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1699 {
1700         struct hdmi_spec *spec = codec->spec;
1701         struct hdmi_spec_per_cvt *per_cvt;
1702         unsigned int chans;
1703         int err;
1704
1705         chans = get_wcaps(codec, cvt_nid);
1706         chans = get_wcaps_channels(chans);
1707
1708         per_cvt = snd_array_new(&spec->cvts);
1709         if (!per_cvt)
1710                 return -ENOMEM;
1711
1712         per_cvt->cvt_nid = cvt_nid;
1713         per_cvt->channels_min = 2;
1714         if (chans <= 16) {
1715                 per_cvt->channels_max = chans;
1716                 if (chans > spec->channels_max)
1717                         spec->channels_max = chans;
1718         }
1719
1720         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1721                                           &per_cvt->rates,
1722                                           &per_cvt->formats,
1723                                           &per_cvt->maxbps);
1724         if (err < 0)
1725                 return err;
1726
1727         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1728                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1729         spec->num_cvts++;
1730
1731         return 0;
1732 }
1733
1734 static int hdmi_parse_codec(struct hda_codec *codec)
1735 {
1736         hda_nid_t nid;
1737         int i, nodes;
1738
1739         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1740         if (!nid || nodes < 0) {
1741                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1742                 return -EINVAL;
1743         }
1744
1745         for (i = 0; i < nodes; i++, nid++) {
1746                 unsigned int caps;
1747                 unsigned int type;
1748
1749                 caps = get_wcaps(codec, nid);
1750                 type = get_wcaps_type(caps);
1751
1752                 if (!(caps & AC_WCAP_DIGITAL))
1753                         continue;
1754
1755                 switch (type) {
1756                 case AC_WID_AUD_OUT:
1757                         hdmi_add_cvt(codec, nid);
1758                         break;
1759                 case AC_WID_PIN:
1760                         hdmi_add_pin(codec, nid);
1761                         break;
1762                 }
1763         }
1764
1765         return 0;
1766 }
1767
1768 /*
1769  */
1770 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1771 {
1772         struct hda_spdif_out *spdif;
1773         bool non_pcm;
1774
1775         mutex_lock(&codec->spdif_mutex);
1776         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1777         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1778         mutex_unlock(&codec->spdif_mutex);
1779         return non_pcm;
1780 }
1781
1782 /* There is a fixed mapping between audio pin node and display port
1783  * on current Intel platforms:
1784  * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1785  * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1786  * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1787  */
1788 static int intel_pin2port(hda_nid_t pin_nid)
1789 {
1790         return pin_nid - 4;
1791 }
1792
1793 /*
1794  * HDMI callbacks
1795  */
1796
1797 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1798                                            struct hda_codec *codec,
1799                                            unsigned int stream_tag,
1800                                            unsigned int format,
1801                                            struct snd_pcm_substream *substream)
1802 {
1803         hda_nid_t cvt_nid = hinfo->nid;
1804         struct hdmi_spec *spec = codec->spec;
1805         int pin_idx = hinfo_to_pin_index(codec, hinfo);
1806         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1807         hda_nid_t pin_nid = per_pin->pin_nid;
1808         struct snd_pcm_runtime *runtime = substream->runtime;
1809         struct i915_audio_component *acomp = codec->bus->core.audio_component;
1810         bool non_pcm;
1811         int pinctl;
1812
1813         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1814                 /* Verify pin:cvt selections to avoid silent audio after S3.
1815                  * After S3, the audio driver restores pin:cvt selections
1816                  * but this can happen before gfx is ready and such selection
1817                  * is overlooked by HW. Thus multiple pins can share a same
1818                  * default convertor and mute control will affect each other,
1819                  * which can cause a resumed audio playback become silent
1820                  * after S3.
1821                  */
1822                 intel_verify_pin_cvt_connect(codec, per_pin);
1823                 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1824         }
1825
1826         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1827         /* Todo: add DP1.2 MST audio support later */
1828         if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1829                 acomp->ops->sync_audio_rate(acomp->dev,
1830                                 intel_pin2port(pin_nid),
1831                                 runtime->rate);
1832
1833         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1834         mutex_lock(&per_pin->lock);
1835         per_pin->channels = substream->runtime->channels;
1836         per_pin->setup = true;
1837
1838         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1839         mutex_unlock(&per_pin->lock);
1840
1841         if (spec->dyn_pin_out) {
1842                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1843                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1844                 snd_hda_codec_write(codec, pin_nid, 0,
1845                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1846                                     pinctl | PIN_OUT);
1847         }
1848
1849         return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1850 }
1851
1852 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1853                                              struct hda_codec *codec,
1854                                              struct snd_pcm_substream *substream)
1855 {
1856         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1857         return 0;
1858 }
1859
1860 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1861                           struct hda_codec *codec,
1862                           struct snd_pcm_substream *substream)
1863 {
1864         struct hdmi_spec *spec = codec->spec;
1865         int cvt_idx, pin_idx;
1866         struct hdmi_spec_per_cvt *per_cvt;
1867         struct hdmi_spec_per_pin *per_pin;
1868         int pinctl;
1869
1870         if (hinfo->nid) {
1871                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1872                 if (snd_BUG_ON(cvt_idx < 0))
1873                         return -EINVAL;
1874                 per_cvt = get_cvt(spec, cvt_idx);
1875
1876                 snd_BUG_ON(!per_cvt->assigned);
1877                 per_cvt->assigned = 0;
1878                 hinfo->nid = 0;
1879
1880                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1881                 if (snd_BUG_ON(pin_idx < 0))
1882                         return -EINVAL;
1883                 per_pin = get_pin(spec, pin_idx);
1884
1885                 if (spec->dyn_pin_out) {
1886                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1887                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1888                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1889                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1890                                             pinctl & ~PIN_OUT);
1891                 }
1892
1893                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1894
1895                 mutex_lock(&per_pin->lock);
1896                 per_pin->chmap_set = false;
1897                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1898
1899                 per_pin->setup = false;
1900                 per_pin->channels = 0;
1901                 mutex_unlock(&per_pin->lock);
1902         }
1903
1904         return 0;
1905 }
1906
1907 static const struct hda_pcm_ops generic_ops = {
1908         .open = hdmi_pcm_open,
1909         .close = hdmi_pcm_close,
1910         .prepare = generic_hdmi_playback_pcm_prepare,
1911         .cleanup = generic_hdmi_playback_pcm_cleanup,
1912 };
1913
1914 /*
1915  * ALSA API channel-map control callbacks
1916  */
1917 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1918                                struct snd_ctl_elem_info *uinfo)
1919 {
1920         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1921         struct hda_codec *codec = info->private_data;
1922         struct hdmi_spec *spec = codec->spec;
1923         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1924         uinfo->count = spec->channels_max;
1925         uinfo->value.integer.min = 0;
1926         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1927         return 0;
1928 }
1929
1930 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1931                                                   int channels)
1932 {
1933         /* If the speaker allocation matches the channel count, it is OK.*/
1934         if (cap->channels != channels)
1935                 return -1;
1936
1937         /* all channels are remappable freely */
1938         return SNDRV_CTL_TLVT_CHMAP_VAR;
1939 }
1940
1941 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1942                                         unsigned int *chmap, int channels)
1943 {
1944         int count = 0;
1945         int c;
1946
1947         for (c = 7; c >= 0; c--) {
1948                 int spk = cap->speakers[c];
1949                 if (!spk)
1950                         continue;
1951
1952                 chmap[count++] = spk_to_chmap(spk);
1953         }
1954
1955         WARN_ON(count != channels);
1956 }
1957
1958 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1959                               unsigned int size, unsigned int __user *tlv)
1960 {
1961         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1962         struct hda_codec *codec = info->private_data;
1963         struct hdmi_spec *spec = codec->spec;
1964         unsigned int __user *dst;
1965         int chs, count = 0;
1966
1967         if (size < 8)
1968                 return -ENOMEM;
1969         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1970                 return -EFAULT;
1971         size -= 8;
1972         dst = tlv + 2;
1973         for (chs = 2; chs <= spec->channels_max; chs++) {
1974                 int i;
1975                 struct cea_channel_speaker_allocation *cap;
1976                 cap = channel_allocations;
1977                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1978                         int chs_bytes = chs * 4;
1979                         int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1980                         unsigned int tlv_chmap[8];
1981
1982                         if (type < 0)
1983                                 continue;
1984                         if (size < 8)
1985                                 return -ENOMEM;
1986                         if (put_user(type, dst) ||
1987                             put_user(chs_bytes, dst + 1))
1988                                 return -EFAULT;
1989                         dst += 2;
1990                         size -= 8;
1991                         count += 8;
1992                         if (size < chs_bytes)
1993                                 return -ENOMEM;
1994                         size -= chs_bytes;
1995                         count += chs_bytes;
1996                         spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1997                         if (copy_to_user(dst, tlv_chmap, chs_bytes))
1998                                 return -EFAULT;
1999                         dst += chs;
2000                 }
2001         }
2002         if (put_user(count, tlv + 1))
2003                 return -EFAULT;
2004         return 0;
2005 }
2006
2007 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2008                               struct snd_ctl_elem_value *ucontrol)
2009 {
2010         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2011         struct hda_codec *codec = info->private_data;
2012         struct hdmi_spec *spec = codec->spec;
2013         int pin_idx = kcontrol->private_value;
2014         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2015         int i;
2016
2017         for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2018                 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2019         return 0;
2020 }
2021
2022 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2023                               struct snd_ctl_elem_value *ucontrol)
2024 {
2025         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2026         struct hda_codec *codec = info->private_data;
2027         struct hdmi_spec *spec = codec->spec;
2028         int pin_idx = kcontrol->private_value;
2029         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2030         unsigned int ctl_idx;
2031         struct snd_pcm_substream *substream;
2032         unsigned char chmap[8];
2033         int i, err, ca, prepared = 0;
2034
2035         ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2036         substream = snd_pcm_chmap_substream(info, ctl_idx);
2037         if (!substream || !substream->runtime)
2038                 return 0; /* just for avoiding error from alsactl restore */
2039         switch (substream->runtime->status->state) {
2040         case SNDRV_PCM_STATE_OPEN:
2041         case SNDRV_PCM_STATE_SETUP:
2042                 break;
2043         case SNDRV_PCM_STATE_PREPARED:
2044                 prepared = 1;
2045                 break;
2046         default:
2047                 return -EBUSY;
2048         }
2049         memset(chmap, 0, sizeof(chmap));
2050         for (i = 0; i < ARRAY_SIZE(chmap); i++)
2051                 chmap[i] = ucontrol->value.integer.value[i];
2052         if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2053                 return 0;
2054         ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2055         if (ca < 0)
2056                 return -EINVAL;
2057         if (spec->ops.chmap_validate) {
2058                 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2059                 if (err)
2060                         return err;
2061         }
2062         mutex_lock(&per_pin->lock);
2063         per_pin->chmap_set = true;
2064         memcpy(per_pin->chmap, chmap, sizeof(chmap));
2065         if (prepared)
2066                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2067         mutex_unlock(&per_pin->lock);
2068
2069         return 0;
2070 }
2071
2072 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2073 {
2074         struct hdmi_spec *spec = codec->spec;
2075         int pin_idx;
2076
2077         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2078                 struct hda_pcm *info;
2079                 struct hda_pcm_stream *pstr;
2080
2081                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2082                 if (!info)
2083                         return -ENOMEM;
2084                 spec->pcm_rec[pin_idx] = info;
2085                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2086                 info->own_chmap = true;
2087
2088                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2089                 pstr->substreams = 1;
2090                 pstr->ops = generic_ops;
2091                 /* other pstr fields are set in open */
2092         }
2093
2094         return 0;
2095 }
2096
2097 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2098 {
2099         char hdmi_str[32] = "HDMI/DP";
2100         struct hdmi_spec *spec = codec->spec;
2101         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2102         int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2103         bool phantom_jack;
2104
2105         if (pcmdev > 0)
2106                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2107         phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2108         if (phantom_jack)
2109                 strncat(hdmi_str, " Phantom",
2110                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2111
2112         return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2113                                      phantom_jack);
2114 }
2115
2116 static int generic_hdmi_build_controls(struct hda_codec *codec)
2117 {
2118         struct hdmi_spec *spec = codec->spec;
2119         int err;
2120         int pin_idx;
2121
2122         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2123                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2124
2125                 err = generic_hdmi_build_jack(codec, pin_idx);
2126                 if (err < 0)
2127                         return err;
2128
2129                 err = snd_hda_create_dig_out_ctls(codec,
2130                                                   per_pin->pin_nid,
2131                                                   per_pin->mux_nids[0],
2132                                                   HDA_PCM_TYPE_HDMI);
2133                 if (err < 0)
2134                         return err;
2135                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2136
2137                 /* add control for ELD Bytes */
2138                 err = hdmi_create_eld_ctl(codec, pin_idx,
2139                                           get_pcm_rec(spec, pin_idx)->device);
2140
2141                 if (err < 0)
2142                         return err;
2143
2144                 hdmi_present_sense(per_pin, 0);
2145         }
2146
2147         /* add channel maps */
2148         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2149                 struct hda_pcm *pcm;
2150                 struct snd_pcm_chmap *chmap;
2151                 struct snd_kcontrol *kctl;
2152                 int i;
2153
2154                 pcm = spec->pcm_rec[pin_idx];
2155                 if (!pcm || !pcm->pcm)
2156                         break;
2157                 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2158                                              SNDRV_PCM_STREAM_PLAYBACK,
2159                                              NULL, 0, pin_idx, &chmap);
2160                 if (err < 0)
2161                         return err;
2162                 /* override handlers */
2163                 chmap->private_data = codec;
2164                 kctl = chmap->kctl;
2165                 for (i = 0; i < kctl->count; i++)
2166                         kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2167                 kctl->info = hdmi_chmap_ctl_info;
2168                 kctl->get = hdmi_chmap_ctl_get;
2169                 kctl->put = hdmi_chmap_ctl_put;
2170                 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2177 {
2178         struct hdmi_spec *spec = codec->spec;
2179         int pin_idx;
2180
2181         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2182                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2183
2184                 per_pin->codec = codec;
2185                 mutex_init(&per_pin->lock);
2186                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2187                 eld_proc_new(per_pin, pin_idx);
2188         }
2189         return 0;
2190 }
2191
2192 static int generic_hdmi_init(struct hda_codec *codec)
2193 {
2194         struct hdmi_spec *spec = codec->spec;
2195         int pin_idx;
2196
2197         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2198                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2199                 hda_nid_t pin_nid = per_pin->pin_nid;
2200
2201                 hdmi_init_pin(codec, pin_nid);
2202                 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2203                         codec->jackpoll_interval > 0 ? jack_callback : NULL);
2204         }
2205         return 0;
2206 }
2207
2208 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2209 {
2210         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2211         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2212 }
2213
2214 static void hdmi_array_free(struct hdmi_spec *spec)
2215 {
2216         snd_array_free(&spec->pins);
2217         snd_array_free(&spec->cvts);
2218 }
2219
2220 static void generic_hdmi_free(struct hda_codec *codec)
2221 {
2222         struct hdmi_spec *spec = codec->spec;
2223         int pin_idx;
2224
2225         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2226                 snd_hdac_i915_register_notifier(NULL);
2227
2228         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2229                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2230
2231                 cancel_delayed_work_sync(&per_pin->work);
2232                 eld_proc_free(per_pin);
2233         }
2234
2235         hdmi_array_free(spec);
2236         kfree(spec);
2237 }
2238
2239 #ifdef CONFIG_PM
2240 static int generic_hdmi_resume(struct hda_codec *codec)
2241 {
2242         struct hdmi_spec *spec = codec->spec;
2243         int pin_idx;
2244
2245         codec->patch_ops.init(codec);
2246         regcache_sync(codec->core.regmap);
2247
2248         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2249                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2250                 hdmi_present_sense(per_pin, 1);
2251         }
2252         return 0;
2253 }
2254 #endif
2255
2256 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2257         .init                   = generic_hdmi_init,
2258         .free                   = generic_hdmi_free,
2259         .build_pcms             = generic_hdmi_build_pcms,
2260         .build_controls         = generic_hdmi_build_controls,
2261         .unsol_event            = hdmi_unsol_event,
2262 #ifdef CONFIG_PM
2263         .resume                 = generic_hdmi_resume,
2264 #endif
2265 };
2266
2267 static const struct hdmi_ops generic_standard_hdmi_ops = {
2268         .pin_get_eld                            = snd_hdmi_get_eld,
2269         .pin_get_slot_channel                   = hdmi_pin_get_slot_channel,
2270         .pin_set_slot_channel                   = hdmi_pin_set_slot_channel,
2271         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2272         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2273         .setup_stream                           = hdmi_setup_stream,
2274         .chmap_cea_alloc_validate_get_type      = hdmi_chmap_cea_alloc_validate_get_type,
2275         .cea_alloc_to_tlv_chmap                 = hdmi_cea_alloc_to_tlv_chmap,
2276 };
2277
2278
2279 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2280                                              hda_nid_t nid)
2281 {
2282         struct hdmi_spec *spec = codec->spec;
2283         hda_nid_t conns[4];
2284         int nconns;
2285
2286         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2287         if (nconns == spec->num_cvts &&
2288             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2289                 return;
2290
2291         /* override pins connection list */
2292         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2293         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2294 }
2295
2296 #define INTEL_VENDOR_NID 0x08
2297 #define INTEL_GET_VENDOR_VERB 0xf81
2298 #define INTEL_SET_VENDOR_VERB 0x781
2299 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2300 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2301
2302 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2303                                           bool update_tree)
2304 {
2305         unsigned int vendor_param;
2306
2307         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2308                                 INTEL_GET_VENDOR_VERB, 0);
2309         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2310                 return;
2311
2312         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2313         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2314                                 INTEL_SET_VENDOR_VERB, vendor_param);
2315         if (vendor_param == -1)
2316                 return;
2317
2318         if (update_tree)
2319                 snd_hda_codec_update_widgets(codec);
2320 }
2321
2322 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2323 {
2324         unsigned int vendor_param;
2325
2326         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2327                                 INTEL_GET_VENDOR_VERB, 0);
2328         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2329                 return;
2330
2331         /* enable DP1.2 mode */
2332         vendor_param |= INTEL_EN_DP12;
2333         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2334         snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2335                                 INTEL_SET_VENDOR_VERB, vendor_param);
2336 }
2337
2338 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2339  * Otherwise you may get severe h/w communication errors.
2340  */
2341 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2342                                 unsigned int power_state)
2343 {
2344         if (power_state == AC_PWRST_D0) {
2345                 intel_haswell_enable_all_pins(codec, false);
2346                 intel_haswell_fixup_enable_dp12(codec);
2347         }
2348
2349         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2350         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2351 }
2352
2353 static void intel_pin_eld_notify(void *audio_ptr, int port)
2354 {
2355         struct hda_codec *codec = audio_ptr;
2356         int pin_nid = port + 0x04;
2357
2358         /* we assume only from port-B to port-D */
2359         if (port < 1 || port > 3)
2360                 return;
2361
2362         /* skip notification during system suspend (but not in runtime PM);
2363          * the state will be updated at resume
2364          */
2365         if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2366                 return;
2367
2368         check_presence_and_report(codec, pin_nid);
2369 }
2370
2371 static int patch_generic_hdmi(struct hda_codec *codec)
2372 {
2373         struct hdmi_spec *spec;
2374
2375         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2376         if (spec == NULL)
2377                 return -ENOMEM;
2378
2379         spec->ops = generic_standard_hdmi_ops;
2380         codec->spec = spec;
2381         hdmi_array_init(spec, 4);
2382
2383         if (is_haswell_plus(codec)) {
2384                 intel_haswell_enable_all_pins(codec, true);
2385                 intel_haswell_fixup_enable_dp12(codec);
2386         }
2387
2388         /* For Valleyview/Cherryview, only the display codec is in the display
2389          * power well and can use link_power ops to request/release the power.
2390          * For Haswell/Broadwell, the controller is also in the power well and
2391          * can cover the codec power request, and so need not set this flag.
2392          * For previous platforms, there is no such power well feature.
2393          */
2394         if (is_valleyview_plus(codec) || is_skylake(codec) ||
2395                         is_broxton(codec))
2396                 codec->core.link_power_control = 1;
2397
2398         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2399                 codec->depop_delay = 0;
2400                 spec->i915_audio_ops.audio_ptr = codec;
2401                 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2402                 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2403         }
2404
2405         if (hdmi_parse_codec(codec) < 0) {
2406                 codec->spec = NULL;
2407                 kfree(spec);
2408                 return -EINVAL;
2409         }
2410         codec->patch_ops = generic_hdmi_patch_ops;
2411         if (is_haswell_plus(codec)) {
2412                 codec->patch_ops.set_power_state = haswell_set_power_state;
2413                 codec->dp_mst = true;
2414         }
2415
2416         /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2417         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2418                 codec->auto_runtime_pm = 1;
2419
2420         generic_hdmi_init_per_pins(codec);
2421
2422         init_channel_allocations();
2423
2424         return 0;
2425 }
2426
2427 /*
2428  * Shared non-generic implementations
2429  */
2430
2431 static int simple_playback_build_pcms(struct hda_codec *codec)
2432 {
2433         struct hdmi_spec *spec = codec->spec;
2434         struct hda_pcm *info;
2435         unsigned int chans;
2436         struct hda_pcm_stream *pstr;
2437         struct hdmi_spec_per_cvt *per_cvt;
2438
2439         per_cvt = get_cvt(spec, 0);
2440         chans = get_wcaps(codec, per_cvt->cvt_nid);
2441         chans = get_wcaps_channels(chans);
2442
2443         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2444         if (!info)
2445                 return -ENOMEM;
2446         spec->pcm_rec[0] = info;
2447         info->pcm_type = HDA_PCM_TYPE_HDMI;
2448         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2449         *pstr = spec->pcm_playback;
2450         pstr->nid = per_cvt->cvt_nid;
2451         if (pstr->channels_max <= 2 && chans && chans <= 16)
2452                 pstr->channels_max = chans;
2453
2454         return 0;
2455 }
2456
2457 /* unsolicited event for jack sensing */
2458 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2459                                     unsigned int res)
2460 {
2461         snd_hda_jack_set_dirty_all(codec);
2462         snd_hda_jack_report_sync(codec);
2463 }
2464
2465 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2466  * as long as spec->pins[] is set correctly
2467  */
2468 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2469
2470 static int simple_playback_build_controls(struct hda_codec *codec)
2471 {
2472         struct hdmi_spec *spec = codec->spec;
2473         struct hdmi_spec_per_cvt *per_cvt;
2474         int err;
2475
2476         per_cvt = get_cvt(spec, 0);
2477         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2478                                           per_cvt->cvt_nid,
2479                                           HDA_PCM_TYPE_HDMI);
2480         if (err < 0)
2481                 return err;
2482         return simple_hdmi_build_jack(codec, 0);
2483 }
2484
2485 static int simple_playback_init(struct hda_codec *codec)
2486 {
2487         struct hdmi_spec *spec = codec->spec;
2488         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2489         hda_nid_t pin = per_pin->pin_nid;
2490
2491         snd_hda_codec_write(codec, pin, 0,
2492                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2493         /* some codecs require to unmute the pin */
2494         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2495                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2496                                     AMP_OUT_UNMUTE);
2497         snd_hda_jack_detect_enable(codec, pin);
2498         return 0;
2499 }
2500
2501 static void simple_playback_free(struct hda_codec *codec)
2502 {
2503         struct hdmi_spec *spec = codec->spec;
2504
2505         hdmi_array_free(spec);
2506         kfree(spec);
2507 }
2508
2509 /*
2510  * Nvidia specific implementations
2511  */
2512
2513 #define Nv_VERB_SET_Channel_Allocation          0xF79
2514 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2515 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2516 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2517
2518 #define nvhdmi_master_con_nid_7x        0x04
2519 #define nvhdmi_master_pin_nid_7x        0x05
2520
2521 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2522         /*front, rear, clfe, rear_surr */
2523         0x6, 0x8, 0xa, 0xc,
2524 };
2525
2526 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2527         /* set audio protect on */
2528         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2529         /* enable digital output on pin widget */
2530         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2531         {} /* terminator */
2532 };
2533
2534 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2535         /* set audio protect on */
2536         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2537         /* enable digital output on pin widget */
2538         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2539         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2540         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2541         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2542         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2543         {} /* terminator */
2544 };
2545
2546 #ifdef LIMITED_RATE_FMT_SUPPORT
2547 /* support only the safe format and rate */
2548 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2549 #define SUPPORTED_MAXBPS        16
2550 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2551 #else
2552 /* support all rates and formats */
2553 #define SUPPORTED_RATES \
2554         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2555         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2556          SNDRV_PCM_RATE_192000)
2557 #define SUPPORTED_MAXBPS        24
2558 #define SUPPORTED_FORMATS \
2559         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2560 #endif
2561
2562 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2563 {
2564         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2565         return 0;
2566 }
2567
2568 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2569 {
2570         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2571         return 0;
2572 }
2573
2574 static unsigned int channels_2_6_8[] = {
2575         2, 6, 8
2576 };
2577
2578 static unsigned int channels_2_8[] = {
2579         2, 8
2580 };
2581
2582 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2583         .count = ARRAY_SIZE(channels_2_6_8),
2584         .list = channels_2_6_8,
2585         .mask = 0,
2586 };
2587
2588 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2589         .count = ARRAY_SIZE(channels_2_8),
2590         .list = channels_2_8,
2591         .mask = 0,
2592 };
2593
2594 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2595                                     struct hda_codec *codec,
2596                                     struct snd_pcm_substream *substream)
2597 {
2598         struct hdmi_spec *spec = codec->spec;
2599         struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2600
2601         switch (codec->preset->vendor_id) {
2602         case 0x10de0002:
2603         case 0x10de0003:
2604         case 0x10de0005:
2605         case 0x10de0006:
2606                 hw_constraints_channels = &hw_constraints_2_8_channels;
2607                 break;
2608         case 0x10de0007:
2609                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2610                 break;
2611         default:
2612                 break;
2613         }
2614
2615         if (hw_constraints_channels != NULL) {
2616                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2617                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2618                                 hw_constraints_channels);
2619         } else {
2620                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2621                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2622         }
2623
2624         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2625 }
2626
2627 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2628                                      struct hda_codec *codec,
2629                                      struct snd_pcm_substream *substream)
2630 {
2631         struct hdmi_spec *spec = codec->spec;
2632         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2633 }
2634
2635 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2636                                        struct hda_codec *codec,
2637                                        unsigned int stream_tag,
2638                                        unsigned int format,
2639                                        struct snd_pcm_substream *substream)
2640 {
2641         struct hdmi_spec *spec = codec->spec;
2642         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2643                                              stream_tag, format, substream);
2644 }
2645
2646 static const struct hda_pcm_stream simple_pcm_playback = {
2647         .substreams = 1,
2648         .channels_min = 2,
2649         .channels_max = 2,
2650         .ops = {
2651                 .open = simple_playback_pcm_open,
2652                 .close = simple_playback_pcm_close,
2653                 .prepare = simple_playback_pcm_prepare
2654         },
2655 };
2656
2657 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2658         .build_controls = simple_playback_build_controls,
2659         .build_pcms = simple_playback_build_pcms,
2660         .init = simple_playback_init,
2661         .free = simple_playback_free,
2662         .unsol_event = simple_hdmi_unsol_event,
2663 };
2664
2665 static int patch_simple_hdmi(struct hda_codec *codec,
2666                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2667 {
2668         struct hdmi_spec *spec;
2669         struct hdmi_spec_per_cvt *per_cvt;
2670         struct hdmi_spec_per_pin *per_pin;
2671
2672         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2673         if (!spec)
2674                 return -ENOMEM;
2675
2676         codec->spec = spec;
2677         hdmi_array_init(spec, 1);
2678
2679         spec->multiout.num_dacs = 0;  /* no analog */
2680         spec->multiout.max_channels = 2;
2681         spec->multiout.dig_out_nid = cvt_nid;
2682         spec->num_cvts = 1;
2683         spec->num_pins = 1;
2684         per_pin = snd_array_new(&spec->pins);
2685         per_cvt = snd_array_new(&spec->cvts);
2686         if (!per_pin || !per_cvt) {
2687                 simple_playback_free(codec);
2688                 return -ENOMEM;
2689         }
2690         per_cvt->cvt_nid = cvt_nid;
2691         per_pin->pin_nid = pin_nid;
2692         spec->pcm_playback = simple_pcm_playback;
2693
2694         codec->patch_ops = simple_hdmi_patch_ops;
2695
2696         return 0;
2697 }
2698
2699 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2700                                                     int channels)
2701 {
2702         unsigned int chanmask;
2703         int chan = channels ? (channels - 1) : 1;
2704
2705         switch (channels) {
2706         default:
2707         case 0:
2708         case 2:
2709                 chanmask = 0x00;
2710                 break;
2711         case 4:
2712                 chanmask = 0x08;
2713                 break;
2714         case 6:
2715                 chanmask = 0x0b;
2716                 break;
2717         case 8:
2718                 chanmask = 0x13;
2719                 break;
2720         }
2721
2722         /* Set the audio infoframe channel allocation and checksum fields.  The
2723          * channel count is computed implicitly by the hardware. */
2724         snd_hda_codec_write(codec, 0x1, 0,
2725                         Nv_VERB_SET_Channel_Allocation, chanmask);
2726
2727         snd_hda_codec_write(codec, 0x1, 0,
2728                         Nv_VERB_SET_Info_Frame_Checksum,
2729                         (0x71 - chan - chanmask));
2730 }
2731
2732 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2733                                    struct hda_codec *codec,
2734                                    struct snd_pcm_substream *substream)
2735 {
2736         struct hdmi_spec *spec = codec->spec;
2737         int i;
2738
2739         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2740                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2741         for (i = 0; i < 4; i++) {
2742                 /* set the stream id */
2743                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2744                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2745                 /* set the stream format */
2746                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2747                                 AC_VERB_SET_STREAM_FORMAT, 0);
2748         }
2749
2750         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2751          * streams are disabled. */
2752         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2753
2754         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2755 }
2756
2757 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2758                                      struct hda_codec *codec,
2759                                      unsigned int stream_tag,
2760                                      unsigned int format,
2761                                      struct snd_pcm_substream *substream)
2762 {
2763         int chs;
2764         unsigned int dataDCC2, channel_id;
2765         int i;
2766         struct hdmi_spec *spec = codec->spec;
2767         struct hda_spdif_out *spdif;
2768         struct hdmi_spec_per_cvt *per_cvt;
2769
2770         mutex_lock(&codec->spdif_mutex);
2771         per_cvt = get_cvt(spec, 0);
2772         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2773
2774         chs = substream->runtime->channels;
2775
2776         dataDCC2 = 0x2;
2777
2778         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2779         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2780                 snd_hda_codec_write(codec,
2781                                 nvhdmi_master_con_nid_7x,
2782                                 0,
2783                                 AC_VERB_SET_DIGI_CONVERT_1,
2784                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2785
2786         /* set the stream id */
2787         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2788                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2789
2790         /* set the stream format */
2791         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2792                         AC_VERB_SET_STREAM_FORMAT, format);
2793
2794         /* turn on again (if needed) */
2795         /* enable and set the channel status audio/data flag */
2796         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2797                 snd_hda_codec_write(codec,
2798                                 nvhdmi_master_con_nid_7x,
2799                                 0,
2800                                 AC_VERB_SET_DIGI_CONVERT_1,
2801                                 spdif->ctls & 0xff);
2802                 snd_hda_codec_write(codec,
2803                                 nvhdmi_master_con_nid_7x,
2804                                 0,
2805                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2806         }
2807
2808         for (i = 0; i < 4; i++) {
2809                 if (chs == 2)
2810                         channel_id = 0;
2811                 else
2812                         channel_id = i * 2;
2813
2814                 /* turn off SPDIF once;
2815                  *otherwise the IEC958 bits won't be updated
2816                  */
2817                 if (codec->spdif_status_reset &&
2818                 (spdif->ctls & AC_DIG1_ENABLE))
2819                         snd_hda_codec_write(codec,
2820                                 nvhdmi_con_nids_7x[i],
2821                                 0,
2822                                 AC_VERB_SET_DIGI_CONVERT_1,
2823                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2824                 /* set the stream id */
2825                 snd_hda_codec_write(codec,
2826                                 nvhdmi_con_nids_7x[i],
2827                                 0,
2828                                 AC_VERB_SET_CHANNEL_STREAMID,
2829                                 (stream_tag << 4) | channel_id);
2830                 /* set the stream format */
2831                 snd_hda_codec_write(codec,
2832                                 nvhdmi_con_nids_7x[i],
2833                                 0,
2834                                 AC_VERB_SET_STREAM_FORMAT,
2835                                 format);
2836                 /* turn on again (if needed) */
2837                 /* enable and set the channel status audio/data flag */
2838                 if (codec->spdif_status_reset &&
2839                 (spdif->ctls & AC_DIG1_ENABLE)) {
2840                         snd_hda_codec_write(codec,
2841                                         nvhdmi_con_nids_7x[i],
2842                                         0,
2843                                         AC_VERB_SET_DIGI_CONVERT_1,
2844                                         spdif->ctls & 0xff);
2845                         snd_hda_codec_write(codec,
2846                                         nvhdmi_con_nids_7x[i],
2847                                         0,
2848                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2849                 }
2850         }
2851
2852         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2853
2854         mutex_unlock(&codec->spdif_mutex);
2855         return 0;
2856 }
2857
2858 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2859         .substreams = 1,
2860         .channels_min = 2,
2861         .channels_max = 8,
2862         .nid = nvhdmi_master_con_nid_7x,
2863         .rates = SUPPORTED_RATES,
2864         .maxbps = SUPPORTED_MAXBPS,
2865         .formats = SUPPORTED_FORMATS,
2866         .ops = {
2867                 .open = simple_playback_pcm_open,
2868                 .close = nvhdmi_8ch_7x_pcm_close,
2869                 .prepare = nvhdmi_8ch_7x_pcm_prepare
2870         },
2871 };
2872
2873 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2874 {
2875         struct hdmi_spec *spec;
2876         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2877                                     nvhdmi_master_pin_nid_7x);
2878         if (err < 0)
2879                 return err;
2880
2881         codec->patch_ops.init = nvhdmi_7x_init_2ch;
2882         /* override the PCM rates, etc, as the codec doesn't give full list */
2883         spec = codec->spec;
2884         spec->pcm_playback.rates = SUPPORTED_RATES;
2885         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2886         spec->pcm_playback.formats = SUPPORTED_FORMATS;
2887         return 0;
2888 }
2889
2890 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2891 {
2892         struct hdmi_spec *spec = codec->spec;
2893         int err = simple_playback_build_pcms(codec);
2894         if (!err) {
2895                 struct hda_pcm *info = get_pcm_rec(spec, 0);
2896                 info->own_chmap = true;
2897         }
2898         return err;
2899 }
2900
2901 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2902 {
2903         struct hdmi_spec *spec = codec->spec;
2904         struct hda_pcm *info;
2905         struct snd_pcm_chmap *chmap;
2906         int err;
2907
2908         err = simple_playback_build_controls(codec);
2909         if (err < 0)
2910                 return err;
2911
2912         /* add channel maps */
2913         info = get_pcm_rec(spec, 0);
2914         err = snd_pcm_add_chmap_ctls(info->pcm,
2915                                      SNDRV_PCM_STREAM_PLAYBACK,
2916                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
2917         if (err < 0)
2918                 return err;
2919         switch (codec->preset->vendor_id) {
2920         case 0x10de0002:
2921         case 0x10de0003:
2922         case 0x10de0005:
2923         case 0x10de0006:
2924                 chmap->channel_mask = (1U << 2) | (1U << 8);
2925                 break;
2926         case 0x10de0007:
2927                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2928         }
2929         return 0;
2930 }
2931
2932 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2933 {
2934         struct hdmi_spec *spec;
2935         int err = patch_nvhdmi_2ch(codec);
2936         if (err < 0)
2937                 return err;
2938         spec = codec->spec;
2939         spec->multiout.max_channels = 8;
2940         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2941         codec->patch_ops.init = nvhdmi_7x_init_8ch;
2942         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2943         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2944
2945         /* Initialize the audio infoframe channel mask and checksum to something
2946          * valid */
2947         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2948
2949         return 0;
2950 }
2951
2952 /*
2953  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2954  * - 0x10de0015
2955  * - 0x10de0040
2956  */
2957 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2958                                                     int channels)
2959 {
2960         if (cap->ca_index == 0x00 && channels == 2)
2961                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2962
2963         return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2964 }
2965
2966 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2967 {
2968         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2969                 return -EINVAL;
2970
2971         return 0;
2972 }
2973
2974 static int patch_nvhdmi(struct hda_codec *codec)
2975 {
2976         struct hdmi_spec *spec;
2977         int err;
2978
2979         err = patch_generic_hdmi(codec);
2980         if (err)
2981                 return err;
2982
2983         spec = codec->spec;
2984         spec->dyn_pin_out = true;
2985
2986         spec->ops.chmap_cea_alloc_validate_get_type =
2987                 nvhdmi_chmap_cea_alloc_validate_get_type;
2988         spec->ops.chmap_validate = nvhdmi_chmap_validate;
2989
2990         return 0;
2991 }
2992
2993 /*
2994  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2995  * accessed using vendor-defined verbs. These registers can be used for
2996  * interoperability between the HDA and HDMI drivers.
2997  */
2998
2999 /* Audio Function Group node */
3000 #define NVIDIA_AFG_NID 0x01
3001
3002 /*
3003  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3004  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3005  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3006  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3007  * additional bit (at position 30) to signal the validity of the format.
3008  *
3009  * | 31      | 30    | 29  16 | 15   0 |
3010  * +---------+-------+--------+--------+
3011  * | TRIGGER | VALID | UNUSED | FORMAT |
3012  * +-----------------------------------|
3013  *
3014  * Note that for the trigger bit to take effect it needs to change value
3015  * (i.e. it needs to be toggled).
3016  */
3017 #define NVIDIA_GET_SCRATCH0             0xfa6
3018 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3019 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3020 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3021 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3022 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3023 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3024
3025 #define NVIDIA_GET_SCRATCH1             0xfab
3026 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3027 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3028 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3029 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3030
3031 /*
3032  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3033  * the format is invalidated so that the HDMI codec can be disabled.
3034  */
3035 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3036 {
3037         unsigned int value;
3038
3039         /* bits [31:30] contain the trigger and valid bits */
3040         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3041                                    NVIDIA_GET_SCRATCH0, 0);
3042         value = (value >> 24) & 0xff;
3043
3044         /* bits [15:0] are used to store the HDA format */
3045         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3046                             NVIDIA_SET_SCRATCH0_BYTE0,
3047                             (format >> 0) & 0xff);
3048         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3049                             NVIDIA_SET_SCRATCH0_BYTE1,
3050                             (format >> 8) & 0xff);
3051
3052         /* bits [16:24] are unused */
3053         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3054                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3055
3056         /*
3057          * Bit 30 signals that the data is valid and hence that HDMI audio can
3058          * be enabled.
3059          */
3060         if (format == 0)
3061                 value &= ~NVIDIA_SCRATCH_VALID;
3062         else
3063                 value |= NVIDIA_SCRATCH_VALID;
3064
3065         /*
3066          * Whenever the trigger bit is toggled, an interrupt is raised in the
3067          * HDMI codec. The HDMI driver will use that as trigger to update its
3068          * configuration.
3069          */
3070         value ^= NVIDIA_SCRATCH_TRIGGER;
3071
3072         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3073                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3074 }
3075
3076 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3077                                   struct hda_codec *codec,
3078                                   unsigned int stream_tag,
3079                                   unsigned int format,
3080                                   struct snd_pcm_substream *substream)
3081 {
3082         int err;
3083
3084         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3085                                                 format, substream);
3086         if (err < 0)
3087                 return err;
3088
3089         /* notify the HDMI codec of the format change */
3090         tegra_hdmi_set_format(codec, format);
3091
3092         return 0;
3093 }
3094
3095 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3096                                   struct hda_codec *codec,
3097                                   struct snd_pcm_substream *substream)
3098 {
3099         /* invalidate the format in the HDMI codec */
3100         tegra_hdmi_set_format(codec, 0);
3101
3102         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3103 }
3104
3105 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3106 {
3107         struct hdmi_spec *spec = codec->spec;
3108         unsigned int i;
3109
3110         for (i = 0; i < spec->num_pins; i++) {
3111                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3112
3113                 if (pcm->pcm_type == type)
3114                         return pcm;
3115         }
3116
3117         return NULL;
3118 }
3119
3120 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3121 {
3122         struct hda_pcm_stream *stream;
3123         struct hda_pcm *pcm;
3124         int err;
3125
3126         err = generic_hdmi_build_pcms(codec);
3127         if (err < 0)
3128                 return err;
3129
3130         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3131         if (!pcm)
3132                 return -ENODEV;
3133
3134         /*
3135          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3136          * codec about format changes.
3137          */
3138         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3139         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3140         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3141
3142         return 0;
3143 }
3144
3145 static int patch_tegra_hdmi(struct hda_codec *codec)
3146 {
3147         int err;
3148
3149         err = patch_generic_hdmi(codec);
3150         if (err)
3151                 return err;
3152
3153         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3154
3155         return 0;
3156 }
3157
3158 /*
3159  * ATI/AMD-specific implementations
3160  */
3161
3162 #define is_amdhdmi_rev3_or_later(codec) \
3163         ((codec)->core.vendor_id == 0x1002aa01 && \
3164          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3165 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3166
3167 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3168 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3169 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3170 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3171 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3172 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3173 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3174 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3175 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3176 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3177 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3178 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3179 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3180 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3181 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3182 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3183 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3184 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3185 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3186 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3187 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3188 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3189 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3190 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3191 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3192
3193 /* AMD specific HDA cvt verbs */
3194 #define ATI_VERB_SET_RAMP_RATE          0x770
3195 #define ATI_VERB_GET_RAMP_RATE          0xf70
3196
3197 #define ATI_OUT_ENABLE 0x1
3198
3199 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3200 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3201
3202 #define ATI_HBR_CAPABLE 0x01
3203 #define ATI_HBR_ENABLE 0x10
3204
3205 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3206                            unsigned char *buf, int *eld_size)
3207 {
3208         /* call hda_eld.c ATI/AMD-specific function */
3209         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3210                                     is_amdhdmi_rev3_or_later(codec));
3211 }
3212
3213 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3214                                         int active_channels, int conn_type)
3215 {
3216         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3217 }
3218
3219 static int atihdmi_paired_swap_fc_lfe(int pos)
3220 {
3221         /*
3222          * ATI/AMD have automatic FC/LFE swap built-in
3223          * when in pairwise mapping mode.
3224          */
3225
3226         switch (pos) {
3227                 /* see channel_allocations[].speakers[] */
3228                 case 2: return 3;
3229                 case 3: return 2;
3230                 default: break;
3231         }
3232
3233         return pos;
3234 }
3235
3236 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3237 {
3238         struct cea_channel_speaker_allocation *cap;
3239         int i, j;
3240
3241         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3242
3243         cap = &channel_allocations[get_channel_allocation_order(ca)];
3244         for (i = 0; i < chs; ++i) {
3245                 int mask = to_spk_mask(map[i]);
3246                 bool ok = false;
3247                 bool companion_ok = false;
3248
3249                 if (!mask)
3250                         continue;
3251
3252                 for (j = 0 + i % 2; j < 8; j += 2) {
3253                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3254                         if (cap->speakers[chan_idx] == mask) {
3255                                 /* channel is in a supported position */
3256                                 ok = true;
3257
3258                                 if (i % 2 == 0 && i + 1 < chs) {
3259                                         /* even channel, check the odd companion */
3260                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3261                                         int comp_mask_req = to_spk_mask(map[i+1]);
3262                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3263
3264                                         if (comp_mask_req == comp_mask_act)
3265                                                 companion_ok = true;
3266                                         else
3267                                                 return -EINVAL;
3268                                 }
3269                                 break;
3270                         }
3271                 }
3272
3273                 if (!ok)
3274                         return -EINVAL;
3275
3276                 if (companion_ok)
3277                         i++; /* companion channel already checked */
3278         }
3279
3280         return 0;
3281 }
3282
3283 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3284                                         int hdmi_slot, int stream_channel)
3285 {
3286         int verb;
3287         int ati_channel_setup = 0;
3288
3289         if (hdmi_slot > 7)
3290                 return -EINVAL;
3291
3292         if (!has_amd_full_remap_support(codec)) {
3293                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3294
3295                 /* In case this is an odd slot but without stream channel, do not
3296                  * disable the slot since the corresponding even slot could have a
3297                  * channel. In case neither have a channel, the slot pair will be
3298                  * disabled when this function is called for the even slot. */
3299                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3300                         return 0;
3301
3302                 hdmi_slot -= hdmi_slot % 2;
3303
3304                 if (stream_channel != 0xf)
3305                         stream_channel -= stream_channel % 2;
3306         }
3307
3308         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3309
3310         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3311
3312         if (stream_channel != 0xf)
3313                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3314
3315         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3316 }
3317
3318 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3319                                         int asp_slot)
3320 {
3321         bool was_odd = false;
3322         int ati_asp_slot = asp_slot;
3323         int verb;
3324         int ati_channel_setup;
3325
3326         if (asp_slot > 7)
3327                 return -EINVAL;
3328
3329         if (!has_amd_full_remap_support(codec)) {
3330                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3331                 if (ati_asp_slot % 2 != 0) {
3332                         ati_asp_slot -= 1;
3333                         was_odd = true;
3334                 }
3335         }
3336
3337         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3338
3339         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3340
3341         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3342                 return 0xf;
3343
3344         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3345 }
3346
3347 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3348                                                             int channels)
3349 {
3350         int c;
3351
3352         /*
3353          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3354          * we need to take that into account (a single channel may take 2
3355          * channel slots if we need to carry a silent channel next to it).
3356          * On Rev3+ AMD codecs this function is not used.
3357          */
3358         int chanpairs = 0;
3359
3360         /* We only produce even-numbered channel count TLVs */
3361         if ((channels % 2) != 0)
3362                 return -1;
3363
3364         for (c = 0; c < 7; c += 2) {
3365                 if (cap->speakers[c] || cap->speakers[c+1])
3366                         chanpairs++;
3367         }
3368
3369         if (chanpairs * 2 != channels)
3370                 return -1;
3371
3372         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3373 }
3374
3375 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3376                                                   unsigned int *chmap, int channels)
3377 {
3378         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3379         int count = 0;
3380         int c;
3381
3382         for (c = 7; c >= 0; c--) {
3383                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3384                 int spk = cap->speakers[chan];
3385                 if (!spk) {
3386                         /* add N/A channel if the companion channel is occupied */
3387                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3388                                 chmap[count++] = SNDRV_CHMAP_NA;
3389
3390                         continue;
3391                 }
3392
3393                 chmap[count++] = spk_to_chmap(spk);
3394         }
3395
3396         WARN_ON(count != channels);
3397 }
3398
3399 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3400                                  bool hbr)
3401 {
3402         int hbr_ctl, hbr_ctl_new;
3403
3404         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3405         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3406                 if (hbr)
3407                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3408                 else
3409                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3410
3411                 codec_dbg(codec,
3412                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3413                                 pin_nid,
3414                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3415                                 hbr_ctl_new);
3416
3417                 if (hbr_ctl != hbr_ctl_new)
3418                         snd_hda_codec_write(codec, pin_nid, 0,
3419                                                 ATI_VERB_SET_HBR_CONTROL,
3420                                                 hbr_ctl_new);
3421
3422         } else if (hbr)
3423                 return -EINVAL;
3424
3425         return 0;
3426 }
3427
3428 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3429                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3430 {
3431
3432         if (is_amdhdmi_rev3_or_later(codec)) {
3433                 int ramp_rate = 180; /* default as per AMD spec */
3434                 /* disable ramp-up/down for non-pcm as per AMD spec */
3435                 if (format & AC_FMT_TYPE_NON_PCM)
3436                         ramp_rate = 0;
3437
3438                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3439         }
3440
3441         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3442 }
3443
3444
3445 static int atihdmi_init(struct hda_codec *codec)
3446 {
3447         struct hdmi_spec *spec = codec->spec;
3448         int pin_idx, err;
3449
3450         err = generic_hdmi_init(codec);
3451
3452         if (err)
3453                 return err;
3454
3455         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3456                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3457
3458                 /* make sure downmix information in infoframe is zero */
3459                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3460
3461                 /* enable channel-wise remap mode if supported */
3462                 if (has_amd_full_remap_support(codec))
3463                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3464                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3465                                             ATI_MULTICHANNEL_MODE_SINGLE);
3466         }
3467
3468         return 0;
3469 }
3470
3471 static int patch_atihdmi(struct hda_codec *codec)
3472 {
3473         struct hdmi_spec *spec;
3474         struct hdmi_spec_per_cvt *per_cvt;
3475         int err, cvt_idx;
3476
3477         err = patch_generic_hdmi(codec);
3478
3479         if (err)
3480                 return err;
3481
3482         codec->patch_ops.init = atihdmi_init;
3483
3484         spec = codec->spec;
3485
3486         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3487         spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3488         spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3489         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3490         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3491         spec->ops.setup_stream = atihdmi_setup_stream;
3492
3493         if (!has_amd_full_remap_support(codec)) {
3494                 /* override to ATI/AMD-specific versions with pairwise mapping */
3495                 spec->ops.chmap_cea_alloc_validate_get_type =
3496                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3497                 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3498                 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3499         }
3500
3501         /* ATI/AMD converters do not advertise all of their capabilities */
3502         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3503                 per_cvt = get_cvt(spec, cvt_idx);
3504                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3505                 per_cvt->rates |= SUPPORTED_RATES;
3506                 per_cvt->formats |= SUPPORTED_FORMATS;
3507                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3508         }
3509
3510         spec->channels_max = max(spec->channels_max, 8u);
3511
3512         return 0;
3513 }
3514
3515 /* VIA HDMI Implementation */
3516 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3517 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3518
3519 static int patch_via_hdmi(struct hda_codec *codec)
3520 {
3521         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3522 }
3523
3524 /*
3525  * patch entries
3526  */
3527 static const struct hda_device_id snd_hda_id_hdmi[] = {
3528 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3529 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3530 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3531 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3532 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3533 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3534 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3535 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3536 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3537 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3538 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3539 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3540 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3541 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3542 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3543 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3544 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3545 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3546 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3547 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3548 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3549 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3550 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3551 /* 17 is known to be absent */
3552 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3553 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3554 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3555 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3556 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3557 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3558 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3559 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3560 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3561 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3562 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3563 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3564 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3565 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3566 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3567 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3568 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3569 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3570 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3571 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3572 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3573 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3574 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3575 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3576 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3577 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3578 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_generic_hdmi),
3579 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3580 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3581 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3582 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_generic_hdmi),
3583 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3584 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3585 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_generic_hdmi),
3586 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_generic_hdmi),
3587 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_generic_hdmi),
3588 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_generic_hdmi),
3589 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_generic_hdmi),
3590 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3591 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3592 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_generic_hdmi),
3593 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3594 /* special ID for generic HDMI */
3595 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3596 {} /* terminator */
3597 };
3598 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3599
3600 MODULE_LICENSE("GPL");
3601 MODULE_DESCRIPTION("HDMI HD-audio codec");
3602 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3603 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3604 MODULE_ALIAS("snd-hda-codec-atihdmi");
3605
3606 static struct hda_codec_driver hdmi_driver = {
3607         .id = snd_hda_id_hdmi,
3608 };
3609
3610 module_hda_codec_driver(hdmi_driver);