kernel/sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_HDA_CGCTL  0x48
  94 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  95 #define INTEL_SCH_HDA_DEVC      0x78
  96 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  97
  98 /* Define IN stream 0 FIFO size offset in VIA controller */
  99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 100 /* Define VIA HD Audio Device ID*/
 101 #define VIA_HDAC_DEVICE_ID              0x3288
 102
 103 /* max number of SDs */
 104 /* ICH, ATI and VIA have 4 playback and 4 capture */
 105 #define ICH6_NUM_CAPTURE        4
 106 #define ICH6_NUM_PLAYBACK       4
 107
 108 /* ULI has 6 playback and 5 capture */
 109 #define ULI_NUM_CAPTURE         5
 110 #define ULI_NUM_PLAYBACK        6
 111
 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 113 #define ATIHDMI_NUM_CAPTURE     0
 114 #define ATIHDMI_NUM_PLAYBACK    8
 115
 116 /* TERA has 4 playback and 3 capture */
 117 #define TERA_NUM_CAPTURE        3
 118 #define TERA_NUM_PLAYBACK       4
 119
 120
 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 124 static char *model[SNDRV_CARDS];
 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_only[SNDRV_CARDS];
 129 static int jackpoll_ms[SNDRV_CARDS];
 130 static bool single_cmd;
 131 static int enable_msi = -1;
 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 133 static char *patch[SNDRV_CARDS];
 134 #endif
 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 137                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 138 #endif
 139
 140 module_param_array(index, int, NULL, 0444);
 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 142 module_param_array(id, charp, NULL, 0444);
 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 144 module_param_array(enable, bool, NULL, 0444);
 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 146 module_param_array(model, charp, NULL, 0444);
 147 MODULE_PARM_DESC(model, "Use the given board model.");
 148 module_param_array(position_fix, int, NULL, 0444);
 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 150                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 151 module_param_array(bdl_pos_adj, int, NULL, 0644);
 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 153 module_param_array(probe_mask, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 155 module_param_array(probe_only, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 157 module_param_array(jackpoll_ms, int, NULL, 0444);
 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 159 module_param(single_cmd, bool, 0444);
 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 161                  "(for debugging only).");
 162 module_param(enable_msi, bint, 0444);
 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 165 module_param_array(patch, charp, NULL, 0444);
 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 167 #endif
 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 169 module_param_array(beep_mode, bool, NULL, 0444);
 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 171                             "(0=off, 1=on) (default=1).");
 172 #endif
 173
 174 #ifdef CONFIG_PM
 175 static int param_set_xint(const char *val, const struct kernel_param *kp);
 176 static const struct kernel_param_ops param_ops_xint = {
 177         .set = param_set_xint,
 178         .get = param_get_int,
 179 };
 180 #define param_check_xint param_check_int
 181
 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 183 module_param(power_save, xint, 0644);
 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 185                  "(in second, 0 = disable).");
 186
 187 /* reset the HD-audio controller in power save mode.
 188  * this may give more power-saving, but will take longer time to
 189  * wake up.
 190  */
 191 static bool power_save_controller = 1;
 192 module_param(power_save_controller, bool, 0644);
 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 194 #else
 195 #define power_save      0
 196 #endif /* CONFIG_PM */
 197
 198 static int align_buffer_size = -1;
 199 module_param(align_buffer_size, bint, 0644);
 200 MODULE_PARM_DESC(align_buffer_size,
 201                 "Force buffer and period sizes to be multiple of 128 bytes.");
 202
 203 #ifdef CONFIG_X86
 204 static int hda_snoop = -1;
 205 module_param_named(snoop, hda_snoop, bint, 0444);
 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 207 #else
 208 #define hda_snoop               true
 209 #endif
 210
 211
 212 MODULE_LICENSE("GPL");
 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 214                          "{Intel, ICH6M},"
 215                          "{Intel, ICH7},"
 216                          "{Intel, ESB2},"
 217                          "{Intel, ICH8},"
 218                          "{Intel, ICH9},"
 219                          "{Intel, ICH10},"
 220                          "{Intel, PCH},"
 221                          "{Intel, CPT},"
 222                          "{Intel, PPT},"
 223                          "{Intel, LPT},"
 224                          "{Intel, LPT_LP},"
 225                          "{Intel, WPT_LP},"
 226                          "{Intel, SPT},"
 227                          "{Intel, SPT_LP},"
 228                          "{Intel, HPT},"
 229                          "{Intel, PBG},"
 230                          "{Intel, SCH},"
 231                          "{ATI, SB450},"
 232                          "{ATI, SB600},"
 233                          "{ATI, RS600},"
 234                          "{ATI, RS690},"
 235                          "{ATI, RS780},"
 236                          "{ATI, R600},"
 237                          "{ATI, RV630},"
 238                          "{ATI, RV610},"
 239                          "{ATI, RV670},"
 240                          "{ATI, RV635},"
 241                          "{ATI, RV620},"
 242                          "{ATI, RV770},"
 243                          "{VIA, VT8251},"
 244                          "{VIA, VT8237A},"
 245                          "{SiS, SIS966},"
 246                          "{ULI, M5461}}");
 247 MODULE_DESCRIPTION("Intel HDA driver");
 248
 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 251 #define SUPPORT_VGA_SWITCHEROO
 252 #endif
 253 #endif
 254
 255
 256 /*
 257  */
 258
 259 /* driver types */
 260 enum {
 261         AZX_DRIVER_ICH,
 262         AZX_DRIVER_PCH,
 263         AZX_DRIVER_SCH,
 264         AZX_DRIVER_HDMI,
 265         AZX_DRIVER_ATI,
 266         AZX_DRIVER_ATIHDMI,
 267         AZX_DRIVER_ATIHDMI_NS,
 268         AZX_DRIVER_VIA,
 269         AZX_DRIVER_SIS,
 270         AZX_DRIVER_ULI,
 271         AZX_DRIVER_NVIDIA,
 272         AZX_DRIVER_TERA,
 273         AZX_DRIVER_CTX,
 274         AZX_DRIVER_CTHDA,
 275         AZX_DRIVER_CMEDIA,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 287
 288 /* quirks for Intel PCH */
 289 #define AZX_DCAPS_INTEL_PCH_NOPM \
 290         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 292
 293 #define AZX_DCAPS_INTEL_PCH \
 294         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 295
 296 #define AZX_DCAPS_INTEL_HASWELL \
 297         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 302 #define AZX_DCAPS_INTEL_BROADWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 #define AZX_DCAPS_INTEL_BAYTRAIL \
 308         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 309
 310 #define AZX_DCAPS_INTEL_BRASWELL \
 311         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 312
 313 #define AZX_DCAPS_INTEL_SKYLAKE \
 314         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 315          AZX_DCAPS_I915_POWERWELL)
 316
 317 #define AZX_DCAPS_INTEL_BROXTON \
 318         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 319          AZX_DCAPS_I915_POWERWELL)
 320
 321 /* quirks for ATI SB / AMD Hudson */
 322 #define AZX_DCAPS_PRESET_ATI_SB \
 323         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 324          AZX_DCAPS_SNOOP_TYPE(ATI))
 325
 326 /* quirks for ATI/AMD HDMI */
 327 #define AZX_DCAPS_PRESET_ATI_HDMI \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 329          AZX_DCAPS_NO_MSI64)
 330
 331 /* quirks for ATI HDMI with snoop off */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 333         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 334
 335 /* quirks for Nvidia */
 336 #define AZX_DCAPS_PRESET_NVIDIA \
 337         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 338          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 339          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 340
 341 #define AZX_DCAPS_PRESET_CTHDA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_NO_64BIT |\
 344          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 345
 346 /*
 347  * vga_switcheroo support
 348  */
 349 #ifdef SUPPORT_VGA_SWITCHEROO
 350 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 351 #else
 352 #define use_vga_switcheroo(chip)        0
 353 #endif
 354
 355 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 356                                         ((pci)->device == 0x0c0c) || \
 357                                         ((pci)->device == 0x0d0c) || \
 358                                         ((pci)->device == 0x160c))
 359
 360 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 361 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 362 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 363 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
 364
 365 static char *driver_short_names[] = {
 366         [AZX_DRIVER_ICH] = "HDA Intel",
 367         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 368         [AZX_DRIVER_SCH] = "HDA Intel MID",
 369         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 370         [AZX_DRIVER_ATI] = "HDA ATI SB",
 371         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 372         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 373         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 374         [AZX_DRIVER_SIS] = "HDA SIS966",
 375         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 376         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 377         [AZX_DRIVER_TERA] = "HDA Teradici",
 378         [AZX_DRIVER_CTX] = "HDA Creative",
 379         [AZX_DRIVER_CTHDA] = "HDA Creative",
 380         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 381         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 382 };
 383
 384 #ifdef CONFIG_X86
 385 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 386 {
 387         int pages;
 388
 389         if (azx_snoop(chip))
 390                 return;
 391         if (!dmab || !dmab->area || !dmab->bytes)
 392                 return;
 393
 394 #ifdef CONFIG_SND_DMA_SGBUF
 395         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 396                 struct snd_sg_buf *sgbuf = dmab->private_data;
 397                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 398                         return; /* deal with only CORB/RIRB buffers */
 399                 if (on)
 400                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 401                 else
 402                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 403                 return;
 404         }
 405 #endif
 406
 407         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 408         if (on)
 409                 set_memory_wc((unsigned long)dmab->area, pages);
 410         else
 411                 set_memory_wb((unsigned long)dmab->area, pages);
 412 }
 413
 414 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 415                                  bool on)
 416 {
 417         __mark_pages_wc(chip, buf, on);
 418 }
 419 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 420                                    struct snd_pcm_substream *substream, bool on)
 421 {
 422         if (azx_dev->wc_marked != on) {
 423                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 424                 azx_dev->wc_marked = on;
 425         }
 426 }
 427 #else
 428 /* NOP for other archs */
 429 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 430                                  bool on)
 431 {
 432 }
 433 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 434                                    struct snd_pcm_substream *substream, bool on)
 435 {
 436 }
 437 #endif
 438
 439 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 440
 441 /*
 442  * initialize the PCI registers
 443  */
 444 /* update bits in a PCI register byte */
 445 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 446                             unsigned char mask, unsigned char val)
 447 {
 448         unsigned char data;
 449
 450         pci_read_config_byte(pci, reg, &data);
 451         data &= ~mask;
 452         data |= (val & mask);
 453         pci_write_config_byte(pci, reg, data);
 454 }
 455
 456 static void azx_init_pci(struct azx *chip)
 457 {
 458         int snoop_type = azx_get_snoop_type(chip);
 459
 460         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 461          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 462          * Ensuring these bits are 0 clears playback static on some HD Audio
 463          * codecs.
 464          * The PCI register TCSEL is defined in the Intel manuals.
 465          */
 466         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 467                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 468                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 469         }
 470
 471         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 472          * we need to enable snoop.
 473          */
 474         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 475                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 476                         azx_snoop(chip));
 477                 update_pci_byte(chip->pci,
 478                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 479                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 480         }
 481
 482         /* For NVIDIA HDA, enable snoop */
 483         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 484                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 485                         azx_snoop(chip));
 486                 update_pci_byte(chip->pci,
 487                                 NVIDIA_HDA_TRANSREG_ADDR,
 488                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 489                 update_pci_byte(chip->pci,
 490                                 NVIDIA_HDA_ISTRM_COH,
 491                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 492                 update_pci_byte(chip->pci,
 493                                 NVIDIA_HDA_OSTRM_COH,
 494                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 495         }
 496
 497         /* Enable SCH/PCH snoop if needed */
 498         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 499                 unsigned short snoop;
 500                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 501                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 502                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 503                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 504                         if (!azx_snoop(chip))
 505                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 506                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 507                         pci_read_config_word(chip->pci,
 508                                 INTEL_SCH_HDA_DEVC, &snoop);
 509                 }
 510                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 511                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 512                         "Disabled" : "Enabled");
 513         }
 514 }
 515
 516 /*
 517  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 518  * and makes an audio stream sensitive to system latencies when
 519  * 24/32 bits are playing.
 520  * Adjusting threshold of DMA fifo to force the DMA request
 521  * sooner to improve latency tolerance at the expense of power.
 522  */
 523 static void bxt_reduce_dma_latency(struct azx *chip)
 524 {
 525         u32 val;
 526
 527         val = azx_readl(chip, SKL_EM4L);
 528         val &= (0x3 << 20);
 529         azx_writel(chip, SKL_EM4L, val);
 530 }
 531
 532 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 533 {
 534         struct hdac_bus *bus = azx_bus(chip);
 535         struct pci_dev *pci = chip->pci;
 536         u32 val;
 537
 538         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 539                 snd_hdac_set_codec_wakeup(bus, true);
 540         if (IS_SKL_PLUS(pci)) {
 541                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 542                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 543                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 544         }
 545         azx_init_chip(chip, full_reset);
 546         if (IS_SKL_PLUS(pci)) {
 547                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 548                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 549                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 550         }
 551         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 552                 snd_hdac_set_codec_wakeup(bus, false);
 553
 554         /* reduce dma latency to avoid noise */
 555         if (IS_BXT(pci))
 556                 bxt_reduce_dma_latency(chip);
 557 }
 558
 559 /* calculate runtime delay from LPIB */
 560 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 561                                    unsigned int pos)
 562 {
 563         struct snd_pcm_substream *substream = azx_dev->core.substream;
 564         int stream = substream->stream;
 565         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 566         int delay;
 567
 568         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 569                 delay = pos - lpib_pos;
 570         else
 571                 delay = lpib_pos - pos;
 572         if (delay < 0) {
 573                 if (delay >= azx_dev->core.delay_negative_threshold)
 574                         delay = 0;
 575                 else
 576                         delay += azx_dev->core.bufsize;
 577         }
 578
 579         if (delay >= azx_dev->core.period_bytes) {
 580                 dev_info(chip->card->dev,
 581                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 582                          delay, azx_dev->core.period_bytes);
 583                 delay = 0;
 584                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 585                 chip->get_delay[stream] = NULL;
 586         }
 587
 588         return bytes_to_frames(substream->runtime, delay);
 589 }
 590
 591 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 592
 593 /* called from IRQ */
 594 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 595 {
 596         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 597         int ok;
 598
 599         ok = azx_position_ok(chip, azx_dev);
 600         if (ok == 1) {
 601                 azx_dev->irq_pending = 0;
 602                 return ok;
 603         } else if (ok == 0) {
 604                 /* bogus IRQ, process it later */
 605                 azx_dev->irq_pending = 1;
 606                 schedule_work(&hda->irq_pending_work);
 607         }
 608         return 0;
 609 }
 610
 611 /* Enable/disable i915 display power for the link */
 612 static int azx_intel_link_power(struct azx *chip, bool enable)
 613 {
 614         struct hdac_bus *bus = azx_bus(chip);
 615
 616         return snd_hdac_display_power(bus, enable);
 617 }
 618
 619 /*
 620  * Check whether the current DMA position is acceptable for updating
 621  * periods.  Returns non-zero if it's OK.
 622  *
 623  * Many HD-audio controllers appear pretty inaccurate about
 624  * the update-IRQ timing.  The IRQ is issued before actually the
 625  * data is processed.  So, we need to process it afterwords in a
 626  * workqueue.
 627  */
 628 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 629 {
 630         struct snd_pcm_substream *substream = azx_dev->core.substream;
 631         int stream = substream->stream;
 632         u32 wallclk;
 633         unsigned int pos;
 634
 635         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 636         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 637                 return -1;      /* bogus (too early) interrupt */
 638
 639         if (chip->get_position[stream])
 640                 pos = chip->get_position[stream](chip, azx_dev);
 641         else { /* use the position buffer as default */
 642                 pos = azx_get_pos_posbuf(chip, azx_dev);
 643                 if (!pos || pos == (u32)-1) {
 644                         dev_info(chip->card->dev,
 645                                  "Invalid position buffer, using LPIB read method instead.\n");
 646                         chip->get_position[stream] = azx_get_pos_lpib;
 647                         if (chip->get_position[0] == azx_get_pos_lpib &&
 648                             chip->get_position[1] == azx_get_pos_lpib)
 649                                 azx_bus(chip)->use_posbuf = false;
 650                         pos = azx_get_pos_lpib(chip, azx_dev);
 651                         chip->get_delay[stream] = NULL;
 652                 } else {
 653                         chip->get_position[stream] = azx_get_pos_posbuf;
 654                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 655                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 656                 }
 657         }
 658
 659         if (pos >= azx_dev->core.bufsize)
 660                 pos = 0;
 661
 662         if (WARN_ONCE(!azx_dev->core.period_bytes,
 663                       "hda-intel: zero azx_dev->period_bytes"))
 664                 return -1; /* this shouldn't happen! */
 665         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 666             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 667                 /* NG - it's below the first next period boundary */
 668                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 669         azx_dev->core.start_wallclk += wallclk;
 670         return 1; /* OK, it's fine */
 671 }
 672
 673 /*
 674  * The work for pending PCM period updates.
 675  */
 676 static void azx_irq_pending_work(struct work_struct *work)
 677 {
 678         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 679         struct azx *chip = &hda->chip;
 680         struct hdac_bus *bus = azx_bus(chip);
 681         struct hdac_stream *s;
 682         int pending, ok;
 683
 684         if (!hda->irq_pending_warned) {
 685                 dev_info(chip->card->dev,
 686                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 687                          chip->card->number);
 688                 hda->irq_pending_warned = 1;
 689         }
 690
 691         for (;;) {
 692                 pending = 0;
 693                 spin_lock_irq(&bus->reg_lock);
 694                 list_for_each_entry(s, &bus->stream_list, list) {
 695                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 696                         if (!azx_dev->irq_pending ||
 697                             !s->substream ||
 698                             !s->running)
 699                                 continue;
 700                         ok = azx_position_ok(chip, azx_dev);
 701                         if (ok > 0) {
 702                                 azx_dev->irq_pending = 0;
 703                                 spin_unlock(&bus->reg_lock);
 704                                 snd_pcm_period_elapsed(s->substream);
 705                                 spin_lock(&bus->reg_lock);
 706                         } else if (ok < 0) {
 707                                 pending = 0;    /* too early */
 708                         } else
 709                                 pending++;
 710                 }
 711                 spin_unlock_irq(&bus->reg_lock);
 712                 if (!pending)
 713                         return;
 714                 msleep(1);
 715         }
 716 }
 717
 718 /* clear irq_pending flags and assure no on-going workq */
 719 static void azx_clear_irq_pending(struct azx *chip)
 720 {
 721         struct hdac_bus *bus = azx_bus(chip);
 722         struct hdac_stream *s;
 723
 724         spin_lock_irq(&bus->reg_lock);
 725         list_for_each_entry(s, &bus->stream_list, list) {
 726                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 727                 azx_dev->irq_pending = 0;
 728         }
 729         spin_unlock_irq(&bus->reg_lock);
 730 }
 731
 732 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 733 {
 734         struct hdac_bus *bus = azx_bus(chip);
 735
 736         if (request_irq(chip->pci->irq, azx_interrupt,
 737                         chip->msi ? 0 : IRQF_SHARED,
 738                         KBUILD_MODNAME, chip)) {
 739                 dev_err(chip->card->dev,
 740                         "unable to grab IRQ %d, disabling device\n",
 741                         chip->pci->irq);
 742                 if (do_disconnect)
 743                         snd_card_disconnect(chip->card);
 744                 return -1;
 745         }
 746         bus->irq = chip->pci->irq;
 747         pci_intx(chip->pci, !chip->msi);
 748         return 0;
 749 }
 750
 751 /* get the current DMA position with correction on VIA chips */
 752 static unsigned int azx_via_get_position(struct azx *chip,
 753                                          struct azx_dev *azx_dev)
 754 {
 755         unsigned int link_pos, mini_pos, bound_pos;
 756         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 757         unsigned int fifo_size;
 758
 759         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 760         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 761                 /* Playback, no problem using link position */
 762                 return link_pos;
 763         }
 764
 765         /* Capture */
 766         /* For new chipset,
 767          * use mod to get the DMA position just like old chipset
 768          */
 769         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 770         mod_dma_pos %= azx_dev->core.period_bytes;
 771
 772         /* azx_dev->fifo_size can't get FIFO size of in stream.
 773          * Get from base address + offset.
 774          */
 775         fifo_size = readw(azx_bus(chip)->remap_addr +
 776                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 777
 778         if (azx_dev->insufficient) {
 779                 /* Link position never gather than FIFO size */
 780                 if (link_pos <= fifo_size)
 781                         return 0;
 782
 783                 azx_dev->insufficient = 0;
 784         }
 785
 786         if (link_pos <= fifo_size)
 787                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 788         else
 789                 mini_pos = link_pos - fifo_size;
 790
 791         /* Find nearest previous boudary */
 792         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 793         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 794         if (mod_link_pos >= fifo_size)
 795                 bound_pos = link_pos - mod_link_pos;
 796         else if (mod_dma_pos >= mod_mini_pos)
 797                 bound_pos = mini_pos - mod_mini_pos;
 798         else {
 799                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 800                 if (bound_pos >= azx_dev->core.bufsize)
 801                         bound_pos = 0;
 802         }
 803
 804         /* Calculate real DMA position we want */
 805         return bound_pos + mod_dma_pos;
 806 }
 807
 808 #ifdef CONFIG_PM
 809 static DEFINE_MUTEX(card_list_lock);
 810 static LIST_HEAD(card_list);
 811
 812 static void azx_add_card_list(struct azx *chip)
 813 {
 814         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 815         mutex_lock(&card_list_lock);
 816         list_add(&hda->list, &card_list);
 817         mutex_unlock(&card_list_lock);
 818 }
 819
 820 static void azx_del_card_list(struct azx *chip)
 821 {
 822         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 823         mutex_lock(&card_list_lock);
 824         list_del_init(&hda->list);
 825         mutex_unlock(&card_list_lock);
 826 }
 827
 828 /* trigger power-save check at writing parameter */
 829 static int param_set_xint(const char *val, const struct kernel_param *kp)
 830 {
 831         struct hda_intel *hda;
 832         struct azx *chip;
 833         int prev = power_save;
 834         int ret = param_set_int(val, kp);
 835
 836         if (ret || prev == power_save)
 837                 return ret;
 838
 839         mutex_lock(&card_list_lock);
 840         list_for_each_entry(hda, &card_list, list) {
 841                 chip = &hda->chip;
 842                 if (!hda->probe_continued || chip->disabled)
 843                         continue;
 844                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 845         }
 846         mutex_unlock(&card_list_lock);
 847         return 0;
 848 }
 849 #else
 850 #define azx_add_card_list(chip) /* NOP */
 851 #define azx_del_card_list(chip) /* NOP */
 852 #endif /* CONFIG_PM */
 853
 854 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
 855  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
 856  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
 857  * BCLK = CDCLK * M / N
 858  * The values will be lost when the display power well is disabled and need to
 859  * be restored to avoid abnormal playback speed.
 860  */
 861 static void haswell_set_bclk(struct hda_intel *hda)
 862 {
 863         struct azx *chip = &hda->chip;
 864         int cdclk_freq;
 865         unsigned int bclk_m, bclk_n;
 866
 867         if (!hda->need_i915_power)
 868                 return;
 869
 870         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
 871         switch (cdclk_freq) {
 872         case 337500:
 873                 bclk_m = 16;
 874                 bclk_n = 225;
 875                 break;
 876
 877         case 450000:
 878         default: /* default CDCLK 450MHz */
 879                 bclk_m = 4;
 880                 bclk_n = 75;
 881                 break;
 882
 883         case 540000:
 884                 bclk_m = 4;
 885                 bclk_n = 90;
 886                 break;
 887
 888         case 675000:
 889                 bclk_m = 8;
 890                 bclk_n = 225;
 891                 break;
 892         }
 893
 894         azx_writew(chip, HSW_EM4, bclk_m);
 895         azx_writew(chip, HSW_EM5, bclk_n);
 896 }
 897
 898 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 899 /*
 900  * power management
 901  */
 902 static int azx_suspend(struct device *dev)
 903 {
 904         struct snd_card *card = dev_get_drvdata(dev);
 905         struct azx *chip;
 906         struct hda_intel *hda;
 907         struct hdac_bus *bus;
 908
 909         if (!card)
 910                 return 0;
 911
 912         chip = card->private_data;
 913         hda = container_of(chip, struct hda_intel, chip);
 914         if (chip->disabled || hda->init_failed || !chip->running)
 915                 return 0;
 916
 917         bus = azx_bus(chip);
 918         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 919         azx_clear_irq_pending(chip);
 920         azx_stop_chip(chip);
 921         azx_enter_link_reset(chip);
 922         if (bus->irq >= 0) {
 923                 free_irq(bus->irq, chip);
 924                 bus->irq = -1;
 925         }
 926
 927         if (chip->msi)
 928                 pci_disable_msi(chip->pci);
 929         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 930                 && hda->need_i915_power)
 931                 snd_hdac_display_power(bus, false);
 932
 933         trace_azx_suspend(chip);
 934         return 0;
 935 }
 936
 937 static int azx_resume(struct device *dev)
 938 {
 939         struct pci_dev *pci = to_pci_dev(dev);
 940         struct snd_card *card = dev_get_drvdata(dev);
 941         struct azx *chip;
 942         struct hda_intel *hda;
 943
 944         if (!card)
 945                 return 0;
 946
 947         chip = card->private_data;
 948         hda = container_of(chip, struct hda_intel, chip);
 949         if (chip->disabled || hda->init_failed || !chip->running)
 950                 return 0;
 951
 952         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 953                 && hda->need_i915_power) {
 954                 snd_hdac_display_power(azx_bus(chip), true);
 955                 haswell_set_bclk(hda);
 956         }
 957         if (chip->msi)
 958                 if (pci_enable_msi(pci) < 0)
 959                         chip->msi = 0;
 960         if (azx_acquire_irq(chip, 1) < 0)
 961                 return -EIO;
 962         azx_init_pci(chip);
 963
 964         hda_intel_init_chip(chip, true);
 965
 966         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 967
 968         trace_azx_resume(chip);
 969         return 0;
 970 }
 971 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 972
 973 #ifdef CONFIG_PM_SLEEP
 974 /* put codec down to D3 at hibernation for Intel SKL+;
 975  * otherwise BIOS may still access the codec and screw up the driver
 976  */
 977 static int azx_freeze_noirq(struct device *dev)
 978 {
 979         struct pci_dev *pci = to_pci_dev(dev);
 980
 981         if (IS_SKL_PLUS(pci))
 982                 pci_set_power_state(pci, PCI_D3hot);
 983
 984         return 0;
 985 }
 986
 987 static int azx_thaw_noirq(struct device *dev)
 988 {
 989         struct pci_dev *pci = to_pci_dev(dev);
 990
 991         if (IS_SKL_PLUS(pci))
 992                 pci_set_power_state(pci, PCI_D0);
 993
 994         return 0;
 995 }
 996 #endif /* CONFIG_PM_SLEEP */
 997
 998 #ifdef CONFIG_PM
 999 static int azx_runtime_suspend(struct device *dev)
1000 {
1001         struct snd_card *card = dev_get_drvdata(dev);
1002         struct azx *chip;
1003         struct hda_intel *hda;
1004
1005         if (!card)
1006                 return 0;
1007
1008         chip = card->private_data;
1009         hda = container_of(chip, struct hda_intel, chip);
1010         if (chip->disabled || hda->init_failed)
1011                 return 0;
1012
1013         if (!azx_has_pm_runtime(chip))
1014                 return 0;
1015
1016         /* enable controller wake up event */
1017         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1018                   STATESTS_INT_MASK);
1019
1020         azx_stop_chip(chip);
1021         azx_enter_link_reset(chip);
1022         azx_clear_irq_pending(chip);
1023         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1024                 && hda->need_i915_power)
1025                 snd_hdac_display_power(azx_bus(chip), false);
1026
1027         trace_azx_runtime_suspend(chip);
1028         return 0;
1029 }
1030
1031 static int azx_runtime_resume(struct device *dev)
1032 {
1033         struct snd_card *card = dev_get_drvdata(dev);
1034         struct azx *chip;
1035         struct hda_intel *hda;
1036         struct hdac_bus *bus;
1037         struct hda_codec *codec;
1038         int status;
1039
1040         if (!card)
1041                 return 0;
1042
1043         chip = card->private_data;
1044         hda = container_of(chip, struct hda_intel, chip);
1045         if (chip->disabled || hda->init_failed)
1046                 return 0;
1047
1048         if (!azx_has_pm_runtime(chip))
1049                 return 0;
1050
1051         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1052                 bus = azx_bus(chip);
1053                 if (hda->need_i915_power) {
1054                         snd_hdac_display_power(bus, true);
1055                         haswell_set_bclk(hda);
1056                 } else {
1057                         /* toggle codec wakeup bit for STATESTS read */
1058                         snd_hdac_set_codec_wakeup(bus, true);
1059                         snd_hdac_set_codec_wakeup(bus, false);
1060                 }
1061         }
1062
1063         /* Read STATESTS before controller reset */
1064         status = azx_readw(chip, STATESTS);
1065
1066         azx_init_pci(chip);
1067         hda_intel_init_chip(chip, true);
1068
1069         if (status) {
1070                 list_for_each_codec(codec, &chip->bus)
1071                         if (status & (1 << codec->addr))
1072                                 schedule_delayed_work(&codec->jackpoll_work,
1073                                                       codec->jackpoll_interval);
1074         }
1075
1076         /* disable controller Wake Up event*/
1077         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1078                         ~STATESTS_INT_MASK);
1079
1080         trace_azx_runtime_resume(chip);
1081         return 0;
1082 }
1083
1084 static int azx_runtime_idle(struct device *dev)
1085 {
1086         struct snd_card *card = dev_get_drvdata(dev);
1087         struct azx *chip;
1088         struct hda_intel *hda;
1089
1090         if (!card)
1091                 return 0;
1092
1093         chip = card->private_data;
1094         hda = container_of(chip, struct hda_intel, chip);
1095         if (chip->disabled || hda->init_failed)
1096                 return 0;
1097
1098         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1099             azx_bus(chip)->codec_powered || !chip->running)
1100                 return -EBUSY;
1101
1102         return 0;
1103 }
1104
1105 static const struct dev_pm_ops azx_pm = {
1106         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1107 #ifdef CONFIG_PM_SLEEP
1108         .freeze_noirq = azx_freeze_noirq,
1109         .thaw_noirq = azx_thaw_noirq,
1110 #endif
1111         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1112 };
1113
1114 #define AZX_PM_OPS      &azx_pm
1115 #else
1116 #define AZX_PM_OPS      NULL
1117 #endif /* CONFIG_PM */
1118
1119
1120 static int azx_probe_continue(struct azx *chip);
1121
1122 #ifdef SUPPORT_VGA_SWITCHEROO
1123 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1124
1125 static void azx_vs_set_state(struct pci_dev *pci,
1126                              enum vga_switcheroo_state state)
1127 {
1128         struct snd_card *card = pci_get_drvdata(pci);
1129         struct azx *chip = card->private_data;
1130         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1131         bool disabled;
1132
1133         wait_for_completion(&hda->probe_wait);
1134         if (hda->init_failed)
1135                 return;
1136
1137         disabled = (state == VGA_SWITCHEROO_OFF);
1138         if (chip->disabled == disabled)
1139                 return;
1140
1141         if (!hda->probe_continued) {
1142                 chip->disabled = disabled;
1143                 if (!disabled) {
1144                         dev_info(chip->card->dev,
1145                                  "Start delayed initialization\n");
1146                         if (azx_probe_continue(chip) < 0) {
1147                                 dev_err(chip->card->dev, "initialization error\n");
1148                                 hda->init_failed = true;
1149                         }
1150                 }
1151         } else {
1152                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1153                          disabled ? "Disabling" : "Enabling");
1154                 if (disabled) {
1155                         pm_runtime_put_sync_suspend(card->dev);
1156                         azx_suspend(card->dev);
1157                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1158                          * however we have no ACPI handle, so pci/acpi can't put us there,
1159                          * put ourselves there */
1160                         pci->current_state = PCI_D3cold;
1161                         chip->disabled = true;
1162                         if (snd_hda_lock_devices(&chip->bus))
1163                                 dev_warn(chip->card->dev,
1164                                          "Cannot lock devices!\n");
1165                 } else {
1166                         snd_hda_unlock_devices(&chip->bus);
1167                         pm_runtime_get_noresume(card->dev);
1168                         chip->disabled = false;
1169                         azx_resume(card->dev);
1170                 }
1171         }
1172 }
1173
1174 static bool azx_vs_can_switch(struct pci_dev *pci)
1175 {
1176         struct snd_card *card = pci_get_drvdata(pci);
1177         struct azx *chip = card->private_data;
1178         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1179
1180         wait_for_completion(&hda->probe_wait);
1181         if (hda->init_failed)
1182                 return false;
1183         if (chip->disabled || !hda->probe_continued)
1184                 return true;
1185         if (snd_hda_lock_devices(&chip->bus))
1186                 return false;
1187         snd_hda_unlock_devices(&chip->bus);
1188         return true;
1189 }
1190
1191 static void init_vga_switcheroo(struct azx *chip)
1192 {
1193         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1194         struct pci_dev *p = get_bound_vga(chip->pci);
1195         if (p) {
1196                 dev_info(chip->card->dev,
1197                          "Handle vga_switcheroo audio client\n");
1198                 hda->use_vga_switcheroo = 1;
1199                 pci_dev_put(p);
1200         }
1201 }
1202
1203 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1204         .set_gpu_state = azx_vs_set_state,
1205         .can_switch = azx_vs_can_switch,
1206 };
1207
1208 static int register_vga_switcheroo(struct azx *chip)
1209 {
1210         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1211         int err;
1212
1213         if (!hda->use_vga_switcheroo)
1214                 return 0;
1215         /* FIXME: currently only handling DIS controller
1216          * is there any machine with two switchable HDMI audio controllers?
1217          */
1218         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1219                                                    VGA_SWITCHEROO_DIS);
1220         if (err < 0)
1221                 return err;
1222         hda->vga_switcheroo_registered = 1;
1223
1224         /* register as an optimus hdmi audio power domain */
1225         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1226                                                          &hda->hdmi_pm_domain);
1227         return 0;
1228 }
1229 #else
1230 #define init_vga_switcheroo(chip)               /* NOP */
1231 #define register_vga_switcheroo(chip)           0
1232 #define check_hdmi_disabled(pci)        false
1233 #endif /* SUPPORT_VGA_SWITCHER */
1234
1235 /*
1236  * destructor
1237  */
1238 static int azx_free(struct azx *chip)
1239 {
1240         struct pci_dev *pci = chip->pci;
1241         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242         struct hdac_bus *bus = azx_bus(chip);
1243
1244         if (azx_has_pm_runtime(chip) && chip->running)
1245                 pm_runtime_get_noresume(&pci->dev);
1246
1247         azx_del_card_list(chip);
1248
1249         hda->init_failed = 1; /* to be sure */
1250         complete_all(&hda->probe_wait);
1251
1252         if (use_vga_switcheroo(hda)) {
1253                 if (chip->disabled && hda->probe_continued)
1254                         snd_hda_unlock_devices(&chip->bus);
1255                 if (hda->vga_switcheroo_registered)
1256                         vga_switcheroo_unregister_client(chip->pci);
1257         }
1258
1259         if (bus->chip_init) {
1260                 azx_clear_irq_pending(chip);
1261                 azx_stop_all_streams(chip);
1262                 azx_stop_chip(chip);
1263         }
1264
1265         if (bus->irq >= 0)
1266                 free_irq(bus->irq, (void*)chip);
1267         if (chip->msi)
1268                 pci_disable_msi(chip->pci);
1269         iounmap(bus->remap_addr);
1270
1271         azx_free_stream_pages(chip);
1272         azx_free_streams(chip);
1273         snd_hdac_bus_exit(bus);
1274
1275         if (chip->region_requested)
1276                 pci_release_regions(chip->pci);
1277
1278         pci_disable_device(chip->pci);
1279 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1280         release_firmware(chip->fw);
1281 #endif
1282
1283         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1284                 if (hda->need_i915_power)
1285                         snd_hdac_display_power(bus, false);
1286                 snd_hdac_i915_exit(bus);
1287         }
1288         kfree(hda);
1289
1290         return 0;
1291 }
1292
1293 static int azx_dev_disconnect(struct snd_device *device)
1294 {
1295         struct azx *chip = device->device_data;
1296
1297         chip->bus.shutdown = 1;
1298         return 0;
1299 }
1300
1301 static int azx_dev_free(struct snd_device *device)
1302 {
1303         return azx_free(device->device_data);
1304 }
1305
1306 #ifdef SUPPORT_VGA_SWITCHEROO
1307 /*
1308  * Check of disabled HDMI controller by vga_switcheroo
1309  */
1310 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1311 {
1312         struct pci_dev *p;
1313
1314         /* check only discrete GPU */
1315         switch (pci->vendor) {
1316         case PCI_VENDOR_ID_ATI:
1317         case PCI_VENDOR_ID_AMD:
1318         case PCI_VENDOR_ID_NVIDIA:
1319                 if (pci->devfn == 1) {
1320                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1321                                                         pci->bus->number, 0);
1322                         if (p) {
1323                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1324                                         return p;
1325                                 pci_dev_put(p);
1326                         }
1327                 }
1328                 break;
1329         }
1330         return NULL;
1331 }
1332
1333 static bool check_hdmi_disabled(struct pci_dev *pci)
1334 {
1335         bool vga_inactive = false;
1336         struct pci_dev *p = get_bound_vga(pci);
1337
1338         if (p) {
1339                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1340                         vga_inactive = true;
1341                 pci_dev_put(p);
1342         }
1343         return vga_inactive;
1344 }
1345 #endif /* SUPPORT_VGA_SWITCHEROO */
1346
1347 /*
1348  * white/black-listing for position_fix
1349  */
1350 static struct snd_pci_quirk position_fix_list[] = {
1351         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1352         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1353         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1354         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1355         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1356         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1357         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1358         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1359         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1360         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1361         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1362         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1363         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1364         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1365         {}
1366 };
1367
1368 static int check_position_fix(struct azx *chip, int fix)
1369 {
1370         const struct snd_pci_quirk *q;
1371
1372         switch (fix) {
1373         case POS_FIX_AUTO:
1374         case POS_FIX_LPIB:
1375         case POS_FIX_POSBUF:
1376         case POS_FIX_VIACOMBO:
1377         case POS_FIX_COMBO:
1378                 return fix;
1379         }
1380
1381         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1382         if (q) {
1383                 dev_info(chip->card->dev,
1384                          "position_fix set to %d for device %04x:%04x\n",
1385                          q->value, q->subvendor, q->subdevice);
1386                 return q->value;
1387         }
1388
1389         /* Check VIA/ATI HD Audio Controller exist */
1390         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1391                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1392                 return POS_FIX_VIACOMBO;
1393         }
1394         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1395                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1396                 return POS_FIX_LPIB;
1397         }
1398         return POS_FIX_AUTO;
1399 }
1400
1401 static void assign_position_fix(struct azx *chip, int fix)
1402 {
1403         static azx_get_pos_callback_t callbacks[] = {
1404                 [POS_FIX_AUTO] = NULL,
1405                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1406                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1407                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1408                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1409         };
1410
1411         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1412
1413         /* combo mode uses LPIB only for playback */
1414         if (fix == POS_FIX_COMBO)
1415                 chip->get_position[1] = NULL;
1416
1417         if (fix == POS_FIX_POSBUF &&
1418             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1419                 chip->get_delay[0] = chip->get_delay[1] =
1420                         azx_get_delay_from_lpib;
1421         }
1422
1423 }
1424
1425 /*
1426  * black-lists for probe_mask
1427  */
1428 static struct snd_pci_quirk probe_mask_list[] = {
1429         /* Thinkpad often breaks the controller communication when accessing
1430          * to the non-working (or non-existing) modem codec slot.
1431          */
1432         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1433         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1434         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1435         /* broken BIOS */
1436         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1437         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1438         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1439         /* forced codec slots */
1440         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1441         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1442         /* WinFast VP200 H (Teradici) user reported broken communication */
1443         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1444         {}
1445 };
1446
1447 #define AZX_FORCE_CODEC_MASK    0x100
1448
1449 static void check_probe_mask(struct azx *chip, int dev)
1450 {
1451         const struct snd_pci_quirk *q;
1452
1453         chip->codec_probe_mask = probe_mask[dev];
1454         if (chip->codec_probe_mask == -1) {
1455                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1456                 if (q) {
1457                         dev_info(chip->card->dev,
1458                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1459                                  q->value, q->subvendor, q->subdevice);
1460                         chip->codec_probe_mask = q->value;
1461                 }
1462         }
1463
1464         /* check forced option */
1465         if (chip->codec_probe_mask != -1 &&
1466             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1467                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1468                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1469                          (int)azx_bus(chip)->codec_mask);
1470         }
1471 }
1472
1473 /*
1474  * white/black-list for enable_msi
1475  */
1476 static struct snd_pci_quirk msi_black_list[] = {
1477         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1478         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1479         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1480         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1481         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1482         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1483         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1484         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1485         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1486         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1487         {}
1488 };
1489
1490 static void check_msi(struct azx *chip)
1491 {
1492         const struct snd_pci_quirk *q;
1493
1494         if (enable_msi >= 0) {
1495                 chip->msi = !!enable_msi;
1496                 return;
1497         }
1498         chip->msi = 1;  /* enable MSI as default */
1499         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1500         if (q) {
1501                 dev_info(chip->card->dev,
1502                          "msi for device %04x:%04x set to %d\n",
1503                          q->subvendor, q->subdevice, q->value);
1504                 chip->msi = q->value;
1505                 return;
1506         }
1507
1508         /* NVidia chipsets seem to cause troubles with MSI */
1509         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1510                 dev_info(chip->card->dev, "Disabling MSI\n");
1511                 chip->msi = 0;
1512         }
1513 }
1514
1515 /* check the snoop mode availability */
1516 static void azx_check_snoop_available(struct azx *chip)
1517 {
1518         int snoop = hda_snoop;
1519
1520         if (snoop >= 0) {
1521                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1522                          snoop ? "snoop" : "non-snoop");
1523                 chip->snoop = snoop;
1524                 return;
1525         }
1526
1527         snoop = true;
1528         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1529             chip->driver_type == AZX_DRIVER_VIA) {
1530                 /* force to non-snoop mode for a new VIA controller
1531                  * when BIOS is set
1532                  */
1533                 u8 val;
1534                 pci_read_config_byte(chip->pci, 0x42, &val);
1535                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1536                         snoop = false;
1537         }
1538
1539         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1540                 snoop = false;
1541
1542         chip->snoop = snoop;
1543         if (!snoop)
1544                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1545 }
1546
1547 static void azx_probe_work(struct work_struct *work)
1548 {
1549         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1550         azx_probe_continue(&hda->chip);
1551 }
1552
1553 /*
1554  * constructor
1555  */
1556 static const struct hdac_io_ops pci_hda_io_ops;
1557 static const struct hda_controller_ops pci_hda_ops;
1558
1559 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1560                       int dev, unsigned int driver_caps,
1561                       struct azx **rchip)
1562 {
1563         static struct snd_device_ops ops = {
1564                 .dev_disconnect = azx_dev_disconnect,
1565                 .dev_free = azx_dev_free,
1566         };
1567         struct hda_intel *hda;
1568         struct azx *chip;
1569         int err;
1570
1571         *rchip = NULL;
1572
1573         err = pci_enable_device(pci);
1574         if (err < 0)
1575                 return err;
1576
1577         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1578         if (!hda) {
1579                 pci_disable_device(pci);
1580                 return -ENOMEM;
1581         }
1582
1583         chip = &hda->chip;
1584         mutex_init(&chip->open_mutex);
1585         chip->card = card;
1586         chip->pci = pci;
1587         chip->ops = &pci_hda_ops;
1588         chip->driver_caps = driver_caps;
1589         chip->driver_type = driver_caps & 0xff;
1590         check_msi(chip);
1591         chip->dev_index = dev;
1592         chip->jackpoll_ms = jackpoll_ms;
1593         INIT_LIST_HEAD(&chip->pcm_list);
1594         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1595         INIT_LIST_HEAD(&hda->list);
1596         init_vga_switcheroo(chip);
1597         init_completion(&hda->probe_wait);
1598
1599         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1600
1601         check_probe_mask(chip, dev);
1602
1603         chip->single_cmd = single_cmd;
1604         azx_check_snoop_available(chip);
1605
1606         if (bdl_pos_adj[dev] < 0) {
1607                 switch (chip->driver_type) {
1608                 case AZX_DRIVER_ICH:
1609                 case AZX_DRIVER_PCH:
1610                         bdl_pos_adj[dev] = 1;
1611                         break;
1612                 default:
1613                         bdl_pos_adj[dev] = 32;
1614                         break;
1615                 }
1616         }
1617         chip->bdl_pos_adj = bdl_pos_adj;
1618
1619         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1620         if (err < 0) {
1621                 kfree(hda);
1622                 pci_disable_device(pci);
1623                 return err;
1624         }
1625
1626         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1627         if (err < 0) {
1628                 dev_err(card->dev, "Error creating device [card]!\n");
1629                 azx_free(chip);
1630                 return err;
1631         }
1632
1633         /* continue probing in work context as may trigger request module */
1634         INIT_WORK(&hda->probe_work, azx_probe_work);
1635
1636         *rchip = chip;
1637
1638         return 0;
1639 }
1640
1641 static int azx_first_init(struct azx *chip)
1642 {
1643         int dev = chip->dev_index;
1644         struct pci_dev *pci = chip->pci;
1645         struct snd_card *card = chip->card;
1646         struct hdac_bus *bus = azx_bus(chip);
1647         int err;
1648         unsigned short gcap;
1649         unsigned int dma_bits = 64;
1650
1651 #if BITS_PER_LONG != 64
1652         /* Fix up base address on ULI M5461 */
1653         if (chip->driver_type == AZX_DRIVER_ULI) {
1654                 u16 tmp3;
1655                 pci_read_config_word(pci, 0x40, &tmp3);
1656                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1657                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1658         }
1659 #endif
1660
1661         err = pci_request_regions(pci, "ICH HD audio");
1662         if (err < 0)
1663                 return err;
1664         chip->region_requested = 1;
1665
1666         bus->addr = pci_resource_start(pci, 0);
1667         bus->remap_addr = pci_ioremap_bar(pci, 0);
1668         if (bus->remap_addr == NULL) {
1669                 dev_err(card->dev, "ioremap error\n");
1670                 return -ENXIO;
1671         }
1672
1673         if (chip->msi) {
1674                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1675                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1676                         pci->no_64bit_msi = true;
1677                 }
1678                 if (pci_enable_msi(pci) < 0)
1679                         chip->msi = 0;
1680         }
1681
1682         if (azx_acquire_irq(chip, 0) < 0)
1683                 return -EBUSY;
1684
1685         pci_set_master(pci);
1686         synchronize_irq(bus->irq);
1687
1688         gcap = azx_readw(chip, GCAP);
1689         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1690
1691         /* AMD devices support 40 or 48bit DMA, take the safe one */
1692         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1693                 dma_bits = 40;
1694
1695         /* disable SB600 64bit support for safety */
1696         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1697                 struct pci_dev *p_smbus;
1698                 dma_bits = 40;
1699                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1700                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1701                                          NULL);
1702                 if (p_smbus) {
1703                         if (p_smbus->revision < 0x30)
1704                                 gcap &= ~AZX_GCAP_64OK;
1705                         pci_dev_put(p_smbus);
1706                 }
1707         }
1708
1709         /* disable 64bit DMA address on some devices */
1710         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1711                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1712                 gcap &= ~AZX_GCAP_64OK;
1713         }
1714
1715         /* disable buffer size rounding to 128-byte multiples if supported */
1716         if (align_buffer_size >= 0)
1717                 chip->align_buffer_size = !!align_buffer_size;
1718         else {
1719                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1720                         chip->align_buffer_size = 0;
1721                 else
1722                         chip->align_buffer_size = 1;
1723         }
1724
1725         /* allow 64bit DMA address if supported by H/W */
1726         if (!(gcap & AZX_GCAP_64OK))
1727                 dma_bits = 32;
1728         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1729                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1730         } else {
1731                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1732                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1733         }
1734
1735         /* read number of streams from GCAP register instead of using
1736          * hardcoded value
1737          */
1738         chip->capture_streams = (gcap >> 8) & 0x0f;
1739         chip->playback_streams = (gcap >> 12) & 0x0f;
1740         if (!chip->playback_streams && !chip->capture_streams) {
1741                 /* gcap didn't give any info, switching to old method */
1742
1743                 switch (chip->driver_type) {
1744                 case AZX_DRIVER_ULI:
1745                         chip->playback_streams = ULI_NUM_PLAYBACK;
1746                         chip->capture_streams = ULI_NUM_CAPTURE;
1747                         break;
1748                 case AZX_DRIVER_ATIHDMI:
1749                 case AZX_DRIVER_ATIHDMI_NS:
1750                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1751                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1752                         break;
1753                 case AZX_DRIVER_GENERIC:
1754                 default:
1755                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1756                         chip->capture_streams = ICH6_NUM_CAPTURE;
1757                         break;
1758                 }
1759         }
1760         chip->capture_index_offset = 0;
1761         chip->playback_index_offset = chip->capture_streams;
1762         chip->num_streams = chip->playback_streams + chip->capture_streams;
1763
1764         /* initialize streams */
1765         err = azx_init_streams(chip);
1766         if (err < 0)
1767                 return err;
1768
1769         err = azx_alloc_stream_pages(chip);
1770         if (err < 0)
1771                 return err;
1772
1773         /* initialize chip */
1774         azx_init_pci(chip);
1775
1776         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1777                 struct hda_intel *hda;
1778
1779                 hda = container_of(chip, struct hda_intel, chip);
1780                 haswell_set_bclk(hda);
1781         }
1782
1783         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1784
1785         /* codec detection */
1786         if (!azx_bus(chip)->codec_mask) {
1787                 dev_err(card->dev, "no codecs found!\n");
1788                 return -ENODEV;
1789         }
1790
1791         strcpy(card->driver, "HDA-Intel");
1792         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1793                 sizeof(card->shortname));
1794         snprintf(card->longname, sizeof(card->longname),
1795                  "%s at 0x%lx irq %i",
1796                  card->shortname, bus->addr, bus->irq);
1797
1798         return 0;
1799 }
1800
1801 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1802 /* callback from request_firmware_nowait() */
1803 static void azx_firmware_cb(const struct firmware *fw, void *context)
1804 {
1805         struct snd_card *card = context;
1806         struct azx *chip = card->private_data;
1807         struct pci_dev *pci = chip->pci;
1808
1809         if (!fw) {
1810                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1811                 goto error;
1812         }
1813
1814         chip->fw = fw;
1815         if (!chip->disabled) {
1816                 /* continue probing */
1817                 if (azx_probe_continue(chip))
1818                         goto error;
1819         }
1820         return; /* OK */
1821
1822  error:
1823         snd_card_free(card);
1824         pci_set_drvdata(pci, NULL);
1825 }
1826 #endif
1827
1828 /*
1829  * HDA controller ops.
1830  */
1831
1832 /* PCI register access. */
1833 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1834 {
1835         writel(value, addr);
1836 }
1837
1838 static u32 pci_azx_readl(u32 __iomem *addr)
1839 {
1840         return readl(addr);
1841 }
1842
1843 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1844 {
1845         writew(value, addr);
1846 }
1847
1848 static u16 pci_azx_readw(u16 __iomem *addr)
1849 {
1850         return readw(addr);
1851 }
1852
1853 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1854 {
1855         writeb(value, addr);
1856 }
1857
1858 static u8 pci_azx_readb(u8 __iomem *addr)
1859 {
1860         return readb(addr);
1861 }
1862
1863 static int disable_msi_reset_irq(struct azx *chip)
1864 {
1865         struct hdac_bus *bus = azx_bus(chip);
1866         int err;
1867
1868         free_irq(bus->irq, chip);
1869         bus->irq = -1;
1870         pci_disable_msi(chip->pci);
1871         chip->msi = 0;
1872         err = azx_acquire_irq(chip, 1);
1873         if (err < 0)
1874                 return err;
1875
1876         return 0;
1877 }
1878
1879 /* DMA page allocation helpers.  */
1880 static int dma_alloc_pages(struct hdac_bus *bus,
1881                            int type,
1882                            size_t size,
1883                            struct snd_dma_buffer *buf)
1884 {
1885         struct azx *chip = bus_to_azx(bus);
1886         int err;
1887
1888         err = snd_dma_alloc_pages(type,
1889                                   bus->dev,
1890                                   size, buf);
1891         if (err < 0)
1892                 return err;
1893         mark_pages_wc(chip, buf, true);
1894         return 0;
1895 }
1896
1897 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1898 {
1899         struct azx *chip = bus_to_azx(bus);
1900
1901         mark_pages_wc(chip, buf, false);
1902         snd_dma_free_pages(buf);
1903 }
1904
1905 static int substream_alloc_pages(struct azx *chip,
1906                                  struct snd_pcm_substream *substream,
1907                                  size_t size)
1908 {
1909         struct azx_dev *azx_dev = get_azx_dev(substream);
1910         int ret;
1911
1912         mark_runtime_wc(chip, azx_dev, substream, false);
1913         ret = snd_pcm_lib_malloc_pages(substream, size);
1914         if (ret < 0)
1915                 return ret;
1916         mark_runtime_wc(chip, azx_dev, substream, true);
1917         return 0;
1918 }
1919
1920 static int substream_free_pages(struct azx *chip,
1921                                 struct snd_pcm_substream *substream)
1922 {
1923         struct azx_dev *azx_dev = get_azx_dev(substream);
1924         mark_runtime_wc(chip, azx_dev, substream, false);
1925         return snd_pcm_lib_free_pages(substream);
1926 }
1927
1928 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1929                              struct vm_area_struct *area)
1930 {
1931 #ifdef CONFIG_X86
1932         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1933         struct azx *chip = apcm->chip;
1934         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1935                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1936 #endif
1937 }
1938
1939 static const struct hdac_io_ops pci_hda_io_ops = {
1940         .reg_writel = pci_azx_writel,
1941         .reg_readl = pci_azx_readl,
1942         .reg_writew = pci_azx_writew,
1943         .reg_readw = pci_azx_readw,
1944         .reg_writeb = pci_azx_writeb,
1945         .reg_readb = pci_azx_readb,
1946         .dma_alloc_pages = dma_alloc_pages,
1947         .dma_free_pages = dma_free_pages,
1948 };
1949
1950 static const struct hda_controller_ops pci_hda_ops = {
1951         .disable_msi_reset_irq = disable_msi_reset_irq,
1952         .substream_alloc_pages = substream_alloc_pages,
1953         .substream_free_pages = substream_free_pages,
1954         .pcm_mmap_prepare = pcm_mmap_prepare,
1955         .position_check = azx_position_check,
1956         .link_power = azx_intel_link_power,
1957 };
1958
1959 static int azx_probe(struct pci_dev *pci,
1960                      const struct pci_device_id *pci_id)
1961 {
1962         static int dev;
1963         struct snd_card *card;
1964         struct hda_intel *hda;
1965         struct azx *chip;
1966         bool schedule_probe;
1967         int err;
1968
1969         if (dev >= SNDRV_CARDS)
1970                 return -ENODEV;
1971         if (!enable[dev]) {
1972                 dev++;
1973                 return -ENOENT;
1974         }
1975
1976         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1977                            0, &card);
1978         if (err < 0) {
1979                 dev_err(&pci->dev, "Error creating card!\n");
1980                 return err;
1981         }
1982
1983         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1984         if (err < 0)
1985                 goto out_free;
1986         card->private_data = chip;
1987         hda = container_of(chip, struct hda_intel, chip);
1988
1989         pci_set_drvdata(pci, card);
1990
1991         err = register_vga_switcheroo(chip);
1992         if (err < 0) {
1993                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1994                 goto out_free;
1995         }
1996
1997         if (check_hdmi_disabled(pci)) {
1998                 dev_info(card->dev, "VGA controller is disabled\n");
1999                 dev_info(card->dev, "Delaying initialization\n");
2000                 chip->disabled = true;
2001         }
2002
2003         schedule_probe = !chip->disabled;
2004
2005 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2006         if (patch[dev] && *patch[dev]) {
2007                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2008                          patch[dev]);
2009                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2010                                               &pci->dev, GFP_KERNEL, card,
2011                                               azx_firmware_cb);
2012                 if (err < 0)
2013                         goto out_free;
2014                 schedule_probe = false; /* continued in azx_firmware_cb() */
2015         }
2016 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2017
2018 #ifndef CONFIG_SND_HDA_I915
2019         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2020                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2021 #endif
2022
2023         if (schedule_probe)
2024                 schedule_work(&hda->probe_work);
2025
2026         dev++;
2027         if (chip->disabled)
2028                 complete_all(&hda->probe_wait);
2029         return 0;
2030
2031 out_free:
2032         snd_card_free(card);
2033         return err;
2034 }
2035
2036 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2037 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2038         [AZX_DRIVER_NVIDIA] = 8,
2039         [AZX_DRIVER_TERA] = 1,
2040 };
2041
2042 static int azx_probe_continue(struct azx *chip)
2043 {
2044         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2045         struct hdac_bus *bus = azx_bus(chip);
2046         struct pci_dev *pci = chip->pci;
2047         int dev = chip->dev_index;
2048         int err;
2049
2050         hda->probe_continued = 1;
2051
2052         /* Request display power well for the HDA controller or codec. For
2053          * Haswell/Broadwell, both the display HDA controller and codec need
2054          * this power. For other platforms, like Baytrail/Braswell, only the
2055          * display codec needs the power and it can be released after probe.
2056          */
2057         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2058                 /* HSW/BDW controllers need this power */
2059                 if (CONTROLLER_IN_GPU(pci))
2060                         hda->need_i915_power = 1;
2061
2062                 err = snd_hdac_i915_init(bus);
2063                 if (err < 0) {
2064                         /* if the controller is bound only with HDMI/DP
2065                          * (for HSW and BDW), we need to abort the probe;
2066                          * for other chips, still continue probing as other
2067                          * codecs can be on the same link.
2068                          */
2069                         if (CONTROLLER_IN_GPU(pci))
2070                                 goto out_free;
2071                         else
2072                                 goto skip_i915;
2073                 }
2074
2075                 err = snd_hdac_display_power(bus, true);
2076                 if (err < 0) {
2077                         dev_err(chip->card->dev,
2078                                 "Cannot turn on display power on i915\n");
2079                         goto i915_power_fail;
2080                 }
2081         }
2082
2083  skip_i915:
2084         err = azx_first_init(chip);
2085         if (err < 0)
2086                 goto out_free;
2087
2088 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2089         chip->beep_mode = beep_mode[dev];
2090 #endif
2091
2092         /* create codec instances */
2093         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2094         if (err < 0)
2095                 goto out_free;
2096
2097 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2098         if (chip->fw) {
2099                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2100                                          chip->fw->data);
2101                 if (err < 0)
2102                         goto out_free;
2103 #ifndef CONFIG_PM
2104                 release_firmware(chip->fw); /* no longer needed */
2105                 chip->fw = NULL;
2106 #endif
2107         }
2108 #endif
2109         if ((probe_only[dev] & 1) == 0) {
2110                 err = azx_codec_configure(chip);
2111                 if (err < 0)
2112                         goto out_free;
2113         }
2114
2115         err = snd_card_register(chip->card);
2116         if (err < 0)
2117                 goto out_free;
2118
2119         chip->running = 1;
2120         azx_add_card_list(chip);
2121         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2122         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2123                 pm_runtime_put_noidle(&pci->dev);
2124
2125 out_free:
2126         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2127                 && !hda->need_i915_power)
2128                 snd_hdac_display_power(bus, false);
2129
2130 i915_power_fail:
2131         if (err < 0)
2132                 hda->init_failed = 1;
2133         complete_all(&hda->probe_wait);
2134         return err;
2135 }
2136
2137 static void azx_remove(struct pci_dev *pci)
2138 {
2139         struct snd_card *card = pci_get_drvdata(pci);
2140         struct azx *chip;
2141         struct hda_intel *hda;
2142
2143         if (card) {
2144                 /* cancel the pending probing work */
2145                 chip = card->private_data;
2146                 hda = container_of(chip, struct hda_intel, chip);
2147                 cancel_work_sync(&hda->probe_work);
2148
2149                 snd_card_free(card);
2150         }
2151 }
2152
2153 static void azx_shutdown(struct pci_dev *pci)
2154 {
2155         struct snd_card *card = pci_get_drvdata(pci);
2156         struct azx *chip;
2157
2158         if (!card)
2159                 return;
2160         chip = card->private_data;
2161         if (chip && chip->running)
2162                 azx_stop_chip(chip);
2163 }
2164
2165 /* PCI IDs */
2166 static const struct pci_device_id azx_ids[] = {
2167         /* CPT */
2168         { PCI_DEVICE(0x8086, 0x1c20),
2169           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2170         /* PBG */
2171         { PCI_DEVICE(0x8086, 0x1d20),
2172           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2173         /* Panther Point */
2174         { PCI_DEVICE(0x8086, 0x1e20),
2175           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2176         /* Lynx Point */
2177         { PCI_DEVICE(0x8086, 0x8c20),
2178           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2179         /* 9 Series */
2180         { PCI_DEVICE(0x8086, 0x8ca0),
2181           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2182         /* Wellsburg */
2183         { PCI_DEVICE(0x8086, 0x8d20),
2184           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2185         { PCI_DEVICE(0x8086, 0x8d21),
2186           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2187         /* Lewisburg */
2188         { PCI_DEVICE(0x8086, 0xa1f0),
2189           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2190         { PCI_DEVICE(0x8086, 0xa270),
2191           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2192         /* Lynx Point-LP */
2193         { PCI_DEVICE(0x8086, 0x9c20),
2194           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2195         /* Lynx Point-LP */
2196         { PCI_DEVICE(0x8086, 0x9c21),
2197           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2198         /* Wildcat Point-LP */
2199         { PCI_DEVICE(0x8086, 0x9ca0),
2200           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2201         /* Sunrise Point */
2202         { PCI_DEVICE(0x8086, 0xa170),
2203           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2204         /* Sunrise Point-LP */
2205         { PCI_DEVICE(0x8086, 0x9d70),
2206           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2207         /* Broxton-P(Apollolake) */
2208         { PCI_DEVICE(0x8086, 0x5a98),
2209           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2210         /* Haswell */
2211         { PCI_DEVICE(0x8086, 0x0a0c),
2212           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2213         { PCI_DEVICE(0x8086, 0x0c0c),
2214           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2215         { PCI_DEVICE(0x8086, 0x0d0c),
2216           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2217         /* Broadwell */
2218         { PCI_DEVICE(0x8086, 0x160c),
2219           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2220         /* 5 Series/3400 */
2221         { PCI_DEVICE(0x8086, 0x3b56),
2222           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2223         /* Poulsbo */
2224         { PCI_DEVICE(0x8086, 0x811b),
2225           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2226         /* Oaktrail */
2227         { PCI_DEVICE(0x8086, 0x080a),
2228           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2229         /* BayTrail */
2230         { PCI_DEVICE(0x8086, 0x0f04),
2231           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2232         /* Braswell */
2233         { PCI_DEVICE(0x8086, 0x2284),
2234           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2235         /* ICH6 */
2236         { PCI_DEVICE(0x8086, 0x2668),
2237           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2238         /* ICH7 */
2239         { PCI_DEVICE(0x8086, 0x27d8),
2240           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2241         /* ESB2 */
2242         { PCI_DEVICE(0x8086, 0x269a),
2243           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2244         /* ICH8 */
2245         { PCI_DEVICE(0x8086, 0x284b),
2246           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2247         /* ICH9 */
2248         { PCI_DEVICE(0x8086, 0x293e),
2249           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2250         /* ICH9 */
2251         { PCI_DEVICE(0x8086, 0x293f),
2252           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2253         /* ICH10 */
2254         { PCI_DEVICE(0x8086, 0x3a3e),
2255           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2256         /* ICH10 */
2257         { PCI_DEVICE(0x8086, 0x3a6e),
2258           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2259         /* Generic Intel */
2260         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2261           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2262           .class_mask = 0xffffff,
2263           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2264         /* ATI SB 450/600/700/800/900 */
2265         { PCI_DEVICE(0x1002, 0x437b),
2266           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2267         { PCI_DEVICE(0x1002, 0x4383),
2268           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2269         /* AMD Hudson */
2270         { PCI_DEVICE(0x1022, 0x780d),
2271           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2272         /* ATI HDMI */
2273         { PCI_DEVICE(0x1002, 0x1308),
2274           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2275         { PCI_DEVICE(0x1002, 0x157a),
2276           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2277         { PCI_DEVICE(0x1002, 0x793b),
2278           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2279         { PCI_DEVICE(0x1002, 0x7919),
2280           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2281         { PCI_DEVICE(0x1002, 0x960f),
2282           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2283         { PCI_DEVICE(0x1002, 0x970f),
2284           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2285         { PCI_DEVICE(0x1002, 0x9840),
2286           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2287         { PCI_DEVICE(0x1002, 0xaa00),
2288           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2289         { PCI_DEVICE(0x1002, 0xaa08),
2290           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2291         { PCI_DEVICE(0x1002, 0xaa10),
2292           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2293         { PCI_DEVICE(0x1002, 0xaa18),
2294           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2295         { PCI_DEVICE(0x1002, 0xaa20),
2296           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2297         { PCI_DEVICE(0x1002, 0xaa28),
2298           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2299         { PCI_DEVICE(0x1002, 0xaa30),
2300           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2301         { PCI_DEVICE(0x1002, 0xaa38),
2302           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2303         { PCI_DEVICE(0x1002, 0xaa40),
2304           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2305         { PCI_DEVICE(0x1002, 0xaa48),
2306           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307         { PCI_DEVICE(0x1002, 0xaa50),
2308           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309         { PCI_DEVICE(0x1002, 0xaa58),
2310           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311         { PCI_DEVICE(0x1002, 0xaa60),
2312           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313         { PCI_DEVICE(0x1002, 0xaa68),
2314           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315         { PCI_DEVICE(0x1002, 0xaa80),
2316           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317         { PCI_DEVICE(0x1002, 0xaa88),
2318           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319         { PCI_DEVICE(0x1002, 0xaa90),
2320           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321         { PCI_DEVICE(0x1002, 0xaa98),
2322           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323         { PCI_DEVICE(0x1002, 0x9902),
2324           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2325         { PCI_DEVICE(0x1002, 0xaaa0),
2326           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2327         { PCI_DEVICE(0x1002, 0xaaa8),
2328           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2329         { PCI_DEVICE(0x1002, 0xaab0),
2330           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2331         { PCI_DEVICE(0x1002, 0xaac0),
2332           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2333         { PCI_DEVICE(0x1002, 0xaac8),
2334           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2335         { PCI_DEVICE(0x1002, 0xaad8),
2336           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2337         { PCI_DEVICE(0x1002, 0xaae8),
2338           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2339         /* VIA VT8251/VT8237A */
2340         { PCI_DEVICE(0x1106, 0x3288),
2341           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2342         /* VIA GFX VT7122/VX900 */
2343         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2344         /* VIA GFX VT6122/VX11 */
2345         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2346         /* SIS966 */
2347         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2348         /* ULI M5461 */
2349         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2350         /* NVIDIA MCP */
2351         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2352           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2353           .class_mask = 0xffffff,
2354           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2355         /* Teradici */
2356         { PCI_DEVICE(0x6549, 0x1200),
2357           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2358         { PCI_DEVICE(0x6549, 0x2200),
2359           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2360         /* Creative X-Fi (CA0110-IBG) */
2361         /* CTHDA chips */
2362         { PCI_DEVICE(0x1102, 0x0010),
2363           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2364         { PCI_DEVICE(0x1102, 0x0012),
2365           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2366 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2367         /* the following entry conflicts with snd-ctxfi driver,
2368          * as ctxfi driver mutates from HD-audio to native mode with
2369          * a special command sequence.
2370          */
2371         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2372           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2373           .class_mask = 0xffffff,
2374           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2375           AZX_DCAPS_NO_64BIT |
2376           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2377 #else
2378         /* this entry seems still valid -- i.e. without emu20kx chip */
2379         { PCI_DEVICE(0x1102, 0x0009),
2380           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2381           AZX_DCAPS_NO_64BIT |
2382           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2383 #endif
2384         /* CM8888 */
2385         { PCI_DEVICE(0x13f6, 0x5011),
2386           .driver_data = AZX_DRIVER_CMEDIA |
2387           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2388         /* Vortex86MX */
2389         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2390         /* VMware HDAudio */
2391         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2392         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2393         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2394           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2395           .class_mask = 0xffffff,
2396           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2397         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2398           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2399           .class_mask = 0xffffff,
2400           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2401         { 0, }
2402 };
2403 MODULE_DEVICE_TABLE(pci, azx_ids);
2404
2405 /* pci_driver definition */
2406 static struct pci_driver azx_driver = {
2407         .name = KBUILD_MODNAME,
2408         .id_table = azx_ids,
2409         .probe = azx_probe,
2410         .remove = azx_remove,
2411         .shutdown = azx_shutdown,
2412         .driver = {
2413                 .pm = AZX_PM_OPS,
2414         },
2415 };
2416
2417 module_pci_driver(azx_driver);