kernel/include/linux/qed/common_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef __COMMON_HSI__
  10 #define __COMMON_HSI__
  11
  12 #define CORE_SPQE_PAGE_SIZE_BYTES                       4096
  13
  14 #define FW_MAJOR_VERSION        8
  15 #define FW_MINOR_VERSION        4
  16 #define FW_REVISION_VERSION     2
  17 #define FW_ENGINEERING_VERSION  0
  18
  19 /***********************/
  20 /* COMMON HW CONSTANTS */
  21 /***********************/
  22
  23 /* PCI functions */
  24 #define MAX_NUM_PORTS_K2        (4)
  25 #define MAX_NUM_PORTS_BB        (2)
  26 #define MAX_NUM_PORTS           (MAX_NUM_PORTS_K2)
  27
  28 #define MAX_NUM_PFS_K2  (16)
  29 #define MAX_NUM_PFS_BB  (8)
  30 #define MAX_NUM_PFS     (MAX_NUM_PFS_K2)
  31 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
  32
  33 #define MAX_NUM_VFS_K2  (192)
  34 #define MAX_NUM_VFS_BB  (120)
  35 #define MAX_NUM_VFS     (MAX_NUM_VFS_K2)
  36
  37 #define MAX_NUM_FUNCTIONS_BB    (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
  38 #define MAX_NUM_FUNCTIONS       (MAX_NUM_PFS + MAX_NUM_VFS)
  39
  40 #define MAX_FUNCTION_NUMBER_BB  (MAX_NUM_PFS + MAX_NUM_VFS_BB)
  41 #define MAX_FUNCTION_NUMBER     (MAX_NUM_PFS + MAX_NUM_VFS)
  42
  43 #define MAX_NUM_VPORTS_K2       (208)
  44 #define MAX_NUM_VPORTS_BB       (160)
  45 #define MAX_NUM_VPORTS          (MAX_NUM_VPORTS_K2)
  46
  47 #define MAX_NUM_L2_QUEUES_K2    (320)
  48 #define MAX_NUM_L2_QUEUES_BB    (256)
  49 #define MAX_NUM_L2_QUEUES       (MAX_NUM_L2_QUEUES_K2)
  50
  51 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
  52 #define NUM_PHYS_TCS_4PORT_K2   (4)
  53 #define NUM_OF_PHYS_TCS         (8)
  54
  55 #define NUM_TCS_4PORT_K2        (NUM_PHYS_TCS_4PORT_K2 + 1)
  56 #define NUM_OF_TCS              (NUM_OF_PHYS_TCS + 1)
  57
  58 #define LB_TC                   (NUM_OF_PHYS_TCS)
  59
  60 /* Num of possible traffic priority values */
  61 #define NUM_OF_PRIO             (8)
  62
  63 #define MAX_NUM_VOQS_K2         (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
  64 #define MAX_NUM_VOQS_BB         (NUM_OF_TCS * MAX_NUM_PORTS_BB)
  65 #define MAX_NUM_VOQS            (MAX_NUM_VOQS_K2)
  66 #define MAX_PHYS_VOQS           (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
  67
  68 /* CIDs */
  69 #define NUM_OF_CONNECTION_TYPES (8)
  70 #define NUM_OF_LCIDS            (320)
  71 #define NUM_OF_LTIDS            (320)
  72
  73 /*****************/
  74 /* CDU CONSTANTS */
  75 /*****************/
  76
  77 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT              (17)
  78 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK             (0x1ffff)
  79
  80 /*****************/
  81 /* DQ CONSTANTS  */
  82 /*****************/
  83
  84 /* DEMS */
  85 #define DQ_DEMS_LEGACY                  0
  86
  87 /* XCM agg val selection */
  88 #define DQ_XCM_AGG_VAL_SEL_WORD2  0
  89 #define DQ_XCM_AGG_VAL_SEL_WORD3  1
  90 #define DQ_XCM_AGG_VAL_SEL_WORD4  2
  91 #define DQ_XCM_AGG_VAL_SEL_WORD5  3
  92 #define DQ_XCM_AGG_VAL_SEL_REG3   4
  93 #define DQ_XCM_AGG_VAL_SEL_REG4   5
  94 #define DQ_XCM_AGG_VAL_SEL_REG5   6
  95 #define DQ_XCM_AGG_VAL_SEL_REG6   7
  96
  97 /* XCM agg val selection */
  98 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
  99         DQ_XCM_AGG_VAL_SEL_WORD2
 100 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
 101         DQ_XCM_AGG_VAL_SEL_WORD3
 102 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
 103         DQ_XCM_AGG_VAL_SEL_WORD3
 104 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
 105         DQ_XCM_AGG_VAL_SEL_WORD4
 106 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
 107         DQ_XCM_AGG_VAL_SEL_WORD4
 108 #define DQ_XCM_CORE_SPQ_PROD_CMD \
 109         DQ_XCM_AGG_VAL_SEL_WORD4
 110 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD            DQ_XCM_AGG_VAL_SEL_WORD5
 111
 112 /* XCM agg counter flag selection */
 113 #define DQ_XCM_AGG_FLG_SHIFT_BIT14  0
 114 #define DQ_XCM_AGG_FLG_SHIFT_BIT15  1
 115 #define DQ_XCM_AGG_FLG_SHIFT_CF12   2
 116 #define DQ_XCM_AGG_FLG_SHIFT_CF13   3
 117 #define DQ_XCM_AGG_FLG_SHIFT_CF18   4
 118 #define DQ_XCM_AGG_FLG_SHIFT_CF19   5
 119 #define DQ_XCM_AGG_FLG_SHIFT_CF22   6
 120 #define DQ_XCM_AGG_FLG_SHIFT_CF23   7
 121
 122 /* XCM agg counter flag selection */
 123 #define DQ_XCM_ETH_DQ_CF_CMD            (1 << \
 124                                         DQ_XCM_AGG_FLG_SHIFT_CF18)
 125 #define DQ_XCM_CORE_DQ_CF_CMD           (1 << \
 126                                         DQ_XCM_AGG_FLG_SHIFT_CF18)
 127 #define DQ_XCM_ETH_TERMINATE_CMD        (1 << \
 128                                         DQ_XCM_AGG_FLG_SHIFT_CF19)
 129 #define DQ_XCM_CORE_TERMINATE_CMD       (1 << \
 130                                         DQ_XCM_AGG_FLG_SHIFT_CF19)
 131 #define DQ_XCM_ETH_SLOW_PATH_CMD        (1 << \
 132                                         DQ_XCM_AGG_FLG_SHIFT_CF22)
 133 #define DQ_XCM_CORE_SLOW_PATH_CMD       (1 << \
 134                                         DQ_XCM_AGG_FLG_SHIFT_CF22)
 135 #define DQ_XCM_ETH_TPH_EN_CMD           (1 << \
 136                                         DQ_XCM_AGG_FLG_SHIFT_CF23)
 137
 138 /*****************/
 139 /* QM CONSTANTS  */
 140 /*****************/
 141
 142 /* number of TX queues in the QM */
 143 #define MAX_QM_TX_QUEUES_K2     512
 144 #define MAX_QM_TX_QUEUES_BB     448
 145 #define MAX_QM_TX_QUEUES        MAX_QM_TX_QUEUES_K2
 146
 147 /* number of Other queues in the QM */
 148 #define MAX_QM_OTHER_QUEUES_BB  64
 149 #define MAX_QM_OTHER_QUEUES_K2  128
 150 #define MAX_QM_OTHER_QUEUES     MAX_QM_OTHER_QUEUES_K2
 151
 152 /* number of queues in a PF queue group */
 153 #define QM_PF_QUEUE_GROUP_SIZE  8
 154
 155 /* base number of Tx PQs in the CM PQ representation.
 156  * should be used when storing PQ IDs in CM PQ registers and context
 157  */
 158 #define CM_TX_PQ_BASE   0x200
 159
 160 /* QM registers data */
 161 #define QM_LINE_CRD_REG_WIDTH           16
 162 #define QM_LINE_CRD_REG_SIGN_BIT        (1 << (QM_LINE_CRD_REG_WIDTH - 1))
 163 #define QM_BYTE_CRD_REG_WIDTH           24
 164 #define QM_BYTE_CRD_REG_SIGN_BIT        (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
 165 #define QM_WFQ_CRD_REG_WIDTH            32
 166 #define QM_WFQ_CRD_REG_SIGN_BIT         (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
 167 #define QM_RL_CRD_REG_WIDTH             32
 168 #define QM_RL_CRD_REG_SIGN_BIT          (1 << (QM_RL_CRD_REG_WIDTH - 1))
 169
 170 /*****************/
 171 /* CAU CONSTANTS */
 172 /*****************/
 173
 174 #define CAU_FSM_ETH_RX  0
 175 #define CAU_FSM_ETH_TX  1
 176
 177 /* Number of Protocol Indices per Status Block */
 178 #define PIS_PER_SB    12
 179
 180 #define CAU_HC_STOPPED_STATE    3
 181 #define CAU_HC_DISABLE_STATE    4
 182 #define CAU_HC_ENABLE_STATE     0
 183
 184 /*****************/
 185 /* IGU CONSTANTS */
 186 /*****************/
 187
 188 #define MAX_SB_PER_PATH_K2      (368)
 189 #define MAX_SB_PER_PATH_BB      (288)
 190 #define MAX_TOT_SB_PER_PATH \
 191         MAX_SB_PER_PATH_K2
 192
 193 #define MAX_SB_PER_PF_MIMD      129
 194 #define MAX_SB_PER_PF_SIMD      64
 195 #define MAX_SB_PER_VF           64
 196
 197 /* Memory addresses on the BAR for the IGU Sub Block */
 198 #define IGU_MEM_BASE                    0x0000
 199
 200 #define IGU_MEM_MSIX_BASE               0x0000
 201 #define IGU_MEM_MSIX_UPPER              0x0101
 202 #define IGU_MEM_MSIX_RESERVED_UPPER     0x01ff
 203
 204 #define IGU_MEM_PBA_MSIX_BASE           0x0200
 205 #define IGU_MEM_PBA_MSIX_UPPER          0x0202
 206 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
 207
 208 #define IGU_CMD_INT_ACK_BASE            0x0400
 209 #define IGU_CMD_INT_ACK_UPPER           (IGU_CMD_INT_ACK_BASE + \
 210                                          MAX_TOT_SB_PER_PATH -  \
 211                                          1)
 212 #define IGU_CMD_INT_ACK_RESERVED_UPPER  0x05ff
 213
 214 #define IGU_CMD_ATTN_BIT_UPD_UPPER      0x05f0
 215 #define IGU_CMD_ATTN_BIT_SET_UPPER      0x05f1
 216 #define IGU_CMD_ATTN_BIT_CLR_UPPER      0x05f2
 217
 218 #define IGU_REG_SISR_MDPC_WMASK_UPPER           0x05f3
 219 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER       0x05f4
 220 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER       0x05f5
 221 #define IGU_REG_SISR_MDPC_WOMASK_UPPER          0x05f6
 222
 223 #define IGU_CMD_PROD_UPD_BASE                   0x0600
 224 #define IGU_CMD_PROD_UPD_UPPER                  (IGU_CMD_PROD_UPD_BASE +\
 225                                                  MAX_TOT_SB_PER_PATH - \
 226                                                  1)
 227 #define IGU_CMD_PROD_UPD_RESERVED_UPPER         0x07ff
 228
 229 /*****************/
 230 /* PXP CONSTANTS */
 231 /*****************/
 232
 233 /* PTT and GTT */
 234 #define PXP_NUM_PF_WINDOWS              12
 235 #define PXP_PER_PF_ENTRY_SIZE           8
 236 #define PXP_NUM_GLOBAL_WINDOWS          243
 237 #define PXP_GLOBAL_ENTRY_SIZE           4
 238 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
 239 #define PXP_PF_WINDOW_ADMIN_START       0
 240 #define PXP_PF_WINDOW_ADMIN_LENGTH      0x1000
 241 #define PXP_PF_WINDOW_ADMIN_END         (PXP_PF_WINDOW_ADMIN_START + \
 242                                          PXP_PF_WINDOW_ADMIN_LENGTH - 1)
 243 #define PXP_PF_WINDOW_ADMIN_PER_PF_START        0
 244 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH       (PXP_NUM_PF_WINDOWS * \
 245                                                  PXP_PER_PF_ENTRY_SIZE)
 246 #define PXP_PF_WINDOW_ADMIN_PER_PF_END  (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
 247                                          PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
 248 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START        0x200
 249 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH       (PXP_NUM_GLOBAL_WINDOWS * \
 250                                                  PXP_GLOBAL_ENTRY_SIZE)
 251 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
 252                 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
 253                  PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
 254 #define PXP_PF_GLOBAL_PRETEND_ADDR      0x1f0
 255 #define PXP_PF_ME_OPAQUE_MASK_ADDR      0xf4
 256 #define PXP_PF_ME_OPAQUE_ADDR           0x1f8
 257 #define PXP_PF_ME_CONCRETE_ADDR         0x1fc
 258
 259 #define PXP_EXTERNAL_BAR_PF_WINDOW_START        0x1000
 260 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM          PXP_NUM_PF_WINDOWS
 261 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE  0x1000
 262 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
 263         (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
 264          PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
 265 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
 266         (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
 267          PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
 268
 269 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
 270         (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
 271 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM              PXP_NUM_GLOBAL_WINDOWS
 272 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE      0x1000
 273 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
 274         (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
 275          PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
 276 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
 277         (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
 278          PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
 279
 280 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN  12
 281 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
 282
 283 /* ILT Records */
 284 #define PXP_NUM_ILT_RECORDS_BB 7600
 285 #define PXP_NUM_ILT_RECORDS_K2 11000
 286 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
 287
 288 /******************/
 289 /* PBF CONSTANTS  */
 290 /******************/
 291
 292 /* Number of PBF command queue lines. Each line is 32B. */
 293 #define PBF_MAX_CMD_LINES 3328
 294
 295 /* Number of BTB blocks. Each block is 256B. */
 296 #define BTB_MAX_BLOCKS 1440
 297
 298 /*****************/
 299 /* PRS CONSTANTS */
 300 /*****************/
 301
 302 /* Async data KCQ CQE */
 303 struct async_data {
 304         __le32  cid;
 305         __le16  itid;
 306         u8      error_code;
 307         u8      fw_debug_param;
 308 };
 309
 310 struct regpair {
 311         __le32  lo;
 312         __le32  hi;
 313 };
 314
 315 /* Event Data Union */
 316 union event_ring_data {
 317         u8                              bytes[8];
 318         struct async_data               async_info;
 319 };
 320
 321 /* Event Ring Entry */
 322 struct event_ring_entry {
 323         u8                      protocol_id;
 324         u8                      opcode;
 325         __le16                  reserved0;
 326         __le16                  echo;
 327         u8                      fw_return_code;
 328         u8                      flags;
 329 #define EVENT_RING_ENTRY_ASYNC_MASK      0x1
 330 #define EVENT_RING_ENTRY_ASYNC_SHIFT     0
 331 #define EVENT_RING_ENTRY_RESERVED1_MASK  0x7F
 332 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
 333         union event_ring_data   data;
 334 };
 335
 336 /* Multi function mode */
 337 enum mf_mode {
 338         SF,
 339         MF_OVLAN,
 340         MF_NPAR,
 341         MAX_MF_MODE
 342 };
 343
 344 /* Per-protocol connection types */
 345 enum protocol_type {
 346         PROTOCOLID_RESERVED1,
 347         PROTOCOLID_RESERVED2,
 348         PROTOCOLID_RESERVED3,
 349         PROTOCOLID_CORE,
 350         PROTOCOLID_ETH,
 351         PROTOCOLID_RESERVED4,
 352         PROTOCOLID_RESERVED5,
 353         PROTOCOLID_PREROCE,
 354         PROTOCOLID_COMMON,
 355         PROTOCOLID_RESERVED6,
 356         MAX_PROTOCOL_TYPE
 357 };
 358
 359 /* status block structure */
 360 struct cau_pi_entry {
 361         u32 prod;
 362 #define CAU_PI_ENTRY_PROD_VAL_MASK    0xFFFF
 363 #define CAU_PI_ENTRY_PROD_VAL_SHIFT   0
 364 #define CAU_PI_ENTRY_PI_TIMESET_MASK  0x7F
 365 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
 366 #define CAU_PI_ENTRY_FSM_SEL_MASK     0x1
 367 #define CAU_PI_ENTRY_FSM_SEL_SHIFT    23
 368 #define CAU_PI_ENTRY_RESERVED_MASK    0xFF
 369 #define CAU_PI_ENTRY_RESERVED_SHIFT   24
 370 };
 371
 372 /* status block structure */
 373 struct cau_sb_entry {
 374         u32 data;
 375 #define CAU_SB_ENTRY_SB_PROD_MASK      0xFFFFFF
 376 #define CAU_SB_ENTRY_SB_PROD_SHIFT     0
 377 #define CAU_SB_ENTRY_STATE0_MASK       0xF
 378 #define CAU_SB_ENTRY_STATE0_SHIFT      24
 379 #define CAU_SB_ENTRY_STATE1_MASK       0xF
 380 #define CAU_SB_ENTRY_STATE1_SHIFT      28
 381         u32 params;
 382 #define CAU_SB_ENTRY_SB_TIMESET0_MASK  0x7F
 383 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
 384 #define CAU_SB_ENTRY_SB_TIMESET1_MASK  0x7F
 385 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
 386 #define CAU_SB_ENTRY_TIMER_RES0_MASK   0x3
 387 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT  14
 388 #define CAU_SB_ENTRY_TIMER_RES1_MASK   0x3
 389 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT  16
 390 #define CAU_SB_ENTRY_VF_NUMBER_MASK    0xFF
 391 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT   18
 392 #define CAU_SB_ENTRY_VF_VALID_MASK     0x1
 393 #define CAU_SB_ENTRY_VF_VALID_SHIFT    26
 394 #define CAU_SB_ENTRY_PF_NUMBER_MASK    0xF
 395 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT   27
 396 #define CAU_SB_ENTRY_TPH_MASK          0x1
 397 #define CAU_SB_ENTRY_TPH_SHIFT         31
 398 };
 399
 400 /* core doorbell data */
 401 struct core_db_data {
 402         u8 params;
 403 #define CORE_DB_DATA_DEST_MASK         0x3
 404 #define CORE_DB_DATA_DEST_SHIFT        0
 405 #define CORE_DB_DATA_AGG_CMD_MASK      0x3
 406 #define CORE_DB_DATA_AGG_CMD_SHIFT     2
 407 #define CORE_DB_DATA_BYPASS_EN_MASK    0x1
 408 #define CORE_DB_DATA_BYPASS_EN_SHIFT   4
 409 #define CORE_DB_DATA_RESERVED_MASK     0x1
 410 #define CORE_DB_DATA_RESERVED_SHIFT    5
 411 #define CORE_DB_DATA_AGG_VAL_SEL_MASK  0x3
 412 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
 413         u8      agg_flags;
 414         __le16  spq_prod;
 415 };
 416
 417 /* Enum of doorbell aggregative command selection */
 418 enum db_agg_cmd_sel {
 419         DB_AGG_CMD_NOP,
 420         DB_AGG_CMD_SET,
 421         DB_AGG_CMD_ADD,
 422         DB_AGG_CMD_MAX,
 423         MAX_DB_AGG_CMD_SEL
 424 };
 425
 426 /* Enum of doorbell destination */
 427 enum db_dest {
 428         DB_DEST_XCM,
 429         DB_DEST_UCM,
 430         DB_DEST_TCM,
 431         DB_NUM_DESTINATIONS,
 432         MAX_DB_DEST
 433 };
 434
 435 /* Structure for doorbell address, in legacy mode */
 436 struct db_legacy_addr {
 437         __le32 addr;
 438 #define DB_LEGACY_ADDR_RESERVED0_MASK  0x3
 439 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
 440 #define DB_LEGACY_ADDR_DEMS_MASK       0x7
 441 #define DB_LEGACY_ADDR_DEMS_SHIFT      2
 442 #define DB_LEGACY_ADDR_ICID_MASK       0x7FFFFFF
 443 #define DB_LEGACY_ADDR_ICID_SHIFT      5
 444 };
 445
 446 /* Igu interrupt command */
 447 enum igu_int_cmd {
 448         IGU_INT_ENABLE  = 0,
 449         IGU_INT_DISABLE = 1,
 450         IGU_INT_NOP     = 2,
 451         IGU_INT_NOP2    = 3,
 452         MAX_IGU_INT_CMD
 453 };
 454
 455 /* IGU producer or consumer update command */
 456 struct igu_prod_cons_update {
 457         u32 sb_id_and_flags;
 458 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK        0xFFFFFF
 459 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT       0
 460 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK     0x1
 461 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT    24
 462 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK      0x3
 463 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT     25
 464 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK  0x1
 465 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
 466 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK      0x1
 467 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT     28
 468 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK       0x3
 469 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT      29
 470 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK    0x1
 471 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT   31
 472         u32 reserved1;
 473 };
 474
 475 /* Igu segments access for default status block only */
 476 enum igu_seg_access {
 477         IGU_SEG_ACCESS_REG      = 0,
 478         IGU_SEG_ACCESS_ATTN     = 1,
 479         MAX_IGU_SEG_ACCESS
 480 };
 481
 482 struct parsing_and_err_flags {
 483         __le16 flags;
 484 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK                      0x3
 485 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT                     0
 486 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK                  0x3
 487 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT                 2
 488 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK                    0x1
 489 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT                   4
 490 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK               0x1
 491 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT              5
 492 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK        0x1
 493 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT       6
 494 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK                 0x1
 495 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT                7
 496 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK           0x1
 497 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT          8
 498 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK                  0x1
 499 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT                 9
 500 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK                0x1
 501 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT               10
 502 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK                 0x1
 503 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT                11
 504 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK         0x1
 505 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT        12
 506 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK            0x1
 507 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT           13
 508 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK  0x1
 509 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
 510 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK          0x1
 511 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT         15
 512 };
 513
 514 /* Concrete Function ID. */
 515 struct pxp_concrete_fid {
 516         __le16 fid;
 517 #define PXP_CONCRETE_FID_PFID_MASK     0xF
 518 #define PXP_CONCRETE_FID_PFID_SHIFT    0
 519 #define PXP_CONCRETE_FID_PORT_MASK     0x3
 520 #define PXP_CONCRETE_FID_PORT_SHIFT    4
 521 #define PXP_CONCRETE_FID_PATH_MASK     0x1
 522 #define PXP_CONCRETE_FID_PATH_SHIFT    6
 523 #define PXP_CONCRETE_FID_VFVALID_MASK  0x1
 524 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
 525 #define PXP_CONCRETE_FID_VFID_MASK     0xFF
 526 #define PXP_CONCRETE_FID_VFID_SHIFT    8
 527 };
 528
 529 struct pxp_pretend_concrete_fid {
 530         __le16 fid;
 531 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK      0xF
 532 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT     0
 533 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK  0x7
 534 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
 535 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK   0x1
 536 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT  7
 537 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK      0xFF
 538 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT     8
 539 };
 540
 541 union pxp_pretend_fid {
 542         struct pxp_pretend_concrete_fid concrete_fid;
 543         __le16                          opaque_fid;
 544 };
 545
 546 /* Pxp Pretend Command Register. */
 547 struct pxp_pretend_cmd {
 548         union pxp_pretend_fid   fid;
 549         __le16                  control;
 550 #define PXP_PRETEND_CMD_PATH_MASK              0x1
 551 #define PXP_PRETEND_CMD_PATH_SHIFT             0
 552 #define PXP_PRETEND_CMD_USE_PORT_MASK          0x1
 553 #define PXP_PRETEND_CMD_USE_PORT_SHIFT         1
 554 #define PXP_PRETEND_CMD_PORT_MASK              0x3
 555 #define PXP_PRETEND_CMD_PORT_SHIFT             2
 556 #define PXP_PRETEND_CMD_RESERVED0_MASK         0xF
 557 #define PXP_PRETEND_CMD_RESERVED0_SHIFT        4
 558 #define PXP_PRETEND_CMD_RESERVED1_MASK         0xF
 559 #define PXP_PRETEND_CMD_RESERVED1_SHIFT        8
 560 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK      0x1
 561 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT     12
 562 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK      0x1
 563 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT     13
 564 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK  0x1
 565 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
 566 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK       0x1
 567 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT      15
 568 };
 569
 570 /* PTT Record in PXP Admin Window. */
 571 struct pxp_ptt_entry {
 572         __le32                  offset;
 573 #define PXP_PTT_ENTRY_OFFSET_MASK     0x7FFFFF
 574 #define PXP_PTT_ENTRY_OFFSET_SHIFT    0
 575 #define PXP_PTT_ENTRY_RESERVED0_MASK  0x1FF
 576 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
 577         struct pxp_pretend_cmd  pretend;
 578 };
 579
 580 /* RSS hash type */
 581 enum rss_hash_type {
 582         RSS_HASH_TYPE_DEFAULT   = 0,
 583         RSS_HASH_TYPE_IPV4      = 1,
 584         RSS_HASH_TYPE_TCP_IPV4  = 2,
 585         RSS_HASH_TYPE_IPV6      = 3,
 586         RSS_HASH_TYPE_TCP_IPV6  = 4,
 587         RSS_HASH_TYPE_UDP_IPV4  = 5,
 588         RSS_HASH_TYPE_UDP_IPV6  = 6,
 589         MAX_RSS_HASH_TYPE
 590 };
 591
 592 /* status block structure */
 593 struct status_block {
 594         __le16  pi_array[PIS_PER_SB];
 595         __le32  sb_num;
 596 #define STATUS_BLOCK_SB_NUM_MASK      0x1FF
 597 #define STATUS_BLOCK_SB_NUM_SHIFT     0
 598 #define STATUS_BLOCK_ZERO_PAD_MASK    0x7F
 599 #define STATUS_BLOCK_ZERO_PAD_SHIFT   9
 600 #define STATUS_BLOCK_ZERO_PAD2_MASK   0xFFFF
 601 #define STATUS_BLOCK_ZERO_PAD2_SHIFT  16
 602         __le32 prod_index;
 603 #define STATUS_BLOCK_PROD_INDEX_MASK  0xFFFFFF
 604 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
 605 #define STATUS_BLOCK_ZERO_PAD3_MASK   0xFF
 606 #define STATUS_BLOCK_ZERO_PAD3_SHIFT  24
 607 };
 608
 609 #endif /* __COMMON_HSI__ */