4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
110 typedef int __bitwise pci_power_t;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
123 static inline const char *pci_power_name(pci_power_t state)
125 return pci_power_names[1 + (int) state];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t;
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t;
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
163 typedef unsigned short __bitwise pci_dev_flags_t;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
173 /* Flag for quirk use to store if quirk-specific ACS is enabled */
174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
175 /* Flag to indicate the device uses dma_alias_devfn */
176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
179 /* Do not use bus resets for device */
180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
181 /* Do not use PM reset even if device advertises NoSoftRst- */
182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
185 enum pci_irq_reroute_variant {
186 INTEL_IRQ_REROUTE_VARIANT = 1,
187 MAX_IRQ_REROUTE_VARIANTS = 3
190 typedef unsigned short __bitwise pci_bus_flags_t;
192 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
193 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
196 /* These values come from the PCI Express Spec */
197 enum pcie_link_width {
198 PCIE_LNK_WIDTH_RESRV = 0x00,
206 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
209 /* Based on the PCI Hotplug Spec, but some values are made up by us */
211 PCI_SPEED_33MHz = 0x00,
212 PCI_SPEED_66MHz = 0x01,
213 PCI_SPEED_66MHz_PCIX = 0x02,
214 PCI_SPEED_100MHz_PCIX = 0x03,
215 PCI_SPEED_133MHz_PCIX = 0x04,
216 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
217 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
218 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
219 PCI_SPEED_66MHz_PCIX_266 = 0x09,
220 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
221 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
227 PCI_SPEED_66MHz_PCIX_533 = 0x11,
228 PCI_SPEED_100MHz_PCIX_533 = 0x12,
229 PCI_SPEED_133MHz_PCIX_533 = 0x13,
230 PCIE_SPEED_2_5GT = 0x14,
231 PCIE_SPEED_5_0GT = 0x15,
232 PCIE_SPEED_8_0GT = 0x16,
233 PCI_SPEED_UNKNOWN = 0xff,
236 struct pci_cap_saved_data {
243 struct pci_cap_saved_state {
244 struct hlist_node next;
245 struct pci_cap_saved_data cap;
248 struct pcie_link_state;
254 * The pci_dev structure is used to describe PCI devices.
257 struct list_head bus_list; /* node in per-bus list */
258 struct pci_bus *bus; /* bus this device is on */
259 struct pci_bus *subordinate; /* bus this device bridges to */
261 void *sysdata; /* hook for sys-specific extension */
262 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
263 struct pci_slot *slot; /* Physical slot this device is in */
265 unsigned int devfn; /* encoded device & function index */
266 unsigned short vendor;
267 unsigned short device;
268 unsigned short subsystem_vendor;
269 unsigned short subsystem_device;
270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
271 u8 revision; /* PCI revision, low byte of class word */
272 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
273 u8 pcie_cap; /* PCIe capability offset */
274 u8 msi_cap; /* MSI capability offset */
275 u8 msix_cap; /* MSI-X capability offset */
276 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
277 u8 rom_base_reg; /* which config register controls the ROM */
278 u8 pin; /* which interrupt pin this device uses */
279 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
280 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
282 struct pci_driver *driver; /* which driver has allocated this device */
283 u64 dma_mask; /* Mask of the bits of bus address this
284 device implements. Normally this is
285 0xffffffff. You only need to change
286 this if your device has broken DMA
287 or supports 64-bit transfers. */
289 struct device_dma_parameters dma_parms;
291 pci_power_t current_state; /* Current operating state. In ACPI-speak,
292 this is D0-D3, D0 being fully functional,
294 u8 pm_cap; /* PM capability offset */
295 unsigned int pme_support:5; /* Bitmask of states from which PME#
297 unsigned int pme_interrupt:1;
298 unsigned int pme_poll:1; /* Poll device's PME status bit */
299 unsigned int d1_support:1; /* Low power state D1 is supported */
300 unsigned int d2_support:1; /* Low power state D2 is supported */
301 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
302 unsigned int no_d3cold:1; /* D3cold is forbidden */
303 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
304 unsigned int mmio_always_on:1; /* disallow turning off io/mem
305 decoding during bar sizing */
306 unsigned int wakeup_prepared:1;
307 unsigned int runtime_d3cold:1; /* whether go through runtime
308 D3cold, not set for devices
309 powered on/off by the
310 corresponding bridge */
311 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
312 unsigned int d3_delay; /* D3->D0 transition time in ms */
313 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
315 #ifdef CONFIG_PCIEASPM
316 struct pcie_link_state *link_state; /* ASPM link state */
319 pci_channel_state_t error_state; /* current connectivity state */
320 struct device dev; /* Generic device interface */
322 int cfg_size; /* Size of configuration space */
325 * Instead of touching interrupt line and base address registers
326 * directly, use the values stored here. They might be different!
329 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
331 bool match_driver; /* Skip attaching driver */
332 /* These fields are used by common fixups */
333 unsigned int transparent:1; /* Subtractive decode PCI bridge */
334 unsigned int multifunction:1;/* Part of multi-function device */
335 /* keep track of device state */
336 unsigned int is_added:1;
337 unsigned int is_busmaster:1; /* device is busmaster */
338 unsigned int no_msi:1; /* device may not use msi */
339 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
340 unsigned int block_cfg_access:1; /* config space access is blocked */
341 unsigned int broken_parity_status:1; /* Device generates false positive parity */
342 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
343 unsigned int msi_enabled:1;
344 unsigned int msix_enabled:1;
345 unsigned int ari_enabled:1; /* ARI forwarding */
346 unsigned int is_managed:1;
347 unsigned int needs_freset:1; /* Dev requires fundamental reset */
348 unsigned int state_saved:1;
349 unsigned int is_physfn:1;
350 unsigned int is_virtfn:1;
351 unsigned int reset_fn:1;
352 unsigned int is_hotplug_bridge:1;
353 unsigned int __aer_firmware_first_valid:1;
354 unsigned int __aer_firmware_first:1;
355 unsigned int broken_intx_masking:1;
356 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
357 unsigned int irq_managed:1;
358 pci_dev_flags_t dev_flags;
359 atomic_t enable_cnt; /* pci_enable_device has been called */
361 u32 saved_config_space[16]; /* config space saved at suspend time */
362 struct hlist_head saved_cap_space;
363 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
364 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
365 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
366 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
367 #ifdef CONFIG_PCI_MSI
368 struct list_head msi_list;
369 const struct attribute_group **msi_irq_groups;
372 #ifdef CONFIG_PCI_ATS
374 struct pci_sriov *sriov; /* SR-IOV capability related */
375 struct pci_dev *physfn; /* the PF this VF is associated with */
377 struct pci_ats *ats; /* Address Translation Service */
379 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
380 size_t romlen; /* Length of ROM if it's not from the BAR */
381 char *driver_override; /* Driver name to force a match */
384 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
386 #ifdef CONFIG_PCI_IOV
393 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
395 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
396 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
398 static inline int pci_channel_offline(struct pci_dev *pdev)
400 return (pdev->error_state != pci_channel_io_normal);
403 struct pci_host_bridge {
405 struct pci_bus *bus; /* root bus */
406 struct list_head windows; /* resource_entry */
407 void (*release_fn)(struct pci_host_bridge *);
409 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
412 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
413 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
414 void (*release_fn)(struct pci_host_bridge *),
417 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
420 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
421 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
422 * buses below host bridges or subtractive decode bridges) go in the list.
423 * Use pci_bus_for_each_resource() to iterate through all the resources.
427 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
428 * and there's no way to program the bridge with the details of the window.
429 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
430 * decode bit set, because they are explicit and can be programmed with _SRS.
432 #define PCI_SUBTRACTIVE_DECODE 0x1
434 struct pci_bus_resource {
435 struct list_head list;
436 struct resource *res;
440 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
443 struct list_head node; /* node in list of buses */
444 struct pci_bus *parent; /* parent bus this bridge is on */
445 struct list_head children; /* list of child buses */
446 struct list_head devices; /* list of devices on this bus */
447 struct pci_dev *self; /* bridge device as seen by parent */
448 struct list_head slots; /* list of slots on this bus */
449 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
450 struct list_head resources; /* address space routed to this bus */
451 struct resource busn_res; /* bus numbers routed to this bus */
453 struct pci_ops *ops; /* configuration access functions */
454 struct msi_controller *msi; /* MSI controller */
455 void *sysdata; /* hook for sys-specific extension */
456 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
458 unsigned char number; /* bus number */
459 unsigned char primary; /* number of primary bridge */
460 unsigned char max_bus_speed; /* enum pci_bus_speed */
461 unsigned char cur_bus_speed; /* enum pci_bus_speed */
462 #ifdef CONFIG_PCI_DOMAINS_GENERIC
468 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
469 pci_bus_flags_t bus_flags; /* inherited by child buses */
470 struct device *bridge;
472 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
473 struct bin_attribute *legacy_mem; /* legacy mem */
474 unsigned int is_added:1;
477 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
480 * Returns true if the PCI bus is root (behind host-PCI bridge),
483 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
484 * This is incorrect because "virtual" buses added for SR-IOV (via
485 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
487 static inline bool pci_is_root_bus(struct pci_bus *pbus)
489 return !(pbus->parent);
493 * pci_is_bridge - check if the PCI device is a bridge
496 * Return true if the PCI device is bridge whether it has subordinate
499 static inline bool pci_is_bridge(struct pci_dev *dev)
501 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
502 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
505 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
507 dev = pci_physfn(dev);
508 if (pci_is_root_bus(dev->bus))
511 return dev->bus->self;
514 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
515 void pci_put_host_bridge_device(struct device *dev);
517 #ifdef CONFIG_PCI_MSI
518 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
520 return pci_dev->msi_enabled || pci_dev->msix_enabled;
523 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
527 * Error values that may be returned by PCI functions.
529 #define PCIBIOS_SUCCESSFUL 0x00
530 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
531 #define PCIBIOS_BAD_VENDOR_ID 0x83
532 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
533 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
534 #define PCIBIOS_SET_FAILED 0x88
535 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
538 * Translate above to generic errno for passing back through non-PCI code.
540 static inline int pcibios_err_to_errno(int err)
542 if (err <= PCIBIOS_SUCCESSFUL)
543 return err; /* Assume already errno */
546 case PCIBIOS_FUNC_NOT_SUPPORTED:
548 case PCIBIOS_BAD_VENDOR_ID:
550 case PCIBIOS_DEVICE_NOT_FOUND:
552 case PCIBIOS_BAD_REGISTER_NUMBER:
554 case PCIBIOS_SET_FAILED:
556 case PCIBIOS_BUFFER_TOO_SMALL:
563 /* Low-level architecture-dependent routines */
566 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
567 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
568 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
572 * ACPI needs to be able to access PCI config space before we've done a
573 * PCI bus scan and created pci_bus structures.
575 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
576 int reg, int len, u32 *val);
577 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
578 int reg, int len, u32 val);
580 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
581 typedef u64 pci_bus_addr_t;
583 typedef u32 pci_bus_addr_t;
586 struct pci_bus_region {
587 pci_bus_addr_t start;
592 spinlock_t lock; /* protects list, index */
593 struct list_head list; /* for IDs added at runtime */
598 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
599 * a set of callbacks in struct pci_error_handlers, that device driver
600 * will be notified of PCI bus errors, and will be driven to recovery
601 * when an error occurs.
604 typedef unsigned int __bitwise pci_ers_result_t;
606 enum pci_ers_result {
607 /* no result/none/not supported in device driver */
608 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
610 /* Device driver can recover without slot reset */
611 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
613 /* Device driver wants slot to be reset. */
614 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
616 /* Device has completely failed, is unrecoverable */
617 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
619 /* Device driver is fully recovered and operational */
620 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
622 /* No AER capabilities registered for the driver */
623 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
626 /* PCI bus error event callbacks */
627 struct pci_error_handlers {
628 /* PCI bus error detected on this device */
629 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
630 enum pci_channel_state error);
632 /* MMIO has been re-enabled, but not DMA */
633 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
635 /* PCI Express link has been reset */
636 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
638 /* PCI slot has been reset */
639 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
641 /* PCI function reset prepare or completed */
642 void (*reset_notify)(struct pci_dev *dev, bool prepare);
644 /* Device driver may resume normal operations */
645 void (*resume)(struct pci_dev *dev);
651 struct list_head node;
653 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
654 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
655 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
656 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
657 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
658 int (*resume_early) (struct pci_dev *dev);
659 int (*resume) (struct pci_dev *dev); /* Device woken up */
660 void (*shutdown) (struct pci_dev *dev);
661 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
662 const struct pci_error_handlers *err_handler;
663 struct device_driver driver;
664 struct pci_dynids dynids;
667 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
670 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
671 * @_table: device table name
673 * This macro is deprecated and should not be used in new code.
675 #define DEFINE_PCI_DEVICE_TABLE(_table) \
676 const struct pci_device_id _table[]
679 * PCI_DEVICE - macro used to describe a specific pci device
680 * @vend: the 16 bit PCI Vendor ID
681 * @dev: the 16 bit PCI Device ID
683 * This macro is used to create a struct pci_device_id that matches a
684 * specific device. The subvendor and subdevice fields will be set to
687 #define PCI_DEVICE(vend,dev) \
688 .vendor = (vend), .device = (dev), \
689 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
692 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
693 * @vend: the 16 bit PCI Vendor ID
694 * @dev: the 16 bit PCI Device ID
695 * @subvend: the 16 bit PCI Subvendor ID
696 * @subdev: the 16 bit PCI Subdevice ID
698 * This macro is used to create a struct pci_device_id that matches a
699 * specific device with subsystem information.
701 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
702 .vendor = (vend), .device = (dev), \
703 .subvendor = (subvend), .subdevice = (subdev)
706 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
707 * @dev_class: the class, subclass, prog-if triple for this device
708 * @dev_class_mask: the class mask for this device
710 * This macro is used to create a struct pci_device_id that matches a
711 * specific PCI class. The vendor, device, subvendor, and subdevice
712 * fields will be set to PCI_ANY_ID.
714 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
715 .class = (dev_class), .class_mask = (dev_class_mask), \
716 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
717 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
720 * PCI_VDEVICE - macro used to describe a specific pci device in short form
721 * @vend: the vendor name
722 * @dev: the 16 bit PCI Device ID
724 * This macro is used to create a struct pci_device_id that matches a
725 * specific PCI device. The subvendor, and subdevice fields will be set
726 * to PCI_ANY_ID. The macro allows the next field to follow as the device
730 #define PCI_VDEVICE(vend, dev) \
731 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
732 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
734 /* these external functions are only available when PCI support is enabled */
737 void pcie_bus_configure_settings(struct pci_bus *bus);
739 enum pcie_bus_config_types {
742 PCIE_BUS_PERFORMANCE,
746 extern enum pcie_bus_config_types pcie_bus_config;
748 extern struct bus_type pci_bus_type;
750 /* Do NOT directly access these two variables, unless you are arch-specific PCI
751 * code, or PCI core code. */
752 extern struct list_head pci_root_buses; /* list of all known PCI buses */
753 /* Some device drivers need know if PCI is initiated */
754 int no_pci_devices(void);
756 void pcibios_resource_survey_bus(struct pci_bus *bus);
757 void pcibios_add_bus(struct pci_bus *bus);
758 void pcibios_remove_bus(struct pci_bus *bus);
759 void pcibios_fixup_bus(struct pci_bus *);
760 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
761 /* Architecture-specific versions may override this (weak) */
762 char *pcibios_setup(char *str);
764 /* Used only when drivers/pci/setup.c is used */
765 resource_size_t pcibios_align_resource(void *, const struct resource *,
768 void pcibios_update_irq(struct pci_dev *, int irq);
770 /* Weak but can be overriden by arch */
771 void pci_fixup_cardbus(struct pci_bus *);
773 /* Generic PCI functions used internally */
775 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
776 struct resource *res);
777 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
778 struct pci_bus_region *region);
779 void pcibios_scan_specific_bus(int busn);
780 struct pci_bus *pci_find_bus(int domain, int busnr);
781 void pci_bus_add_devices(const struct pci_bus *bus);
782 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
783 struct pci_ops *ops, void *sysdata);
784 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
785 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
786 struct pci_ops *ops, void *sysdata,
787 struct list_head *resources);
788 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
789 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
790 void pci_bus_release_busn_res(struct pci_bus *b);
791 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
792 struct pci_ops *ops, void *sysdata,
793 struct list_head *resources);
794 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
796 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
797 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
799 struct hotplug_slot *hotplug);
800 void pci_destroy_slot(struct pci_slot *slot);
801 int pci_scan_slot(struct pci_bus *bus, int devfn);
802 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
803 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
804 unsigned int pci_scan_child_bus(struct pci_bus *bus);
805 void pci_bus_add_device(struct pci_dev *dev);
806 void pci_read_bridge_bases(struct pci_bus *child);
807 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
808 struct resource *res);
809 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
810 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
811 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
812 struct pci_dev *pci_dev_get(struct pci_dev *dev);
813 void pci_dev_put(struct pci_dev *dev);
814 void pci_remove_bus(struct pci_bus *b);
815 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
816 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
817 void pci_stop_root_bus(struct pci_bus *bus);
818 void pci_remove_root_bus(struct pci_bus *bus);
819 void pci_setup_cardbus(struct pci_bus *bus);
820 void pci_sort_breadthfirst(void);
821 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
822 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
823 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
825 /* Generic PCI functions exported to card drivers */
827 enum pci_lost_interrupt_reason {
828 PCI_LOST_IRQ_NO_INFORMATION = 0,
829 PCI_LOST_IRQ_DISABLE_MSI,
830 PCI_LOST_IRQ_DISABLE_MSIX,
831 PCI_LOST_IRQ_DISABLE_ACPI,
833 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
834 int pci_find_capability(struct pci_dev *dev, int cap);
835 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
836 int pci_find_ext_capability(struct pci_dev *dev, int cap);
837 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
838 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
839 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
840 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
842 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
843 struct pci_dev *from);
844 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
845 unsigned int ss_vendor, unsigned int ss_device,
846 struct pci_dev *from);
847 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
848 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
850 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
853 return pci_get_domain_bus_and_slot(0, bus, devfn);
855 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
856 int pci_dev_present(const struct pci_device_id *ids);
858 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
860 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
861 int where, u16 *val);
862 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
863 int where, u32 *val);
864 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
866 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
868 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
871 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
872 int where, int size, u32 *val);
873 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
874 int where, int size, u32 val);
875 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
876 int where, int size, u32 *val);
877 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
878 int where, int size, u32 val);
880 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
882 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
884 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
886 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
888 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
890 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
893 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
895 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
897 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
899 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
901 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
903 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
906 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
909 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
910 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
911 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
912 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
913 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
915 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
918 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
921 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
924 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
927 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
930 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
933 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
936 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
939 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
942 /* user-space driven config access */
943 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
944 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
945 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
946 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
947 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
948 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
950 int __must_check pci_enable_device(struct pci_dev *dev);
951 int __must_check pci_enable_device_io(struct pci_dev *dev);
952 int __must_check pci_enable_device_mem(struct pci_dev *dev);
953 int __must_check pci_reenable_device(struct pci_dev *);
954 int __must_check pcim_enable_device(struct pci_dev *pdev);
955 void pcim_pin_device(struct pci_dev *pdev);
957 static inline int pci_is_enabled(struct pci_dev *pdev)
959 return (atomic_read(&pdev->enable_cnt) > 0);
962 static inline int pci_is_managed(struct pci_dev *pdev)
964 return pdev->is_managed;
967 void pci_disable_device(struct pci_dev *dev);
969 extern unsigned int pcibios_max_latency;
970 void pci_set_master(struct pci_dev *dev);
971 void pci_clear_master(struct pci_dev *dev);
973 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
974 int pci_set_cacheline_size(struct pci_dev *dev);
975 #define HAVE_PCI_SET_MWI
976 int __must_check pci_set_mwi(struct pci_dev *dev);
977 int pci_try_set_mwi(struct pci_dev *dev);
978 void pci_clear_mwi(struct pci_dev *dev);
979 void pci_intx(struct pci_dev *dev, int enable);
980 bool pci_intx_mask_supported(struct pci_dev *dev);
981 bool pci_check_and_mask_intx(struct pci_dev *dev);
982 bool pci_check_and_unmask_intx(struct pci_dev *dev);
983 void pci_msi_off(struct pci_dev *dev);
984 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
985 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
986 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
987 int pci_wait_for_pending_transaction(struct pci_dev *dev);
988 int pcix_get_max_mmrbc(struct pci_dev *dev);
989 int pcix_get_mmrbc(struct pci_dev *dev);
990 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
991 int pcie_get_readrq(struct pci_dev *dev);
992 int pcie_set_readrq(struct pci_dev *dev, int rq);
993 int pcie_get_mps(struct pci_dev *dev);
994 int pcie_set_mps(struct pci_dev *dev, int mps);
995 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
996 enum pcie_link_width *width);
997 int __pci_reset_function(struct pci_dev *dev);
998 int __pci_reset_function_locked(struct pci_dev *dev);
999 int pci_reset_function(struct pci_dev *dev);
1000 int pci_try_reset_function(struct pci_dev *dev);
1001 int pci_probe_reset_slot(struct pci_slot *slot);
1002 int pci_reset_slot(struct pci_slot *slot);
1003 int pci_try_reset_slot(struct pci_slot *slot);
1004 int pci_probe_reset_bus(struct pci_bus *bus);
1005 int pci_reset_bus(struct pci_bus *bus);
1006 int pci_try_reset_bus(struct pci_bus *bus);
1007 void pci_reset_secondary_bus(struct pci_dev *dev);
1008 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1009 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1010 void pci_update_resource(struct pci_dev *dev, int resno);
1011 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1012 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1013 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1014 bool pci_device_is_present(struct pci_dev *pdev);
1015 void pci_ignore_hotplug(struct pci_dev *dev);
1017 /* ROM control related routines */
1018 int pci_enable_rom(struct pci_dev *pdev);
1019 void pci_disable_rom(struct pci_dev *pdev);
1020 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1021 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1022 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1023 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1025 /* Power management related routines */
1026 int pci_save_state(struct pci_dev *dev);
1027 void pci_restore_state(struct pci_dev *dev);
1028 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1029 int pci_load_saved_state(struct pci_dev *dev,
1030 struct pci_saved_state *state);
1031 int pci_load_and_free_saved_state(struct pci_dev *dev,
1032 struct pci_saved_state **state);
1033 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1034 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1036 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1037 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1038 u16 cap, unsigned int size);
1039 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1040 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1041 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1042 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1043 void pci_pme_active(struct pci_dev *dev, bool enable);
1044 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1045 bool runtime, bool enable);
1046 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1047 int pci_prepare_to_sleep(struct pci_dev *dev);
1048 int pci_back_from_sleep(struct pci_dev *dev);
1049 bool pci_dev_run_wake(struct pci_dev *dev);
1050 bool pci_check_pme_status(struct pci_dev *dev);
1051 void pci_pme_wakeup_bus(struct pci_bus *bus);
1053 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1056 return __pci_enable_wake(dev, state, false, enable);
1059 /* PCI Virtual Channel */
1060 int pci_save_vc_state(struct pci_dev *dev);
1061 void pci_restore_vc_state(struct pci_dev *dev);
1062 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1064 /* For use by arch with custom probe code */
1065 void set_pcie_port_type(struct pci_dev *pdev);
1066 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1068 /* Functions for PCI Hotplug drivers to use */
1069 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1070 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1071 unsigned int pci_rescan_bus(struct pci_bus *bus);
1072 void pci_lock_rescan_remove(void);
1073 void pci_unlock_rescan_remove(void);
1075 /* Vital product data routines */
1076 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1077 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1079 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1080 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1081 void pci_bus_assign_resources(const struct pci_bus *bus);
1082 void pci_bus_size_bridges(struct pci_bus *bus);
1083 int pci_claim_resource(struct pci_dev *, int);
1084 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1085 void pci_assign_unassigned_resources(void);
1086 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1087 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1088 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1089 void pdev_enable_device(struct pci_dev *);
1090 int pci_enable_resources(struct pci_dev *, int mask);
1091 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1092 int (*)(const struct pci_dev *, u8, u8));
1093 #define HAVE_PCI_REQ_REGIONS 2
1094 int __must_check pci_request_regions(struct pci_dev *, const char *);
1095 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1096 void pci_release_regions(struct pci_dev *);
1097 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1098 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1099 void pci_release_region(struct pci_dev *, int);
1100 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1101 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1102 void pci_release_selected_regions(struct pci_dev *, int);
1104 /* drivers/pci/bus.c */
1105 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1106 void pci_bus_put(struct pci_bus *bus);
1107 void pci_add_resource(struct list_head *resources, struct resource *res);
1108 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1109 resource_size_t offset);
1110 void pci_free_resource_list(struct list_head *resources);
1111 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1112 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1113 void pci_bus_remove_resources(struct pci_bus *bus);
1115 #define pci_bus_for_each_resource(bus, res, i) \
1117 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1120 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1121 struct resource *res, resource_size_t size,
1122 resource_size_t align, resource_size_t min,
1123 unsigned long type_mask,
1124 resource_size_t (*alignf)(void *,
1125 const struct resource *,
1131 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1133 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1135 struct pci_bus_region region;
1137 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1138 return region.start;
1141 /* Proper probing supporting hot-pluggable devices */
1142 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1143 const char *mod_name);
1146 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1148 #define pci_register_driver(driver) \
1149 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1151 void pci_unregister_driver(struct pci_driver *dev);
1154 * module_pci_driver() - Helper macro for registering a PCI driver
1155 * @__pci_driver: pci_driver struct
1157 * Helper macro for PCI drivers which do not do anything special in module
1158 * init/exit. This eliminates a lot of boilerplate. Each module may only
1159 * use this macro once, and calling it replaces module_init() and module_exit()
1161 #define module_pci_driver(__pci_driver) \
1162 module_driver(__pci_driver, pci_register_driver, \
1163 pci_unregister_driver)
1165 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1166 int pci_add_dynid(struct pci_driver *drv,
1167 unsigned int vendor, unsigned int device,
1168 unsigned int subvendor, unsigned int subdevice,
1169 unsigned int class, unsigned int class_mask,
1170 unsigned long driver_data);
1171 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1172 struct pci_dev *dev);
1173 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1176 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1178 int pci_cfg_space_size(struct pci_dev *dev);
1179 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1180 void pci_setup_bridge(struct pci_bus *bus);
1181 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1182 unsigned long type);
1183 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1185 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1186 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1188 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1189 unsigned int command_bits, u32 flags);
1190 /* kmem_cache style wrapper around pci_alloc_consistent() */
1192 #include <linux/pci-dma.h>
1193 #include <linux/dmapool.h>
1195 #define pci_pool dma_pool
1196 #define pci_pool_create(name, pdev, size, align, allocation) \
1197 dma_pool_create(name, &pdev->dev, size, align, allocation)
1198 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1199 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1200 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1202 enum pci_dma_burst_strategy {
1203 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1204 strategy_parameter is N/A */
1205 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1207 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1208 strategy_parameter byte boundaries */
1212 u32 vector; /* kernel uses to write allocated vector */
1213 u16 entry; /* driver uses to specify entry, OS writes */
1217 #ifdef CONFIG_PCI_MSI
1218 int pci_msi_vec_count(struct pci_dev *dev);
1219 void pci_msi_shutdown(struct pci_dev *dev);
1220 void pci_disable_msi(struct pci_dev *dev);
1221 int pci_msix_vec_count(struct pci_dev *dev);
1222 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1223 void pci_msix_shutdown(struct pci_dev *dev);
1224 void pci_disable_msix(struct pci_dev *dev);
1225 void pci_restore_msi_state(struct pci_dev *dev);
1226 int pci_msi_enabled(void);
1227 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1228 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1230 int rc = pci_enable_msi_range(dev, nvec, nvec);
1235 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1236 int minvec, int maxvec);
1237 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1238 struct msix_entry *entries, int nvec)
1240 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1246 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1247 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1248 static inline void pci_disable_msi(struct pci_dev *dev) { }
1249 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1250 static inline int pci_enable_msix(struct pci_dev *dev,
1251 struct msix_entry *entries, int nvec)
1253 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1254 static inline void pci_disable_msix(struct pci_dev *dev) { }
1255 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1256 static inline int pci_msi_enabled(void) { return 0; }
1257 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1260 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1262 static inline int pci_enable_msix_range(struct pci_dev *dev,
1263 struct msix_entry *entries, int minvec, int maxvec)
1265 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1266 struct msix_entry *entries, int nvec)
1270 #ifdef CONFIG_PCIEPORTBUS
1271 extern bool pcie_ports_disabled;
1272 extern bool pcie_ports_auto;
1274 #define pcie_ports_disabled true
1275 #define pcie_ports_auto false
1278 #ifdef CONFIG_PCIEASPM
1279 bool pcie_aspm_support_enabled(void);
1281 static inline bool pcie_aspm_support_enabled(void) { return false; }
1284 #ifdef CONFIG_PCIEAER
1285 void pci_no_aer(void);
1286 bool pci_aer_available(void);
1288 static inline void pci_no_aer(void) { }
1289 static inline bool pci_aer_available(void) { return false; }
1292 #ifdef CONFIG_PCIE_ECRC
1293 void pcie_set_ecrc_checking(struct pci_dev *dev);
1294 void pcie_ecrc_get_policy(char *str);
1296 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1297 static inline void pcie_ecrc_get_policy(char *str) { }
1300 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1302 #ifdef CONFIG_HT_IRQ
1303 /* The functions a driver should call */
1304 int ht_create_irq(struct pci_dev *dev, int idx);
1305 void ht_destroy_irq(unsigned int irq);
1306 #endif /* CONFIG_HT_IRQ */
1308 void pci_cfg_access_lock(struct pci_dev *dev);
1309 bool pci_cfg_access_trylock(struct pci_dev *dev);
1310 void pci_cfg_access_unlock(struct pci_dev *dev);
1313 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1314 * a PCI domain is defined to be a set of PCI buses which share
1315 * configuration space.
1317 #ifdef CONFIG_PCI_DOMAINS
1318 extern int pci_domains_supported;
1319 int pci_get_new_domain_nr(void);
1321 enum { pci_domains_supported = 0 };
1322 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1323 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1324 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1325 #endif /* CONFIG_PCI_DOMAINS */
1328 * Generic implementation for PCI domain support. If your
1329 * architecture does not need custom management of PCI
1330 * domains then this implementation will be used
1332 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1333 static inline int pci_domain_nr(struct pci_bus *bus)
1335 return bus->domain_nr;
1337 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1339 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1340 struct device *parent)
1345 /* some architectures require additional setup to direct VGA traffic */
1346 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1347 unsigned int command_bits, u32 flags);
1348 void pci_register_set_vga_state(arch_set_vga_state_t func);
1350 #else /* CONFIG_PCI is not enabled */
1353 * If the system does not have PCI, clearly these return errors. Define
1354 * these as simple inline functions to avoid hair in drivers.
1357 #define _PCI_NOP(o, s, t) \
1358 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1360 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1362 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1363 _PCI_NOP(o, word, u16 x) \
1364 _PCI_NOP(o, dword, u32 x)
1365 _PCI_NOP_ALL(read, *)
1366 _PCI_NOP_ALL(write,)
1368 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1369 unsigned int device,
1370 struct pci_dev *from)
1373 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1374 unsigned int device,
1375 unsigned int ss_vendor,
1376 unsigned int ss_device,
1377 struct pci_dev *from)
1380 static inline struct pci_dev *pci_get_class(unsigned int class,
1381 struct pci_dev *from)
1384 #define pci_dev_present(ids) (0)
1385 #define no_pci_devices() (1)
1386 #define pci_dev_put(dev) do { } while (0)
1388 static inline void pci_set_master(struct pci_dev *dev) { }
1389 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1390 static inline void pci_disable_device(struct pci_dev *dev) { }
1391 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1393 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1395 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1398 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1401 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1403 static inline int __pci_register_driver(struct pci_driver *drv,
1404 struct module *owner)
1406 static inline int pci_register_driver(struct pci_driver *drv)
1408 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1409 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1411 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1414 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1417 /* Power management related routines */
1418 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1419 static inline void pci_restore_state(struct pci_dev *dev) { }
1420 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1422 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1424 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1427 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1431 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1433 static inline void pci_release_regions(struct pci_dev *dev) { }
1435 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1437 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1438 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1440 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1442 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1444 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1447 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1451 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1452 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1453 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1455 #define dev_is_pci(d) (false)
1456 #define dev_is_pf(d) (false)
1457 #define dev_num_vf(d) (0)
1458 #endif /* CONFIG_PCI */
1460 /* Include architecture-dependent settings and functions */
1462 #include <asm/pci.h>
1464 /* these helpers provide future and backwards compatibility
1465 * for accessing popular PCI BAR info */
1466 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1467 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1468 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1469 #define pci_resource_len(dev,bar) \
1470 ((pci_resource_start((dev), (bar)) == 0 && \
1471 pci_resource_end((dev), (bar)) == \
1472 pci_resource_start((dev), (bar))) ? 0 : \
1474 (pci_resource_end((dev), (bar)) - \
1475 pci_resource_start((dev), (bar)) + 1))
1477 /* Similar to the helpers above, these manipulate per-pci_dev
1478 * driver-specific data. They are really just a wrapper around
1479 * the generic device structure functions of these calls.
1481 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1483 return dev_get_drvdata(&pdev->dev);
1486 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1488 dev_set_drvdata(&pdev->dev, data);
1491 /* If you want to know what to call your pci_dev, ask this function.
1492 * Again, it's a wrapper around the generic device.
1494 static inline const char *pci_name(const struct pci_dev *pdev)
1496 return dev_name(&pdev->dev);
1500 /* Some archs don't want to expose struct resource to userland as-is
1501 * in sysfs and /proc
1503 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1504 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1505 const struct resource *rsrc, resource_size_t *start,
1506 resource_size_t *end)
1508 *start = rsrc->start;
1511 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1515 * The world is not perfect and supplies us with broken PCI devices.
1516 * For at least a part of these bugs we need a work-around, so both
1517 * generic (drivers/pci/quirks.c) and per-architecture code can define
1518 * fixup hooks to be called for particular buggy devices.
1522 u16 vendor; /* You can use PCI_ANY_ID here of course */
1523 u16 device; /* You can use PCI_ANY_ID here of course */
1524 u32 class; /* You can use PCI_ANY_ID here too */
1525 unsigned int class_shift; /* should be 0, 8, 16 */
1526 void (*hook)(struct pci_dev *dev);
1529 enum pci_fixup_pass {
1530 pci_fixup_early, /* Before probing BARs */
1531 pci_fixup_header, /* After reading configuration header */
1532 pci_fixup_final, /* Final phase of device fixups */
1533 pci_fixup_enable, /* pci_enable_device() time */
1534 pci_fixup_resume, /* pci_device_resume() */
1535 pci_fixup_suspend, /* pci_device_suspend() */
1536 pci_fixup_resume_early, /* pci_device_resume_early() */
1537 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1540 /* Anonymous variables would be nice... */
1541 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1542 class_shift, hook) \
1543 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1544 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1545 = { vendor, device, class, class_shift, hook };
1547 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1548 class_shift, hook) \
1549 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1550 hook, vendor, device, class, class_shift, hook)
1551 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1552 class_shift, hook) \
1553 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1554 hook, vendor, device, class, class_shift, hook)
1555 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1556 class_shift, hook) \
1557 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1558 hook, vendor, device, class, class_shift, hook)
1559 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1560 class_shift, hook) \
1561 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1562 hook, vendor, device, class, class_shift, hook)
1563 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1564 class_shift, hook) \
1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1566 resume##hook, vendor, device, class, \
1568 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1569 class_shift, hook) \
1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1571 resume_early##hook, vendor, device, \
1572 class, class_shift, hook)
1573 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1574 class_shift, hook) \
1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1576 suspend##hook, vendor, device, class, \
1578 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1579 class_shift, hook) \
1580 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1581 suspend_late##hook, vendor, device, \
1582 class, class_shift, hook)
1584 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1586 hook, vendor, device, PCI_ANY_ID, 0, hook)
1587 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1589 hook, vendor, device, PCI_ANY_ID, 0, hook)
1590 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1591 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1592 hook, vendor, device, PCI_ANY_ID, 0, hook)
1593 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1594 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1595 hook, vendor, device, PCI_ANY_ID, 0, hook)
1596 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1597 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1598 resume##hook, vendor, device, \
1599 PCI_ANY_ID, 0, hook)
1600 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1601 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1602 resume_early##hook, vendor, device, \
1603 PCI_ANY_ID, 0, hook)
1604 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1605 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1606 suspend##hook, vendor, device, \
1607 PCI_ANY_ID, 0, hook)
1608 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1609 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1610 suspend_late##hook, vendor, device, \
1611 PCI_ANY_ID, 0, hook)
1613 #ifdef CONFIG_PCI_QUIRKS
1614 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1615 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1616 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1618 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1619 struct pci_dev *dev) { }
1620 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1625 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1628 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1629 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1630 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1631 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1632 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1634 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1636 extern int pci_pci_problems;
1637 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1638 #define PCIPCI_TRITON 2
1639 #define PCIPCI_NATOMA 4
1640 #define PCIPCI_VIAETBF 8
1641 #define PCIPCI_VSFX 16
1642 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1643 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1645 extern unsigned long pci_cardbus_io_size;
1646 extern unsigned long pci_cardbus_mem_size;
1647 extern u8 pci_dfl_cache_line_size;
1648 extern u8 pci_cache_line_size;
1650 extern unsigned long pci_hotplug_io_size;
1651 extern unsigned long pci_hotplug_mem_size;
1653 /* Architecture-specific versions may override these (weak) */
1654 void pcibios_disable_device(struct pci_dev *dev);
1655 void pcibios_set_master(struct pci_dev *dev);
1656 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1657 enum pcie_reset_state state);
1658 int pcibios_add_device(struct pci_dev *dev);
1659 void pcibios_release_device(struct pci_dev *dev);
1660 void pcibios_penalize_isa_irq(int irq, int active);
1662 #ifdef CONFIG_HIBERNATE_CALLBACKS
1663 extern struct dev_pm_ops pcibios_pm_ops;
1666 #ifdef CONFIG_PCI_MMCONFIG
1667 void __init pci_mmcfg_early_init(void);
1668 void __init pci_mmcfg_late_init(void);
1670 static inline void pci_mmcfg_early_init(void) { }
1671 static inline void pci_mmcfg_late_init(void) { }
1674 int pci_ext_cfg_avail(void);
1676 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1678 #ifdef CONFIG_PCI_IOV
1679 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1680 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1682 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1683 void pci_disable_sriov(struct pci_dev *dev);
1684 int pci_num_vf(struct pci_dev *dev);
1685 int pci_vfs_assigned(struct pci_dev *dev);
1686 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1687 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1688 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1690 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1694 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1698 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1700 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1701 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1702 static inline int pci_vfs_assigned(struct pci_dev *dev)
1704 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1706 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1708 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1712 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1713 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1714 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1718 * pci_pcie_cap - get the saved PCIe capability offset
1721 * PCIe capability offset is calculated at PCI device initialization
1722 * time and saved in the data structure. This function returns saved
1723 * PCIe capability offset. Using this instead of pci_find_capability()
1724 * reduces unnecessary search in the PCI configuration space. If you
1725 * need to calculate PCIe capability offset from raw device for some
1726 * reasons, please use pci_find_capability() instead.
1728 static inline int pci_pcie_cap(struct pci_dev *dev)
1730 return dev->pcie_cap;
1734 * pci_is_pcie - check if the PCI device is PCI Express capable
1737 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1739 static inline bool pci_is_pcie(struct pci_dev *dev)
1741 return pci_pcie_cap(dev);
1745 * pcie_caps_reg - get the PCIe Capabilities Register
1748 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1750 return dev->pcie_flags_reg;
1754 * pci_pcie_type - get the PCIe device/port type
1757 static inline int pci_pcie_type(const struct pci_dev *dev)
1759 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1762 void pci_request_acs(void);
1763 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1764 bool pci_acs_path_enabled(struct pci_dev *start,
1765 struct pci_dev *end, u16 acs_flags);
1767 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1768 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1770 /* Large Resource Data Type Tag Item Names */
1771 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1772 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1773 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1775 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1776 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1777 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1779 /* Small Resource Data Type Tag Item Names */
1780 #define PCI_VPD_STIN_END 0x78 /* End */
1782 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1784 #define PCI_VPD_SRDT_TIN_MASK 0x78
1785 #define PCI_VPD_SRDT_LEN_MASK 0x07
1787 #define PCI_VPD_LRDT_TAG_SIZE 3
1788 #define PCI_VPD_SRDT_TAG_SIZE 1
1790 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1792 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1793 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1794 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1795 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1798 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1799 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1801 * Returns the extracted Large Resource Data Type length.
1803 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1805 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1809 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1810 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1812 * Returns the extracted Small Resource Data Type length.
1814 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1816 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1820 * pci_vpd_info_field_size - Extracts the information field length
1821 * @lrdt: Pointer to the beginning of an information field header
1823 * Returns the extracted information field length.
1825 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1827 return info_field[2];
1831 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1832 * @buf: Pointer to buffered vpd data
1833 * @off: The offset into the buffer at which to begin the search
1834 * @len: The length of the vpd buffer
1835 * @rdt: The Resource Data Type to search for
1837 * Returns the index where the Resource Data Type was found or
1838 * -ENOENT otherwise.
1840 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1843 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1844 * @buf: Pointer to buffered vpd data
1845 * @off: The offset into the buffer at which to begin the search
1846 * @len: The length of the buffer area, relative to off, in which to search
1847 * @kw: The keyword to search for
1849 * Returns the index where the information field keyword was found or
1850 * -ENOENT otherwise.
1852 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1853 unsigned int len, const char *kw);
1855 /* PCI <-> OF binding helpers */
1858 void pci_set_of_node(struct pci_dev *dev);
1859 void pci_release_of_node(struct pci_dev *dev);
1860 void pci_set_bus_of_node(struct pci_bus *bus);
1861 void pci_release_bus_of_node(struct pci_bus *bus);
1863 /* Arch may override this (weak) */
1864 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1866 static inline struct device_node *
1867 pci_device_to_OF_node(const struct pci_dev *pdev)
1869 return pdev ? pdev->dev.of_node : NULL;
1872 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1874 return bus ? bus->dev.of_node : NULL;
1877 #else /* CONFIG_OF */
1878 static inline void pci_set_of_node(struct pci_dev *dev) { }
1879 static inline void pci_release_of_node(struct pci_dev *dev) { }
1880 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1881 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1882 static inline struct device_node *
1883 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1884 #endif /* CONFIG_OF */
1887 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1889 return pdev->dev.archdata.edev;
1893 int pci_for_each_dma_alias(struct pci_dev *pdev,
1894 int (*fn)(struct pci_dev *pdev,
1895 u16 alias, void *data), void *data);
1897 /* helper functions for operation of device flag */
1898 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
1900 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
1902 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
1904 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
1906 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
1908 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
1910 #endif /* LINUX_PCI_H */