2 * DA9055 declarations for DA9055 PMICs.
4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
6 * Author: David Dajun Chen <dchen@diasemi.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __DA9055_REG_H
25 #define __DA9055_REG_H
31 #define DA9055_REG_PAGE_CON 0x00
33 /* System Control and Event Registers */
34 #define DA9055_REG_STATUS_A 0x01
35 #define DA9055_REG_STATUS_B 0x02
36 #define DA9055_REG_FAULT_LOG 0x03
37 #define DA9055_REG_EVENT_A 0x04
38 #define DA9055_REG_EVENT_B 0x05
39 #define DA9055_REG_EVENT_C 0x06
40 #define DA9055_REG_IRQ_MASK_A 0x07
41 #define DA9055_REG_IRQ_MASK_B 0x08
42 #define DA9055_REG_IRQ_MASK_C 0x09
43 #define DA9055_REG_CONTROL_A 0x0A
44 #define DA9055_REG_CONTROL_B 0x0B
45 #define DA9055_REG_CONTROL_C 0x0C
46 #define DA9055_REG_CONTROL_D 0x0D
47 #define DA9055_REG_CONTROL_E 0x0E
48 #define DA9055_REG_PD_DIS 0x0F
50 /* GPIO Control Registers */
51 #define DA9055_REG_GPIO0_1 0x10
52 #define DA9055_REG_GPIO2 0x11
53 #define DA9055_REG_GPIO_MODE0_2 0x12
55 /* Regulator Control Registers */
56 #define DA9055_REG_BCORE_CONT 0x13
57 #define DA9055_REG_BMEM_CONT 0x14
58 #define DA9055_REG_LDO1_CONT 0x15
59 #define DA9055_REG_LDO2_CONT 0x16
60 #define DA9055_REG_LDO3_CONT 0x17
61 #define DA9055_REG_LDO4_CONT 0x18
62 #define DA9055_REG_LDO5_CONT 0x19
63 #define DA9055_REG_LDO6_CONT 0x1A
65 /* GP-ADC Control Registers */
66 #define DA9055_REG_ADC_MAN 0x1B
67 #define DA9055_REG_ADC_CONT 0x1C
68 #define DA9055_REG_VSYS_MON 0x1D
69 #define DA9055_REG_ADC_RES_L 0x1E
70 #define DA9055_REG_ADC_RES_H 0x1F
71 #define DA9055_REG_VSYS_RES 0x20
72 #define DA9055_REG_ADCIN1_RES 0x21
73 #define DA9055_REG_ADCIN2_RES 0x22
74 #define DA9055_REG_ADCIN3_RES 0x23
76 /* Sequencer Control Registers */
77 #define DA9055_REG_EN_32K 0x35
79 /* Regulator Setting Registers */
80 #define DA9055_REG_BUCK_LIM 0x37
81 #define DA9055_REG_BCORE_MODE 0x38
82 #define DA9055_REG_VBCORE_A 0x39
83 #define DA9055_REG_VBMEM_A 0x3A
84 #define DA9055_REG_VLDO1_A 0x3B
85 #define DA9055_REG_VLDO2_A 0x3C
86 #define DA9055_REG_VLDO3_A 0x3D
87 #define DA9055_REG_VLDO4_A 0x3E
88 #define DA9055_REG_VLDO5_A 0x3F
89 #define DA9055_REG_VLDO6_A 0x40
90 #define DA9055_REG_VBCORE_B 0x41
91 #define DA9055_REG_VBMEM_B 0x42
92 #define DA9055_REG_VLDO1_B 0x43
93 #define DA9055_REG_VLDO2_B 0x44
94 #define DA9055_REG_VLDO3_B 0x45
95 #define DA9055_REG_VLDO4_B 0x46
96 #define DA9055_REG_VLDO5_B 0x47
97 #define DA9055_REG_VLDO6_B 0x48
99 /* GP-ADC Threshold Registers */
100 #define DA9055_REG_AUTO1_HIGH 0x49
101 #define DA9055_REG_AUTO1_LOW 0x4A
102 #define DA9055_REG_AUTO2_HIGH 0x4B
103 #define DA9055_REG_AUTO2_LOW 0x4C
104 #define DA9055_REG_AUTO3_HIGH 0x4D
105 #define DA9055_REG_AUTO3_LOW 0x4E
108 #define DA9055_REG_OPT_COUNT 0x50
109 #define DA9055_REG_OPT_ADDR 0x51
110 #define DA9055_REG_OPT_DATA 0x52
112 /* RTC Calendar and Alarm Registers */
113 #define DA9055_REG_COUNT_S 0x53
114 #define DA9055_REG_COUNT_MI 0x54
115 #define DA9055_REG_COUNT_H 0x55
116 #define DA9055_REG_COUNT_D 0x56
117 #define DA9055_REG_COUNT_MO 0x57
118 #define DA9055_REG_COUNT_Y 0x58
119 #define DA9055_REG_ALARM_MI 0x59
120 #define DA9055_REG_ALARM_H 0x5A
121 #define DA9055_REG_ALARM_D 0x5B
122 #define DA9055_REG_ALARM_MO 0x5C
123 #define DA9055_REG_ALARM_Y 0x5D
124 #define DA9055_REG_SECOND_A 0x5E
125 #define DA9055_REG_SECOND_B 0x5F
126 #define DA9055_REG_SECOND_C 0x60
127 #define DA9055_REG_SECOND_D 0x61
129 /* Customer Trim and Configuration */
130 #define DA9055_REG_T_OFFSET 0x63
131 #define DA9055_REG_INTERFACE 0x64
132 #define DA9055_REG_CONFIG_A 0x65
133 #define DA9055_REG_CONFIG_B 0x66
134 #define DA9055_REG_CONFIG_C 0x67
135 #define DA9055_REG_CONFIG_D 0x68
136 #define DA9055_REG_CONFIG_E 0x69
137 #define DA9055_REG_TRIM_CLDR 0x6F
139 /* General Purpose Registers */
140 #define DA9055_REG_GP_ID_0 0x70
141 #define DA9055_REG_GP_ID_1 0x71
142 #define DA9055_REG_GP_ID_2 0x72
143 #define DA9055_REG_GP_ID_3 0x73
144 #define DA9055_REG_GP_ID_4 0x74
145 #define DA9055_REG_GP_ID_5 0x75
146 #define DA9055_REG_GP_ID_6 0x76
147 #define DA9055_REG_GP_ID_7 0x77
148 #define DA9055_REG_GP_ID_8 0x78
149 #define DA9055_REG_GP_ID_9 0x79
150 #define DA9055_REG_GP_ID_10 0x7A
151 #define DA9055_REG_GP_ID_11 0x7B
152 #define DA9055_REG_GP_ID_12 0x7C
153 #define DA9055_REG_GP_ID_13 0x7D
154 #define DA9055_REG_GP_ID_14 0x7E
155 #define DA9055_REG_GP_ID_15 0x7F
156 #define DA9055_REG_GP_ID_16 0x80
157 #define DA9055_REG_GP_ID_17 0x81
158 #define DA9055_REG_GP_ID_18 0x82
159 #define DA9055_REG_GP_ID_19 0x83
161 #define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19
164 * PMIC registers bits
167 /* DA9055_REG_PAGE_CON (addr=0x00) */
168 #define DA9055_PAGE_WRITE_MODE (0<<6)
169 #define DA9055_REPEAT_WRITE_MODE (1<<6)
171 /* DA9055_REG_STATUS_A (addr=0x01) */
172 #define DA9055_NOKEY_STS 0x01
173 #define DA9055_WAKE_STS 0x02
174 #define DA9055_DVC_BUSY_STS 0x04
175 #define DA9055_COMP1V2_STS 0x08
176 #define DA9055_NJIG_STS 0x10
177 #define DA9055_LDO5_LIM_STS 0x20
178 #define DA9055_LDO6_LIM_STS 0x40
180 /* DA9055_REG_STATUS_B (addr=0x02) */
181 #define DA9055_GPI0_STS 0x01
182 #define DA9055_GPI1_STS 0x02
183 #define DA9055_GPI2_STS 0x04
185 /* DA9055_REG_FAULT_LOG (addr=0x03) */
186 #define DA9055_TWD_ERROR_FLG 0x01
187 #define DA9055_POR_FLG 0x02
188 #define DA9055_VDD_FAULT_FLG 0x04
189 #define DA9055_VDD_START_FLG 0x08
190 #define DA9055_TEMP_CRIT_FLG 0x10
191 #define DA9055_KEY_RESET_FLG 0x20
192 #define DA9055_WAIT_SHUT_FLG 0x80
194 /* DA9055_REG_EVENT_A (addr=0x04) */
195 #define DA9055_NOKEY_EINT 0x01
196 #define DA9055_ALARM_EINT 0x02
197 #define DA9055_TICK_EINT 0x04
198 #define DA9055_ADC_RDY_EINT 0x08
199 #define DA9055_SEQ_RDY_EINT 0x10
200 #define DA9055_EVENTS_B_EINT 0x20
201 #define DA9055_EVENTS_C_EINT 0x40
203 /* DA9055_REG_EVENT_B (addr=0x05) */
204 #define DA9055_E_WAKE_EINT 0x01
205 #define DA9055_E_TEMP_EINT 0x02
206 #define DA9055_E_COMP1V2_EINT 0x04
207 #define DA9055_E_LDO_LIM_EINT 0x08
208 #define DA9055_E_NJIG_EINT 0x20
209 #define DA9055_E_VDD_MON_EINT 0x40
210 #define DA9055_E_VDD_WARN_EINT 0x80
212 /* DA9055_REG_EVENT_C (addr=0x06) */
213 #define DA9055_E_GPI0_EINT 0x01
214 #define DA9055_E_GPI1_EINT 0x02
215 #define DA9055_E_GPI2_EINT 0x04
217 /* DA9055_REG_IRQ_MASK_A (addr=0x07) */
218 #define DA9055_M_NONKEY_EINT 0x01
219 #define DA9055_M_ALARM_EINT 0x02
220 #define DA9055_M_TICK_EINT 0x04
221 #define DA9055_M_ADC_RDY_EINT 0x08
222 #define DA9055_M_SEQ_RDY_EINT 0x10
224 /* DA9055_REG_IRQ_MASK_B (addr=0x08) */
225 #define DA9055_M_WAKE_EINT 0x01
226 #define DA9055_M_TEMP_EINT 0x02
227 #define DA9055_M_COMP_1V2_EINT 0x04
228 #define DA9055_M_LDO_LIM_EINT 0x08
229 #define DA9055_M_NJIG_EINT 0x20
230 #define DA9055_M_VDD_MON_EINT 0x40
231 #define DA9055_M_VDD_WARN_EINT 0x80
233 /* DA9055_REG_IRQ_MASK_C (addr=0x09) */
234 #define DA9055_M_GPI0_EINT 0x01
235 #define DA9055_M_GPI1_EINT 0x02
236 #define DA9055_M_GPI2_EINT 0x04
238 /* DA9055_REG_CONTROL_A (addr=0xA) */
239 #define DA9055_DEBOUNCING_SHIFT 0x00
240 #define DA9055_DEBOUNCING_MASK 0x07
241 #define DA9055_NRES_MODE_SHIFT 0x03
242 #define DA9055_NRES_MODE_MASK 0x08
243 #define DA9055_SLEW_RATE_SHIFT 0x04
244 #define DA9055_SLEW_RATE_MASK 0x30
245 #define DA9055_NOKEY_LOCK_SHIFT 0x06
246 #define DA9055_NOKEY_LOCK_MASK 0x40
248 /* DA9055_REG_CONTROL_B (addr=0xB) */
249 #define DA9055_RTC_MODE_PD 0x01
250 #define DA9055_RTC_MODE_SD_SHIFT 0x01
251 #define DA9055_RTC_MODE_SD 0x02
252 #define DA9055_RTC_EN 0x04
253 #define DA9055_ECO_MODE_SHIFT 0x03
254 #define DA9055_ECO_MODE_MASK 0x08
255 #define DA9055_TWDSCALE_SHIFT 4
256 #define DA9055_TWDSCALE_MASK 0x70
257 #define DA9055_V_LOCK_SHIFT 0x07
258 #define DA9055_V_LOCK_MASK 0x80
260 /* DA9055_REG_CONTROL_C (addr=0xC) */
261 #define DA9055_SYSTEM_EN_SHIFT 0x00
262 #define DA9055_SYSTEM_EN_MASK 0x01
263 #define DA9055_POWERN_EN_SHIFT 0x01
264 #define DA9055_POWERN_EN_MASK 0x02
265 #define DA9055_POWER1_EN_SHIFT 0x02
266 #define DA9055_POWER1_EN_MASK 0x04
268 /* DA9055_REG_CONTROL_D (addr=0xD) */
269 #define DA9055_STANDBY_SHIFT 0x02
270 #define DA9055_STANDBY_MASK 0x08
271 #define DA9055_AUTO_BOOT_SHIFT 0x03
272 #define DA9055_AUTO_BOOT_MASK 0x04
274 /* DA9055_REG_CONTROL_E (addr=0xE) */
275 #define DA9055_WATCHDOG_SHIFT 0x00
276 #define DA9055_WATCHDOG_MASK 0x01
277 #define DA9055_SHUTDOWN_SHIFT 0x01
278 #define DA9055_SHUTDOWN_MASK 0x02
279 #define DA9055_WAKE_UP_SHIFT 0x02
280 #define DA9055_WAKE_UP_MASK 0x04
282 /* DA9055_REG_GPIO (addr=0x10/0x11) */
283 #define DA9055_GPIO0_PIN_SHIFT 0x00
284 #define DA9055_GPIO0_PIN_MASK 0x03
285 #define DA9055_GPIO0_TYPE_SHIFT 0x02
286 #define DA9055_GPIO0_TYPE_MASK 0x04
287 #define DA9055_GPIO0_WEN_SHIFT 0x03
288 #define DA9055_GPIO0_WEN_MASK 0x08
289 #define DA9055_GPIO1_PIN_SHIFT 0x04
290 #define DA9055_GPIO1_PIN_MASK 0x30
291 #define DA9055_GPIO1_TYPE_SHIFT 0x06
292 #define DA9055_GPIO1_TYPE_MASK 0x40
293 #define DA9055_GPIO1_WEN_SHIFT 0x07
294 #define DA9055_GPIO1_WEN_MASK 0x80
295 #define DA9055_GPIO2_PIN_SHIFT 0x00
296 #define DA9055_GPIO2_PIN_MASK 0x30
297 #define DA9055_GPIO2_TYPE_SHIFT 0x02
298 #define DA9055_GPIO2_TYPE_MASK 0x04
299 #define DA9055_GPIO2_WEN_SHIFT 0x03
300 #define DA9055_GPIO2_WEN_MASK 0x08
302 /* DA9055_REG_GPIO_MODE (addr=0x12) */
303 #define DA9055_GPIO0_MODE_SHIFT 0x00
304 #define DA9055_GPIO0_MODE_MASK 0x01
305 #define DA9055_GPIO1_MODE_SHIFT 0x01
306 #define DA9055_GPIO1_MODE_MASK 0x02
307 #define DA9055_GPIO2_MODE_SHIFT 0x02
308 #define DA9055_GPIO2_MODE_MASK 0x04
310 /* DA9055_REG_BCORE_CONT (addr=0x13) */
311 #define DA9055_BCORE_EN_SHIFT 0x00
312 #define DA9055_BCORE_EN_MASK 0x01
313 #define DA9055_BCORE_GPI_SHIFT 0x01
314 #define DA9055_BCORE_GPI_MASK 0x02
315 #define DA9055_BCORE_PD_DIS_SHIFT 0x03
316 #define DA9055_BCORE_PD_DIS_MASK 0x04
317 #define DA9055_VBCORE_SEL_SHIFT 0x04
318 #define DA9055_SEL_REG_A 0x0
319 #define DA9055_SEL_REG_B 0x10
320 #define DA9055_VBCORE_SEL_MASK 0x10
321 #define DA9055_V_GPI_MASK 0x60
322 #define DA9055_V_GPI_SHIFT 0x05
323 #define DA9055_E_GPI_MASK 0x06
324 #define DA9055_E_GPI_SHIFT 0x01
325 #define DA9055_VBCORE_GPI_SHIFT 0x05
326 #define DA9055_VBCORE_GPI_MASK 0x60
327 #define DA9055_BCORE_CONF_SHIFT 0x07
328 #define DA9055_BCORE_CONF_MASK 0x80
330 /* DA9055_REG_BMEM_CONT (addr=0x14) */
331 #define DA9055_BMEM_EN_SHIFT 0x00
332 #define DA9055_BMEM_EN_MASK 0x01
333 #define DA9055_BMEM_GPI_SHIFT 0x01
334 #define DA9055_BMEM_GPI_MASK 0x06
335 #define DA9055_BMEM_PD_DIS_SHIFT 0x03
336 #define DA9055_BMEM_PD_DIS_MASK 0x08
337 #define DA9055_VBMEM_SEL_SHIT 0x04
338 #define DA9055_VBMEM_SEL_VBMEM_A (0<<4)
339 #define DA9055_VBMEM_SEL_VBMEM_B (1<<4)
340 #define DA9055_VBMEM_SEL_MASK 0x10
341 #define DA9055_VBMEM_GPI_SHIFT 0x05
342 #define DA9055_VBMEM_GPI_MASK 0x60
343 #define DA9055_BMEM_CONF_SHIFT 0x07
344 #define DA9055_BMEM_CONF_MASK 0x80
346 /* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
347 #define DA9055_LDO_EN_SHIFT 0x00
348 #define DA9055_LDO_EN_MASK 0x01
349 #define DA9055_LDO_GPI_SHIFT 0x01
350 #define DA9055_LDO_GPI_MASK 0x06
351 #define DA9055_LDO_PD_DIS_SHIFT 0x03
352 #define DA9055_LDO_PD_DIS_MASK 0x08
353 #define DA9055_VLDO_SEL_SHIFT 0x04
354 #define DA9055_VLDO_SEL_MASK 0x10
355 #define DA9055_VLDO_SEL_VLDO_A 0x00
356 #define DA9055_VLDO_SEL_VLDO_B 0x01
357 #define DA9055_VLDO_GPI_SHIFT 0x05
358 #define DA9055_VLDO_GPI_MASK 0x60
359 #define DA9055_LDO_CONF_SHIFT 0x07
360 #define DA9055_LDO_CONF_MASK 0x80
361 #define DA9055_REGUALTOR_SET_A 0x00
362 #define DA9055_REGUALTOR_SET_B 0x10
364 /* DA9055_REG_ADC_MAN (addr=0x1B) */
365 #define DA9055_ADC_MUX_SHIFT 0
366 #define DA9055_ADC_MUX_MASK 0xF
367 #define DA9055_ADC_MUX_VSYS 0x0
368 #define DA9055_ADC_MUX_ADCIN1 0x01
369 #define DA9055_ADC_MUX_ADCIN2 0x02
370 #define DA9055_ADC_MUX_ADCIN3 0x03
371 #define DA9055_ADC_MUX_T_SENSE 0x04
372 #define DA9055_ADC_MAN_SHIFT 0x04
373 #define DA9055_ADC_MAN_CONV 0x10
374 #define DA9055_ADC_LSB_MASK 0X03
375 #define DA9055_ADC_MODE_MASK 0x20
376 #define DA9055_ADC_MODE_SHIFT 5
377 #define DA9055_ADC_MODE_1MS (1<<5)
378 #define DA9055_COMP1V2_EN_SHIFT 7
380 /* DA9055_REG_ADC_CONT (addr=0x1C) */
381 #define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0
382 #define DA9055_ADC_AUTO_AD1_EN_SHIFT 1
383 #define DA9055_ADC_AUTO_AD2_EN_SHIFT 2
384 #define DA9055_ADC_AUTO_AD3_EN_SHIFT 3
385 #define DA9055_ADC_ISRC_EN_SHIFT 4
386 #define DA9055_ADC_ADCIN1_DEB_SHIFT 5
387 #define DA9055_ADC_ADCIN2_DEB_SHIFT 6
388 #define DA9055_ADC_ADCIN3_DEB_SHIFT 7
389 #define DA9055_AD1_ISRC_MASK 0x10
390 #define DA9055_AD1_ISRC_SHIFT 4
392 /* DA9055_REG_VSYS_MON (addr=0x1D) */
393 #define DA9055_VSYS_VAL_SHIFT 0
394 #define DA9055_VSYS_VAL_MASK 0xFF
395 #define DA9055_VSYS_VAL_BASE 0x00
396 #define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK
397 #define DA9055_VSYS_VOLT_BASE 2500
398 #define DA9055_VSYS_VOLT_INC 10
399 #define DA9055_VSYS_STEPS 255
400 #define DA9055_VSYS_VOLT_MIN 2500
402 /* DA9044_REG_XXX_RES (addr=0x20-0x23) */
403 #define DA9055_ADC_VAL_SHIFT 0
404 #define DA9055_ADC_VAL_MASK 0xFF
405 #define DA9055_ADC_VAL_BASE 0x00
406 #define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK
407 #define DA9055_ADC_VOLT_BASE 0
408 #define DA9055_ADC_VSYS_VOLT_BASE 2500
409 #define DA9055_ADC_VOLT_INC 10
410 #define DA9055_ADC_VSYS_VOLT_INC 12
411 #define DA9055_ADC_STEPS 255
413 /* DA9055_REG_EN_32K (addr=0x35)*/
414 #define DA9055_STARTUP_TIME_MASK 0x07
415 #define DA9055_STARTUP_TIME_0S 0x0
416 #define DA9055_STARTUP_TIME_0_52S 0x1
417 #define DA9055_STARTUP_TIME_1S 0x2
418 #define DA9055_CRYSTAL_EN 0x08
419 #define DA9055_DELAY_MODE_EN 0x10
420 #define DA9055_OUT_CLCK_GATED 0x20
421 #define DA9055_RTC_CLOCK_GATED 0x40
422 #define DA9055_EN_32KOUT_BUF 0x80
424 /* DA9055_REG_RESET (addr=0x36) */
425 /* Timer up to 31.744 ms */
426 #define DA9055_RESET_TIMER_VAL_SHIFT 0
427 #define DA9055_RESET_LOW_VAL_MASK 0x3F
428 #define DA9055_RESET_LOW_VAL_BASE 0
429 #define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK
430 #define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */
431 #define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */
432 #define DA9055_RESET_US_LOW_STEP 30
434 /* Timer up to 1048.576ms */
435 #define DA9055_RESET_HIGH_VAL_MASK 0x3F
436 #define DA9055_RESET_HIGH_VAL_BASE 0
437 #define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK
438 #define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */
439 #define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */
440 #define DA9055_RESET_US_HIGH_STEP 31
442 /* DA9055_REG_BUCK_ILIM (addr=0x37)*/
443 #define DA9055_BMEM_ILIM_SHIFT 0
444 #define DA9055_ILIM_MASK 0x3
445 #define DA9055_ILIM_500MA 0x0
446 #define DA9055_ILIM_600MA 0x1
447 #define DA9055_ILIM_700MA 0x2
448 #define DA9055_ILIM_800MA 0x3
449 #define DA9055_BCORE_ILIM_SHIFT 2
451 /* DA9055_REG_BCORE_MODE (addr=0x38) */
452 #define DA9055_BMEM_MODE_SHIFT 0
453 #define DA9055_MODE_MASK 0x3
454 #define DA9055_MODE_AB 0x0
455 #define DA9055_MODE_SLEEP 0x1
456 #define DA9055_MODE_SYNCHRO 0x2
457 #define DA9055_MODE_AUTO 0x3
458 #define DA9055_BCORE_MODE_SHIFT 2
460 /* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
461 #define DA9055_VBCORE_VAL_SHIFT 0
462 #define DA9055_VBCORE_VAL_MASK 0x3F
463 #define DA9055_VBCORE_VAL_BASE 0x09
464 #define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK
465 #define DA9055_VBCORE_VOLT_BASE 750
466 #define DA9055_VBCORE_VOLT_INC 25
467 #define DA9055_VBCORE_STEPS 53
468 #define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE
469 #define DA9055_BCORE_SL_SYNCHRO (0<<7)
470 #define DA9055_BCORE_SL_SLEEP (1<<7)
472 /* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
473 #define DA9055_VBMEM_VAL_SHIFT 0
474 #define DA9055_VBMEM_VAL_MASK 0x3F
475 #define DA9055_VBMEM_VAL_BASE 0x00
476 #define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK
477 #define DA9055_VBMEM_VOLT_BASE 925
478 #define DA9055_VBMEM_VOLT_INC 25
479 #define DA9055_VBMEM_STEPS 63
480 #define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE
481 #define DA9055_BCMEM_SL_SYNCHRO (0<<7)
482 #define DA9055_BCMEM_SL_SLEEP (1<<7)
485 /* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
486 #define DA9055_VLDO_VAL_SHIFT 0
487 #define DA9055_VLDO_VAL_MASK 0x3F
488 #define DA9055_VLDO6_VAL_MASK 0x7F
489 #define DA9055_VLDO_VAL_BASE 0x02
490 #define DA9055_VLDO2_VAL_BASE 0x03
491 #define DA9055_VLDO6_VAL_BASE 0x00
492 #define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK
493 #define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK
494 #define DA9055_VLDO_VOLT_BASE 900
495 #define DA9055_VLDO_VOLT_INC 50
496 #define DA9055_VLDO6_VOLT_INC 20
497 #define DA9055_VLDO_STEPS 48
498 #define DA9055_VLDO5_STEPS 37
499 #define DA9055_VLDO6_STEPS 120
500 #define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE
501 #define DA9055_LDO_MODE_SHIFT 7
502 #define DA9055_LDO_SL_NORMAL 0
503 #define DA9055_LDO_SL_SLEEP 1
505 /* DA9055_REG_OTP_CONT (addr=0x50) */
506 #define DA9055_OTP_TIM_NORMAL (0<<0)
507 #define DA9055_OTP_TIM_MARGINAL (1<<0)
508 #define DA9055_OTP_GP_RD_SHIFT 1
509 #define DA9055_OTP_APPS_RD_SHIFT 2
510 #define DA9055_PC_DONE_SHIFT 3
511 #define DA9055_OTP_GP_LOCK_SHIFT 4
512 #define DA9055_OTP_APPS_LOCK_SHIFT 5
513 #define DA9055_OTP_CONF_LOCK_SHIFT 6
514 #define DA9055_OTP_WRITE_DIS_SHIFT 7
516 /* DA9055_REG_COUNT_S (addr=0x53) */
517 #define DA9055_RTC_SEC 0x3F
518 #define DA9055_RTC_MONITOR_EN 0x40
519 #define DA9055_RTC_READ 0x80
521 /* DA9055_REG_COUNT_MI (addr=0x54) */
522 #define DA9055_RTC_MIN 0x3F
524 /* DA9055_REG_COUNT_H (addr=0x55) */
525 #define DA9055_RTC_HOUR 0x1F
527 /* DA9055_REG_COUNT_D (addr=0x56) */
528 #define DA9055_RTC_DAY 0x1F
530 /* DA9055_REG_COUNT_MO (addr=0x57) */
531 #define DA9055_RTC_MONTH 0x0F
533 /* DA9055_REG_COUNT_Y (addr=0x58) */
534 #define DA9055_RTC_YEAR 0x3F
535 #define DA9055_RTC_YEAR_BASE 2000
537 /* DA9055_REG_ALARM_MI (addr=0x59) */
538 #define DA9055_RTC_ALM_MIN 0x3F
539 #define DA9055_ALARM_STATUS_SHIFT 6
540 #define DA9055_ALARM_STATUS_MASK 0x3
541 #define DA9055_ALARM_STATUS_NO_ALARM 0x0
542 #define DA9055_ALARM_STATUS_TICK 0x1
543 #define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
544 #define DA9055_ALARM_STATUS_BOTH 0x3
546 /* DA9055_REG_ALARM_H (addr=0x5A) */
547 #define DA9055_RTC_ALM_HOUR 0x1F
549 /* DA9055_REG_ALARM_D (addr=0x5B) */
550 #define DA9055_RTC_ALM_DAY 0x1F
552 /* DA9055_REG_ALARM_MO (addr=0x5C) */
553 #define DA9055_RTC_ALM_MONTH 0x0F
554 #define DA9055_RTC_TICK_WAKE_MASK 0x20
555 #define DA9055_RTC_TICK_WAKE_SHIFT 5
556 #define DA9055_RTC_TICK_TYPE 0x10
557 #define DA9055_RTC_TICK_TYPE_SHIFT 0x4
558 #define DA9055_RTC_TICK_SEC 0x0
559 #define DA9055_RTC_TICK_MIN 0x1
560 #define DA9055_ALARAM_TICK_WAKE 0x20
562 /* DA9055_REG_ALARM_Y (addr=0x5D) */
563 #define DA9055_RTC_TICK_EN 0x80
564 #define DA9055_RTC_ALM_EN 0x40
565 #define DA9055_RTC_TICK_ALM_MASK 0xC0
566 #define DA9055_RTC_ALM_YEAR 0x3F
568 /* DA9055_REG_TRIM_CLDR (addr=0x62) */
569 #define DA9055_TRIM_32K_SHIFT 0
570 #define DA9055_TRIM_32K_MASK 0x7F
571 #define DA9055_TRIM_DECREMENT (1<<7)
572 #define DA9055_TRIM_INCREMENT (0<<7)
573 #define DA9055_TRIM_VAL_BASE 0x0
574 #define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */
575 #define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */
576 #define DA9055_TRIM_STEPS 127
578 /* DA9055_REG_CONFIG_A (addr=0x65) */
579 #define DA9055_PM_I_V_VDDCORE (0<<0)
580 #define DA9055_PM_I_V_VDD_IO (1<<0)
581 #define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1)
582 #define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1)
583 #define DA9055_PM_O_TYPE_PUSH_PULL (0<<2)
584 #define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2)
585 #define DA9055_IRQ_TYPE_ACT_LOW (0<<3)
586 #define DA9055_IRQ_TYPE_ACT_HIGH (1<<3)
587 #define DA9055_NIRQ_MODE_IMM (0<<4)
588 #define DA9055_NIRQ_MODE_ACTIVE (1<<4)
589 #define DA9055_GPI_V_VDDCORE (0<<5)
590 #define DA9055_GPI_V_VDD_IO (1<<5)
591 #define DA9055_PM_IF_V_VDDCORE (0<<6)
592 #define DA9055_PM_IF_V_VDD_IO (1<<6)
594 /* DA9055_REG_CONFIG_B (addr=0x66) */
595 #define DA9055_VDD_FAULT_VAL_SHIFT 0
596 #define DA9055_VDD_FAULT_VAL_MASK 0xF
597 #define DA9055_VDD_FAULT_VAL_BASE 0x0
598 #define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK
599 #define DA9055_VDD_FAULT_VOLT_BASE 2500
600 #define DA9055_VDD_FAULT_VOLT_INC 50
601 #define DA9055_VDD_FAULT_STEPS 15
603 #define DA9055_VDD_HYST_VAL_SHIFT 4
604 #define DA9055_VDD_HYST_VAL_MASK 0x7
605 #define DA9055_VDD_HYST_VAL_BASE 0x0
606 #define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK
607 #define DA9055_VDD_HYST_VOLT_BASE 100
608 #define DA9055_VDD_HYST_VOLT_INC 50
609 #define DA9055_VDD_HYST_STEPS 7
610 #define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE
612 #define DA9055_VDD_FAULT_EN_SHIFT 7
614 /* DA9055_REG_CONFIG_C (addr=0x67) */
615 #define DA9055_BCORE_CLK_INV_SHIFT 0
616 #define DA9055_BMEM_CLK_INV_SHIFT 1
617 #define DA9055_NFAULT_CONF_SHIFT 2
618 #define DA9055_LDO_SD_SHIFT 4
619 #define DA9055_LDO5_BYP_SHIFT 6
620 #define DA9055_LDO6_BYP_SHIFT 7
622 /* DA9055_REG_CONFIG_D (addr=0x68) */
623 #define DA9055_NONKEY_PIN_SHIFT 0
624 #define DA9055_NONKEY_PIN_MASK 0x3
625 #define DA9055_NONKEY_PIN_PORT_MODE 0x0
626 #define DA9055_NONKEY_PIN_KEY_MODE 0x1
627 #define DA9055_NONKEY_PIN_MULTI_FUNC 0x2
628 #define DA9055_NONKEY_PIN_DEDICT 0x3
629 #define DA9055_NONKEY_SD_SHIFT 2
630 #define DA9055_KEY_DELAY_SHIFT 3
631 #define DA9055_KEY_DELAY_MASK 0x3
632 #define DA9055_KEY_DELAY_4S 0x0
633 #define DA9055_KEY_DELAY_6S 0x1
634 #define DA9055_KEY_DELAY_8S 0x2
635 #define DA9055_KEY_DELAY_10S 0x3
637 /* DA9055_REG_CONFIG_E (addr=0x69) */
638 #define DA9055_GPIO_PUPD_PULL_UP 0x0
639 #define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1
640 #define DA9055_GPIO0_PUPD_SHIFT 0
641 #define DA9055_GPIO1_PUPD_SHIFT 1
642 #define DA9055_GPIO2_PUPD_SHIFT 2
643 #define DA9055_UVOV_DELAY_SHIFT 4
644 #define DA9055_UVOV_DELAY_MASK 0x3
645 #define DA9055_RESET_DURATION_SHIFT 6
646 #define DA9055_RESET_DURATION_MASK 0x3
647 #define DA9055_RESET_DURATION_0MS 0x0
648 #define DA9055_RESET_DURATION_100MS 0x1
649 #define DA9055_RESET_DURATION_500MS 0x2
650 #define DA9055_RESET_DURATION_1000MS 0x3
652 /* DA9055_REG_MON_REG_1 (addr=0x6A) */
653 #define DA9055_MON_THRES_SHIFT 0
654 #define DA9055_MON_THRES_MASK 0x3
655 #define DA9055_MON_RES_SHIFT 2
656 #define DA9055_MON_DEB_SHIFT 3
657 #define DA9055_MON_MODE_SHIFT 4
658 #define DA9055_MON_MODE_MASK 0x3
659 #define DA9055_START_MAX_SHIFT 6
660 #define DA9055_START_MAX_MASK 0x3
662 /* DA9055_REG_MON_REG_2 (addr=0x6B) */
663 #define DA9055_LDO1_MON_EN_SHIFT 0
664 #define DA9055_LDO2_MON_EN_SHIFT 1
665 #define DA9055_LDO3_MON_EN_SHIFT 2
666 #define DA9055_LDO4_MON_EN_SHIFT 3
667 #define DA9055_LDO5_MON_EN_SHIFT 4
668 #define DA9055_LDO6_MON_EN_SHIFT 5
669 #define DA9055_BCORE_MON_EN_SHIFT 6
670 #define DA9055_BMEM_MON_EN_SHIFT 7
672 /* DA9055_REG_CONFIG_F (addr=0x6C) */
673 #define DA9055_LDO1_DEF_SHIFT 0
674 #define DA9055_LDO2_DEF_SHIFT 1
675 #define DA9055_LDO3_DEF_SHIFT 2
676 #define DA9055_LDO4_DEF_SHIFT 3
677 #define DA9055_LDO5_DEF_SHIFT 4
678 #define DA9055_LDO6_DEF_SHIFT 5
679 #define DA9055_BCORE_DEF_SHIFT 6
680 #define DA9055_BMEM_DEF_SHIFT 7
682 /* DA9055_REG_MON_REG_4 (addr=0x6D) */
683 #define DA9055_MON_A8_IDX_SHIFT 0
684 #define DA9055_MON_A89_IDX_MASK 0x3
685 #define DA9055_MON_A89_IDX_NONE 0x0
686 #define DA9055_MON_A89_IDX_BUCKCORE 0x1
687 #define DA9055_MON_A89_IDX_LDO3 0x2
688 #define DA9055_MON_A9_IDX_SHIFT 5
690 /* DA9055_REG_MON_REG_5 (addr=0x6E) */
691 #define DA9055_MON_A10_IDX_SHIFT 0
692 #define DA9055_MON_A10_IDX_MASK 0x3
693 #define DA9055_MON_A10_IDX_NONE 0x0
694 #define DA9055_MON_A10_IDX_LDO1 0x1
695 #define DA9055_MON_A10_IDX_LDO2 0x2
696 #define DA9055_MON_A10_IDX_LDO5 0x3
697 #define DA9055_MON_A10_IDX_LDO6 0x4
699 #endif /* __DA9055_REG_H */
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