kernel/include/linux/mfd/abx500/ab8500-sysctrl.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6 #ifndef __AB8500_SYSCTRL_H
   7 #define __AB8500_SYSCTRL_H
   8
   9 #include <linux/bitops.h>
  10
  11 #ifdef CONFIG_AB8500_CORE
  12
  13 int ab8500_sysctrl_read(u16 reg, u8 *value);
  14 int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
  15
  16 #else
  17
  18 static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
  19 {
  20         return 0;
  21 }
  22
  23 static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
  24 {
  25         return 0;
  26 }
  27
  28 #endif /* CONFIG_AB8500_CORE */
  29
  30 static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
  31 {
  32         return ab8500_sysctrl_write(reg, bits, bits);
  33 }
  34
  35 static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
  36 {
  37         return ab8500_sysctrl_write(reg, bits, 0);
  38 }
  39
  40 /* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
  41 struct ab8500_sysctrl_platform_data {
  42         u8 initial_req_buf_config[8];
  43         u16 (*reboot_reason_code)(const char *cmd);
  44 };
  45
  46 /* Registers */
  47 #define AB8500_TURNONSTATUS             0x100
  48 #define AB8500_RESETSTATUS              0x101
  49 #define AB8500_PONKEY1PRESSSTATUS       0x102
  50 #define AB8500_SYSCLKREQSTATUS          0x142
  51 #define AB8500_STW4500CTRL1             0x180
  52 #define AB8500_STW4500CTRL2             0x181
  53 #define AB8500_STW4500CTRL3             0x200
  54 #define AB8500_MAINWDOGCTRL             0x201
  55 #define AB8500_MAINWDOGTIMER            0x202
  56 #define AB8500_LOWBAT                   0x203
  57 #define AB8500_BATTOK                   0x204
  58 #define AB8500_SYSCLKTIMER              0x205
  59 #define AB8500_SMPSCLKCTRL              0x206
  60 #define AB8500_SMPSCLKSEL1              0x207
  61 #define AB8500_SMPSCLKSEL2              0x208
  62 #define AB8500_SMPSCLKSEL3              0x209
  63 #define AB8500_SYSULPCLKCONF            0x20A
  64 #define AB8500_SYSULPCLKCTRL1           0x20B
  65 #define AB8500_SYSCLKCTRL               0x20C
  66 #define AB8500_SYSCLKREQ1VALID          0x20D
  67 #define AB8500_SYSTEMCTRLSUP            0x20F
  68 #define AB8500_SYSCLKREQ1RFCLKBUF       0x210
  69 #define AB8500_SYSCLKREQ2RFCLKBUF       0x211
  70 #define AB8500_SYSCLKREQ3RFCLKBUF       0x212
  71 #define AB8500_SYSCLKREQ4RFCLKBUF       0x213
  72 #define AB8500_SYSCLKREQ5RFCLKBUF       0x214
  73 #define AB8500_SYSCLKREQ6RFCLKBUF       0x215
  74 #define AB8500_SYSCLKREQ7RFCLKBUF       0x216
  75 #define AB8500_SYSCLKREQ8RFCLKBUF       0x217
  76 #define AB8500_DITHERCLKCTRL            0x220
  77 #define AB8500_SWATCTRL                 0x230
  78 #define AB8500_HIQCLKCTRL               0x232
  79 #define AB8500_VSIMSYSCLKCTRL           0x233
  80 #define AB9540_SYSCLK12BUFCTRL          0x234
  81 #define AB9540_SYSCLK12CONFCTRL         0x235
  82 #define AB9540_SYSCLK12BUFCTRL2         0x236
  83 #define AB9540_SYSCLK12BUF1VALID        0x237
  84 #define AB9540_SYSCLK12BUF2VALID        0x238
  85 #define AB9540_SYSCLK12BUF3VALID        0x239
  86 #define AB9540_SYSCLK12BUF4VALID        0x23A
  87
  88 /* Bits */
  89 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
  90 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
  91 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
  92 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
  93 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
  94 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
  95 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
  96
  97 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
  98 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
  99
 100 #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
 101 #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
 102
 103 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
 104 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
 105 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
 106 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
 107 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
 108 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
 109 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
 110 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
 111
 112 #define AB8500_STW4500CTRL1_SWOFF BIT(0)
 113 #define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
 114 #define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
 115
 116 #define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
 117 #define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
 118 #define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
 119 #define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
 120 #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
 121 #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
 122 #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
 123 #define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
 124
 125 #define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
 126 #define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
 127 #define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
 128 #define AB8500_STW4500CTRL3_THSDENA BIT(3)
 129
 130 #define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
 131 #define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
 132 #define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
 133
 134 #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
 135 #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
 136
 137 #define AB8500_LOWBAT_LOWBATENA BIT(0)
 138 #define AB8500_LOWBAT_LOWBAT_MASK 0x7E
 139 #define AB8500_LOWBAT_LOWBAT_SHIFT 1
 140
 141 #define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
 142 #define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
 143 #define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
 144 #define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
 145
 146 #define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
 147 #define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
 148 #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
 149 #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
 150
 151 #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
 152 #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
 153 #define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
 154
 155 #define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
 156 #define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
 157 #define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
 158 #define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
 159
 160 #define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
 161 #define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
 162 #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
 163 #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
 164
 165 #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
 166 #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
 167 #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
 168 #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
 169
 170 #define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
 171 #define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
 172 #define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
 173 #define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
 174 #define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
 175 #define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
 176 #define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
 177 #define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
 178
 179 #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
 180 #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
 181 #define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
 182 #define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
 183 #define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
 184 #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
 185 #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
 186 #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
 187
 188 #define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
 189 #define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
 190 #define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
 191
 192 #define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
 193 #define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
 194 #define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
 195
 196 #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
 197 #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
 198 #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
 199 #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
 200 #define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
 201
 202 #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
 203 #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
 204 #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
 205
 206 #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
 207 #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
 208 #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
 209
 210 #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
 211 #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
 212 #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
 213
 214 #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
 215 #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
 216 #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
 217
 218 #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
 219 #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
 220 #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
 221
 222 #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
 223 #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
 224 #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
 225
 226 #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
 227 #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
 228 #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
 229
 230 #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
 231 #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
 232 #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
 233
 234 #define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
 235 #define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
 236 #define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
 237 #define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
 238 #define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
 239 #define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
 240 #define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
 241 #define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
 242
 243 #define AB8500_SWATCTRL_UPDATERF BIT(0)
 244 #define AB8500_SWATCTRL_SWATENABLE BIT(1)
 245 #define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
 246 #define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
 247 #define AB8500_SWATCTRL_SWATBIT5 BIT(6)
 248
 249 #define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
 250 #define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
 251 #define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
 252 #define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
 253 #define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
 254 #define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
 255 #define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
 256 #define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
 257
 258 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
 259 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
 260 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
 261 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
 262 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
 263 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
 264 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
 265 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
 266
 267 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
 268 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
 269 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
 270 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
 271 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
 272 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
 273 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
 274 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
 275 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
 276 #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
 277
 278 #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
 279 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
 280 #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
 281 #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
 282 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
 283 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
 284 #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
 285
 286 #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
 287 #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
 288 #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
 289 #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
 290
 291 #define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
 292 #define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
 293
 294 #define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
 295 #define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
 296
 297 #define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
 298 #define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
 299
 300 #define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
 301 #define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
 302
 303 #define AB8500_ENABLE_WD 0x1
 304 #define AB8500_KICK_WD 0x2
 305 #define AB8500_WD_RESTART_ON_EXPIRE 0x10
 306
 307 #endif /* __AB8500_SYSCTRL_H */