5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 * IRQ_NO_SOFTIRQ_CALL - No softirq processing in the irq thread context (RT)
78 IRQ_TYPE_NONE = 0x00000000,
79 IRQ_TYPE_EDGE_RISING = 0x00000001,
80 IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 IRQ_TYPE_SENSE_MASK = 0x0000000f,
86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
88 IRQ_TYPE_PROBE = 0x00000010,
91 IRQ_PER_CPU = (1 << 9),
92 IRQ_NOPROBE = (1 << 10),
93 IRQ_NOREQUEST = (1 << 11),
94 IRQ_NOAUTOEN = (1 << 12),
95 IRQ_NO_BALANCING = (1 << 13),
96 IRQ_MOVE_PCNTXT = (1 << 14),
97 IRQ_NESTED_THREAD = (1 << 15),
98 IRQ_NOTHREAD = (1 << 16),
99 IRQ_PER_CPU_DEVID = (1 << 17),
100 IRQ_IS_POLLED = (1 << 18),
101 IRQ_NO_SOFTIRQ_CALL = (1 << 19),
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_NO_SOFTIRQ_CALL)
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 * Return value for chip->irq_set_affinity()
115 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendent irqchips.
123 IRQ_SET_MASK_OK_NOCOPY,
124 IRQ_SET_MASK_OK_DONE,
131 * struct irq_data - per irq and irq chip data passed down to chip functions
132 * @mask: precomputed bitmask for accessing the chip registers
133 * @irq: interrupt number
134 * @hwirq: hardware interrupt number, local to the interrupt domain
135 * @node: node index useful for balancing
136 * @state_use_accessors: status information for irq chip functions.
137 * Use accessor functions to deal with it
138 * @chip: low level interrupt hardware access
139 * @domain: Interrupt translation domain; responsible for mapping
140 * between hwirq number and linux irq number.
141 * @parent_data: pointer to parent struct irq_data to support hierarchy
143 * @handler_data: per-IRQ data for the irq_chip methods
144 * @chip_data: platform-specific per-chip private data for the chip
145 * methods, to allow shared chip implementations
146 * @msi_desc: MSI descriptor
147 * @affinity: IRQ affinity on SMP
149 * The fields here need to overlay the ones in irq_desc until we
150 * cleaned up the direct references and switched everything over to
158 unsigned int state_use_accessors;
159 struct irq_chip *chip;
160 struct irq_domain *domain;
161 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
162 struct irq_data *parent_data;
166 struct msi_desc *msi_desc;
167 cpumask_var_t affinity;
171 * Bit masks for irq_data.state
173 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
174 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
175 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
176 * IRQD_PER_CPU - Interrupt is per cpu
177 * IRQD_AFFINITY_SET - Interrupt affinity was set
178 * IRQD_LEVEL - Interrupt is level triggered
179 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
181 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
183 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
184 * IRQD_IRQ_MASKED - Masked state of the interrupt
185 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
186 * IRQD_WAKEUP_ARMED - Wakeup mode armed
189 IRQD_TRIGGER_MASK = 0xf,
190 IRQD_SETAFFINITY_PENDING = (1 << 8),
191 IRQD_NO_BALANCING = (1 << 10),
192 IRQD_PER_CPU = (1 << 11),
193 IRQD_AFFINITY_SET = (1 << 12),
194 IRQD_LEVEL = (1 << 13),
195 IRQD_WAKEUP_STATE = (1 << 14),
196 IRQD_MOVE_PCNTXT = (1 << 15),
197 IRQD_IRQ_DISABLED = (1 << 16),
198 IRQD_IRQ_MASKED = (1 << 17),
199 IRQD_IRQ_INPROGRESS = (1 << 18),
200 IRQD_WAKEUP_ARMED = (1 << 19),
203 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
205 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
208 static inline bool irqd_is_per_cpu(struct irq_data *d)
210 return d->state_use_accessors & IRQD_PER_CPU;
213 static inline bool irqd_can_balance(struct irq_data *d)
215 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
218 static inline bool irqd_affinity_was_set(struct irq_data *d)
220 return d->state_use_accessors & IRQD_AFFINITY_SET;
223 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
225 d->state_use_accessors |= IRQD_AFFINITY_SET;
228 static inline u32 irqd_get_trigger_type(struct irq_data *d)
230 return d->state_use_accessors & IRQD_TRIGGER_MASK;
234 * Must only be called inside irq_chip.irq_set_type() functions.
236 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
238 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
239 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
242 static inline bool irqd_is_level_type(struct irq_data *d)
244 return d->state_use_accessors & IRQD_LEVEL;
247 static inline bool irqd_is_wakeup_set(struct irq_data *d)
249 return d->state_use_accessors & IRQD_WAKEUP_STATE;
252 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
254 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
257 static inline bool irqd_irq_disabled(struct irq_data *d)
259 return d->state_use_accessors & IRQD_IRQ_DISABLED;
262 static inline bool irqd_irq_masked(struct irq_data *d)
264 return d->state_use_accessors & IRQD_IRQ_MASKED;
267 static inline bool irqd_irq_inprogress(struct irq_data *d)
269 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
272 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
274 return d->state_use_accessors & IRQD_WAKEUP_ARMED;
279 * Functions for chained handlers which can be enabled/disabled by the
280 * standard disable_irq/enable_irq calls. Must be called with
281 * irq_desc->lock held.
283 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
285 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
288 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
290 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
293 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
299 * struct irq_chip - hardware interrupt chip descriptor
301 * @name: name for /proc/interrupts
302 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
303 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
304 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
305 * @irq_disable: disable the interrupt
306 * @irq_ack: start of a new interrupt
307 * @irq_mask: mask an interrupt source
308 * @irq_mask_ack: ack and mask an interrupt source
309 * @irq_unmask: unmask an interrupt source
310 * @irq_eoi: end of interrupt
311 * @irq_set_affinity: set the CPU affinity on SMP machines
312 * @irq_retrigger: resend an IRQ to the CPU
313 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
314 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
315 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
316 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
317 * @irq_cpu_online: configure an interrupt source for a secondary CPU
318 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
319 * @irq_suspend: function called from core code on suspend once per chip
320 * @irq_resume: function called from core code on resume once per chip
321 * @irq_pm_shutdown: function called from core code on shutdown once per chip
322 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
323 * @irq_print_chip: optional to print special chip info in show_interrupts
324 * @irq_request_resources: optional to request resources before calling
325 * any other callback related to this irq
326 * @irq_release_resources: optional to release resources acquired with
327 * irq_request_resources
328 * @irq_compose_msi_msg: optional to compose message content for MSI
329 * @irq_write_msi_msg: optional to write message content for MSI
330 * @irq_get_irqchip_state: return the internal state of an interrupt
331 * @irq_set_irqchip_state: set the internal state of a interrupt
332 * @flags: chip specific flags
336 unsigned int (*irq_startup)(struct irq_data *data);
337 void (*irq_shutdown)(struct irq_data *data);
338 void (*irq_enable)(struct irq_data *data);
339 void (*irq_disable)(struct irq_data *data);
341 void (*irq_ack)(struct irq_data *data);
342 void (*irq_mask)(struct irq_data *data);
343 void (*irq_mask_ack)(struct irq_data *data);
344 void (*irq_unmask)(struct irq_data *data);
345 void (*irq_eoi)(struct irq_data *data);
347 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
348 int (*irq_retrigger)(struct irq_data *data);
349 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
350 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
352 void (*irq_bus_lock)(struct irq_data *data);
353 void (*irq_bus_sync_unlock)(struct irq_data *data);
355 void (*irq_cpu_online)(struct irq_data *data);
356 void (*irq_cpu_offline)(struct irq_data *data);
358 void (*irq_suspend)(struct irq_data *data);
359 void (*irq_resume)(struct irq_data *data);
360 void (*irq_pm_shutdown)(struct irq_data *data);
362 void (*irq_calc_mask)(struct irq_data *data);
364 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
365 int (*irq_request_resources)(struct irq_data *data);
366 void (*irq_release_resources)(struct irq_data *data);
368 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
369 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
371 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
372 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
378 * irq_chip specific flags
380 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
381 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
382 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
383 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
385 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
386 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
387 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
390 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
391 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
392 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
393 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
394 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
395 IRQCHIP_ONESHOT_SAFE = (1 << 5),
396 IRQCHIP_EOI_THREADED = (1 << 6),
399 /* This include will go away once we isolated irq_desc usage to core code */
400 #include <linux/irqdesc.h>
403 * Pick up the arch-dependent methods:
405 #include <asm/hw_irq.h>
407 #ifndef NR_IRQS_LEGACY
408 # define NR_IRQS_LEGACY 0
411 #ifndef ARCH_IRQ_INIT_FLAGS
412 # define ARCH_IRQ_INIT_FLAGS 0
415 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
418 extern int setup_irq(unsigned int irq, struct irqaction *new);
419 extern void remove_irq(unsigned int irq, struct irqaction *act);
420 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
421 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
423 extern void irq_cpu_online(void);
424 extern void irq_cpu_offline(void);
425 extern int irq_set_affinity_locked(struct irq_data *data,
426 const struct cpumask *cpumask, bool force);
428 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
429 void irq_move_irq(struct irq_data *data);
430 void irq_move_masked_irq(struct irq_data *data);
432 static inline void irq_move_irq(struct irq_data *data) { }
433 static inline void irq_move_masked_irq(struct irq_data *data) { }
436 extern int no_irq_affinity;
438 #ifdef CONFIG_HARDIRQS_SW_RESEND
439 int irq_set_parent(int irq, int parent_irq);
441 static inline int irq_set_parent(int irq, int parent_irq)
448 * Built-in IRQ handlers for various IRQ types,
449 * callable via desc->handle_irq()
451 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
452 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
453 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
454 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
455 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
456 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
457 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
458 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
459 extern void handle_nested_irq(unsigned int irq);
461 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
462 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
463 extern void irq_chip_ack_parent(struct irq_data *data);
464 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
465 extern void irq_chip_mask_parent(struct irq_data *data);
466 extern void irq_chip_unmask_parent(struct irq_data *data);
467 extern void irq_chip_eoi_parent(struct irq_data *data);
468 extern int irq_chip_set_affinity_parent(struct irq_data *data,
469 const struct cpumask *dest,
471 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
472 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
475 /* Handling of unhandled and spurious interrupts: */
476 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
477 irqreturn_t action_ret);
480 /* Enable/disable irq debugging output: */
481 extern int noirqdebug_setup(char *str);
483 /* Checks whether the interrupt can be requested by request_irq(): */
484 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
486 /* Dummy irq-chip implementations: */
487 extern struct irq_chip no_irq_chip;
488 extern struct irq_chip dummy_irq_chip;
491 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
492 irq_flow_handler_t handle, const char *name);
494 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
495 irq_flow_handler_t handle)
497 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
500 extern int irq_set_percpu_devid(unsigned int irq);
503 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
507 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
509 __irq_set_handler(irq, handle, 0, NULL);
513 * Set a highlevel chained flow handler for a given IRQ.
514 * (a chained handler is automatically enabled and set to
515 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
518 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
520 __irq_set_handler(irq, handle, 1, NULL);
523 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
525 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
527 irq_modify_status(irq, 0, set);
530 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
532 irq_modify_status(irq, clr, 0);
535 static inline void irq_set_noprobe(unsigned int irq)
537 irq_modify_status(irq, 0, IRQ_NOPROBE);
540 static inline void irq_set_probe(unsigned int irq)
542 irq_modify_status(irq, IRQ_NOPROBE, 0);
545 static inline void irq_set_nothread(unsigned int irq)
547 irq_modify_status(irq, 0, IRQ_NOTHREAD);
550 static inline void irq_set_thread(unsigned int irq)
552 irq_modify_status(irq, IRQ_NOTHREAD, 0);
555 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
558 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
560 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
563 static inline void irq_set_percpu_devid_flags(unsigned int irq)
565 irq_set_status_flags(irq,
566 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
567 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
570 /* Set/get chip/data for an IRQ: */
571 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
572 extern int irq_set_handler_data(unsigned int irq, void *data);
573 extern int irq_set_chip_data(unsigned int irq, void *data);
574 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
575 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
576 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
577 struct msi_desc *entry);
578 extern struct irq_data *irq_get_irq_data(unsigned int irq);
580 static inline struct irq_chip *irq_get_chip(unsigned int irq)
582 struct irq_data *d = irq_get_irq_data(irq);
583 return d ? d->chip : NULL;
586 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
591 static inline void *irq_get_chip_data(unsigned int irq)
593 struct irq_data *d = irq_get_irq_data(irq);
594 return d ? d->chip_data : NULL;
597 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
602 static inline void *irq_get_handler_data(unsigned int irq)
604 struct irq_data *d = irq_get_irq_data(irq);
605 return d ? d->handler_data : NULL;
608 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
610 return d->handler_data;
613 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
615 struct irq_data *d = irq_get_irq_data(irq);
616 return d ? d->msi_desc : NULL;
619 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
624 static inline u32 irq_get_trigger_type(unsigned int irq)
626 struct irq_data *d = irq_get_irq_data(irq);
627 return d ? irqd_get_trigger_type(d) : 0;
630 unsigned int arch_dynirq_lower_bound(unsigned int from);
632 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
633 struct module *owner);
635 /* use macros to avoid needing export.h for THIS_MODULE */
636 #define irq_alloc_descs(irq, from, cnt, node) \
637 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
639 #define irq_alloc_desc(node) \
640 irq_alloc_descs(-1, 0, 1, node)
642 #define irq_alloc_desc_at(at, node) \
643 irq_alloc_descs(at, at, 1, node)
645 #define irq_alloc_desc_from(from, node) \
646 irq_alloc_descs(-1, from, 1, node)
648 #define irq_alloc_descs_from(from, cnt, node) \
649 irq_alloc_descs(-1, from, cnt, node)
651 void irq_free_descs(unsigned int irq, unsigned int cnt);
652 static inline void irq_free_desc(unsigned int irq)
654 irq_free_descs(irq, 1);
657 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
658 unsigned int irq_alloc_hwirqs(int cnt, int node);
659 static inline unsigned int irq_alloc_hwirq(int node)
661 return irq_alloc_hwirqs(1, node);
663 void irq_free_hwirqs(unsigned int from, int cnt);
664 static inline void irq_free_hwirq(unsigned int irq)
666 return irq_free_hwirqs(irq, 1);
668 int arch_setup_hwirq(unsigned int irq, int node);
669 void arch_teardown_hwirq(unsigned int irq);
672 #ifdef CONFIG_GENERIC_IRQ_LEGACY
673 void irq_init_desc(unsigned int irq);
677 * struct irq_chip_regs - register offsets for struct irq_gci
678 * @enable: Enable register offset to reg_base
679 * @disable: Disable register offset to reg_base
680 * @mask: Mask register offset to reg_base
681 * @ack: Ack register offset to reg_base
682 * @eoi: Eoi register offset to reg_base
683 * @type: Type configuration register offset to reg_base
684 * @polarity: Polarity configuration register offset to reg_base
686 struct irq_chip_regs {
687 unsigned long enable;
688 unsigned long disable;
693 unsigned long polarity;
697 * struct irq_chip_type - Generic interrupt chip instance for a flow type
698 * @chip: The real interrupt chip which provides the callbacks
699 * @regs: Register offsets for this chip
700 * @handler: Flow handler associated with this chip
701 * @type: Chip can handle these flow types
702 * @mask_cache_priv: Cached mask register private to the chip type
703 * @mask_cache: Pointer to cached mask register
705 * A irq_generic_chip can have several instances of irq_chip_type when
706 * it requires different functions and register offsets for different
709 struct irq_chip_type {
710 struct irq_chip chip;
711 struct irq_chip_regs regs;
712 irq_flow_handler_t handler;
719 * struct irq_chip_generic - Generic irq chip data structure
720 * @lock: Lock to protect register and cache data access
721 * @reg_base: Register base address (virtual)
722 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
723 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
724 * @irq_base: Interrupt base nr for this chip
725 * @irq_cnt: Number of interrupts handled by this chip
726 * @mask_cache: Cached mask register shared between all chip types
727 * @type_cache: Cached type register
728 * @polarity_cache: Cached polarity register
729 * @wake_enabled: Interrupt can wakeup from suspend
730 * @wake_active: Interrupt is marked as an wakeup from suspend source
731 * @num_ct: Number of available irq_chip_type instances (usually 1)
732 * @private: Private data for non generic chip callbacks
733 * @installed: bitfield to denote installed interrupts
734 * @unused: bitfield to denote unused interrupts
735 * @domain: irq domain pointer
736 * @list: List head for keeping track of instances
737 * @chip_types: Array of interrupt irq_chip_types
739 * Note, that irq_chip_generic can have multiple irq_chip_type
740 * implementations which can be associated to a particular irq line of
741 * an irq_chip_generic instance. That allows to share and protect
742 * state in an irq_chip_generic instance when we need to implement
743 * different flow mechanisms (level/edge) for it.
745 struct irq_chip_generic {
747 void __iomem *reg_base;
748 u32 (*reg_readl)(void __iomem *addr);
749 void (*reg_writel)(u32 val, void __iomem *addr);
750 unsigned int irq_base;
751 unsigned int irq_cnt;
759 unsigned long installed;
760 unsigned long unused;
761 struct irq_domain *domain;
762 struct list_head list;
763 struct irq_chip_type chip_types[0];
767 * enum irq_gc_flags - Initialization flags for generic irq chips
768 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
769 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
770 * irq chips which need to call irq_set_wake() on
771 * the parent irq. Usually GPIO implementations
772 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
773 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
774 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
777 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
778 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
779 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
780 IRQ_GC_NO_MASK = 1 << 3,
781 IRQ_GC_BE_IO = 1 << 4,
785 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
786 * @irqs_per_chip: Number of interrupts per chip
787 * @num_chips: Number of chips
788 * @irq_flags_to_set: IRQ* flags to set on irq setup
789 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
790 * @gc_flags: Generic chip specific setup flags
791 * @gc: Array of pointers to generic interrupt chips
793 struct irq_domain_chip_generic {
794 unsigned int irqs_per_chip;
795 unsigned int num_chips;
796 unsigned int irq_flags_to_clear;
797 unsigned int irq_flags_to_set;
798 enum irq_gc_flags gc_flags;
799 struct irq_chip_generic *gc[0];
802 /* Generic chip callback functions */
803 void irq_gc_noop(struct irq_data *d);
804 void irq_gc_mask_disable_reg(struct irq_data *d);
805 void irq_gc_mask_set_bit(struct irq_data *d);
806 void irq_gc_mask_clr_bit(struct irq_data *d);
807 void irq_gc_unmask_enable_reg(struct irq_data *d);
808 void irq_gc_ack_set_bit(struct irq_data *d);
809 void irq_gc_ack_clr_bit(struct irq_data *d);
810 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
811 void irq_gc_eoi(struct irq_data *d);
812 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
814 /* Setup functions for irq_chip_generic */
815 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
816 irq_hw_number_t hw_irq);
817 struct irq_chip_generic *
818 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
819 void __iomem *reg_base, irq_flow_handler_t handler);
820 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
821 enum irq_gc_flags flags, unsigned int clr,
823 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
824 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
825 unsigned int clr, unsigned int set);
827 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
828 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
829 int num_ct, const char *name,
830 irq_flow_handler_t handler,
831 unsigned int clr, unsigned int set,
832 enum irq_gc_flags flags);
835 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
837 return container_of(d->chip, struct irq_chip_type, chip);
840 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
843 static inline void irq_gc_lock(struct irq_chip_generic *gc)
845 raw_spin_lock(&gc->lock);
848 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
850 raw_spin_unlock(&gc->lock);
853 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
854 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
857 static inline void irq_reg_writel(struct irq_chip_generic *gc,
858 u32 val, int reg_offset)
861 gc->reg_writel(val, gc->reg_base + reg_offset);
863 writel(val, gc->reg_base + reg_offset);
866 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
870 return gc->reg_readl(gc->reg_base + reg_offset);
872 return readl(gc->reg_base + reg_offset);
875 #endif /* _LINUX_IRQ_H */