kernel/drivers/video/fbdev/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42
  43 #include <video/omapdss.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47 #include "dispc.h"
  48
  49 /* DISPC */
  50 #define DISPC_SZ_REGS                   SZ_4K
  51
  52 enum omap_burst_size {
  53         BURST_SIZE_X2 = 0,
  54         BURST_SIZE_X4 = 1,
  55         BURST_SIZE_X8 = 2,
  56 };
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dispc_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end)                               \
  62         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  63
  64 struct dispc_features {
  65         u8 sw_start;
  66         u8 fp_start;
  67         u8 bp_start;
  68         u16 sw_max;
  69         u16 vp_max;
  70         u16 hp_max;
  71         u8 mgr_width_start;
  72         u8 mgr_height_start;
  73         u16 mgr_width_max;
  74         u16 mgr_height_max;
  75         unsigned long max_lcd_pclk;
  76         unsigned long max_tv_pclk;
  77         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  78                 const struct omap_video_timings *mgr_timings,
  79                 u16 width, u16 height, u16 out_width, u16 out_height,
  80                 enum omap_color_mode color_mode, bool *five_taps,
  81                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  82                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  83         unsigned long (*calc_core_clk) (unsigned long pclk,
  84                 u16 width, u16 height, u16 out_width, u16 out_height,
  85                 bool mem_to_mem);
  86         u8 num_fifos;
  87
  88         /* swap GFX & WB fifos */
  89         bool gfx_fifo_workaround:1;
  90
  91         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  92         bool no_framedone_tv:1;
  93
  94         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  95         bool mstandby_workaround:1;
  96
  97         bool set_max_preload:1;
  98 };
  99
 100 #define DISPC_MAX_NR_FIFOS 5
 101
 102 static struct {
 103         struct platform_device *pdev;
 104         void __iomem    *base;
 105
 106         int irq;
 107         irq_handler_t user_handler;
 108         void *user_data;
 109
 110         unsigned long core_clk_rate;
 111         unsigned long tv_pclk_rate;
 112
 113         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 114         /* maps which plane is using a fifo. fifo-id -> plane-id */
 115         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120         const struct dispc_features *feat;
 121
 122         bool is_enabled;
 123
 124         struct regmap *syscon_pol;
 125         u32 syscon_pol_offset;
 126
 127         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 128         spinlock_t control_lock;
 129 } dispc;
 130
 131 enum omap_color_component {
 132         /* used for all color formats for OMAP3 and earlier
 133          * and for RGB and Y color component on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 136         /* used for UV component for
 137          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 138          * color formats on OMAP4
 139          */
 140         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 141 };
 142
 143 enum mgr_reg_fields {
 144         DISPC_MGR_FLD_ENABLE,
 145         DISPC_MGR_FLD_STNTFT,
 146         DISPC_MGR_FLD_GO,
 147         DISPC_MGR_FLD_TFTDATALINES,
 148         DISPC_MGR_FLD_STALLMODE,
 149         DISPC_MGR_FLD_TCKENABLE,
 150         DISPC_MGR_FLD_TCKSELECTION,
 151         DISPC_MGR_FLD_CPR,
 152         DISPC_MGR_FLD_FIFOHANDCHECK,
 153         /* used to maintain a count of the above fields */
 154         DISPC_MGR_FLD_NUM,
 155 };
 156
 157 struct dispc_reg_field {
 158         u16 reg;
 159         u8 high;
 160         u8 low;
 161 };
 162
 163 static const struct {
 164         const char *name;
 165         u32 vsync_irq;
 166         u32 framedone_irq;
 167         u32 sync_lost_irq;
 168         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 169 } mgr_desc[] = {
 170         [OMAP_DSS_CHANNEL_LCD] = {
 171                 .name           = "LCD",
 172                 .vsync_irq      = DISPC_IRQ_VSYNC,
 173                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 174                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 175                 .reg_desc       = {
 176                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 177                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 178                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 179                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 180                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 181                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 182                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 183                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 184                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 185                 },
 186         },
 187         [OMAP_DSS_CHANNEL_DIGIT] = {
 188                 .name           = "DIGIT",
 189                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 190                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 191                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 192                 .reg_desc       = {
 193                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 194                         [DISPC_MGR_FLD_STNTFT]          = { },
 195                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 196                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 197                         [DISPC_MGR_FLD_STALLMODE]       = { },
 198                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 199                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 200                         [DISPC_MGR_FLD_CPR]             = { },
 201                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 202                 },
 203         },
 204         [OMAP_DSS_CHANNEL_LCD2] = {
 205                 .name           = "LCD2",
 206                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 207                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 208                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 209                 .reg_desc       = {
 210                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 211                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 212                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 213                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 214                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 215                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 216                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 217                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 218                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 219                 },
 220         },
 221         [OMAP_DSS_CHANNEL_LCD3] = {
 222                 .name           = "LCD3",
 223                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 224                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 225                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 226                 .reg_desc       = {
 227                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 228                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 229                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 230                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 231                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 232                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 233                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 234                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 235                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 236                 },
 237         },
 238 };
 239
 240 struct color_conv_coef {
 241         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 242         int full_range;
 243 };
 244
 245 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 246 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 247
 248 static inline void dispc_write_reg(const u16 idx, u32 val)
 249 {
 250         __raw_writel(val, dispc.base + idx);
 251 }
 252
 253 static inline u32 dispc_read_reg(const u16 idx)
 254 {
 255         return __raw_readl(dispc.base + idx);
 256 }
 257
 258 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 259 {
 260         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 261         return REG_GET(rfld.reg, rfld.high, rfld.low);
 262 }
 263
 264 static void mgr_fld_write(enum omap_channel channel,
 265                                         enum mgr_reg_fields regfld, int val) {
 266         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 267         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 268         unsigned long flags;
 269
 270         if (need_lock)
 271                 spin_lock_irqsave(&dispc.control_lock, flags);
 272
 273         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 274
 275         if (need_lock)
 276                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 277 }
 278
 279 #define SR(reg) \
 280         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 281 #define RR(reg) \
 282         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 283
 284 static void dispc_save_context(void)
 285 {
 286         int i, j;
 287
 288         DSSDBG("dispc_save_context\n");
 289
 290         SR(IRQENABLE);
 291         SR(CONTROL);
 292         SR(CONFIG);
 293         SR(LINE_NUMBER);
 294         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 295                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 296                 SR(GLOBAL_ALPHA);
 297         if (dss_has_feature(FEAT_MGR_LCD2)) {
 298                 SR(CONTROL2);
 299                 SR(CONFIG2);
 300         }
 301         if (dss_has_feature(FEAT_MGR_LCD3)) {
 302                 SR(CONTROL3);
 303                 SR(CONFIG3);
 304         }
 305
 306         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 307                 SR(DEFAULT_COLOR(i));
 308                 SR(TRANS_COLOR(i));
 309                 SR(SIZE_MGR(i));
 310                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 311                         continue;
 312                 SR(TIMING_H(i));
 313                 SR(TIMING_V(i));
 314                 SR(POL_FREQ(i));
 315                 SR(DIVISORo(i));
 316
 317                 SR(DATA_CYCLE1(i));
 318                 SR(DATA_CYCLE2(i));
 319                 SR(DATA_CYCLE3(i));
 320
 321                 if (dss_has_feature(FEAT_CPR)) {
 322                         SR(CPR_COEF_R(i));
 323                         SR(CPR_COEF_G(i));
 324                         SR(CPR_COEF_B(i));
 325                 }
 326         }
 327
 328         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 329                 SR(OVL_BA0(i));
 330                 SR(OVL_BA1(i));
 331                 SR(OVL_POSITION(i));
 332                 SR(OVL_SIZE(i));
 333                 SR(OVL_ATTRIBUTES(i));
 334                 SR(OVL_FIFO_THRESHOLD(i));
 335                 SR(OVL_ROW_INC(i));
 336                 SR(OVL_PIXEL_INC(i));
 337                 if (dss_has_feature(FEAT_PRELOAD))
 338                         SR(OVL_PRELOAD(i));
 339                 if (i == OMAP_DSS_GFX) {
 340                         SR(OVL_WINDOW_SKIP(i));
 341                         SR(OVL_TABLE_BA(i));
 342                         continue;
 343                 }
 344                 SR(OVL_FIR(i));
 345                 SR(OVL_PICTURE_SIZE(i));
 346                 SR(OVL_ACCU0(i));
 347                 SR(OVL_ACCU1(i));
 348
 349                 for (j = 0; j < 8; j++)
 350                         SR(OVL_FIR_COEF_H(i, j));
 351
 352                 for (j = 0; j < 8; j++)
 353                         SR(OVL_FIR_COEF_HV(i, j));
 354
 355                 for (j = 0; j < 5; j++)
 356                         SR(OVL_CONV_COEF(i, j));
 357
 358                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 359                         for (j = 0; j < 8; j++)
 360                                 SR(OVL_FIR_COEF_V(i, j));
 361                 }
 362
 363                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 364                         SR(OVL_BA0_UV(i));
 365                         SR(OVL_BA1_UV(i));
 366                         SR(OVL_FIR2(i));
 367                         SR(OVL_ACCU2_0(i));
 368                         SR(OVL_ACCU2_1(i));
 369
 370                         for (j = 0; j < 8; j++)
 371                                 SR(OVL_FIR_COEF_H2(i, j));
 372
 373                         for (j = 0; j < 8; j++)
 374                                 SR(OVL_FIR_COEF_HV2(i, j));
 375
 376                         for (j = 0; j < 8; j++)
 377                                 SR(OVL_FIR_COEF_V2(i, j));
 378                 }
 379                 if (dss_has_feature(FEAT_ATTR2))
 380                         SR(OVL_ATTRIBUTES2(i));
 381         }
 382
 383         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 384                 SR(DIVISOR);
 385
 386         dispc.ctx_valid = true;
 387
 388         DSSDBG("context saved\n");
 389 }
 390
 391 static void dispc_restore_context(void)
 392 {
 393         int i, j;
 394
 395         DSSDBG("dispc_restore_context\n");
 396
 397         if (!dispc.ctx_valid)
 398                 return;
 399
 400         /*RR(IRQENABLE);*/
 401         /*RR(CONTROL);*/
 402         RR(CONFIG);
 403         RR(LINE_NUMBER);
 404         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 405                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 406                 RR(GLOBAL_ALPHA);
 407         if (dss_has_feature(FEAT_MGR_LCD2))
 408                 RR(CONFIG2);
 409         if (dss_has_feature(FEAT_MGR_LCD3))
 410                 RR(CONFIG3);
 411
 412         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 413                 RR(DEFAULT_COLOR(i));
 414                 RR(TRANS_COLOR(i));
 415                 RR(SIZE_MGR(i));
 416                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 417                         continue;
 418                 RR(TIMING_H(i));
 419                 RR(TIMING_V(i));
 420                 RR(POL_FREQ(i));
 421                 RR(DIVISORo(i));
 422
 423                 RR(DATA_CYCLE1(i));
 424                 RR(DATA_CYCLE2(i));
 425                 RR(DATA_CYCLE3(i));
 426
 427                 if (dss_has_feature(FEAT_CPR)) {
 428                         RR(CPR_COEF_R(i));
 429                         RR(CPR_COEF_G(i));
 430                         RR(CPR_COEF_B(i));
 431                 }
 432         }
 433
 434         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 435                 RR(OVL_BA0(i));
 436                 RR(OVL_BA1(i));
 437                 RR(OVL_POSITION(i));
 438                 RR(OVL_SIZE(i));
 439                 RR(OVL_ATTRIBUTES(i));
 440                 RR(OVL_FIFO_THRESHOLD(i));
 441                 RR(OVL_ROW_INC(i));
 442                 RR(OVL_PIXEL_INC(i));
 443                 if (dss_has_feature(FEAT_PRELOAD))
 444                         RR(OVL_PRELOAD(i));
 445                 if (i == OMAP_DSS_GFX) {
 446                         RR(OVL_WINDOW_SKIP(i));
 447                         RR(OVL_TABLE_BA(i));
 448                         continue;
 449                 }
 450                 RR(OVL_FIR(i));
 451                 RR(OVL_PICTURE_SIZE(i));
 452                 RR(OVL_ACCU0(i));
 453                 RR(OVL_ACCU1(i));
 454
 455                 for (j = 0; j < 8; j++)
 456                         RR(OVL_FIR_COEF_H(i, j));
 457
 458                 for (j = 0; j < 8; j++)
 459                         RR(OVL_FIR_COEF_HV(i, j));
 460
 461                 for (j = 0; j < 5; j++)
 462                         RR(OVL_CONV_COEF(i, j));
 463
 464                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 465                         for (j = 0; j < 8; j++)
 466                                 RR(OVL_FIR_COEF_V(i, j));
 467                 }
 468
 469                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 470                         RR(OVL_BA0_UV(i));
 471                         RR(OVL_BA1_UV(i));
 472                         RR(OVL_FIR2(i));
 473                         RR(OVL_ACCU2_0(i));
 474                         RR(OVL_ACCU2_1(i));
 475
 476                         for (j = 0; j < 8; j++)
 477                                 RR(OVL_FIR_COEF_H2(i, j));
 478
 479                         for (j = 0; j < 8; j++)
 480                                 RR(OVL_FIR_COEF_HV2(i, j));
 481
 482                         for (j = 0; j < 8; j++)
 483                                 RR(OVL_FIR_COEF_V2(i, j));
 484                 }
 485                 if (dss_has_feature(FEAT_ATTR2))
 486                         RR(OVL_ATTRIBUTES2(i));
 487         }
 488
 489         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 490                 RR(DIVISOR);
 491
 492         /* enable last, because LCD & DIGIT enable are here */
 493         RR(CONTROL);
 494         if (dss_has_feature(FEAT_MGR_LCD2))
 495                 RR(CONTROL2);
 496         if (dss_has_feature(FEAT_MGR_LCD3))
 497                 RR(CONTROL3);
 498         /* clear spurious SYNC_LOST_DIGIT interrupts */
 499         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 500
 501         /*
 502          * enable last so IRQs won't trigger before
 503          * the context is fully restored
 504          */
 505         RR(IRQENABLE);
 506
 507         DSSDBG("context restored\n");
 508 }
 509
 510 #undef SR
 511 #undef RR
 512
 513 int dispc_runtime_get(void)
 514 {
 515         int r;
 516
 517         DSSDBG("dispc_runtime_get\n");
 518
 519         r = pm_runtime_get_sync(&dispc.pdev->dev);
 520         WARN_ON(r < 0);
 521         return r < 0 ? r : 0;
 522 }
 523 EXPORT_SYMBOL(dispc_runtime_get);
 524
 525 void dispc_runtime_put(void)
 526 {
 527         int r;
 528
 529         DSSDBG("dispc_runtime_put\n");
 530
 531         r = pm_runtime_put_sync(&dispc.pdev->dev);
 532         WARN_ON(r < 0 && r != -ENOSYS);
 533 }
 534 EXPORT_SYMBOL(dispc_runtime_put);
 535
 536 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 537 {
 538         return mgr_desc[channel].vsync_irq;
 539 }
 540 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 541
 542 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 543 {
 544         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 545                 return 0;
 546
 547         return mgr_desc[channel].framedone_irq;
 548 }
 549 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 550
 551 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 552 {
 553         return mgr_desc[channel].sync_lost_irq;
 554 }
 555 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 556
 557 u32 dispc_wb_get_framedone_irq(void)
 558 {
 559         return DISPC_IRQ_FRAMEDONEWB;
 560 }
 561
 562 bool dispc_mgr_go_busy(enum omap_channel channel)
 563 {
 564         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 565 }
 566 EXPORT_SYMBOL(dispc_mgr_go_busy);
 567
 568 void dispc_mgr_go(enum omap_channel channel)
 569 {
 570         WARN_ON(dispc_mgr_is_enabled(channel) == false);
 571         WARN_ON(dispc_mgr_go_busy(channel));
 572
 573         DSSDBG("GO %s\n", mgr_desc[channel].name);
 574
 575         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 576 }
 577 EXPORT_SYMBOL(dispc_mgr_go);
 578
 579 bool dispc_wb_go_busy(void)
 580 {
 581         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 582 }
 583
 584 void dispc_wb_go(void)
 585 {
 586         enum omap_plane plane = OMAP_DSS_WB;
 587         bool enable, go;
 588
 589         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 590
 591         if (!enable)
 592                 return;
 593
 594         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 595         if (go) {
 596                 DSSERR("GO bit not down for WB\n");
 597                 return;
 598         }
 599
 600         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 601 }
 602
 603 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 604 {
 605         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 606 }
 607
 608 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 609 {
 610         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 611 }
 612
 613 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 614 {
 615         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 616 }
 617
 618 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 619 {
 620         BUG_ON(plane == OMAP_DSS_GFX);
 621
 622         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 623 }
 624
 625 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 626                 u32 value)
 627 {
 628         BUG_ON(plane == OMAP_DSS_GFX);
 629
 630         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 631 }
 632
 633 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 634 {
 635         BUG_ON(plane == OMAP_DSS_GFX);
 636
 637         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 638 }
 639
 640 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 641                                 int fir_vinc, int five_taps,
 642                                 enum omap_color_component color_comp)
 643 {
 644         const struct dispc_coef *h_coef, *v_coef;
 645         int i;
 646
 647         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 648         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 649
 650         for (i = 0; i < 8; i++) {
 651                 u32 h, hv;
 652
 653                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 654                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 655                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 656                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 657                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 658                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 659                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 660                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 661
 662                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 663                         dispc_ovl_write_firh_reg(plane, i, h);
 664                         dispc_ovl_write_firhv_reg(plane, i, hv);
 665                 } else {
 666                         dispc_ovl_write_firh2_reg(plane, i, h);
 667                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 668                 }
 669
 670         }
 671
 672         if (five_taps) {
 673                 for (i = 0; i < 8; i++) {
 674                         u32 v;
 675                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 676                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 677                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 678                                 dispc_ovl_write_firv_reg(plane, i, v);
 679                         else
 680                                 dispc_ovl_write_firv2_reg(plane, i, v);
 681                 }
 682         }
 683 }
 684
 685
 686 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 687                 const struct color_conv_coef *ct)
 688 {
 689 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 690
 691         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 692         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 693         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 694         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 695         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 696
 697         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 698
 699 #undef CVAL
 700 }
 701
 702 static void dispc_setup_color_conv_coef(void)
 703 {
 704         int i;
 705         int num_ovl = dss_feat_get_num_ovls();
 706         int num_wb = dss_feat_get_num_wbs();
 707         const struct color_conv_coef ctbl_bt601_5_ovl = {
 708                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 709         };
 710         const struct color_conv_coef ctbl_bt601_5_wb = {
 711                 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
 712         };
 713
 714         for (i = 1; i < num_ovl; i++)
 715                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 716
 717         for (; i < num_wb; i++)
 718                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
 719 }
 720
 721 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 722 {
 723         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 724 }
 725
 726 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 727 {
 728         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 729 }
 730
 731 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 732 {
 733         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 734 }
 735
 736 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 737 {
 738         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 739 }
 740
 741 static void dispc_ovl_set_pos(enum omap_plane plane,
 742                 enum omap_overlay_caps caps, int x, int y)
 743 {
 744         u32 val;
 745
 746         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 747                 return;
 748
 749         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 750
 751         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 752 }
 753
 754 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 755                 int height)
 756 {
 757         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 758
 759         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 760                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 761         else
 762                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 763 }
 764
 765 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 766                 int height)
 767 {
 768         u32 val;
 769
 770         BUG_ON(plane == OMAP_DSS_GFX);
 771
 772         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 773
 774         if (plane == OMAP_DSS_WB)
 775                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 776         else
 777                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 778 }
 779
 780 static void dispc_ovl_set_zorder(enum omap_plane plane,
 781                 enum omap_overlay_caps caps, u8 zorder)
 782 {
 783         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 784                 return;
 785
 786         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 787 }
 788
 789 static void dispc_ovl_enable_zorder_planes(void)
 790 {
 791         int i;
 792
 793         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 794                 return;
 795
 796         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 797                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 798 }
 799
 800 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 801                 enum omap_overlay_caps caps, bool enable)
 802 {
 803         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 804                 return;
 805
 806         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 807 }
 808
 809 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 810                 enum omap_overlay_caps caps, u8 global_alpha)
 811 {
 812         static const unsigned shifts[] = { 0, 8, 16, 24, };
 813         int shift;
 814
 815         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 816                 return;
 817
 818         shift = shifts[plane];
 819         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 820 }
 821
 822 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 823 {
 824         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 825 }
 826
 827 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 828 {
 829         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 830 }
 831
 832 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 833                 enum omap_color_mode color_mode)
 834 {
 835         u32 m = 0;
 836         if (plane != OMAP_DSS_GFX) {
 837                 switch (color_mode) {
 838                 case OMAP_DSS_COLOR_NV12:
 839                         m = 0x0; break;
 840                 case OMAP_DSS_COLOR_RGBX16:
 841                         m = 0x1; break;
 842                 case OMAP_DSS_COLOR_RGBA16:
 843                         m = 0x2; break;
 844                 case OMAP_DSS_COLOR_RGB12U:
 845                         m = 0x4; break;
 846                 case OMAP_DSS_COLOR_ARGB16:
 847                         m = 0x5; break;
 848                 case OMAP_DSS_COLOR_RGB16:
 849                         m = 0x6; break;
 850                 case OMAP_DSS_COLOR_ARGB16_1555:
 851                         m = 0x7; break;
 852                 case OMAP_DSS_COLOR_RGB24U:
 853                         m = 0x8; break;
 854                 case OMAP_DSS_COLOR_RGB24P:
 855                         m = 0x9; break;
 856                 case OMAP_DSS_COLOR_YUV2:
 857                         m = 0xa; break;
 858                 case OMAP_DSS_COLOR_UYVY:
 859                         m = 0xb; break;
 860                 case OMAP_DSS_COLOR_ARGB32:
 861                         m = 0xc; break;
 862                 case OMAP_DSS_COLOR_RGBA32:
 863                         m = 0xd; break;
 864                 case OMAP_DSS_COLOR_RGBX32:
 865                         m = 0xe; break;
 866                 case OMAP_DSS_COLOR_XRGB16_1555:
 867                         m = 0xf; break;
 868                 default:
 869                         BUG(); return;
 870                 }
 871         } else {
 872                 switch (color_mode) {
 873                 case OMAP_DSS_COLOR_CLUT1:
 874                         m = 0x0; break;
 875                 case OMAP_DSS_COLOR_CLUT2:
 876                         m = 0x1; break;
 877                 case OMAP_DSS_COLOR_CLUT4:
 878                         m = 0x2; break;
 879                 case OMAP_DSS_COLOR_CLUT8:
 880                         m = 0x3; break;
 881                 case OMAP_DSS_COLOR_RGB12U:
 882                         m = 0x4; break;
 883                 case OMAP_DSS_COLOR_ARGB16:
 884                         m = 0x5; break;
 885                 case OMAP_DSS_COLOR_RGB16:
 886                         m = 0x6; break;
 887                 case OMAP_DSS_COLOR_ARGB16_1555:
 888                         m = 0x7; break;
 889                 case OMAP_DSS_COLOR_RGB24U:
 890                         m = 0x8; break;
 891                 case OMAP_DSS_COLOR_RGB24P:
 892                         m = 0x9; break;
 893                 case OMAP_DSS_COLOR_RGBX16:
 894                         m = 0xa; break;
 895                 case OMAP_DSS_COLOR_RGBA16:
 896                         m = 0xb; break;
 897                 case OMAP_DSS_COLOR_ARGB32:
 898                         m = 0xc; break;
 899                 case OMAP_DSS_COLOR_RGBA32:
 900                         m = 0xd; break;
 901                 case OMAP_DSS_COLOR_RGBX32:
 902                         m = 0xe; break;
 903                 case OMAP_DSS_COLOR_XRGB16_1555:
 904                         m = 0xf; break;
 905                 default:
 906                         BUG(); return;
 907                 }
 908         }
 909
 910         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 911 }
 912
 913 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 914                 enum omap_dss_rotation_type rotation_type)
 915 {
 916         if (dss_has_feature(FEAT_BURST_2D) == 0)
 917                 return;
 918
 919         if (rotation_type == OMAP_DSS_ROT_TILER)
 920                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 921         else
 922                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 923 }
 924
 925 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 926 {
 927         int shift;
 928         u32 val;
 929         int chan = 0, chan2 = 0;
 930
 931         switch (plane) {
 932         case OMAP_DSS_GFX:
 933                 shift = 8;
 934                 break;
 935         case OMAP_DSS_VIDEO1:
 936         case OMAP_DSS_VIDEO2:
 937         case OMAP_DSS_VIDEO3:
 938                 shift = 16;
 939                 break;
 940         default:
 941                 BUG();
 942                 return;
 943         }
 944
 945         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 946         if (dss_has_feature(FEAT_MGR_LCD2)) {
 947                 switch (channel) {
 948                 case OMAP_DSS_CHANNEL_LCD:
 949                         chan = 0;
 950                         chan2 = 0;
 951                         break;
 952                 case OMAP_DSS_CHANNEL_DIGIT:
 953                         chan = 1;
 954                         chan2 = 0;
 955                         break;
 956                 case OMAP_DSS_CHANNEL_LCD2:
 957                         chan = 0;
 958                         chan2 = 1;
 959                         break;
 960                 case OMAP_DSS_CHANNEL_LCD3:
 961                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 962                                 chan = 0;
 963                                 chan2 = 2;
 964                         } else {
 965                                 BUG();
 966                                 return;
 967                         }
 968                         break;
 969                 default:
 970                         BUG();
 971                         return;
 972                 }
 973
 974                 val = FLD_MOD(val, chan, shift, shift);
 975                 val = FLD_MOD(val, chan2, 31, 30);
 976         } else {
 977                 val = FLD_MOD(val, channel, shift, shift);
 978         }
 979         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 980 }
 981 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
 982
 983 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 984 {
 985         int shift;
 986         u32 val;
 987         enum omap_channel channel;
 988
 989         switch (plane) {
 990         case OMAP_DSS_GFX:
 991                 shift = 8;
 992                 break;
 993         case OMAP_DSS_VIDEO1:
 994         case OMAP_DSS_VIDEO2:
 995         case OMAP_DSS_VIDEO3:
 996                 shift = 16;
 997                 break;
 998         default:
 999                 BUG();
1000                 return 0;
1001         }
1002
1003         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
1005         if (dss_has_feature(FEAT_MGR_LCD3)) {
1006                 if (FLD_GET(val, 31, 30) == 0)
1007                         channel = FLD_GET(val, shift, shift);
1008                 else if (FLD_GET(val, 31, 30) == 1)
1009                         channel = OMAP_DSS_CHANNEL_LCD2;
1010                 else
1011                         channel = OMAP_DSS_CHANNEL_LCD3;
1012         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1013                 if (FLD_GET(val, 31, 30) == 0)
1014                         channel = FLD_GET(val, shift, shift);
1015                 else
1016                         channel = OMAP_DSS_CHANNEL_LCD2;
1017         } else {
1018                 channel = FLD_GET(val, shift, shift);
1019         }
1020
1021         return channel;
1022 }
1023
1024 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025 {
1026         enum omap_plane plane = OMAP_DSS_WB;
1027
1028         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029 }
1030
1031 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1032                 enum omap_burst_size burst_size)
1033 {
1034         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1035         int shift;
1036
1037         shift = shifts[plane];
1038         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1039 }
1040
1041 static void dispc_configure_burst_sizes(void)
1042 {
1043         int i;
1044         const int burst_size = BURST_SIZE_X8;
1045
1046         /* Configure burst size always to maximum size */
1047         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1048                 dispc_ovl_set_burst_size(i, burst_size);
1049 }
1050
1051 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1052 {
1053         unsigned unit = dss_feat_get_burst_size_unit();
1054         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055         return unit * 8;
1056 }
1057
1058 void dispc_enable_gamma_table(bool enable)
1059 {
1060         /*
1061          * This is partially implemented to support only disabling of
1062          * the gamma table.
1063          */
1064         if (enable) {
1065                 DSSWARN("Gamma table enabling for TV not yet supported");
1066                 return;
1067         }
1068
1069         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070 }
1071
1072 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1073 {
1074         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1075                 return;
1076
1077         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1078 }
1079
1080 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1081                 const struct omap_dss_cpr_coefs *coefs)
1082 {
1083         u32 coef_r, coef_g, coef_b;
1084
1085         if (!dss_mgr_is_lcd(channel))
1086                 return;
1087
1088         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089                 FLD_VAL(coefs->rb, 9, 0);
1090         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091                 FLD_VAL(coefs->gb, 9, 0);
1092         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093                 FLD_VAL(coefs->bb, 9, 0);
1094
1095         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098 }
1099
1100 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1101 {
1102         u32 val;
1103
1104         BUG_ON(plane == OMAP_DSS_GFX);
1105
1106         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1107         val = FLD_MOD(val, enable, 9, 9);
1108         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1109 }
1110
1111 static void dispc_ovl_enable_replication(enum omap_plane plane,
1112                 enum omap_overlay_caps caps, bool enable)
1113 {
1114         static const unsigned shifts[] = { 5, 10, 10, 10 };
1115         int shift;
1116
1117         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118                 return;
1119
1120         shift = shifts[plane];
1121         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1122 }
1123
1124 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1125                 u16 height)
1126 {
1127         u32 val;
1128
1129         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
1132         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1133 }
1134
1135 static void dispc_init_fifos(void)
1136 {
1137         u32 size;
1138         int fifo;
1139         u8 start, end;
1140         u32 unit;
1141         int i;
1142
1143         unit = dss_feat_get_buffer_size_unit();
1144
1145         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1146
1147         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1148                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1149                 size *= unit;
1150                 dispc.fifo_size[fifo] = size;
1151
1152                 /*
1153                  * By default fifos are mapped directly to overlays, fifo 0 to
1154                  * ovl 0, fifo 1 to ovl 1, etc.
1155                  */
1156                 dispc.fifo_assignment[fifo] = fifo;
1157         }
1158
1159         /*
1160          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1161          * causes problems with certain use cases, like using the tiler in 2D
1162          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1163          * giving GFX plane a larger fifo. WB but should work fine with a
1164          * smaller fifo.
1165          */
1166         if (dispc.feat->gfx_fifo_workaround) {
1167                 u32 v;
1168
1169                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1170
1171                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1172                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1173                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1174                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1175
1176                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1177
1178                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1179                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1180         }
1181
1182         /*
1183          * Setup default fifo thresholds.
1184          */
1185         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1186                 u32 low, high;
1187                 const bool use_fifomerge = false;
1188                 const bool manual_update = false;
1189
1190                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1191                         use_fifomerge, manual_update);
1192
1193                 dispc_ovl_set_fifo_threshold(i, low, high);
1194         }
1195 }
1196
1197 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1198 {
1199         int fifo;
1200         u32 size = 0;
1201
1202         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1203                 if (dispc.fifo_assignment[fifo] == plane)
1204                         size += dispc.fifo_size[fifo];
1205         }
1206
1207         return size;
1208 }
1209
1210 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1211 {
1212         u8 hi_start, hi_end, lo_start, lo_end;
1213         u32 unit;
1214
1215         unit = dss_feat_get_buffer_size_unit();
1216
1217         WARN_ON(low % unit != 0);
1218         WARN_ON(high % unit != 0);
1219
1220         low /= unit;
1221         high /= unit;
1222
1223         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1224         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1225
1226         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1227                         plane,
1228                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1229                                 lo_start, lo_end) * unit,
1230                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1231                                 hi_start, hi_end) * unit,
1232                         low * unit, high * unit);
1233
1234         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1235                         FLD_VAL(high, hi_start, hi_end) |
1236                         FLD_VAL(low, lo_start, lo_end));
1237
1238         /*
1239          * configure the preload to the pipeline's high threhold, if HT it's too
1240          * large for the preload field, set the threshold to the maximum value
1241          * that can be held by the preload register
1242          */
1243         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1244                         plane != OMAP_DSS_WB)
1245                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1246 }
1247 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1248
1249 void dispc_enable_fifomerge(bool enable)
1250 {
1251         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1252                 WARN_ON(enable);
1253                 return;
1254         }
1255
1256         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1257         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1258 }
1259
1260 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1261                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1262                 bool manual_update)
1263 {
1264         /*
1265          * All sizes are in bytes. Both the buffer and burst are made of
1266          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1267          */
1268
1269         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1270         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1271         int i;
1272
1273         burst_size = dispc_ovl_get_burst_size(plane);
1274         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1275
1276         if (use_fifomerge) {
1277                 total_fifo_size = 0;
1278                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1279                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1280         } else {
1281                 total_fifo_size = ovl_fifo_size;
1282         }
1283
1284         /*
1285          * We use the same low threshold for both fifomerge and non-fifomerge
1286          * cases, but for fifomerge we calculate the high threshold using the
1287          * combined fifo size
1288          */
1289
1290         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1291                 *fifo_low = ovl_fifo_size - burst_size * 2;
1292                 *fifo_high = total_fifo_size - burst_size;
1293         } else if (plane == OMAP_DSS_WB) {
1294                 /*
1295                  * Most optimal configuration for writeback is to push out data
1296                  * to the interconnect the moment writeback pushes enough pixels
1297                  * in the FIFO to form a burst
1298                  */
1299                 *fifo_low = 0;
1300                 *fifo_high = burst_size;
1301         } else {
1302                 *fifo_low = ovl_fifo_size - burst_size;
1303                 *fifo_high = total_fifo_size - buf_unit;
1304         }
1305 }
1306 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1307
1308 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1309 {
1310         int bit;
1311
1312         if (plane == OMAP_DSS_GFX)
1313                 bit = 14;
1314         else
1315                 bit = 23;
1316
1317         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1318 }
1319
1320 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1321         int low, int high)
1322 {
1323         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1324                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1325 }
1326
1327 static void dispc_init_mflag(void)
1328 {
1329         int i;
1330
1331         /*
1332          * HACK: NV12 color format and MFLAG seem to have problems working
1333          * together: using two displays, and having an NV12 overlay on one of
1334          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1335          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1336          * remove the errors, but there doesn't seem to be a clear logic on
1337          * which values work and which not.
1338          *
1339          * As a work-around, set force MFLAG to always on.
1340          */
1341         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1342                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1343                 (0 << 2));      /* MFLAG_START = disable */
1344
1345         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1346                 u32 size = dispc_ovl_get_fifo_size(i);
1347                 u32 unit = dss_feat_get_buffer_size_unit();
1348                 u32 low, high;
1349
1350                 dispc_ovl_set_mflag(i, true);
1351
1352                 /*
1353                  * Simulation team suggests below thesholds:
1354                  * HT = fifosize * 5 / 8;
1355                  * LT = fifosize * 4 / 8;
1356                  */
1357
1358                 low = size * 4 / 8 / unit;
1359                 high = size * 5 / 8 / unit;
1360
1361                 dispc_ovl_set_mflag_threshold(i, low, high);
1362         }
1363 }
1364
1365 static void dispc_ovl_set_fir(enum omap_plane plane,
1366                                 int hinc, int vinc,
1367                                 enum omap_color_component color_comp)
1368 {
1369         u32 val;
1370
1371         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1372                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1373
1374                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1375                                         &hinc_start, &hinc_end);
1376                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1377                                         &vinc_start, &vinc_end);
1378                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1379                                 FLD_VAL(hinc, hinc_start, hinc_end);
1380
1381                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1382         } else {
1383                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1384                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1385         }
1386 }
1387
1388 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1389 {
1390         u32 val;
1391         u8 hor_start, hor_end, vert_start, vert_end;
1392
1393         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1394         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1395
1396         val = FLD_VAL(vaccu, vert_start, vert_end) |
1397                         FLD_VAL(haccu, hor_start, hor_end);
1398
1399         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1400 }
1401
1402 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1403 {
1404         u32 val;
1405         u8 hor_start, hor_end, vert_start, vert_end;
1406
1407         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1408         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1409
1410         val = FLD_VAL(vaccu, vert_start, vert_end) |
1411                         FLD_VAL(haccu, hor_start, hor_end);
1412
1413         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1414 }
1415
1416 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1417                 int vaccu)
1418 {
1419         u32 val;
1420
1421         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1422         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1423 }
1424
1425 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1426                 int vaccu)
1427 {
1428         u32 val;
1429
1430         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1431         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1432 }
1433
1434 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1435                 u16 orig_width, u16 orig_height,
1436                 u16 out_width, u16 out_height,
1437                 bool five_taps, u8 rotation,
1438                 enum omap_color_component color_comp)
1439 {
1440         int fir_hinc, fir_vinc;
1441
1442         fir_hinc = 1024 * orig_width / out_width;
1443         fir_vinc = 1024 * orig_height / out_height;
1444
1445         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1446                                 color_comp);
1447         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1448 }
1449
1450 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1451                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1452                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1453 {
1454         int h_accu2_0, h_accu2_1;
1455         int v_accu2_0, v_accu2_1;
1456         int chroma_hinc, chroma_vinc;
1457         int idx;
1458
1459         struct accu {
1460                 s8 h0_m, h0_n;
1461                 s8 h1_m, h1_n;
1462                 s8 v0_m, v0_n;
1463                 s8 v1_m, v1_n;
1464         };
1465
1466         const struct accu *accu_table;
1467         const struct accu *accu_val;
1468
1469         static const struct accu accu_nv12[4] = {
1470                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1471                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1472                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1473                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1474         };
1475
1476         static const struct accu accu_nv12_ilace[4] = {
1477                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1478                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1479                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1480                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1481         };
1482
1483         static const struct accu accu_yuv[4] = {
1484                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1485                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1486                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1487                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1488         };
1489
1490         switch (rotation) {
1491         case OMAP_DSS_ROT_0:
1492                 idx = 0;
1493                 break;
1494         case OMAP_DSS_ROT_90:
1495                 idx = 1;
1496                 break;
1497         case OMAP_DSS_ROT_180:
1498                 idx = 2;
1499                 break;
1500         case OMAP_DSS_ROT_270:
1501                 idx = 3;
1502                 break;
1503         default:
1504                 BUG();
1505                 return;
1506         }
1507
1508         switch (color_mode) {
1509         case OMAP_DSS_COLOR_NV12:
1510                 if (ilace)
1511                         accu_table = accu_nv12_ilace;
1512                 else
1513                         accu_table = accu_nv12;
1514                 break;
1515         case OMAP_DSS_COLOR_YUV2:
1516         case OMAP_DSS_COLOR_UYVY:
1517                 accu_table = accu_yuv;
1518                 break;
1519         default:
1520                 BUG();
1521                 return;
1522         }
1523
1524         accu_val = &accu_table[idx];
1525
1526         chroma_hinc = 1024 * orig_width / out_width;
1527         chroma_vinc = 1024 * orig_height / out_height;
1528
1529         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1530         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1531         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1532         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1533
1534         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1535         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1536 }
1537
1538 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1539                 u16 orig_width, u16 orig_height,
1540                 u16 out_width, u16 out_height,
1541                 bool ilace, bool five_taps,
1542                 bool fieldmode, enum omap_color_mode color_mode,
1543                 u8 rotation)
1544 {
1545         int accu0 = 0;
1546         int accu1 = 0;
1547         u32 l;
1548
1549         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1550                                 out_width, out_height, five_taps,
1551                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1552         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1553
1554         /* RESIZEENABLE and VERTICALTAPS */
1555         l &= ~((0x3 << 5) | (0x1 << 21));
1556         l |= (orig_width != out_width) ? (1 << 5) : 0;
1557         l |= (orig_height != out_height) ? (1 << 6) : 0;
1558         l |= five_taps ? (1 << 21) : 0;
1559
1560         /* VRESIZECONF and HRESIZECONF */
1561         if (dss_has_feature(FEAT_RESIZECONF)) {
1562                 l &= ~(0x3 << 7);
1563                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1564                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1565         }
1566
1567         /* LINEBUFFERSPLIT */
1568         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1569                 l &= ~(0x1 << 22);
1570                 l |= five_taps ? (1 << 22) : 0;
1571         }
1572
1573         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1574
1575         /*
1576          * field 0 = even field = bottom field
1577          * field 1 = odd field = top field
1578          */
1579         if (ilace && !fieldmode) {
1580                 accu1 = 0;
1581                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1582                 if (accu0 >= 1024/2) {
1583                         accu1 = 1024/2;
1584                         accu0 -= accu1;
1585                 }
1586         }
1587
1588         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1589         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1590 }
1591
1592 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1593                 u16 orig_width, u16 orig_height,
1594                 u16 out_width, u16 out_height,
1595                 bool ilace, bool five_taps,
1596                 bool fieldmode, enum omap_color_mode color_mode,
1597                 u8 rotation)
1598 {
1599         int scale_x = out_width != orig_width;
1600         int scale_y = out_height != orig_height;
1601         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1602
1603         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1604                 return;
1605         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1606                         color_mode != OMAP_DSS_COLOR_UYVY &&
1607                         color_mode != OMAP_DSS_COLOR_NV12)) {
1608                 /* reset chroma resampling for RGB formats  */
1609                 if (plane != OMAP_DSS_WB)
1610                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1611                 return;
1612         }
1613
1614         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1615                         out_height, ilace, color_mode, rotation);
1616
1617         switch (color_mode) {
1618         case OMAP_DSS_COLOR_NV12:
1619                 if (chroma_upscale) {
1620                         /* UV is subsampled by 2 horizontally and vertically */
1621                         orig_height >>= 1;
1622                         orig_width >>= 1;
1623                 } else {
1624                         /* UV is downsampled by 2 horizontally and vertically */
1625                         orig_height <<= 1;
1626                         orig_width <<= 1;
1627                 }
1628
1629                 break;
1630         case OMAP_DSS_COLOR_YUV2:
1631         case OMAP_DSS_COLOR_UYVY:
1632                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1633                 if (rotation == OMAP_DSS_ROT_0 ||
1634                                 rotation == OMAP_DSS_ROT_180) {
1635                         if (chroma_upscale)
1636                                 /* UV is subsampled by 2 horizontally */
1637                                 orig_width >>= 1;
1638                         else
1639                                 /* UV is downsampled by 2 horizontally */
1640                                 orig_width <<= 1;
1641                 }
1642
1643                 /* must use FIR for YUV422 if rotated */
1644                 if (rotation != OMAP_DSS_ROT_0)
1645                         scale_x = scale_y = true;
1646
1647                 break;
1648         default:
1649                 BUG();
1650                 return;
1651         }
1652
1653         if (out_width != orig_width)
1654                 scale_x = true;
1655         if (out_height != orig_height)
1656                 scale_y = true;
1657
1658         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1659                         out_width, out_height, five_taps,
1660                                 rotation, DISPC_COLOR_COMPONENT_UV);
1661
1662         if (plane != OMAP_DSS_WB)
1663                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1664                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1665
1666         /* set H scaling */
1667         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1668         /* set V scaling */
1669         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1670 }
1671
1672 static void dispc_ovl_set_scaling(enum omap_plane plane,
1673                 u16 orig_width, u16 orig_height,
1674                 u16 out_width, u16 out_height,
1675                 bool ilace, bool five_taps,
1676                 bool fieldmode, enum omap_color_mode color_mode,
1677                 u8 rotation)
1678 {
1679         BUG_ON(plane == OMAP_DSS_GFX);
1680
1681         dispc_ovl_set_scaling_common(plane,
1682                         orig_width, orig_height,
1683                         out_width, out_height,
1684                         ilace, five_taps,
1685                         fieldmode, color_mode,
1686                         rotation);
1687
1688         dispc_ovl_set_scaling_uv(plane,
1689                 orig_width, orig_height,
1690                 out_width, out_height,
1691                 ilace, five_taps,
1692                 fieldmode, color_mode,
1693                 rotation);
1694 }
1695
1696 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1697                 enum omap_dss_rotation_type rotation_type,
1698                 bool mirroring, enum omap_color_mode color_mode)
1699 {
1700         bool row_repeat = false;
1701         int vidrot = 0;
1702
1703         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1704                         color_mode == OMAP_DSS_COLOR_UYVY) {
1705
1706                 if (mirroring) {
1707                         switch (rotation) {
1708                         case OMAP_DSS_ROT_0:
1709                                 vidrot = 2;
1710                                 break;
1711                         case OMAP_DSS_ROT_90:
1712                                 vidrot = 1;
1713                                 break;
1714                         case OMAP_DSS_ROT_180:
1715                                 vidrot = 0;
1716                                 break;
1717                         case OMAP_DSS_ROT_270:
1718                                 vidrot = 3;
1719                                 break;
1720                         }
1721                 } else {
1722                         switch (rotation) {
1723                         case OMAP_DSS_ROT_0:
1724                                 vidrot = 0;
1725                                 break;
1726                         case OMAP_DSS_ROT_90:
1727                                 vidrot = 1;
1728                                 break;
1729                         case OMAP_DSS_ROT_180:
1730                                 vidrot = 2;
1731                                 break;
1732                         case OMAP_DSS_ROT_270:
1733                                 vidrot = 3;
1734                                 break;
1735                         }
1736                 }
1737
1738                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1739                         row_repeat = true;
1740                 else
1741                         row_repeat = false;
1742         }
1743
1744         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1745         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1746                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1747                         row_repeat ? 1 : 0, 18, 18);
1748
1749         if (color_mode == OMAP_DSS_COLOR_NV12) {
1750                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1751                                         (rotation == OMAP_DSS_ROT_0 ||
1752                                         rotation == OMAP_DSS_ROT_180);
1753                 /* DOUBLESTRIDE */
1754                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1755         }
1756
1757 }
1758
1759 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1760 {
1761         switch (color_mode) {
1762         case OMAP_DSS_COLOR_CLUT1:
1763                 return 1;
1764         case OMAP_DSS_COLOR_CLUT2:
1765                 return 2;
1766         case OMAP_DSS_COLOR_CLUT4:
1767                 return 4;
1768         case OMAP_DSS_COLOR_CLUT8:
1769         case OMAP_DSS_COLOR_NV12:
1770                 return 8;
1771         case OMAP_DSS_COLOR_RGB12U:
1772         case OMAP_DSS_COLOR_RGB16:
1773         case OMAP_DSS_COLOR_ARGB16:
1774         case OMAP_DSS_COLOR_YUV2:
1775         case OMAP_DSS_COLOR_UYVY:
1776         case OMAP_DSS_COLOR_RGBA16:
1777         case OMAP_DSS_COLOR_RGBX16:
1778         case OMAP_DSS_COLOR_ARGB16_1555:
1779         case OMAP_DSS_COLOR_XRGB16_1555:
1780                 return 16;
1781         case OMAP_DSS_COLOR_RGB24P:
1782                 return 24;
1783         case OMAP_DSS_COLOR_RGB24U:
1784         case OMAP_DSS_COLOR_ARGB32:
1785         case OMAP_DSS_COLOR_RGBA32:
1786         case OMAP_DSS_COLOR_RGBX32:
1787                 return 32;
1788         default:
1789                 BUG();
1790                 return 0;
1791         }
1792 }
1793
1794 static s32 pixinc(int pixels, u8 ps)
1795 {
1796         if (pixels == 1)
1797                 return 1;
1798         else if (pixels > 1)
1799                 return 1 + (pixels - 1) * ps;
1800         else if (pixels < 0)
1801                 return 1 - (-pixels + 1) * ps;
1802         else
1803                 BUG();
1804                 return 0;
1805 }
1806
1807 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1808                 u16 screen_width,
1809                 u16 width, u16 height,
1810                 enum omap_color_mode color_mode, bool fieldmode,
1811                 unsigned int field_offset,
1812                 unsigned *offset0, unsigned *offset1,
1813                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1814 {
1815         u8 ps;
1816
1817         /* FIXME CLUT formats */
1818         switch (color_mode) {
1819         case OMAP_DSS_COLOR_CLUT1:
1820         case OMAP_DSS_COLOR_CLUT2:
1821         case OMAP_DSS_COLOR_CLUT4:
1822         case OMAP_DSS_COLOR_CLUT8:
1823                 BUG();
1824                 return;
1825         case OMAP_DSS_COLOR_YUV2:
1826         case OMAP_DSS_COLOR_UYVY:
1827                 ps = 4;
1828                 break;
1829         default:
1830                 ps = color_mode_to_bpp(color_mode) / 8;
1831                 break;
1832         }
1833
1834         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1835                         width, height);
1836
1837         /*
1838          * field 0 = even field = bottom field
1839          * field 1 = odd field = top field
1840          */
1841         switch (rotation + mirror * 4) {
1842         case OMAP_DSS_ROT_0:
1843         case OMAP_DSS_ROT_180:
1844                 /*
1845                  * If the pixel format is YUV or UYVY divide the width
1846                  * of the image by 2 for 0 and 180 degree rotation.
1847                  */
1848                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1849                         color_mode == OMAP_DSS_COLOR_UYVY)
1850                         width = width >> 1;
1851         case OMAP_DSS_ROT_90:
1852         case OMAP_DSS_ROT_270:
1853                 *offset1 = 0;
1854                 if (field_offset)
1855                         *offset0 = field_offset * screen_width * ps;
1856                 else
1857                         *offset0 = 0;
1858
1859                 *row_inc = pixinc(1 +
1860                         (y_predecim * screen_width - x_predecim * width) +
1861                         (fieldmode ? screen_width : 0), ps);
1862                 *pix_inc = pixinc(x_predecim, ps);
1863                 break;
1864
1865         case OMAP_DSS_ROT_0 + 4:
1866         case OMAP_DSS_ROT_180 + 4:
1867                 /* If the pixel format is YUV or UYVY divide the width
1868                  * of the image by 2  for 0 degree and 180 degree
1869                  */
1870                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1871                         color_mode == OMAP_DSS_COLOR_UYVY)
1872                         width = width >> 1;
1873         case OMAP_DSS_ROT_90 + 4:
1874         case OMAP_DSS_ROT_270 + 4:
1875                 *offset1 = 0;
1876                 if (field_offset)
1877                         *offset0 = field_offset * screen_width * ps;
1878                 else
1879                         *offset0 = 0;
1880                 *row_inc = pixinc(1 -
1881                         (y_predecim * screen_width + x_predecim * width) -
1882                         (fieldmode ? screen_width : 0), ps);
1883                 *pix_inc = pixinc(x_predecim, ps);
1884                 break;
1885
1886         default:
1887                 BUG();
1888                 return;
1889         }
1890 }
1891
1892 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1893                 u16 screen_width,
1894                 u16 width, u16 height,
1895                 enum omap_color_mode color_mode, bool fieldmode,
1896                 unsigned int field_offset,
1897                 unsigned *offset0, unsigned *offset1,
1898                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1899 {
1900         u8 ps;
1901         u16 fbw, fbh;
1902
1903         /* FIXME CLUT formats */
1904         switch (color_mode) {
1905         case OMAP_DSS_COLOR_CLUT1:
1906         case OMAP_DSS_COLOR_CLUT2:
1907         case OMAP_DSS_COLOR_CLUT4:
1908         case OMAP_DSS_COLOR_CLUT8:
1909                 BUG();
1910                 return;
1911         default:
1912                 ps = color_mode_to_bpp(color_mode) / 8;
1913                 break;
1914         }
1915
1916         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1917                         width, height);
1918
1919         /* width & height are overlay sizes, convert to fb sizes */
1920
1921         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1922                 fbw = width;
1923                 fbh = height;
1924         } else {
1925                 fbw = height;
1926                 fbh = width;
1927         }
1928
1929         /*
1930          * field 0 = even field = bottom field
1931          * field 1 = odd field = top field
1932          */
1933         switch (rotation + mirror * 4) {
1934         case OMAP_DSS_ROT_0:
1935                 *offset1 = 0;
1936                 if (field_offset)
1937                         *offset0 = *offset1 + field_offset * screen_width * ps;
1938                 else
1939                         *offset0 = *offset1;
1940                 *row_inc = pixinc(1 +
1941                         (y_predecim * screen_width - fbw * x_predecim) +
1942                         (fieldmode ? screen_width : 0), ps);
1943                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1944                         color_mode == OMAP_DSS_COLOR_UYVY)
1945                         *pix_inc = pixinc(x_predecim, 2 * ps);
1946                 else
1947                         *pix_inc = pixinc(x_predecim, ps);
1948                 break;
1949         case OMAP_DSS_ROT_90:
1950                 *offset1 = screen_width * (fbh - 1) * ps;
1951                 if (field_offset)
1952                         *offset0 = *offset1 + field_offset * ps;
1953                 else
1954                         *offset0 = *offset1;
1955                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1956                                 y_predecim + (fieldmode ? 1 : 0), ps);
1957                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1958                 break;
1959         case OMAP_DSS_ROT_180:
1960                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1961                 if (field_offset)
1962                         *offset0 = *offset1 - field_offset * screen_width * ps;
1963                 else
1964                         *offset0 = *offset1;
1965                 *row_inc = pixinc(-1 -
1966                         (y_predecim * screen_width - fbw * x_predecim) -
1967                         (fieldmode ? screen_width : 0), ps);
1968                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1969                         color_mode == OMAP_DSS_COLOR_UYVY)
1970                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1971                 else
1972                         *pix_inc = pixinc(-x_predecim, ps);
1973                 break;
1974         case OMAP_DSS_ROT_270:
1975                 *offset1 = (fbw - 1) * ps;
1976                 if (field_offset)
1977                         *offset0 = *offset1 - field_offset * ps;
1978                 else
1979                         *offset0 = *offset1;
1980                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1981                                 y_predecim - (fieldmode ? 1 : 0), ps);
1982                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1983                 break;
1984
1985         /* mirroring */
1986         case OMAP_DSS_ROT_0 + 4:
1987                 *offset1 = (fbw - 1) * ps;
1988                 if (field_offset)
1989                         *offset0 = *offset1 + field_offset * screen_width * ps;
1990                 else
1991                         *offset0 = *offset1;
1992                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1993                                 (fieldmode ? screen_width : 0),
1994                                 ps);
1995                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1996                         color_mode == OMAP_DSS_COLOR_UYVY)
1997                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1998                 else
1999                         *pix_inc = pixinc(-x_predecim, ps);
2000                 break;
2001
2002         case OMAP_DSS_ROT_90 + 4:
2003                 *offset1 = 0;
2004                 if (field_offset)
2005                         *offset0 = *offset1 + field_offset * ps;
2006                 else
2007                         *offset0 = *offset1;
2008                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2009                                 y_predecim + (fieldmode ? 1 : 0),
2010                                 ps);
2011                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2012                 break;
2013
2014         case OMAP_DSS_ROT_180 + 4:
2015                 *offset1 = screen_width * (fbh - 1) * ps;
2016                 if (field_offset)
2017                         *offset0 = *offset1 - field_offset * screen_width * ps;
2018                 else
2019                         *offset0 = *offset1;
2020                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2021                                 (fieldmode ? screen_width : 0),
2022                                 ps);
2023                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2024                         color_mode == OMAP_DSS_COLOR_UYVY)
2025                         *pix_inc = pixinc(x_predecim, 2 * ps);
2026                 else
2027                         *pix_inc = pixinc(x_predecim, ps);
2028                 break;
2029
2030         case OMAP_DSS_ROT_270 + 4:
2031                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2032                 if (field_offset)
2033                         *offset0 = *offset1 - field_offset * ps;
2034                 else
2035                         *offset0 = *offset1;
2036                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2037                                 y_predecim - (fieldmode ? 1 : 0),
2038                                 ps);
2039                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2040                 break;
2041
2042         default:
2043                 BUG();
2044                 return;
2045         }
2046 }
2047
2048 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2049                 enum omap_color_mode color_mode, bool fieldmode,
2050                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2051                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2052 {
2053         u8 ps;
2054
2055         switch (color_mode) {
2056         case OMAP_DSS_COLOR_CLUT1:
2057         case OMAP_DSS_COLOR_CLUT2:
2058         case OMAP_DSS_COLOR_CLUT4:
2059         case OMAP_DSS_COLOR_CLUT8:
2060                 BUG();
2061                 return;
2062         default:
2063                 ps = color_mode_to_bpp(color_mode) / 8;
2064                 break;
2065         }
2066
2067         DSSDBG("scrw %d, width %d\n", screen_width, width);
2068
2069         /*
2070          * field 0 = even field = bottom field
2071          * field 1 = odd field = top field
2072          */
2073         *offset1 = 0;
2074         if (field_offset)
2075                 *offset0 = *offset1 + field_offset * screen_width * ps;
2076         else
2077                 *offset0 = *offset1;
2078         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2079                         (fieldmode ? screen_width : 0), ps);
2080         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2081                 color_mode == OMAP_DSS_COLOR_UYVY)
2082                 *pix_inc = pixinc(x_predecim, 2 * ps);
2083         else
2084                 *pix_inc = pixinc(x_predecim, ps);
2085 }
2086
2087 /*
2088  * This function is used to avoid synclosts in OMAP3, because of some
2089  * undocumented horizontal position and timing related limitations.
2090  */
2091 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2092                 const struct omap_video_timings *t, u16 pos_x,
2093                 u16 width, u16 height, u16 out_width, u16 out_height,
2094                 bool five_taps)
2095 {
2096         const int ds = DIV_ROUND_UP(height, out_height);
2097         unsigned long nonactive;
2098         static const u8 limits[3] = { 8, 10, 20 };
2099         u64 val, blank;
2100         int i;
2101
2102         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2103
2104         i = 0;
2105         if (out_height < height)
2106                 i++;
2107         if (out_width < width)
2108                 i++;
2109         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2110         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2111         if (blank <= limits[i])
2112                 return -EINVAL;
2113
2114         /* FIXME add checks for 3-tap filter once the limitations are known */
2115         if (!five_taps)
2116                 return 0;
2117
2118         /*
2119          * Pixel data should be prepared before visible display point starts.
2120          * So, atleast DS-2 lines must have already been fetched by DISPC
2121          * during nonactive - pos_x period.
2122          */
2123         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2124         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2125                 val, max(0, ds - 2) * width);
2126         if (val < max(0, ds - 2) * width)
2127                 return -EINVAL;
2128
2129         /*
2130          * All lines need to be refilled during the nonactive period of which
2131          * only one line can be loaded during the active period. So, atleast
2132          * DS - 1 lines should be loaded during nonactive period.
2133          */
2134         val =  div_u64((u64)nonactive * lclk, pclk);
2135         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2136                 val, max(0, ds - 1) * width);
2137         if (val < max(0, ds - 1) * width)
2138                 return -EINVAL;
2139
2140         return 0;
2141 }
2142
2143 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2144                 const struct omap_video_timings *mgr_timings, u16 width,
2145                 u16 height, u16 out_width, u16 out_height,
2146                 enum omap_color_mode color_mode)
2147 {
2148         u32 core_clk = 0;
2149         u64 tmp;
2150
2151         if (height <= out_height && width <= out_width)
2152                 return (unsigned long) pclk;
2153
2154         if (height > out_height) {
2155                 unsigned int ppl = mgr_timings->x_res;
2156
2157                 tmp = pclk * height * out_width;
2158                 do_div(tmp, 2 * out_height * ppl);
2159                 core_clk = tmp;
2160
2161                 if (height > 2 * out_height) {
2162                         if (ppl == out_width)
2163                                 return 0;
2164
2165                         tmp = pclk * (height - 2 * out_height) * out_width;
2166                         do_div(tmp, 2 * out_height * (ppl - out_width));
2167                         core_clk = max_t(u32, core_clk, tmp);
2168                 }
2169         }
2170
2171         if (width > out_width) {
2172                 tmp = pclk * width;
2173                 do_div(tmp, out_width);
2174                 core_clk = max_t(u32, core_clk, tmp);
2175
2176                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2177                         core_clk <<= 1;
2178         }
2179
2180         return core_clk;
2181 }
2182
2183 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2184                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2185 {
2186         if (height > out_height && width > out_width)
2187                 return pclk * 4;
2188         else
2189                 return pclk * 2;
2190 }
2191
2192 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2193                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2194 {
2195         unsigned int hf, vf;
2196
2197         /*
2198          * FIXME how to determine the 'A' factor
2199          * for the no downscaling case ?
2200          */
2201
2202         if (width > 3 * out_width)
2203                 hf = 4;
2204         else if (width > 2 * out_width)
2205                 hf = 3;
2206         else if (width > out_width)
2207                 hf = 2;
2208         else
2209                 hf = 1;
2210         if (height > out_height)
2211                 vf = 2;
2212         else
2213                 vf = 1;
2214
2215         return pclk * vf * hf;
2216 }
2217
2218 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2219                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2220 {
2221         /*
2222          * If the overlay/writeback is in mem to mem mode, there are no
2223          * downscaling limitations with respect to pixel clock, return 1 as
2224          * required core clock to represent that we have sufficient enough
2225          * core clock to do maximum downscaling
2226          */
2227         if (mem_to_mem)
2228                 return 1;
2229
2230         if (width > out_width)
2231                 return DIV_ROUND_UP(pclk, out_width) * width;
2232         else
2233                 return pclk;
2234 }
2235
2236 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2237                 const struct omap_video_timings *mgr_timings,
2238                 u16 width, u16 height, u16 out_width, u16 out_height,
2239                 enum omap_color_mode color_mode, bool *five_taps,
2240                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2241                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2242 {
2243         int error;
2244         u16 in_width, in_height;
2245         int min_factor = min(*decim_x, *decim_y);
2246         const int maxsinglelinewidth =
2247                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2248
2249         *five_taps = false;
2250
2251         do {
2252                 in_height = height / *decim_y;
2253                 in_width = width / *decim_x;
2254                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2255                                 in_height, out_width, out_height, mem_to_mem);
2256                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2257                         *core_clk > dispc_core_clk_rate());
2258                 if (error) {
2259                         if (*decim_x == *decim_y) {
2260                                 *decim_x = min_factor;
2261                                 ++*decim_y;
2262                         } else {
2263                                 swap(*decim_x, *decim_y);
2264                                 if (*decim_x < *decim_y)
2265                                         ++*decim_x;
2266                         }
2267                 }
2268         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2269
2270         if (in_width > maxsinglelinewidth) {
2271                 DSSERR("Cannot scale max input width exceeded");
2272                 return -EINVAL;
2273         }
2274         return 0;
2275 }
2276
2277 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2278                 const struct omap_video_timings *mgr_timings,
2279                 u16 width, u16 height, u16 out_width, u16 out_height,
2280                 enum omap_color_mode color_mode, bool *five_taps,
2281                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2282                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2283 {
2284         int error;
2285         u16 in_width, in_height;
2286         int min_factor = min(*decim_x, *decim_y);
2287         const int maxsinglelinewidth =
2288                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2289
2290         do {
2291                 in_height = height / *decim_y;
2292                 in_width = width / *decim_x;
2293                 *five_taps = in_height > out_height;
2294
2295                 if (in_width > maxsinglelinewidth)
2296                         if (in_height > out_height &&
2297                                                 in_height < out_height * 2)
2298                                 *five_taps = false;
2299 again:
2300                 if (*five_taps)
2301                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2302                                                 in_width, in_height, out_width,
2303                                                 out_height, color_mode);
2304                 else
2305                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2306                                         in_height, out_width, out_height,
2307                                         mem_to_mem);
2308
2309                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2310                                 pos_x, in_width, in_height, out_width,
2311                                 out_height, *five_taps);
2312                 if (error && *five_taps) {
2313                         *five_taps = false;
2314                         goto again;
2315                 }
2316
2317                 error = (error || in_width > maxsinglelinewidth * 2 ||
2318                         (in_width > maxsinglelinewidth && *five_taps) ||
2319                         !*core_clk || *core_clk > dispc_core_clk_rate());
2320                 if (error) {
2321                         if (*decim_x == *decim_y) {
2322                                 *decim_x = min_factor;
2323                                 ++*decim_y;
2324                         } else {
2325                                 swap(*decim_x, *decim_y);
2326                                 if (*decim_x < *decim_y)
2327                                         ++*decim_x;
2328                         }
2329                 }
2330         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2331
2332         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2333                                 height, out_width, out_height, *five_taps)) {
2334                         DSSERR("horizontal timing too tight\n");
2335                         return -EINVAL;
2336         }
2337
2338         if (in_width > (maxsinglelinewidth * 2)) {
2339                 DSSERR("Cannot setup scaling");
2340                 DSSERR("width exceeds maximum width possible");
2341                 return -EINVAL;
2342         }
2343
2344         if (in_width > maxsinglelinewidth && *five_taps) {
2345                 DSSERR("cannot setup scaling with five taps");
2346                 return -EINVAL;
2347         }
2348         return 0;
2349 }
2350
2351 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2352                 const struct omap_video_timings *mgr_timings,
2353                 u16 width, u16 height, u16 out_width, u16 out_height,
2354                 enum omap_color_mode color_mode, bool *five_taps,
2355                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2356                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2357 {
2358         u16 in_width, in_width_max;
2359         int decim_x_min = *decim_x;
2360         u16 in_height = height / *decim_y;
2361         const int maxsinglelinewidth =
2362                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2363         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2364
2365         if (mem_to_mem) {
2366                 in_width_max = out_width * maxdownscale;
2367         } else {
2368                 in_width_max = dispc_core_clk_rate() /
2369                                         DIV_ROUND_UP(pclk, out_width);
2370         }
2371
2372         *decim_x = DIV_ROUND_UP(width, in_width_max);
2373
2374         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2375         if (*decim_x > *x_predecim)
2376                 return -EINVAL;
2377
2378         do {
2379                 in_width = width / *decim_x;
2380         } while (*decim_x <= *x_predecim &&
2381                         in_width > maxsinglelinewidth && ++*decim_x);
2382
2383         if (in_width > maxsinglelinewidth) {
2384                 DSSERR("Cannot scale width exceeds max line width");
2385                 return -EINVAL;
2386         }
2387
2388         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2389                                 out_width, out_height, mem_to_mem);
2390         return 0;
2391 }
2392
2393 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2394                 enum omap_overlay_caps caps,
2395                 const struct omap_video_timings *mgr_timings,
2396                 u16 width, u16 height, u16 out_width, u16 out_height,
2397                 enum omap_color_mode color_mode, bool *five_taps,
2398                 int *x_predecim, int *y_predecim, u16 pos_x,
2399                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2400 {
2401         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2402         const int max_decim_limit = 16;
2403         unsigned long core_clk = 0;
2404         int decim_x, decim_y, ret;
2405
2406         if (width == out_width && height == out_height)
2407                 return 0;
2408
2409         if (pclk == 0 || mgr_timings->pixelclock == 0) {
2410                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2411                 return -EINVAL;
2412         }
2413
2414         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2415                 return -EINVAL;
2416
2417         if (mem_to_mem) {
2418                 *x_predecim = *y_predecim = 1;
2419         } else {
2420                 *x_predecim = max_decim_limit;
2421                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2422                                 dss_has_feature(FEAT_BURST_2D)) ?
2423                                 2 : max_decim_limit;
2424         }
2425
2426         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2427             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2428             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2429             color_mode == OMAP_DSS_COLOR_CLUT8) {
2430                 *x_predecim = 1;
2431                 *y_predecim = 1;
2432                 *five_taps = false;
2433                 return 0;
2434         }
2435
2436         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2437         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2438
2439         if (decim_x > *x_predecim || out_width > width * 8)
2440                 return -EINVAL;
2441
2442         if (decim_y > *y_predecim || out_height > height * 8)
2443                 return -EINVAL;
2444
2445         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2446                 out_width, out_height, color_mode, five_taps,
2447                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2448                 mem_to_mem);
2449         if (ret)
2450                 return ret;
2451
2452         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2453         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2454
2455         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2456                 DSSERR("failed to set up scaling, "
2457                         "required core clk rate = %lu Hz, "
2458                         "current core clk rate = %lu Hz\n",
2459                         core_clk, dispc_core_clk_rate());
2460                 return -EINVAL;
2461         }
2462
2463         *x_predecim = decim_x;
2464         *y_predecim = decim_y;
2465         return 0;
2466 }
2467
2468 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2469                 const struct omap_overlay_info *oi,
2470                 const struct omap_video_timings *timings,
2471                 int *x_predecim, int *y_predecim)
2472 {
2473         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2474         bool five_taps = true;
2475         bool fieldmode = false;
2476         u16 in_height = oi->height;
2477         u16 in_width = oi->width;
2478         bool ilace = timings->interlace;
2479         u16 out_width, out_height;
2480         int pos_x = oi->pos_x;
2481         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2482         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2483
2484         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2485         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2486
2487         if (ilace && oi->height == out_height)
2488                 fieldmode = true;
2489
2490         if (ilace) {
2491                 if (fieldmode)
2492                         in_height /= 2;
2493                 out_height /= 2;
2494
2495                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2496                                 in_height, out_height);
2497         }
2498
2499         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2500                 return -EINVAL;
2501
2502         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2503                         in_height, out_width, out_height, oi->color_mode,
2504                         &five_taps, x_predecim, y_predecim, pos_x,
2505                         oi->rotation_type, false);
2506 }
2507 EXPORT_SYMBOL(dispc_ovl_check);
2508
2509 static int dispc_ovl_setup_common(enum omap_plane plane,
2510                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2511                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2512                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2513                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2514                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2515                 bool replication, const struct omap_video_timings *mgr_timings,
2516                 bool mem_to_mem)
2517 {
2518         bool five_taps = true;
2519         bool fieldmode = false;
2520         int r, cconv = 0;
2521         unsigned offset0, offset1;
2522         s32 row_inc;
2523         s32 pix_inc;
2524         u16 frame_width, frame_height;
2525         unsigned int field_offset = 0;
2526         u16 in_height = height;
2527         u16 in_width = width;
2528         int x_predecim = 1, y_predecim = 1;
2529         bool ilace = mgr_timings->interlace;
2530         unsigned long pclk = dispc_plane_pclk_rate(plane);
2531         unsigned long lclk = dispc_plane_lclk_rate(plane);
2532
2533         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2534                 return -EINVAL;
2535
2536         out_width = out_width == 0 ? width : out_width;
2537         out_height = out_height == 0 ? height : out_height;
2538
2539         if (ilace && height == out_height)
2540                 fieldmode = true;
2541
2542         if (ilace) {
2543                 if (fieldmode)
2544                         in_height /= 2;
2545                 pos_y /= 2;
2546                 out_height /= 2;
2547
2548                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2549                         "out_height %d\n", in_height, pos_y,
2550                         out_height);
2551         }
2552
2553         if (!dss_feat_color_mode_supported(plane, color_mode))
2554                 return -EINVAL;
2555
2556         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2557                         in_height, out_width, out_height, color_mode,
2558                         &five_taps, &x_predecim, &y_predecim, pos_x,
2559                         rotation_type, mem_to_mem);
2560         if (r)
2561                 return r;
2562
2563         in_width = in_width / x_predecim;
2564         in_height = in_height / y_predecim;
2565
2566         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2567                         color_mode == OMAP_DSS_COLOR_UYVY ||
2568                         color_mode == OMAP_DSS_COLOR_NV12)
2569                 cconv = 1;
2570
2571         if (ilace && !fieldmode) {
2572                 /*
2573                  * when downscaling the bottom field may have to start several
2574                  * source lines below the top field. Unfortunately ACCUI
2575                  * registers will only hold the fractional part of the offset
2576                  * so the integer part must be added to the base address of the
2577                  * bottom field.
2578                  */
2579                 if (!in_height || in_height == out_height)
2580                         field_offset = 0;
2581                 else
2582                         field_offset = in_height / out_height / 2;
2583         }
2584
2585         /* Fields are independent but interleaved in memory. */
2586         if (fieldmode)
2587                 field_offset = 1;
2588
2589         offset0 = 0;
2590         offset1 = 0;
2591         row_inc = 0;
2592         pix_inc = 0;
2593
2594         if (plane == OMAP_DSS_WB) {
2595                 frame_width = out_width;
2596                 frame_height = out_height;
2597         } else {
2598                 frame_width = in_width;
2599                 frame_height = height;
2600         }
2601
2602         if (rotation_type == OMAP_DSS_ROT_TILER)
2603                 calc_tiler_rotation_offset(screen_width, frame_width,
2604                                 color_mode, fieldmode, field_offset,
2605                                 &offset0, &offset1, &row_inc, &pix_inc,
2606                                 x_predecim, y_predecim);
2607         else if (rotation_type == OMAP_DSS_ROT_DMA)
2608                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2609                                 frame_width, frame_height,
2610                                 color_mode, fieldmode, field_offset,
2611                                 &offset0, &offset1, &row_inc, &pix_inc,
2612                                 x_predecim, y_predecim);
2613         else
2614                 calc_vrfb_rotation_offset(rotation, mirror,
2615                                 screen_width, frame_width, frame_height,
2616                                 color_mode, fieldmode, field_offset,
2617                                 &offset0, &offset1, &row_inc, &pix_inc,
2618                                 x_predecim, y_predecim);
2619
2620         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2621                         offset0, offset1, row_inc, pix_inc);
2622
2623         dispc_ovl_set_color_mode(plane, color_mode);
2624
2625         dispc_ovl_configure_burst_type(plane, rotation_type);
2626
2627         dispc_ovl_set_ba0(plane, paddr + offset0);
2628         dispc_ovl_set_ba1(plane, paddr + offset1);
2629
2630         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2631                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2632                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2633         }
2634
2635         dispc_ovl_set_row_inc(plane, row_inc);
2636         dispc_ovl_set_pix_inc(plane, pix_inc);
2637
2638         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2639                         in_height, out_width, out_height);
2640
2641         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2642
2643         dispc_ovl_set_input_size(plane, in_width, in_height);
2644
2645         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2646                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2647                                    out_height, ilace, five_taps, fieldmode,
2648                                    color_mode, rotation);
2649                 dispc_ovl_set_output_size(plane, out_width, out_height);
2650                 dispc_ovl_set_vid_color_conv(plane, cconv);
2651         }
2652
2653         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2654                         color_mode);
2655
2656         dispc_ovl_set_zorder(plane, caps, zorder);
2657         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2658         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2659
2660         dispc_ovl_enable_replication(plane, caps, replication);
2661
2662         return 0;
2663 }
2664
2665 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2666                 bool replication, const struct omap_video_timings *mgr_timings,
2667                 bool mem_to_mem)
2668 {
2669         int r;
2670         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2671         enum omap_channel channel;
2672
2673         channel = dispc_ovl_get_channel_out(plane);
2674
2675         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2676                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2677                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2678                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2679                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2680
2681         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2682                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2683                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2684                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2685                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2686
2687         return r;
2688 }
2689 EXPORT_SYMBOL(dispc_ovl_setup);
2690
2691 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2692                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2693 {
2694         int r;
2695         u32 l;
2696         enum omap_plane plane = OMAP_DSS_WB;
2697         const int pos_x = 0, pos_y = 0;
2698         const u8 zorder = 0, global_alpha = 0;
2699         const bool replication = false;
2700         bool truncation;
2701         int in_width = mgr_timings->x_res;
2702         int in_height = mgr_timings->y_res;
2703         enum omap_overlay_caps caps =
2704                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2705
2706         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2707                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2708                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2709                 wi->mirror);
2710
2711         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2712                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2713                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2714                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2715                 replication, mgr_timings, mem_to_mem);
2716
2717         switch (wi->color_mode) {
2718         case OMAP_DSS_COLOR_RGB16:
2719         case OMAP_DSS_COLOR_RGB24P:
2720         case OMAP_DSS_COLOR_ARGB16:
2721         case OMAP_DSS_COLOR_RGBA16:
2722         case OMAP_DSS_COLOR_RGB12U:
2723         case OMAP_DSS_COLOR_ARGB16_1555:
2724         case OMAP_DSS_COLOR_XRGB16_1555:
2725         case OMAP_DSS_COLOR_RGBX16:
2726                 truncation = true;
2727                 break;
2728         default:
2729                 truncation = false;
2730                 break;
2731         }
2732
2733         /* setup extra DISPC_WB_ATTRIBUTES */
2734         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2735         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2736         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2737         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2738
2739         return r;
2740 }
2741
2742 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2743 {
2744         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2745
2746         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2747
2748         return 0;
2749 }
2750 EXPORT_SYMBOL(dispc_ovl_enable);
2751
2752 bool dispc_ovl_enabled(enum omap_plane plane)
2753 {
2754         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2755 }
2756 EXPORT_SYMBOL(dispc_ovl_enabled);
2757
2758 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2759 {
2760         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2761         /* flush posted write */
2762         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2763 }
2764 EXPORT_SYMBOL(dispc_mgr_enable);
2765
2766 bool dispc_mgr_is_enabled(enum omap_channel channel)
2767 {
2768         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2769 }
2770 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2771
2772 void dispc_wb_enable(bool enable)
2773 {
2774         dispc_ovl_enable(OMAP_DSS_WB, enable);
2775 }
2776
2777 bool dispc_wb_is_enabled(void)
2778 {
2779         return dispc_ovl_enabled(OMAP_DSS_WB);
2780 }
2781
2782 static void dispc_lcd_enable_signal_polarity(bool act_high)
2783 {
2784         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2785                 return;
2786
2787         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2788 }
2789
2790 void dispc_lcd_enable_signal(bool enable)
2791 {
2792         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2793                 return;
2794
2795         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2796 }
2797
2798 void dispc_pck_free_enable(bool enable)
2799 {
2800         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2801                 return;
2802
2803         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2804 }
2805
2806 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2807 {
2808         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2809 }
2810
2811
2812 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2813 {
2814         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2815 }
2816
2817 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2818 {
2819         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2820 }
2821
2822
2823 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2824 {
2825         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2826 }
2827
2828 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2829                 enum omap_dss_trans_key_type type,
2830                 u32 trans_key)
2831 {
2832         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2833
2834         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2835 }
2836
2837 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2838 {
2839         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2840 }
2841
2842 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2843                 bool enable)
2844 {
2845         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2846                 return;
2847
2848         if (ch == OMAP_DSS_CHANNEL_LCD)
2849                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2850         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2851                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2852 }
2853
2854 void dispc_mgr_setup(enum omap_channel channel,
2855                 const struct omap_overlay_manager_info *info)
2856 {
2857         dispc_mgr_set_default_color(channel, info->default_color);
2858         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2859         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2860         dispc_mgr_enable_alpha_fixed_zorder(channel,
2861                         info->partial_alpha_enabled);
2862         if (dss_has_feature(FEAT_CPR)) {
2863                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2864                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2865         }
2866 }
2867 EXPORT_SYMBOL(dispc_mgr_setup);
2868
2869 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2870 {
2871         int code;
2872
2873         switch (data_lines) {
2874         case 12:
2875                 code = 0;
2876                 break;
2877         case 16:
2878                 code = 1;
2879                 break;
2880         case 18:
2881                 code = 2;
2882                 break;
2883         case 24:
2884                 code = 3;
2885                 break;
2886         default:
2887                 BUG();
2888                 return;
2889         }
2890
2891         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2892 }
2893
2894 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2895 {
2896         u32 l;
2897         int gpout0, gpout1;
2898
2899         switch (mode) {
2900         case DSS_IO_PAD_MODE_RESET:
2901                 gpout0 = 0;
2902                 gpout1 = 0;
2903                 break;
2904         case DSS_IO_PAD_MODE_RFBI:
2905                 gpout0 = 1;
2906                 gpout1 = 0;
2907                 break;
2908         case DSS_IO_PAD_MODE_BYPASS:
2909                 gpout0 = 1;
2910                 gpout1 = 1;
2911                 break;
2912         default:
2913                 BUG();
2914                 return;
2915         }
2916
2917         l = dispc_read_reg(DISPC_CONTROL);
2918         l = FLD_MOD(l, gpout0, 15, 15);
2919         l = FLD_MOD(l, gpout1, 16, 16);
2920         dispc_write_reg(DISPC_CONTROL, l);
2921 }
2922
2923 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2924 {
2925         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2926 }
2927
2928 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2929                 const struct dss_lcd_mgr_config *config)
2930 {
2931         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2932
2933         dispc_mgr_enable_stallmode(channel, config->stallmode);
2934         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2935
2936         dispc_mgr_set_clock_div(channel, &config->clock_info);
2937
2938         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2939
2940         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2941
2942         dispc_mgr_set_lcd_type_tft(channel);
2943 }
2944 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2945
2946 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2947 {
2948         return width <= dispc.feat->mgr_width_max &&
2949                 height <= dispc.feat->mgr_height_max;
2950 }
2951
2952 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2953                 int vsw, int vfp, int vbp)
2954 {
2955         if (hsw < 1 || hsw > dispc.feat->sw_max ||
2956                         hfp < 1 || hfp > dispc.feat->hp_max ||
2957                         hbp < 1 || hbp > dispc.feat->hp_max ||
2958                         vsw < 1 || vsw > dispc.feat->sw_max ||
2959                         vfp < 0 || vfp > dispc.feat->vp_max ||
2960                         vbp < 0 || vbp > dispc.feat->vp_max)
2961                 return false;
2962         return true;
2963 }
2964
2965 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2966                 unsigned long pclk)
2967 {
2968         if (dss_mgr_is_lcd(channel))
2969                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2970         else
2971                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2972 }
2973
2974 bool dispc_mgr_timings_ok(enum omap_channel channel,
2975                 const struct omap_video_timings *timings)
2976 {
2977         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2978                 return false;
2979
2980         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2981                 return false;
2982
2983         if (dss_mgr_is_lcd(channel)) {
2984                 /* TODO: OMAP4+ supports interlace for LCD outputs */
2985                 if (timings->interlace)
2986                         return false;
2987
2988                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2989                                 timings->hbp, timings->vsw, timings->vfp,
2990                                 timings->vbp))
2991                         return false;
2992         }
2993
2994         return true;
2995 }
2996
2997 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2998                 int hfp, int hbp, int vsw, int vfp, int vbp,
2999                 enum omap_dss_signal_level vsync_level,
3000                 enum omap_dss_signal_level hsync_level,
3001                 enum omap_dss_signal_edge data_pclk_edge,
3002                 enum omap_dss_signal_level de_level,
3003                 enum omap_dss_signal_edge sync_pclk_edge)
3004
3005 {
3006         u32 timing_h, timing_v, l;
3007         bool onoff, rf, ipc, vs, hs, de;
3008
3009         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3010                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3011                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3012         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3013                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3014                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3015
3016         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3017         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3018
3019         switch (vsync_level) {
3020         case OMAPDSS_SIG_ACTIVE_LOW:
3021                 vs = true;
3022                 break;
3023         case OMAPDSS_SIG_ACTIVE_HIGH:
3024                 vs = false;
3025                 break;
3026         default:
3027                 BUG();
3028         }
3029
3030         switch (hsync_level) {
3031         case OMAPDSS_SIG_ACTIVE_LOW:
3032                 hs = true;
3033                 break;
3034         case OMAPDSS_SIG_ACTIVE_HIGH:
3035                 hs = false;
3036                 break;
3037         default:
3038                 BUG();
3039         }
3040
3041         switch (de_level) {
3042         case OMAPDSS_SIG_ACTIVE_LOW:
3043                 de = true;
3044                 break;
3045         case OMAPDSS_SIG_ACTIVE_HIGH:
3046                 de = false;
3047                 break;
3048         default:
3049                 BUG();
3050         }
3051
3052         switch (data_pclk_edge) {
3053         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3054                 ipc = false;
3055                 break;
3056         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3057                 ipc = true;
3058                 break;
3059         default:
3060                 BUG();
3061         }
3062
3063         /* always use the 'rf' setting */
3064         onoff = true;
3065
3066         switch (sync_pclk_edge) {
3067         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3068                 rf = false;
3069                 break;
3070         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3071                 rf = true;
3072                 break;
3073         default:
3074                 BUG();
3075         }
3076
3077         l = FLD_VAL(onoff, 17, 17) |
3078                 FLD_VAL(rf, 16, 16) |
3079                 FLD_VAL(de, 15, 15) |
3080                 FLD_VAL(ipc, 14, 14) |
3081                 FLD_VAL(hs, 13, 13) |
3082                 FLD_VAL(vs, 12, 12);
3083
3084         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3085
3086         if (dispc.syscon_pol) {
3087                 const int shifts[] = {
3088                         [OMAP_DSS_CHANNEL_LCD] = 0,
3089                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3090                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3091                 };
3092
3093                 u32 mask, val;
3094
3095                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3096                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3097
3098                 mask <<= 16 + shifts[channel];
3099                 val <<= 16 + shifts[channel];
3100
3101                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3102                         mask, val);
3103         }
3104 }
3105
3106 /* change name to mode? */
3107 void dispc_mgr_set_timings(enum omap_channel channel,
3108                 const struct omap_video_timings *timings)
3109 {
3110         unsigned xtot, ytot;
3111         unsigned long ht, vt;
3112         struct omap_video_timings t = *timings;
3113
3114         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3115
3116         if (!dispc_mgr_timings_ok(channel, &t)) {
3117                 BUG();
3118                 return;
3119         }
3120
3121         if (dss_mgr_is_lcd(channel)) {
3122                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3123                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3124                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3125
3126                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3127                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3128
3129                 ht = timings->pixelclock / xtot;
3130                 vt = timings->pixelclock / xtot / ytot;
3131
3132                 DSSDBG("pck %u\n", timings->pixelclock);
3133                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3134                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3135                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3136                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3137                         t.de_level, t.sync_pclk_edge);
3138
3139                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3140         } else {
3141                 if (t.interlace == true)
3142                         t.y_res /= 2;
3143         }
3144
3145         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3146 }
3147 EXPORT_SYMBOL(dispc_mgr_set_timings);
3148
3149 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3150                 u16 pck_div)
3151 {
3152         BUG_ON(lck_div < 1);
3153         BUG_ON(pck_div < 1);
3154
3155         dispc_write_reg(DISPC_DIVISORo(channel),
3156                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3157
3158         if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3159                         channel == OMAP_DSS_CHANNEL_LCD)
3160                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3161 }
3162
3163 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3164                 int *pck_div)
3165 {
3166         u32 l;
3167         l = dispc_read_reg(DISPC_DIVISORo(channel));
3168         *lck_div = FLD_GET(l, 23, 16);
3169         *pck_div = FLD_GET(l, 7, 0);
3170 }
3171
3172 unsigned long dispc_fclk_rate(void)
3173 {
3174         struct dss_pll *pll;
3175         unsigned long r = 0;
3176
3177         switch (dss_get_dispc_clk_source()) {
3178         case OMAP_DSS_CLK_SRC_FCK:
3179                 r = dss_get_dispc_clk_rate();
3180                 break;
3181         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3182                 pll = dss_pll_find("dsi0");
3183                 if (!pll)
3184                         pll = dss_pll_find("video0");
3185
3186                 r = pll->cinfo.clkout[0];
3187                 break;
3188         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3189                 pll = dss_pll_find("dsi1");
3190                 if (!pll)
3191                         pll = dss_pll_find("video1");
3192
3193                 r = pll->cinfo.clkout[0];
3194                 break;
3195         default:
3196                 BUG();
3197                 return 0;
3198         }
3199
3200         return r;
3201 }
3202
3203 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3204 {
3205         struct dss_pll *pll;
3206         int lcd;
3207         unsigned long r;
3208         u32 l;
3209
3210         if (dss_mgr_is_lcd(channel)) {
3211                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3212
3213                 lcd = FLD_GET(l, 23, 16);
3214
3215                 switch (dss_get_lcd_clk_source(channel)) {
3216                 case OMAP_DSS_CLK_SRC_FCK:
3217                         r = dss_get_dispc_clk_rate();
3218                         break;
3219                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3220                         pll = dss_pll_find("dsi0");
3221                         if (!pll)
3222                                 pll = dss_pll_find("video0");
3223
3224                         r = pll->cinfo.clkout[0];
3225                         break;
3226                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3227                         pll = dss_pll_find("dsi1");
3228                         if (!pll)
3229                                 pll = dss_pll_find("video1");
3230
3231                         r = pll->cinfo.clkout[0];
3232                         break;
3233                 default:
3234                         BUG();
3235                         return 0;
3236                 }
3237
3238                 return r / lcd;
3239         } else {
3240                 return dispc_fclk_rate();
3241         }
3242 }
3243
3244 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3245 {
3246         unsigned long r;
3247
3248         if (dss_mgr_is_lcd(channel)) {
3249                 int pcd;
3250                 u32 l;
3251
3252                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3253
3254                 pcd = FLD_GET(l, 7, 0);
3255
3256                 r = dispc_mgr_lclk_rate(channel);
3257
3258                 return r / pcd;
3259         } else {
3260                 return dispc.tv_pclk_rate;
3261         }
3262 }
3263
3264 void dispc_set_tv_pclk(unsigned long pclk)
3265 {
3266         dispc.tv_pclk_rate = pclk;
3267 }
3268
3269 unsigned long dispc_core_clk_rate(void)
3270 {
3271         return dispc.core_clk_rate;
3272 }
3273
3274 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3275 {
3276         enum omap_channel channel;
3277
3278         if (plane == OMAP_DSS_WB)
3279                 return 0;
3280
3281         channel = dispc_ovl_get_channel_out(plane);
3282
3283         return dispc_mgr_pclk_rate(channel);
3284 }
3285
3286 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3287 {
3288         enum omap_channel channel;
3289
3290         if (plane == OMAP_DSS_WB)
3291                 return 0;
3292
3293         channel = dispc_ovl_get_channel_out(plane);
3294
3295         return dispc_mgr_lclk_rate(channel);
3296 }
3297
3298 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3299 {
3300         int lcd, pcd;
3301         enum omap_dss_clk_source lcd_clk_src;
3302
3303         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3304
3305         lcd_clk_src = dss_get_lcd_clk_source(channel);
3306
3307         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3308                 dss_get_generic_clk_source_name(lcd_clk_src),
3309                 dss_feat_get_clk_source_name(lcd_clk_src));
3310
3311         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3312
3313         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3314                 dispc_mgr_lclk_rate(channel), lcd);
3315         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3316                 dispc_mgr_pclk_rate(channel), pcd);
3317 }
3318
3319 void dispc_dump_clocks(struct seq_file *s)
3320 {
3321         int lcd;
3322         u32 l;
3323         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3324
3325         if (dispc_runtime_get())
3326                 return;
3327
3328         seq_printf(s, "- DISPC -\n");
3329
3330         seq_printf(s, "dispc fclk source = %s (%s)\n",
3331                         dss_get_generic_clk_source_name(dispc_clk_src),
3332                         dss_feat_get_clk_source_name(dispc_clk_src));
3333
3334         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3335
3336         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3337                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3338                 l = dispc_read_reg(DISPC_DIVISOR);
3339                 lcd = FLD_GET(l, 23, 16);
3340
3341                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3342                                 (dispc_fclk_rate()/lcd), lcd);
3343         }
3344
3345         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3346
3347         if (dss_has_feature(FEAT_MGR_LCD2))
3348                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3349         if (dss_has_feature(FEAT_MGR_LCD3))
3350                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3351
3352         dispc_runtime_put();
3353 }
3354
3355 static void dispc_dump_regs(struct seq_file *s)
3356 {
3357         int i, j;
3358         const char *mgr_names[] = {
3359                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3360                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3361                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3362                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3363         };
3364         const char *ovl_names[] = {
3365                 [OMAP_DSS_GFX]          = "GFX",
3366                 [OMAP_DSS_VIDEO1]       = "VID1",
3367                 [OMAP_DSS_VIDEO2]       = "VID2",
3368                 [OMAP_DSS_VIDEO3]       = "VID3",
3369         };
3370         const char **p_names;
3371
3372 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3373
3374         if (dispc_runtime_get())
3375                 return;
3376
3377         /* DISPC common registers */
3378         DUMPREG(DISPC_REVISION);
3379         DUMPREG(DISPC_SYSCONFIG);
3380         DUMPREG(DISPC_SYSSTATUS);
3381         DUMPREG(DISPC_IRQSTATUS);
3382         DUMPREG(DISPC_IRQENABLE);
3383         DUMPREG(DISPC_CONTROL);
3384         DUMPREG(DISPC_CONFIG);
3385         DUMPREG(DISPC_CAPABLE);
3386         DUMPREG(DISPC_LINE_STATUS);
3387         DUMPREG(DISPC_LINE_NUMBER);
3388         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3389                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3390                 DUMPREG(DISPC_GLOBAL_ALPHA);
3391         if (dss_has_feature(FEAT_MGR_LCD2)) {
3392                 DUMPREG(DISPC_CONTROL2);
3393                 DUMPREG(DISPC_CONFIG2);
3394         }
3395         if (dss_has_feature(FEAT_MGR_LCD3)) {
3396                 DUMPREG(DISPC_CONTROL3);
3397                 DUMPREG(DISPC_CONFIG3);
3398         }
3399         if (dss_has_feature(FEAT_MFLAG))
3400                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3401
3402 #undef DUMPREG
3403
3404 #define DISPC_REG(i, name) name(i)
3405 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3406         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3407         dispc_read_reg(DISPC_REG(i, r)))
3408
3409         p_names = mgr_names;
3410
3411         /* DISPC channel specific registers */
3412         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3413                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3414                 DUMPREG(i, DISPC_TRANS_COLOR);
3415                 DUMPREG(i, DISPC_SIZE_MGR);
3416
3417                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3418                         continue;
3419
3420                 DUMPREG(i, DISPC_TIMING_H);
3421                 DUMPREG(i, DISPC_TIMING_V);
3422                 DUMPREG(i, DISPC_POL_FREQ);
3423                 DUMPREG(i, DISPC_DIVISORo);
3424
3425                 DUMPREG(i, DISPC_DATA_CYCLE1);
3426                 DUMPREG(i, DISPC_DATA_CYCLE2);
3427                 DUMPREG(i, DISPC_DATA_CYCLE3);
3428
3429                 if (dss_has_feature(FEAT_CPR)) {
3430                         DUMPREG(i, DISPC_CPR_COEF_R);
3431                         DUMPREG(i, DISPC_CPR_COEF_G);
3432                         DUMPREG(i, DISPC_CPR_COEF_B);
3433                 }
3434         }
3435
3436         p_names = ovl_names;
3437
3438         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3439                 DUMPREG(i, DISPC_OVL_BA0);
3440                 DUMPREG(i, DISPC_OVL_BA1);
3441                 DUMPREG(i, DISPC_OVL_POSITION);
3442                 DUMPREG(i, DISPC_OVL_SIZE);
3443                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3444                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3445                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3446                 DUMPREG(i, DISPC_OVL_ROW_INC);
3447                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3448
3449                 if (dss_has_feature(FEAT_PRELOAD))
3450                         DUMPREG(i, DISPC_OVL_PRELOAD);
3451                 if (dss_has_feature(FEAT_MFLAG))
3452                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3453
3454                 if (i == OMAP_DSS_GFX) {
3455                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3456                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3457                         continue;
3458                 }
3459
3460                 DUMPREG(i, DISPC_OVL_FIR);
3461                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3462                 DUMPREG(i, DISPC_OVL_ACCU0);
3463                 DUMPREG(i, DISPC_OVL_ACCU1);
3464                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3465                         DUMPREG(i, DISPC_OVL_BA0_UV);
3466                         DUMPREG(i, DISPC_OVL_BA1_UV);
3467                         DUMPREG(i, DISPC_OVL_FIR2);
3468                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3469                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3470                 }
3471                 if (dss_has_feature(FEAT_ATTR2))
3472                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3473         }
3474
3475 #undef DISPC_REG
3476 #undef DUMPREG
3477
3478 #define DISPC_REG(plane, name, i) name(plane, i)
3479 #define DUMPREG(plane, name, i) \
3480         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3481         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3482         dispc_read_reg(DISPC_REG(plane, name, i)))
3483
3484         /* Video pipeline coefficient registers */
3485
3486         /* start from OMAP_DSS_VIDEO1 */
3487         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3488                 for (j = 0; j < 8; j++)
3489                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3490
3491                 for (j = 0; j < 8; j++)
3492                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3493
3494                 for (j = 0; j < 5; j++)
3495                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3496
3497                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3498                         for (j = 0; j < 8; j++)
3499                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3500                 }
3501
3502                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3503                         for (j = 0; j < 8; j++)
3504                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3505
3506                         for (j = 0; j < 8; j++)
3507                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3508
3509                         for (j = 0; j < 8; j++)
3510                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3511                 }
3512         }
3513
3514         dispc_runtime_put();
3515
3516 #undef DISPC_REG
3517 #undef DUMPREG
3518 }
3519
3520 /* calculate clock rates using dividers in cinfo */
3521 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3522                 struct dispc_clock_info *cinfo)
3523 {
3524         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3525                 return -EINVAL;
3526         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3527                 return -EINVAL;
3528
3529         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3530         cinfo->pck = cinfo->lck / cinfo->pck_div;
3531
3532         return 0;
3533 }
3534
3535 bool dispc_div_calc(unsigned long dispc,
3536                 unsigned long pck_min, unsigned long pck_max,
3537                 dispc_div_calc_func func, void *data)
3538 {
3539         int lckd, lckd_start, lckd_stop;
3540         int pckd, pckd_start, pckd_stop;
3541         unsigned long pck, lck;
3542         unsigned long lck_max;
3543         unsigned long pckd_hw_min, pckd_hw_max;
3544         unsigned min_fck_per_pck;
3545         unsigned long fck;
3546
3547 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3548         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3549 #else
3550         min_fck_per_pck = 0;
3551 #endif
3552
3553         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3554         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3555
3556         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3557
3558         pck_min = pck_min ? pck_min : 1;
3559         pck_max = pck_max ? pck_max : ULONG_MAX;
3560
3561         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3562         lckd_stop = min(dispc / pck_min, 255ul);
3563
3564         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3565                 lck = dispc / lckd;
3566
3567                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3568                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3569
3570                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3571                         pck = lck / pckd;
3572
3573                         /*
3574                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3575                          * clock, which means we're configuring DISPC fclk here
3576                          * also. Thus we need to use the calculated lck. For
3577                          * OMAP4+ the DISPC fclk is a separate clock.
3578                          */
3579                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3580                                 fck = dispc_core_clk_rate();
3581                         else
3582                                 fck = lck;
3583
3584                         if (fck < pck * min_fck_per_pck)
3585                                 continue;
3586
3587                         if (func(lckd, pckd, lck, pck, data))
3588                                 return true;
3589                 }
3590         }
3591
3592         return false;
3593 }
3594
3595 void dispc_mgr_set_clock_div(enum omap_channel channel,
3596                 const struct dispc_clock_info *cinfo)
3597 {
3598         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3599         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3600
3601         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3602 }
3603
3604 int dispc_mgr_get_clock_div(enum omap_channel channel,
3605                 struct dispc_clock_info *cinfo)
3606 {
3607         unsigned long fck;
3608
3609         fck = dispc_fclk_rate();
3610
3611         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3612         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3613
3614         cinfo->lck = fck / cinfo->lck_div;
3615         cinfo->pck = cinfo->lck / cinfo->pck_div;
3616
3617         return 0;
3618 }
3619
3620 u32 dispc_read_irqstatus(void)
3621 {
3622         return dispc_read_reg(DISPC_IRQSTATUS);
3623 }
3624 EXPORT_SYMBOL(dispc_read_irqstatus);
3625
3626 void dispc_clear_irqstatus(u32 mask)
3627 {
3628         dispc_write_reg(DISPC_IRQSTATUS, mask);
3629 }
3630 EXPORT_SYMBOL(dispc_clear_irqstatus);
3631
3632 u32 dispc_read_irqenable(void)
3633 {
3634         return dispc_read_reg(DISPC_IRQENABLE);
3635 }
3636 EXPORT_SYMBOL(dispc_read_irqenable);
3637
3638 void dispc_write_irqenable(u32 mask)
3639 {
3640         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3641
3642         /* clear the irqstatus for newly enabled irqs */
3643         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3644
3645         dispc_write_reg(DISPC_IRQENABLE, mask);
3646 }
3647 EXPORT_SYMBOL(dispc_write_irqenable);
3648
3649 void dispc_enable_sidle(void)
3650 {
3651         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3652 }
3653
3654 void dispc_disable_sidle(void)
3655 {
3656         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3657 }
3658
3659 static void _omap_dispc_initial_config(void)
3660 {
3661         u32 l;
3662
3663         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3664         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3665                 l = dispc_read_reg(DISPC_DIVISOR);
3666                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3667                 l = FLD_MOD(l, 1, 0, 0);
3668                 l = FLD_MOD(l, 1, 23, 16);
3669                 dispc_write_reg(DISPC_DIVISOR, l);
3670
3671                 dispc.core_clk_rate = dispc_fclk_rate();
3672         }
3673
3674         /* FUNCGATED */
3675         if (dss_has_feature(FEAT_FUNCGATED))
3676                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3677
3678         dispc_setup_color_conv_coef();
3679
3680         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3681
3682         dispc_init_fifos();
3683
3684         dispc_configure_burst_sizes();
3685
3686         dispc_ovl_enable_zorder_planes();
3687
3688         if (dispc.feat->mstandby_workaround)
3689                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3690
3691         if (dss_has_feature(FEAT_MFLAG))
3692                 dispc_init_mflag();
3693 }
3694
3695 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3696         .sw_start               =       5,
3697         .fp_start               =       15,
3698         .bp_start               =       27,
3699         .sw_max                 =       64,
3700         .vp_max                 =       255,
3701         .hp_max                 =       256,
3702         .mgr_width_start        =       10,
3703         .mgr_height_start       =       26,
3704         .mgr_width_max          =       2048,
3705         .mgr_height_max         =       2048,
3706         .max_lcd_pclk           =       66500000,
3707         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3708         .calc_core_clk          =       calc_core_clk_24xx,
3709         .num_fifos              =       3,
3710         .no_framedone_tv        =       true,
3711         .set_max_preload        =       false,
3712 };
3713
3714 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3715         .sw_start               =       5,
3716         .fp_start               =       15,
3717         .bp_start               =       27,
3718         .sw_max                 =       64,
3719         .vp_max                 =       255,
3720         .hp_max                 =       256,
3721         .mgr_width_start        =       10,
3722         .mgr_height_start       =       26,
3723         .mgr_width_max          =       2048,
3724         .mgr_height_max         =       2048,
3725         .max_lcd_pclk           =       173000000,
3726         .max_tv_pclk            =       59000000,
3727         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3728         .calc_core_clk          =       calc_core_clk_34xx,
3729         .num_fifos              =       3,
3730         .no_framedone_tv        =       true,
3731         .set_max_preload        =       false,
3732 };
3733
3734 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3735         .sw_start               =       7,
3736         .fp_start               =       19,
3737         .bp_start               =       31,
3738         .sw_max                 =       256,
3739         .vp_max                 =       4095,
3740         .hp_max                 =       4096,
3741         .mgr_width_start        =       10,
3742         .mgr_height_start       =       26,
3743         .mgr_width_max          =       2048,
3744         .mgr_height_max         =       2048,
3745         .max_lcd_pclk           =       173000000,
3746         .max_tv_pclk            =       59000000,
3747         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3748         .calc_core_clk          =       calc_core_clk_34xx,
3749         .num_fifos              =       3,
3750         .no_framedone_tv        =       true,
3751         .set_max_preload        =       false,
3752 };
3753
3754 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3755         .sw_start               =       7,
3756         .fp_start               =       19,
3757         .bp_start               =       31,
3758         .sw_max                 =       256,
3759         .vp_max                 =       4095,
3760         .hp_max                 =       4096,
3761         .mgr_width_start        =       10,
3762         .mgr_height_start       =       26,
3763         .mgr_width_max          =       2048,
3764         .mgr_height_max         =       2048,
3765         .max_lcd_pclk           =       170000000,
3766         .max_tv_pclk            =       185625000,
3767         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3768         .calc_core_clk          =       calc_core_clk_44xx,
3769         .num_fifos              =       5,
3770         .gfx_fifo_workaround    =       true,
3771         .set_max_preload        =       true,
3772 };
3773
3774 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3775         .sw_start               =       7,
3776         .fp_start               =       19,
3777         .bp_start               =       31,
3778         .sw_max                 =       256,
3779         .vp_max                 =       4095,
3780         .hp_max                 =       4096,
3781         .mgr_width_start        =       11,
3782         .mgr_height_start       =       27,
3783         .mgr_width_max          =       4096,
3784         .mgr_height_max         =       4096,
3785         .max_lcd_pclk           =       170000000,
3786         .max_tv_pclk            =       186000000,
3787         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3788         .calc_core_clk          =       calc_core_clk_44xx,
3789         .num_fifos              =       5,
3790         .gfx_fifo_workaround    =       true,
3791         .mstandby_workaround    =       true,
3792         .set_max_preload        =       true,
3793 };
3794
3795 static int __init dispc_init_features(struct platform_device *pdev)
3796 {
3797         const struct dispc_features *src;
3798         struct dispc_features *dst;
3799
3800         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3801         if (!dst) {
3802                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3803                 return -ENOMEM;
3804         }
3805
3806         switch (omapdss_get_version()) {
3807         case OMAPDSS_VER_OMAP24xx:
3808                 src = &omap24xx_dispc_feats;
3809                 break;
3810
3811         case OMAPDSS_VER_OMAP34xx_ES1:
3812                 src = &omap34xx_rev1_0_dispc_feats;
3813                 break;
3814
3815         case OMAPDSS_VER_OMAP34xx_ES3:
3816         case OMAPDSS_VER_OMAP3630:
3817         case OMAPDSS_VER_AM35xx:
3818         case OMAPDSS_VER_AM43xx:
3819                 src = &omap34xx_rev3_0_dispc_feats;
3820                 break;
3821
3822         case OMAPDSS_VER_OMAP4430_ES1:
3823         case OMAPDSS_VER_OMAP4430_ES2:
3824         case OMAPDSS_VER_OMAP4:
3825                 src = &omap44xx_dispc_feats;
3826                 break;
3827
3828         case OMAPDSS_VER_OMAP5:
3829         case OMAPDSS_VER_DRA7xx:
3830                 src = &omap54xx_dispc_feats;
3831                 break;
3832
3833         default:
3834                 return -ENODEV;
3835         }
3836
3837         memcpy(dst, src, sizeof(*dst));
3838         dispc.feat = dst;
3839
3840         return 0;
3841 }
3842
3843 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3844 {
3845         if (!dispc.is_enabled)
3846                 return IRQ_NONE;
3847
3848         return dispc.user_handler(irq, dispc.user_data);
3849 }
3850
3851 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3852 {
3853         int r;
3854
3855         if (dispc.user_handler != NULL)
3856                 return -EBUSY;
3857
3858         dispc.user_handler = handler;
3859         dispc.user_data = dev_id;
3860
3861         /* ensure the dispc_irq_handler sees the values above */
3862         smp_wmb();
3863
3864         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3865                              IRQF_SHARED, "OMAP DISPC", &dispc);
3866         if (r) {
3867                 dispc.user_handler = NULL;
3868                 dispc.user_data = NULL;
3869         }
3870
3871         return r;
3872 }
3873 EXPORT_SYMBOL(dispc_request_irq);
3874
3875 void dispc_free_irq(void *dev_id)
3876 {
3877         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3878
3879         dispc.user_handler = NULL;
3880         dispc.user_data = NULL;
3881 }
3882 EXPORT_SYMBOL(dispc_free_irq);
3883
3884 /* DISPC HW IP initialisation */
3885 static int __init omap_dispchw_probe(struct platform_device *pdev)
3886 {
3887         u32 rev;
3888         int r = 0;
3889         struct resource *dispc_mem;
3890         struct device_node *np = pdev->dev.of_node;
3891
3892         dispc.pdev = pdev;
3893
3894         spin_lock_init(&dispc.control_lock);
3895
3896         r = dispc_init_features(dispc.pdev);
3897         if (r)
3898                 return r;
3899
3900         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3901         if (!dispc_mem) {
3902                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3903                 return -EINVAL;
3904         }
3905
3906         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3907                                   resource_size(dispc_mem));
3908         if (!dispc.base) {
3909                 DSSERR("can't ioremap DISPC\n");
3910                 return -ENOMEM;
3911         }
3912
3913         dispc.irq = platform_get_irq(dispc.pdev, 0);
3914         if (dispc.irq < 0) {
3915                 DSSERR("platform_get_irq failed\n");
3916                 return -ENODEV;
3917         }
3918
3919         if (np && of_property_read_bool(np, "syscon-pol")) {
3920                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3921                 if (IS_ERR(dispc.syscon_pol)) {
3922                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3923                         return PTR_ERR(dispc.syscon_pol);
3924                 }
3925
3926                 if (of_property_read_u32_index(np, "syscon-pol", 1,
3927                                 &dispc.syscon_pol_offset)) {
3928                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3929                         return -EINVAL;
3930                 }
3931         }
3932
3933         pm_runtime_enable(&pdev->dev);
3934
3935         r = dispc_runtime_get();
3936         if (r)
3937                 goto err_runtime_get;
3938
3939         _omap_dispc_initial_config();
3940
3941         rev = dispc_read_reg(DISPC_REVISION);
3942         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3943                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3944
3945         dispc_runtime_put();
3946
3947         dss_init_overlay_managers();
3948
3949         dss_debugfs_create_file("dispc", dispc_dump_regs);
3950
3951         return 0;
3952
3953 err_runtime_get:
3954         pm_runtime_disable(&pdev->dev);
3955         return r;
3956 }
3957
3958 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3959 {
3960         pm_runtime_disable(&pdev->dev);
3961
3962         dss_uninit_overlay_managers();
3963
3964         return 0;
3965 }
3966
3967 static int dispc_runtime_suspend(struct device *dev)
3968 {
3969         dispc.is_enabled = false;
3970         /* ensure the dispc_irq_handler sees the is_enabled value */
3971         smp_wmb();
3972         /* wait for current handler to finish before turning the DISPC off */
3973         synchronize_irq(dispc.irq);
3974
3975         dispc_save_context();
3976
3977         return 0;
3978 }
3979
3980 static int dispc_runtime_resume(struct device *dev)
3981 {
3982         /*
3983          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3984          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3985          * _omap_dispc_initial_config(). We can thus use it to detect if
3986          * we have lost register context.
3987          */
3988         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
3989                 _omap_dispc_initial_config();
3990
3991                 dispc_restore_context();
3992         }
3993
3994         dispc.is_enabled = true;
3995         /* ensure the dispc_irq_handler sees the is_enabled value */
3996         smp_wmb();
3997
3998         return 0;
3999 }
4000
4001 static const struct dev_pm_ops dispc_pm_ops = {
4002         .runtime_suspend = dispc_runtime_suspend,
4003         .runtime_resume = dispc_runtime_resume,
4004 };
4005
4006 static const struct of_device_id dispc_of_match[] = {
4007         { .compatible = "ti,omap2-dispc", },
4008         { .compatible = "ti,omap3-dispc", },
4009         { .compatible = "ti,omap4-dispc", },
4010         { .compatible = "ti,omap5-dispc", },
4011         { .compatible = "ti,dra7-dispc", },
4012         {},
4013 };
4014
4015 static struct platform_driver omap_dispchw_driver = {
4016         .remove         = __exit_p(omap_dispchw_remove),
4017         .driver         = {
4018                 .name   = "omapdss_dispc",
4019                 .pm     = &dispc_pm_ops,
4020                 .of_match_table = dispc_of_match,
4021                 .suppress_bind_attrs = true,
4022         },
4023 };
4024
4025 int __init dispc_init_platform_driver(void)
4026 {
4027         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
4028 }
4029
4030 void __exit dispc_uninit_platform_driver(void)
4031 {
4032         platform_driver_unregister(&omap_dispchw_driver);
4033 }