kernel/drivers/video/fbdev/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include <video/omapdss.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48 #include "dispc.h"
  49
  50 /* DISPC */
  51 #define DISPC_SZ_REGS                   SZ_4K
  52
  53 enum omap_burst_size {
  54         BURST_SIZE_X2 = 0,
  55         BURST_SIZE_X4 = 1,
  56         BURST_SIZE_X8 = 2,
  57 };
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dispc_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end)                               \
  63         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  64
  65 struct dispc_features {
  66         u8 sw_start;
  67         u8 fp_start;
  68         u8 bp_start;
  69         u16 sw_max;
  70         u16 vp_max;
  71         u16 hp_max;
  72         u8 mgr_width_start;
  73         u8 mgr_height_start;
  74         u16 mgr_width_max;
  75         u16 mgr_height_max;
  76         unsigned long max_lcd_pclk;
  77         unsigned long max_tv_pclk;
  78         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  79                 const struct omap_video_timings *mgr_timings,
  80                 u16 width, u16 height, u16 out_width, u16 out_height,
  81                 enum omap_color_mode color_mode, bool *five_taps,
  82                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  83                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  84         unsigned long (*calc_core_clk) (unsigned long pclk,
  85                 u16 width, u16 height, u16 out_width, u16 out_height,
  86                 bool mem_to_mem);
  87         u8 num_fifos;
  88
  89         /* swap GFX & WB fifos */
  90         bool gfx_fifo_workaround:1;
  91
  92         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  93         bool no_framedone_tv:1;
  94
  95         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  96         bool mstandby_workaround:1;
  97
  98         bool set_max_preload:1;
  99
 100         /* PIXEL_INC is not added to the last pixel of a line */
 101         bool last_pixel_inc_missing:1;
 102 };
 103
 104 #define DISPC_MAX_NR_FIFOS 5
 105
 106 static struct {
 107         struct platform_device *pdev;
 108         void __iomem    *base;
 109
 110         int irq;
 111         irq_handler_t user_handler;
 112         void *user_data;
 113
 114         unsigned long core_clk_rate;
 115         unsigned long tv_pclk_rate;
 116
 117         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 118         /* maps which plane is using a fifo. fifo-id -> plane-id */
 119         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 120
 121         bool            ctx_valid;
 122         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 123
 124         const struct dispc_features *feat;
 125
 126         bool is_enabled;
 127
 128         struct regmap *syscon_pol;
 129         u32 syscon_pol_offset;
 130
 131         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 132         spinlock_t control_lock;
 133 } dispc;
 134
 135 enum omap_color_component {
 136         /* used for all color formats for OMAP3 and earlier
 137          * and for RGB and Y color component on OMAP4
 138          */
 139         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 140         /* used for UV component for
 141          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 142          * color formats on OMAP4
 143          */
 144         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 145 };
 146
 147 enum mgr_reg_fields {
 148         DISPC_MGR_FLD_ENABLE,
 149         DISPC_MGR_FLD_STNTFT,
 150         DISPC_MGR_FLD_GO,
 151         DISPC_MGR_FLD_TFTDATALINES,
 152         DISPC_MGR_FLD_STALLMODE,
 153         DISPC_MGR_FLD_TCKENABLE,
 154         DISPC_MGR_FLD_TCKSELECTION,
 155         DISPC_MGR_FLD_CPR,
 156         DISPC_MGR_FLD_FIFOHANDCHECK,
 157         /* used to maintain a count of the above fields */
 158         DISPC_MGR_FLD_NUM,
 159 };
 160
 161 struct dispc_reg_field {
 162         u16 reg;
 163         u8 high;
 164         u8 low;
 165 };
 166
 167 static const struct {
 168         const char *name;
 169         u32 vsync_irq;
 170         u32 framedone_irq;
 171         u32 sync_lost_irq;
 172         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 173 } mgr_desc[] = {
 174         [OMAP_DSS_CHANNEL_LCD] = {
 175                 .name           = "LCD",
 176                 .vsync_irq      = DISPC_IRQ_VSYNC,
 177                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 178                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 179                 .reg_desc       = {
 180                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 181                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 182                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 183                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 184                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 185                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 186                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 187                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 188                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 189                 },
 190         },
 191         [OMAP_DSS_CHANNEL_DIGIT] = {
 192                 .name           = "DIGIT",
 193                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 194                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 195                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 196                 .reg_desc       = {
 197                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 198                         [DISPC_MGR_FLD_STNTFT]          = { },
 199                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 200                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 201                         [DISPC_MGR_FLD_STALLMODE]       = { },
 202                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 203                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 204                         [DISPC_MGR_FLD_CPR]             = { },
 205                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 206                 },
 207         },
 208         [OMAP_DSS_CHANNEL_LCD2] = {
 209                 .name           = "LCD2",
 210                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 211                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 212                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 213                 .reg_desc       = {
 214                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 215                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 216                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 217                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 218                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 219                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 220                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 221                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 222                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 223                 },
 224         },
 225         [OMAP_DSS_CHANNEL_LCD3] = {
 226                 .name           = "LCD3",
 227                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 228                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 229                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 230                 .reg_desc       = {
 231                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 232                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 233                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 234                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 235                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 236                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 237                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 238                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 239                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 240                 },
 241         },
 242 };
 243
 244 struct color_conv_coef {
 245         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 246         int full_range;
 247 };
 248
 249 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 250 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 251
 252 static inline void dispc_write_reg(const u16 idx, u32 val)
 253 {
 254         __raw_writel(val, dispc.base + idx);
 255 }
 256
 257 static inline u32 dispc_read_reg(const u16 idx)
 258 {
 259         return __raw_readl(dispc.base + idx);
 260 }
 261
 262 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 263 {
 264         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 265         return REG_GET(rfld.reg, rfld.high, rfld.low);
 266 }
 267
 268 static void mgr_fld_write(enum omap_channel channel,
 269                                         enum mgr_reg_fields regfld, int val) {
 270         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 271         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 272         unsigned long flags;
 273
 274         if (need_lock)
 275                 spin_lock_irqsave(&dispc.control_lock, flags);
 276
 277         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 278
 279         if (need_lock)
 280                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 281 }
 282
 283 #define SR(reg) \
 284         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 285 #define RR(reg) \
 286         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 287
 288 static void dispc_save_context(void)
 289 {
 290         int i, j;
 291
 292         DSSDBG("dispc_save_context\n");
 293
 294         SR(IRQENABLE);
 295         SR(CONTROL);
 296         SR(CONFIG);
 297         SR(LINE_NUMBER);
 298         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 299                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 300                 SR(GLOBAL_ALPHA);
 301         if (dss_has_feature(FEAT_MGR_LCD2)) {
 302                 SR(CONTROL2);
 303                 SR(CONFIG2);
 304         }
 305         if (dss_has_feature(FEAT_MGR_LCD3)) {
 306                 SR(CONTROL3);
 307                 SR(CONFIG3);
 308         }
 309
 310         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 311                 SR(DEFAULT_COLOR(i));
 312                 SR(TRANS_COLOR(i));
 313                 SR(SIZE_MGR(i));
 314                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 315                         continue;
 316                 SR(TIMING_H(i));
 317                 SR(TIMING_V(i));
 318                 SR(POL_FREQ(i));
 319                 SR(DIVISORo(i));
 320
 321                 SR(DATA_CYCLE1(i));
 322                 SR(DATA_CYCLE2(i));
 323                 SR(DATA_CYCLE3(i));
 324
 325                 if (dss_has_feature(FEAT_CPR)) {
 326                         SR(CPR_COEF_R(i));
 327                         SR(CPR_COEF_G(i));
 328                         SR(CPR_COEF_B(i));
 329                 }
 330         }
 331
 332         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 333                 SR(OVL_BA0(i));
 334                 SR(OVL_BA1(i));
 335                 SR(OVL_POSITION(i));
 336                 SR(OVL_SIZE(i));
 337                 SR(OVL_ATTRIBUTES(i));
 338                 SR(OVL_FIFO_THRESHOLD(i));
 339                 SR(OVL_ROW_INC(i));
 340                 SR(OVL_PIXEL_INC(i));
 341                 if (dss_has_feature(FEAT_PRELOAD))
 342                         SR(OVL_PRELOAD(i));
 343                 if (i == OMAP_DSS_GFX) {
 344                         SR(OVL_WINDOW_SKIP(i));
 345                         SR(OVL_TABLE_BA(i));
 346                         continue;
 347                 }
 348                 SR(OVL_FIR(i));
 349                 SR(OVL_PICTURE_SIZE(i));
 350                 SR(OVL_ACCU0(i));
 351                 SR(OVL_ACCU1(i));
 352
 353                 for (j = 0; j < 8; j++)
 354                         SR(OVL_FIR_COEF_H(i, j));
 355
 356                 for (j = 0; j < 8; j++)
 357                         SR(OVL_FIR_COEF_HV(i, j));
 358
 359                 for (j = 0; j < 5; j++)
 360                         SR(OVL_CONV_COEF(i, j));
 361
 362                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 363                         for (j = 0; j < 8; j++)
 364                                 SR(OVL_FIR_COEF_V(i, j));
 365                 }
 366
 367                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 368                         SR(OVL_BA0_UV(i));
 369                         SR(OVL_BA1_UV(i));
 370                         SR(OVL_FIR2(i));
 371                         SR(OVL_ACCU2_0(i));
 372                         SR(OVL_ACCU2_1(i));
 373
 374                         for (j = 0; j < 8; j++)
 375                                 SR(OVL_FIR_COEF_H2(i, j));
 376
 377                         for (j = 0; j < 8; j++)
 378                                 SR(OVL_FIR_COEF_HV2(i, j));
 379
 380                         for (j = 0; j < 8; j++)
 381                                 SR(OVL_FIR_COEF_V2(i, j));
 382                 }
 383                 if (dss_has_feature(FEAT_ATTR2))
 384                         SR(OVL_ATTRIBUTES2(i));
 385         }
 386
 387         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 388                 SR(DIVISOR);
 389
 390         dispc.ctx_valid = true;
 391
 392         DSSDBG("context saved\n");
 393 }
 394
 395 static void dispc_restore_context(void)
 396 {
 397         int i, j;
 398
 399         DSSDBG("dispc_restore_context\n");
 400
 401         if (!dispc.ctx_valid)
 402                 return;
 403
 404         /*RR(IRQENABLE);*/
 405         /*RR(CONTROL);*/
 406         RR(CONFIG);
 407         RR(LINE_NUMBER);
 408         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 409                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 410                 RR(GLOBAL_ALPHA);
 411         if (dss_has_feature(FEAT_MGR_LCD2))
 412                 RR(CONFIG2);
 413         if (dss_has_feature(FEAT_MGR_LCD3))
 414                 RR(CONFIG3);
 415
 416         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 417                 RR(DEFAULT_COLOR(i));
 418                 RR(TRANS_COLOR(i));
 419                 RR(SIZE_MGR(i));
 420                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 421                         continue;
 422                 RR(TIMING_H(i));
 423                 RR(TIMING_V(i));
 424                 RR(POL_FREQ(i));
 425                 RR(DIVISORo(i));
 426
 427                 RR(DATA_CYCLE1(i));
 428                 RR(DATA_CYCLE2(i));
 429                 RR(DATA_CYCLE3(i));
 430
 431                 if (dss_has_feature(FEAT_CPR)) {
 432                         RR(CPR_COEF_R(i));
 433                         RR(CPR_COEF_G(i));
 434                         RR(CPR_COEF_B(i));
 435                 }
 436         }
 437
 438         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 439                 RR(OVL_BA0(i));
 440                 RR(OVL_BA1(i));
 441                 RR(OVL_POSITION(i));
 442                 RR(OVL_SIZE(i));
 443                 RR(OVL_ATTRIBUTES(i));
 444                 RR(OVL_FIFO_THRESHOLD(i));
 445                 RR(OVL_ROW_INC(i));
 446                 RR(OVL_PIXEL_INC(i));
 447                 if (dss_has_feature(FEAT_PRELOAD))
 448                         RR(OVL_PRELOAD(i));
 449                 if (i == OMAP_DSS_GFX) {
 450                         RR(OVL_WINDOW_SKIP(i));
 451                         RR(OVL_TABLE_BA(i));
 452                         continue;
 453                 }
 454                 RR(OVL_FIR(i));
 455                 RR(OVL_PICTURE_SIZE(i));
 456                 RR(OVL_ACCU0(i));
 457                 RR(OVL_ACCU1(i));
 458
 459                 for (j = 0; j < 8; j++)
 460                         RR(OVL_FIR_COEF_H(i, j));
 461
 462                 for (j = 0; j < 8; j++)
 463                         RR(OVL_FIR_COEF_HV(i, j));
 464
 465                 for (j = 0; j < 5; j++)
 466                         RR(OVL_CONV_COEF(i, j));
 467
 468                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 469                         for (j = 0; j < 8; j++)
 470                                 RR(OVL_FIR_COEF_V(i, j));
 471                 }
 472
 473                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 474                         RR(OVL_BA0_UV(i));
 475                         RR(OVL_BA1_UV(i));
 476                         RR(OVL_FIR2(i));
 477                         RR(OVL_ACCU2_0(i));
 478                         RR(OVL_ACCU2_1(i));
 479
 480                         for (j = 0; j < 8; j++)
 481                                 RR(OVL_FIR_COEF_H2(i, j));
 482
 483                         for (j = 0; j < 8; j++)
 484                                 RR(OVL_FIR_COEF_HV2(i, j));
 485
 486                         for (j = 0; j < 8; j++)
 487                                 RR(OVL_FIR_COEF_V2(i, j));
 488                 }
 489                 if (dss_has_feature(FEAT_ATTR2))
 490                         RR(OVL_ATTRIBUTES2(i));
 491         }
 492
 493         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 494                 RR(DIVISOR);
 495
 496         /* enable last, because LCD & DIGIT enable are here */
 497         RR(CONTROL);
 498         if (dss_has_feature(FEAT_MGR_LCD2))
 499                 RR(CONTROL2);
 500         if (dss_has_feature(FEAT_MGR_LCD3))
 501                 RR(CONTROL3);
 502         /* clear spurious SYNC_LOST_DIGIT interrupts */
 503         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 504
 505         /*
 506          * enable last so IRQs won't trigger before
 507          * the context is fully restored
 508          */
 509         RR(IRQENABLE);
 510
 511         DSSDBG("context restored\n");
 512 }
 513
 514 #undef SR
 515 #undef RR
 516
 517 int dispc_runtime_get(void)
 518 {
 519         int r;
 520
 521         DSSDBG("dispc_runtime_get\n");
 522
 523         r = pm_runtime_get_sync(&dispc.pdev->dev);
 524         WARN_ON(r < 0);
 525         return r < 0 ? r : 0;
 526 }
 527 EXPORT_SYMBOL(dispc_runtime_get);
 528
 529 void dispc_runtime_put(void)
 530 {
 531         int r;
 532
 533         DSSDBG("dispc_runtime_put\n");
 534
 535         r = pm_runtime_put_sync(&dispc.pdev->dev);
 536         WARN_ON(r < 0 && r != -ENOSYS);
 537 }
 538 EXPORT_SYMBOL(dispc_runtime_put);
 539
 540 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 541 {
 542         return mgr_desc[channel].vsync_irq;
 543 }
 544 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 545
 546 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 547 {
 548         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 549                 return 0;
 550
 551         return mgr_desc[channel].framedone_irq;
 552 }
 553 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 554
 555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 556 {
 557         return mgr_desc[channel].sync_lost_irq;
 558 }
 559 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 560
 561 u32 dispc_wb_get_framedone_irq(void)
 562 {
 563         return DISPC_IRQ_FRAMEDONEWB;
 564 }
 565
 566 bool dispc_mgr_go_busy(enum omap_channel channel)
 567 {
 568         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 569 }
 570 EXPORT_SYMBOL(dispc_mgr_go_busy);
 571
 572 void dispc_mgr_go(enum omap_channel channel)
 573 {
 574         WARN_ON(dispc_mgr_is_enabled(channel) == false);
 575         WARN_ON(dispc_mgr_go_busy(channel));
 576
 577         DSSDBG("GO %s\n", mgr_desc[channel].name);
 578
 579         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 580 }
 581 EXPORT_SYMBOL(dispc_mgr_go);
 582
 583 bool dispc_wb_go_busy(void)
 584 {
 585         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 586 }
 587
 588 void dispc_wb_go(void)
 589 {
 590         enum omap_plane plane = OMAP_DSS_WB;
 591         bool enable, go;
 592
 593         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 594
 595         if (!enable)
 596                 return;
 597
 598         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 599         if (go) {
 600                 DSSERR("GO bit not down for WB\n");
 601                 return;
 602         }
 603
 604         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 605 }
 606
 607 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 608 {
 609         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 610 }
 611
 612 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 613 {
 614         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 615 }
 616
 617 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 618 {
 619         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 620 }
 621
 622 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 623 {
 624         BUG_ON(plane == OMAP_DSS_GFX);
 625
 626         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 627 }
 628
 629 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 630                 u32 value)
 631 {
 632         BUG_ON(plane == OMAP_DSS_GFX);
 633
 634         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 635 }
 636
 637 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 638 {
 639         BUG_ON(plane == OMAP_DSS_GFX);
 640
 641         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 642 }
 643
 644 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 645                                 int fir_vinc, int five_taps,
 646                                 enum omap_color_component color_comp)
 647 {
 648         const struct dispc_coef *h_coef, *v_coef;
 649         int i;
 650
 651         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 652         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 653
 654         for (i = 0; i < 8; i++) {
 655                 u32 h, hv;
 656
 657                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 658                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 659                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 660                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 661                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 662                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 663                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 664                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 665
 666                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 667                         dispc_ovl_write_firh_reg(plane, i, h);
 668                         dispc_ovl_write_firhv_reg(plane, i, hv);
 669                 } else {
 670                         dispc_ovl_write_firh2_reg(plane, i, h);
 671                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 672                 }
 673
 674         }
 675
 676         if (five_taps) {
 677                 for (i = 0; i < 8; i++) {
 678                         u32 v;
 679                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 680                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 681                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 682                                 dispc_ovl_write_firv_reg(plane, i, v);
 683                         else
 684                                 dispc_ovl_write_firv2_reg(plane, i, v);
 685                 }
 686         }
 687 }
 688
 689
 690 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 691                 const struct color_conv_coef *ct)
 692 {
 693 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 694
 695         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 696         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 697         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 698         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 699         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 700
 701         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 702
 703 #undef CVAL
 704 }
 705
 706 static void dispc_setup_color_conv_coef(void)
 707 {
 708         int i;
 709         int num_ovl = dss_feat_get_num_ovls();
 710         int num_wb = dss_feat_get_num_wbs();
 711         const struct color_conv_coef ctbl_bt601_5_ovl = {
 712                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 713         };
 714         const struct color_conv_coef ctbl_bt601_5_wb = {
 715                 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
 716         };
 717
 718         for (i = 1; i < num_ovl; i++)
 719                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 720
 721         for (; i < num_wb; i++)
 722                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
 723 }
 724
 725 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 726 {
 727         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 728 }
 729
 730 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 731 {
 732         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 733 }
 734
 735 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 736 {
 737         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 738 }
 739
 740 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 741 {
 742         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 743 }
 744
 745 static void dispc_ovl_set_pos(enum omap_plane plane,
 746                 enum omap_overlay_caps caps, int x, int y)
 747 {
 748         u32 val;
 749
 750         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 751                 return;
 752
 753         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 754
 755         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 756 }
 757
 758 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 759                 int height)
 760 {
 761         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 762
 763         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 764                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 765         else
 766                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 767 }
 768
 769 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 770                 int height)
 771 {
 772         u32 val;
 773
 774         BUG_ON(plane == OMAP_DSS_GFX);
 775
 776         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 777
 778         if (plane == OMAP_DSS_WB)
 779                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 780         else
 781                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 782 }
 783
 784 static void dispc_ovl_set_zorder(enum omap_plane plane,
 785                 enum omap_overlay_caps caps, u8 zorder)
 786 {
 787         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 788                 return;
 789
 790         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 791 }
 792
 793 static void dispc_ovl_enable_zorder_planes(void)
 794 {
 795         int i;
 796
 797         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 798                 return;
 799
 800         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 801                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 802 }
 803
 804 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 805                 enum omap_overlay_caps caps, bool enable)
 806 {
 807         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 808                 return;
 809
 810         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 811 }
 812
 813 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 814                 enum omap_overlay_caps caps, u8 global_alpha)
 815 {
 816         static const unsigned shifts[] = { 0, 8, 16, 24, };
 817         int shift;
 818
 819         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 820                 return;
 821
 822         shift = shifts[plane];
 823         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 824 }
 825
 826 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 827 {
 828         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 829 }
 830
 831 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 832 {
 833         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 834 }
 835
 836 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 837                 enum omap_color_mode color_mode)
 838 {
 839         u32 m = 0;
 840         if (plane != OMAP_DSS_GFX) {
 841                 switch (color_mode) {
 842                 case OMAP_DSS_COLOR_NV12:
 843                         m = 0x0; break;
 844                 case OMAP_DSS_COLOR_RGBX16:
 845                         m = 0x1; break;
 846                 case OMAP_DSS_COLOR_RGBA16:
 847                         m = 0x2; break;
 848                 case OMAP_DSS_COLOR_RGB12U:
 849                         m = 0x4; break;
 850                 case OMAP_DSS_COLOR_ARGB16:
 851                         m = 0x5; break;
 852                 case OMAP_DSS_COLOR_RGB16:
 853                         m = 0x6; break;
 854                 case OMAP_DSS_COLOR_ARGB16_1555:
 855                         m = 0x7; break;
 856                 case OMAP_DSS_COLOR_RGB24U:
 857                         m = 0x8; break;
 858                 case OMAP_DSS_COLOR_RGB24P:
 859                         m = 0x9; break;
 860                 case OMAP_DSS_COLOR_YUV2:
 861                         m = 0xa; break;
 862                 case OMAP_DSS_COLOR_UYVY:
 863                         m = 0xb; break;
 864                 case OMAP_DSS_COLOR_ARGB32:
 865                         m = 0xc; break;
 866                 case OMAP_DSS_COLOR_RGBA32:
 867                         m = 0xd; break;
 868                 case OMAP_DSS_COLOR_RGBX32:
 869                         m = 0xe; break;
 870                 case OMAP_DSS_COLOR_XRGB16_1555:
 871                         m = 0xf; break;
 872                 default:
 873                         BUG(); return;
 874                 }
 875         } else {
 876                 switch (color_mode) {
 877                 case OMAP_DSS_COLOR_CLUT1:
 878                         m = 0x0; break;
 879                 case OMAP_DSS_COLOR_CLUT2:
 880                         m = 0x1; break;
 881                 case OMAP_DSS_COLOR_CLUT4:
 882                         m = 0x2; break;
 883                 case OMAP_DSS_COLOR_CLUT8:
 884                         m = 0x3; break;
 885                 case OMAP_DSS_COLOR_RGB12U:
 886                         m = 0x4; break;
 887                 case OMAP_DSS_COLOR_ARGB16:
 888                         m = 0x5; break;
 889                 case OMAP_DSS_COLOR_RGB16:
 890                         m = 0x6; break;
 891                 case OMAP_DSS_COLOR_ARGB16_1555:
 892                         m = 0x7; break;
 893                 case OMAP_DSS_COLOR_RGB24U:
 894                         m = 0x8; break;
 895                 case OMAP_DSS_COLOR_RGB24P:
 896                         m = 0x9; break;
 897                 case OMAP_DSS_COLOR_RGBX16:
 898                         m = 0xa; break;
 899                 case OMAP_DSS_COLOR_RGBA16:
 900                         m = 0xb; break;
 901                 case OMAP_DSS_COLOR_ARGB32:
 902                         m = 0xc; break;
 903                 case OMAP_DSS_COLOR_RGBA32:
 904                         m = 0xd; break;
 905                 case OMAP_DSS_COLOR_RGBX32:
 906                         m = 0xe; break;
 907                 case OMAP_DSS_COLOR_XRGB16_1555:
 908                         m = 0xf; break;
 909                 default:
 910                         BUG(); return;
 911                 }
 912         }
 913
 914         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 915 }
 916
 917 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 918                 enum omap_dss_rotation_type rotation_type)
 919 {
 920         if (dss_has_feature(FEAT_BURST_2D) == 0)
 921                 return;
 922
 923         if (rotation_type == OMAP_DSS_ROT_TILER)
 924                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 925         else
 926                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 927 }
 928
 929 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 930 {
 931         int shift;
 932         u32 val;
 933         int chan = 0, chan2 = 0;
 934
 935         switch (plane) {
 936         case OMAP_DSS_GFX:
 937                 shift = 8;
 938                 break;
 939         case OMAP_DSS_VIDEO1:
 940         case OMAP_DSS_VIDEO2:
 941         case OMAP_DSS_VIDEO3:
 942                 shift = 16;
 943                 break;
 944         default:
 945                 BUG();
 946                 return;
 947         }
 948
 949         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 950         if (dss_has_feature(FEAT_MGR_LCD2)) {
 951                 switch (channel) {
 952                 case OMAP_DSS_CHANNEL_LCD:
 953                         chan = 0;
 954                         chan2 = 0;
 955                         break;
 956                 case OMAP_DSS_CHANNEL_DIGIT:
 957                         chan = 1;
 958                         chan2 = 0;
 959                         break;
 960                 case OMAP_DSS_CHANNEL_LCD2:
 961                         chan = 0;
 962                         chan2 = 1;
 963                         break;
 964                 case OMAP_DSS_CHANNEL_LCD3:
 965                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 966                                 chan = 0;
 967                                 chan2 = 2;
 968                         } else {
 969                                 BUG();
 970                                 return;
 971                         }
 972                         break;
 973                 default:
 974                         BUG();
 975                         return;
 976                 }
 977
 978                 val = FLD_MOD(val, chan, shift, shift);
 979                 val = FLD_MOD(val, chan2, 31, 30);
 980         } else {
 981                 val = FLD_MOD(val, channel, shift, shift);
 982         }
 983         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 984 }
 985 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
 986
 987 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 988 {
 989         int shift;
 990         u32 val;
 991         enum omap_channel channel;
 992
 993         switch (plane) {
 994         case OMAP_DSS_GFX:
 995                 shift = 8;
 996                 break;
 997         case OMAP_DSS_VIDEO1:
 998         case OMAP_DSS_VIDEO2:
 999         case OMAP_DSS_VIDEO3:
1000                 shift = 16;
1001                 break;
1002         default:
1003                 BUG();
1004                 return 0;
1005         }
1006
1007         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1008
1009         if (dss_has_feature(FEAT_MGR_LCD3)) {
1010                 if (FLD_GET(val, 31, 30) == 0)
1011                         channel = FLD_GET(val, shift, shift);
1012                 else if (FLD_GET(val, 31, 30) == 1)
1013                         channel = OMAP_DSS_CHANNEL_LCD2;
1014                 else
1015                         channel = OMAP_DSS_CHANNEL_LCD3;
1016         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1017                 if (FLD_GET(val, 31, 30) == 0)
1018                         channel = FLD_GET(val, shift, shift);
1019                 else
1020                         channel = OMAP_DSS_CHANNEL_LCD2;
1021         } else {
1022                 channel = FLD_GET(val, shift, shift);
1023         }
1024
1025         return channel;
1026 }
1027
1028 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1029 {
1030         enum omap_plane plane = OMAP_DSS_WB;
1031
1032         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1033 }
1034
1035 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1036                 enum omap_burst_size burst_size)
1037 {
1038         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1039         int shift;
1040
1041         shift = shifts[plane];
1042         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1043 }
1044
1045 static void dispc_configure_burst_sizes(void)
1046 {
1047         int i;
1048         const int burst_size = BURST_SIZE_X8;
1049
1050         /* Configure burst size always to maximum size */
1051         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1052                 dispc_ovl_set_burst_size(i, burst_size);
1053 }
1054
1055 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1056 {
1057         unsigned unit = dss_feat_get_burst_size_unit();
1058         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1059         return unit * 8;
1060 }
1061
1062 void dispc_enable_gamma_table(bool enable)
1063 {
1064         /*
1065          * This is partially implemented to support only disabling of
1066          * the gamma table.
1067          */
1068         if (enable) {
1069                 DSSWARN("Gamma table enabling for TV not yet supported");
1070                 return;
1071         }
1072
1073         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1074 }
1075
1076 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1077 {
1078         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1079                 return;
1080
1081         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1082 }
1083
1084 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1085                 const struct omap_dss_cpr_coefs *coefs)
1086 {
1087         u32 coef_r, coef_g, coef_b;
1088
1089         if (!dss_mgr_is_lcd(channel))
1090                 return;
1091
1092         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1093                 FLD_VAL(coefs->rb, 9, 0);
1094         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1095                 FLD_VAL(coefs->gb, 9, 0);
1096         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1097                 FLD_VAL(coefs->bb, 9, 0);
1098
1099         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1100         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1101         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1102 }
1103
1104 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1105 {
1106         u32 val;
1107
1108         BUG_ON(plane == OMAP_DSS_GFX);
1109
1110         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1111         val = FLD_MOD(val, enable, 9, 9);
1112         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1113 }
1114
1115 static void dispc_ovl_enable_replication(enum omap_plane plane,
1116                 enum omap_overlay_caps caps, bool enable)
1117 {
1118         static const unsigned shifts[] = { 5, 10, 10, 10 };
1119         int shift;
1120
1121         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1122                 return;
1123
1124         shift = shifts[plane];
1125         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1126 }
1127
1128 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1129                 u16 height)
1130 {
1131         u32 val;
1132
1133         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1134                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1135
1136         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1137 }
1138
1139 static void dispc_init_fifos(void)
1140 {
1141         u32 size;
1142         int fifo;
1143         u8 start, end;
1144         u32 unit;
1145         int i;
1146
1147         unit = dss_feat_get_buffer_size_unit();
1148
1149         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1150
1151         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1152                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1153                 size *= unit;
1154                 dispc.fifo_size[fifo] = size;
1155
1156                 /*
1157                  * By default fifos are mapped directly to overlays, fifo 0 to
1158                  * ovl 0, fifo 1 to ovl 1, etc.
1159                  */
1160                 dispc.fifo_assignment[fifo] = fifo;
1161         }
1162
1163         /*
1164          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1165          * causes problems with certain use cases, like using the tiler in 2D
1166          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1167          * giving GFX plane a larger fifo. WB but should work fine with a
1168          * smaller fifo.
1169          */
1170         if (dispc.feat->gfx_fifo_workaround) {
1171                 u32 v;
1172
1173                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1174
1175                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1176                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1177                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1178                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1179
1180                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1181
1182                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1183                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1184         }
1185
1186         /*
1187          * Setup default fifo thresholds.
1188          */
1189         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1190                 u32 low, high;
1191                 const bool use_fifomerge = false;
1192                 const bool manual_update = false;
1193
1194                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1195                         use_fifomerge, manual_update);
1196
1197                 dispc_ovl_set_fifo_threshold(i, low, high);
1198         }
1199 }
1200
1201 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1202 {
1203         int fifo;
1204         u32 size = 0;
1205
1206         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1207                 if (dispc.fifo_assignment[fifo] == plane)
1208                         size += dispc.fifo_size[fifo];
1209         }
1210
1211         return size;
1212 }
1213
1214 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1215 {
1216         u8 hi_start, hi_end, lo_start, lo_end;
1217         u32 unit;
1218
1219         unit = dss_feat_get_buffer_size_unit();
1220
1221         WARN_ON(low % unit != 0);
1222         WARN_ON(high % unit != 0);
1223
1224         low /= unit;
1225         high /= unit;
1226
1227         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1228         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1229
1230         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1231                         plane,
1232                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1233                                 lo_start, lo_end) * unit,
1234                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1235                                 hi_start, hi_end) * unit,
1236                         low * unit, high * unit);
1237
1238         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1239                         FLD_VAL(high, hi_start, hi_end) |
1240                         FLD_VAL(low, lo_start, lo_end));
1241
1242         /*
1243          * configure the preload to the pipeline's high threhold, if HT it's too
1244          * large for the preload field, set the threshold to the maximum value
1245          * that can be held by the preload register
1246          */
1247         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1248                         plane != OMAP_DSS_WB)
1249                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1250 }
1251 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1252
1253 void dispc_enable_fifomerge(bool enable)
1254 {
1255         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1256                 WARN_ON(enable);
1257                 return;
1258         }
1259
1260         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1261         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1262 }
1263
1264 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1265                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1266                 bool manual_update)
1267 {
1268         /*
1269          * All sizes are in bytes. Both the buffer and burst are made of
1270          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1271          */
1272
1273         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1274         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1275         int i;
1276
1277         burst_size = dispc_ovl_get_burst_size(plane);
1278         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1279
1280         if (use_fifomerge) {
1281                 total_fifo_size = 0;
1282                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1283                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1284         } else {
1285                 total_fifo_size = ovl_fifo_size;
1286         }
1287
1288         /*
1289          * We use the same low threshold for both fifomerge and non-fifomerge
1290          * cases, but for fifomerge we calculate the high threshold using the
1291          * combined fifo size
1292          */
1293
1294         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1295                 *fifo_low = ovl_fifo_size - burst_size * 2;
1296                 *fifo_high = total_fifo_size - burst_size;
1297         } else if (plane == OMAP_DSS_WB) {
1298                 /*
1299                  * Most optimal configuration for writeback is to push out data
1300                  * to the interconnect the moment writeback pushes enough pixels
1301                  * in the FIFO to form a burst
1302                  */
1303                 *fifo_low = 0;
1304                 *fifo_high = burst_size;
1305         } else {
1306                 *fifo_low = ovl_fifo_size - burst_size;
1307                 *fifo_high = total_fifo_size - buf_unit;
1308         }
1309 }
1310 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1311
1312 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1313 {
1314         int bit;
1315
1316         if (plane == OMAP_DSS_GFX)
1317                 bit = 14;
1318         else
1319                 bit = 23;
1320
1321         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1322 }
1323
1324 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1325         int low, int high)
1326 {
1327         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1328                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1329 }
1330
1331 static void dispc_init_mflag(void)
1332 {
1333         int i;
1334
1335         /*
1336          * HACK: NV12 color format and MFLAG seem to have problems working
1337          * together: using two displays, and having an NV12 overlay on one of
1338          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1339          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1340          * remove the errors, but there doesn't seem to be a clear logic on
1341          * which values work and which not.
1342          *
1343          * As a work-around, set force MFLAG to always on.
1344          */
1345         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1346                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1347                 (0 << 2));      /* MFLAG_START = disable */
1348
1349         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1350                 u32 size = dispc_ovl_get_fifo_size(i);
1351                 u32 unit = dss_feat_get_buffer_size_unit();
1352                 u32 low, high;
1353
1354                 dispc_ovl_set_mflag(i, true);
1355
1356                 /*
1357                  * Simulation team suggests below thesholds:
1358                  * HT = fifosize * 5 / 8;
1359                  * LT = fifosize * 4 / 8;
1360                  */
1361
1362                 low = size * 4 / 8 / unit;
1363                 high = size * 5 / 8 / unit;
1364
1365                 dispc_ovl_set_mflag_threshold(i, low, high);
1366         }
1367 }
1368
1369 static void dispc_ovl_set_fir(enum omap_plane plane,
1370                                 int hinc, int vinc,
1371                                 enum omap_color_component color_comp)
1372 {
1373         u32 val;
1374
1375         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1376                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1377
1378                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1379                                         &hinc_start, &hinc_end);
1380                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1381                                         &vinc_start, &vinc_end);
1382                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1383                                 FLD_VAL(hinc, hinc_start, hinc_end);
1384
1385                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1386         } else {
1387                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1388                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1389         }
1390 }
1391
1392 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1393 {
1394         u32 val;
1395         u8 hor_start, hor_end, vert_start, vert_end;
1396
1397         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1398         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1399
1400         val = FLD_VAL(vaccu, vert_start, vert_end) |
1401                         FLD_VAL(haccu, hor_start, hor_end);
1402
1403         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1404 }
1405
1406 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1407 {
1408         u32 val;
1409         u8 hor_start, hor_end, vert_start, vert_end;
1410
1411         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1412         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1413
1414         val = FLD_VAL(vaccu, vert_start, vert_end) |
1415                         FLD_VAL(haccu, hor_start, hor_end);
1416
1417         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1418 }
1419
1420 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1421                 int vaccu)
1422 {
1423         u32 val;
1424
1425         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1426         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1427 }
1428
1429 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1430                 int vaccu)
1431 {
1432         u32 val;
1433
1434         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1435         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1436 }
1437
1438 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1439                 u16 orig_width, u16 orig_height,
1440                 u16 out_width, u16 out_height,
1441                 bool five_taps, u8 rotation,
1442                 enum omap_color_component color_comp)
1443 {
1444         int fir_hinc, fir_vinc;
1445
1446         fir_hinc = 1024 * orig_width / out_width;
1447         fir_vinc = 1024 * orig_height / out_height;
1448
1449         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1450                                 color_comp);
1451         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1452 }
1453
1454 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1455                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1456                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1457 {
1458         int h_accu2_0, h_accu2_1;
1459         int v_accu2_0, v_accu2_1;
1460         int chroma_hinc, chroma_vinc;
1461         int idx;
1462
1463         struct accu {
1464                 s8 h0_m, h0_n;
1465                 s8 h1_m, h1_n;
1466                 s8 v0_m, v0_n;
1467                 s8 v1_m, v1_n;
1468         };
1469
1470         const struct accu *accu_table;
1471         const struct accu *accu_val;
1472
1473         static const struct accu accu_nv12[4] = {
1474                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1475                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1476                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1477                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1478         };
1479
1480         static const struct accu accu_nv12_ilace[4] = {
1481                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1482                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1483                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1484                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1485         };
1486
1487         static const struct accu accu_yuv[4] = {
1488                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1489                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1490                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1491                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1492         };
1493
1494         switch (rotation) {
1495         case OMAP_DSS_ROT_0:
1496                 idx = 0;
1497                 break;
1498         case OMAP_DSS_ROT_90:
1499                 idx = 1;
1500                 break;
1501         case OMAP_DSS_ROT_180:
1502                 idx = 2;
1503                 break;
1504         case OMAP_DSS_ROT_270:
1505                 idx = 3;
1506                 break;
1507         default:
1508                 BUG();
1509                 return;
1510         }
1511
1512         switch (color_mode) {
1513         case OMAP_DSS_COLOR_NV12:
1514                 if (ilace)
1515                         accu_table = accu_nv12_ilace;
1516                 else
1517                         accu_table = accu_nv12;
1518                 break;
1519         case OMAP_DSS_COLOR_YUV2:
1520         case OMAP_DSS_COLOR_UYVY:
1521                 accu_table = accu_yuv;
1522                 break;
1523         default:
1524                 BUG();
1525                 return;
1526         }
1527
1528         accu_val = &accu_table[idx];
1529
1530         chroma_hinc = 1024 * orig_width / out_width;
1531         chroma_vinc = 1024 * orig_height / out_height;
1532
1533         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1534         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1535         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1536         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1537
1538         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1539         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1540 }
1541
1542 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1543                 u16 orig_width, u16 orig_height,
1544                 u16 out_width, u16 out_height,
1545                 bool ilace, bool five_taps,
1546                 bool fieldmode, enum omap_color_mode color_mode,
1547                 u8 rotation)
1548 {
1549         int accu0 = 0;
1550         int accu1 = 0;
1551         u32 l;
1552
1553         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1554                                 out_width, out_height, five_taps,
1555                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1556         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1557
1558         /* RESIZEENABLE and VERTICALTAPS */
1559         l &= ~((0x3 << 5) | (0x1 << 21));
1560         l |= (orig_width != out_width) ? (1 << 5) : 0;
1561         l |= (orig_height != out_height) ? (1 << 6) : 0;
1562         l |= five_taps ? (1 << 21) : 0;
1563
1564         /* VRESIZECONF and HRESIZECONF */
1565         if (dss_has_feature(FEAT_RESIZECONF)) {
1566                 l &= ~(0x3 << 7);
1567                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1568                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1569         }
1570
1571         /* LINEBUFFERSPLIT */
1572         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1573                 l &= ~(0x1 << 22);
1574                 l |= five_taps ? (1 << 22) : 0;
1575         }
1576
1577         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1578
1579         /*
1580          * field 0 = even field = bottom field
1581          * field 1 = odd field = top field
1582          */
1583         if (ilace && !fieldmode) {
1584                 accu1 = 0;
1585                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1586                 if (accu0 >= 1024/2) {
1587                         accu1 = 1024/2;
1588                         accu0 -= accu1;
1589                 }
1590         }
1591
1592         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1593         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1594 }
1595
1596 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1597                 u16 orig_width, u16 orig_height,
1598                 u16 out_width, u16 out_height,
1599                 bool ilace, bool five_taps,
1600                 bool fieldmode, enum omap_color_mode color_mode,
1601                 u8 rotation)
1602 {
1603         int scale_x = out_width != orig_width;
1604         int scale_y = out_height != orig_height;
1605         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1606
1607         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1608                 return;
1609         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1610                         color_mode != OMAP_DSS_COLOR_UYVY &&
1611                         color_mode != OMAP_DSS_COLOR_NV12)) {
1612                 /* reset chroma resampling for RGB formats  */
1613                 if (plane != OMAP_DSS_WB)
1614                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1615                 return;
1616         }
1617
1618         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1619                         out_height, ilace, color_mode, rotation);
1620
1621         switch (color_mode) {
1622         case OMAP_DSS_COLOR_NV12:
1623                 if (chroma_upscale) {
1624                         /* UV is subsampled by 2 horizontally and vertically */
1625                         orig_height >>= 1;
1626                         orig_width >>= 1;
1627                 } else {
1628                         /* UV is downsampled by 2 horizontally and vertically */
1629                         orig_height <<= 1;
1630                         orig_width <<= 1;
1631                 }
1632
1633                 break;
1634         case OMAP_DSS_COLOR_YUV2:
1635         case OMAP_DSS_COLOR_UYVY:
1636                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1637                 if (rotation == OMAP_DSS_ROT_0 ||
1638                                 rotation == OMAP_DSS_ROT_180) {
1639                         if (chroma_upscale)
1640                                 /* UV is subsampled by 2 horizontally */
1641                                 orig_width >>= 1;
1642                         else
1643                                 /* UV is downsampled by 2 horizontally */
1644                                 orig_width <<= 1;
1645                 }
1646
1647                 /* must use FIR for YUV422 if rotated */
1648                 if (rotation != OMAP_DSS_ROT_0)
1649                         scale_x = scale_y = true;
1650
1651                 break;
1652         default:
1653                 BUG();
1654                 return;
1655         }
1656
1657         if (out_width != orig_width)
1658                 scale_x = true;
1659         if (out_height != orig_height)
1660                 scale_y = true;
1661
1662         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1663                         out_width, out_height, five_taps,
1664                                 rotation, DISPC_COLOR_COMPONENT_UV);
1665
1666         if (plane != OMAP_DSS_WB)
1667                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1668                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1669
1670         /* set H scaling */
1671         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1672         /* set V scaling */
1673         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1674 }
1675
1676 static void dispc_ovl_set_scaling(enum omap_plane plane,
1677                 u16 orig_width, u16 orig_height,
1678                 u16 out_width, u16 out_height,
1679                 bool ilace, bool five_taps,
1680                 bool fieldmode, enum omap_color_mode color_mode,
1681                 u8 rotation)
1682 {
1683         BUG_ON(plane == OMAP_DSS_GFX);
1684
1685         dispc_ovl_set_scaling_common(plane,
1686                         orig_width, orig_height,
1687                         out_width, out_height,
1688                         ilace, five_taps,
1689                         fieldmode, color_mode,
1690                         rotation);
1691
1692         dispc_ovl_set_scaling_uv(plane,
1693                 orig_width, orig_height,
1694                 out_width, out_height,
1695                 ilace, five_taps,
1696                 fieldmode, color_mode,
1697                 rotation);
1698 }
1699
1700 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1701                 enum omap_dss_rotation_type rotation_type,
1702                 bool mirroring, enum omap_color_mode color_mode)
1703 {
1704         bool row_repeat = false;
1705         int vidrot = 0;
1706
1707         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1708                         color_mode == OMAP_DSS_COLOR_UYVY) {
1709
1710                 if (mirroring) {
1711                         switch (rotation) {
1712                         case OMAP_DSS_ROT_0:
1713                                 vidrot = 2;
1714                                 break;
1715                         case OMAP_DSS_ROT_90:
1716                                 vidrot = 1;
1717                                 break;
1718                         case OMAP_DSS_ROT_180:
1719                                 vidrot = 0;
1720                                 break;
1721                         case OMAP_DSS_ROT_270:
1722                                 vidrot = 3;
1723                                 break;
1724                         }
1725                 } else {
1726                         switch (rotation) {
1727                         case OMAP_DSS_ROT_0:
1728                                 vidrot = 0;
1729                                 break;
1730                         case OMAP_DSS_ROT_90:
1731                                 vidrot = 1;
1732                                 break;
1733                         case OMAP_DSS_ROT_180:
1734                                 vidrot = 2;
1735                                 break;
1736                         case OMAP_DSS_ROT_270:
1737                                 vidrot = 3;
1738                                 break;
1739                         }
1740                 }
1741
1742                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1743                         row_repeat = true;
1744                 else
1745                         row_repeat = false;
1746         }
1747
1748         /*
1749          * OMAP4/5 Errata i631:
1750          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1751          * rows beyond the framebuffer, which may cause OCP error.
1752          */
1753         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1754                         rotation_type != OMAP_DSS_ROT_TILER)
1755                 vidrot = 1;
1756
1757         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1758         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1759                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1760                         row_repeat ? 1 : 0, 18, 18);
1761
1762         if (color_mode == OMAP_DSS_COLOR_NV12) {
1763                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1764                                         (rotation == OMAP_DSS_ROT_0 ||
1765                                         rotation == OMAP_DSS_ROT_180);
1766                 /* DOUBLESTRIDE */
1767                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1768         }
1769
1770 }
1771
1772 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1773 {
1774         switch (color_mode) {
1775         case OMAP_DSS_COLOR_CLUT1:
1776                 return 1;
1777         case OMAP_DSS_COLOR_CLUT2:
1778                 return 2;
1779         case OMAP_DSS_COLOR_CLUT4:
1780                 return 4;
1781         case OMAP_DSS_COLOR_CLUT8:
1782         case OMAP_DSS_COLOR_NV12:
1783                 return 8;
1784         case OMAP_DSS_COLOR_RGB12U:
1785         case OMAP_DSS_COLOR_RGB16:
1786         case OMAP_DSS_COLOR_ARGB16:
1787         case OMAP_DSS_COLOR_YUV2:
1788         case OMAP_DSS_COLOR_UYVY:
1789         case OMAP_DSS_COLOR_RGBA16:
1790         case OMAP_DSS_COLOR_RGBX16:
1791         case OMAP_DSS_COLOR_ARGB16_1555:
1792         case OMAP_DSS_COLOR_XRGB16_1555:
1793                 return 16;
1794         case OMAP_DSS_COLOR_RGB24P:
1795                 return 24;
1796         case OMAP_DSS_COLOR_RGB24U:
1797         case OMAP_DSS_COLOR_ARGB32:
1798         case OMAP_DSS_COLOR_RGBA32:
1799         case OMAP_DSS_COLOR_RGBX32:
1800                 return 32;
1801         default:
1802                 BUG();
1803                 return 0;
1804         }
1805 }
1806
1807 static s32 pixinc(int pixels, u8 ps)
1808 {
1809         if (pixels == 1)
1810                 return 1;
1811         else if (pixels > 1)
1812                 return 1 + (pixels - 1) * ps;
1813         else if (pixels < 0)
1814                 return 1 - (-pixels + 1) * ps;
1815         else
1816                 BUG();
1817                 return 0;
1818 }
1819
1820 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1821                 u16 screen_width,
1822                 u16 width, u16 height,
1823                 enum omap_color_mode color_mode, bool fieldmode,
1824                 unsigned int field_offset,
1825                 unsigned *offset0, unsigned *offset1,
1826                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1827 {
1828         u8 ps;
1829
1830         /* FIXME CLUT formats */
1831         switch (color_mode) {
1832         case OMAP_DSS_COLOR_CLUT1:
1833         case OMAP_DSS_COLOR_CLUT2:
1834         case OMAP_DSS_COLOR_CLUT4:
1835         case OMAP_DSS_COLOR_CLUT8:
1836                 BUG();
1837                 return;
1838         case OMAP_DSS_COLOR_YUV2:
1839         case OMAP_DSS_COLOR_UYVY:
1840                 ps = 4;
1841                 break;
1842         default:
1843                 ps = color_mode_to_bpp(color_mode) / 8;
1844                 break;
1845         }
1846
1847         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1848                         width, height);
1849
1850         /*
1851          * field 0 = even field = bottom field
1852          * field 1 = odd field = top field
1853          */
1854         switch (rotation + mirror * 4) {
1855         case OMAP_DSS_ROT_0:
1856         case OMAP_DSS_ROT_180:
1857                 /*
1858                  * If the pixel format is YUV or UYVY divide the width
1859                  * of the image by 2 for 0 and 180 degree rotation.
1860                  */
1861                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1862                         color_mode == OMAP_DSS_COLOR_UYVY)
1863                         width = width >> 1;
1864         case OMAP_DSS_ROT_90:
1865         case OMAP_DSS_ROT_270:
1866                 *offset1 = 0;
1867                 if (field_offset)
1868                         *offset0 = field_offset * screen_width * ps;
1869                 else
1870                         *offset0 = 0;
1871
1872                 *row_inc = pixinc(1 +
1873                         (y_predecim * screen_width - x_predecim * width) +
1874                         (fieldmode ? screen_width : 0), ps);
1875                 *pix_inc = pixinc(x_predecim, ps);
1876                 break;
1877
1878         case OMAP_DSS_ROT_0 + 4:
1879         case OMAP_DSS_ROT_180 + 4:
1880                 /* If the pixel format is YUV or UYVY divide the width
1881                  * of the image by 2  for 0 degree and 180 degree
1882                  */
1883                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1884                         color_mode == OMAP_DSS_COLOR_UYVY)
1885                         width = width >> 1;
1886         case OMAP_DSS_ROT_90 + 4:
1887         case OMAP_DSS_ROT_270 + 4:
1888                 *offset1 = 0;
1889                 if (field_offset)
1890                         *offset0 = field_offset * screen_width * ps;
1891                 else
1892                         *offset0 = 0;
1893                 *row_inc = pixinc(1 -
1894                         (y_predecim * screen_width + x_predecim * width) -
1895                         (fieldmode ? screen_width : 0), ps);
1896                 *pix_inc = pixinc(x_predecim, ps);
1897                 break;
1898
1899         default:
1900                 BUG();
1901                 return;
1902         }
1903 }
1904
1905 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1906                 u16 screen_width,
1907                 u16 width, u16 height,
1908                 enum omap_color_mode color_mode, bool fieldmode,
1909                 unsigned int field_offset,
1910                 unsigned *offset0, unsigned *offset1,
1911                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1912 {
1913         u8 ps;
1914         u16 fbw, fbh;
1915
1916         /* FIXME CLUT formats */
1917         switch (color_mode) {
1918         case OMAP_DSS_COLOR_CLUT1:
1919         case OMAP_DSS_COLOR_CLUT2:
1920         case OMAP_DSS_COLOR_CLUT4:
1921         case OMAP_DSS_COLOR_CLUT8:
1922                 BUG();
1923                 return;
1924         default:
1925                 ps = color_mode_to_bpp(color_mode) / 8;
1926                 break;
1927         }
1928
1929         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1930                         width, height);
1931
1932         /* width & height are overlay sizes, convert to fb sizes */
1933
1934         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1935                 fbw = width;
1936                 fbh = height;
1937         } else {
1938                 fbw = height;
1939                 fbh = width;
1940         }
1941
1942         /*
1943          * field 0 = even field = bottom field
1944          * field 1 = odd field = top field
1945          */
1946         switch (rotation + mirror * 4) {
1947         case OMAP_DSS_ROT_0:
1948                 *offset1 = 0;
1949                 if (field_offset)
1950                         *offset0 = *offset1 + field_offset * screen_width * ps;
1951                 else
1952                         *offset0 = *offset1;
1953                 *row_inc = pixinc(1 +
1954                         (y_predecim * screen_width - fbw * x_predecim) +
1955                         (fieldmode ? screen_width : 0), ps);
1956                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1957                         color_mode == OMAP_DSS_COLOR_UYVY)
1958                         *pix_inc = pixinc(x_predecim, 2 * ps);
1959                 else
1960                         *pix_inc = pixinc(x_predecim, ps);
1961                 break;
1962         case OMAP_DSS_ROT_90:
1963                 *offset1 = screen_width * (fbh - 1) * ps;
1964                 if (field_offset)
1965                         *offset0 = *offset1 + field_offset * ps;
1966                 else
1967                         *offset0 = *offset1;
1968                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1969                                 y_predecim + (fieldmode ? 1 : 0), ps);
1970                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1971                 break;
1972         case OMAP_DSS_ROT_180:
1973                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1974                 if (field_offset)
1975                         *offset0 = *offset1 - field_offset * screen_width * ps;
1976                 else
1977                         *offset0 = *offset1;
1978                 *row_inc = pixinc(-1 -
1979                         (y_predecim * screen_width - fbw * x_predecim) -
1980                         (fieldmode ? screen_width : 0), ps);
1981                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1982                         color_mode == OMAP_DSS_COLOR_UYVY)
1983                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1984                 else
1985                         *pix_inc = pixinc(-x_predecim, ps);
1986                 break;
1987         case OMAP_DSS_ROT_270:
1988                 *offset1 = (fbw - 1) * ps;
1989                 if (field_offset)
1990                         *offset0 = *offset1 - field_offset * ps;
1991                 else
1992                         *offset0 = *offset1;
1993                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1994                                 y_predecim - (fieldmode ? 1 : 0), ps);
1995                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1996                 break;
1997
1998         /* mirroring */
1999         case OMAP_DSS_ROT_0 + 4:
2000                 *offset1 = (fbw - 1) * ps;
2001                 if (field_offset)
2002                         *offset0 = *offset1 + field_offset * screen_width * ps;
2003                 else
2004                         *offset0 = *offset1;
2005                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2006                                 (fieldmode ? screen_width : 0),
2007                                 ps);
2008                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2009                         color_mode == OMAP_DSS_COLOR_UYVY)
2010                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2011                 else
2012                         *pix_inc = pixinc(-x_predecim, ps);
2013                 break;
2014
2015         case OMAP_DSS_ROT_90 + 4:
2016                 *offset1 = 0;
2017                 if (field_offset)
2018                         *offset0 = *offset1 + field_offset * ps;
2019                 else
2020                         *offset0 = *offset1;
2021                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2022                                 y_predecim + (fieldmode ? 1 : 0),
2023                                 ps);
2024                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2025                 break;
2026
2027         case OMAP_DSS_ROT_180 + 4:
2028                 *offset1 = screen_width * (fbh - 1) * ps;
2029                 if (field_offset)
2030                         *offset0 = *offset1 - field_offset * screen_width * ps;
2031                 else
2032                         *offset0 = *offset1;
2033                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2034                                 (fieldmode ? screen_width : 0),
2035                                 ps);
2036                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2037                         color_mode == OMAP_DSS_COLOR_UYVY)
2038                         *pix_inc = pixinc(x_predecim, 2 * ps);
2039                 else
2040                         *pix_inc = pixinc(x_predecim, ps);
2041                 break;
2042
2043         case OMAP_DSS_ROT_270 + 4:
2044                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2045                 if (field_offset)
2046                         *offset0 = *offset1 - field_offset * ps;
2047                 else
2048                         *offset0 = *offset1;
2049                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2050                                 y_predecim - (fieldmode ? 1 : 0),
2051                                 ps);
2052                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2053                 break;
2054
2055         default:
2056                 BUG();
2057                 return;
2058         }
2059 }
2060
2061 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2062                 enum omap_color_mode color_mode, bool fieldmode,
2063                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2064                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2065 {
2066         u8 ps;
2067
2068         switch (color_mode) {
2069         case OMAP_DSS_COLOR_CLUT1:
2070         case OMAP_DSS_COLOR_CLUT2:
2071         case OMAP_DSS_COLOR_CLUT4:
2072         case OMAP_DSS_COLOR_CLUT8:
2073                 BUG();
2074                 return;
2075         default:
2076                 ps = color_mode_to_bpp(color_mode) / 8;
2077                 break;
2078         }
2079
2080         DSSDBG("scrw %d, width %d\n", screen_width, width);
2081
2082         /*
2083          * field 0 = even field = bottom field
2084          * field 1 = odd field = top field
2085          */
2086         *offset1 = 0;
2087         if (field_offset)
2088                 *offset0 = *offset1 + field_offset * screen_width * ps;
2089         else
2090                 *offset0 = *offset1;
2091         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2092                         (fieldmode ? screen_width : 0), ps);
2093         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2094                 color_mode == OMAP_DSS_COLOR_UYVY)
2095                 *pix_inc = pixinc(x_predecim, 2 * ps);
2096         else
2097                 *pix_inc = pixinc(x_predecim, ps);
2098 }
2099
2100 /*
2101  * This function is used to avoid synclosts in OMAP3, because of some
2102  * undocumented horizontal position and timing related limitations.
2103  */
2104 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2105                 const struct omap_video_timings *t, u16 pos_x,
2106                 u16 width, u16 height, u16 out_width, u16 out_height,
2107                 bool five_taps)
2108 {
2109         const int ds = DIV_ROUND_UP(height, out_height);
2110         unsigned long nonactive;
2111         static const u8 limits[3] = { 8, 10, 20 };
2112         u64 val, blank;
2113         int i;
2114
2115         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2116
2117         i = 0;
2118         if (out_height < height)
2119                 i++;
2120         if (out_width < width)
2121                 i++;
2122         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2123         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2124         if (blank <= limits[i])
2125                 return -EINVAL;
2126
2127         /* FIXME add checks for 3-tap filter once the limitations are known */
2128         if (!five_taps)
2129                 return 0;
2130
2131         /*
2132          * Pixel data should be prepared before visible display point starts.
2133          * So, atleast DS-2 lines must have already been fetched by DISPC
2134          * during nonactive - pos_x period.
2135          */
2136         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2137         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2138                 val, max(0, ds - 2) * width);
2139         if (val < max(0, ds - 2) * width)
2140                 return -EINVAL;
2141
2142         /*
2143          * All lines need to be refilled during the nonactive period of which
2144          * only one line can be loaded during the active period. So, atleast
2145          * DS - 1 lines should be loaded during nonactive period.
2146          */
2147         val =  div_u64((u64)nonactive * lclk, pclk);
2148         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2149                 val, max(0, ds - 1) * width);
2150         if (val < max(0, ds - 1) * width)
2151                 return -EINVAL;
2152
2153         return 0;
2154 }
2155
2156 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2157                 const struct omap_video_timings *mgr_timings, u16 width,
2158                 u16 height, u16 out_width, u16 out_height,
2159                 enum omap_color_mode color_mode)
2160 {
2161         u32 core_clk = 0;
2162         u64 tmp;
2163
2164         if (height <= out_height && width <= out_width)
2165                 return (unsigned long) pclk;
2166
2167         if (height > out_height) {
2168                 unsigned int ppl = mgr_timings->x_res;
2169
2170                 tmp = (u64)pclk * height * out_width;
2171                 do_div(tmp, 2 * out_height * ppl);
2172                 core_clk = tmp;
2173
2174                 if (height > 2 * out_height) {
2175                         if (ppl == out_width)
2176                                 return 0;
2177
2178                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2179                         do_div(tmp, 2 * out_height * (ppl - out_width));
2180                         core_clk = max_t(u32, core_clk, tmp);
2181                 }
2182         }
2183
2184         if (width > out_width) {
2185                 tmp = (u64)pclk * width;
2186                 do_div(tmp, out_width);
2187                 core_clk = max_t(u32, core_clk, tmp);
2188
2189                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2190                         core_clk <<= 1;
2191         }
2192
2193         return core_clk;
2194 }
2195
2196 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2197                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2198 {
2199         if (height > out_height && width > out_width)
2200                 return pclk * 4;
2201         else
2202                 return pclk * 2;
2203 }
2204
2205 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2206                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2207 {
2208         unsigned int hf, vf;
2209
2210         /*
2211          * FIXME how to determine the 'A' factor
2212          * for the no downscaling case ?
2213          */
2214
2215         if (width > 3 * out_width)
2216                 hf = 4;
2217         else if (width > 2 * out_width)
2218                 hf = 3;
2219         else if (width > out_width)
2220                 hf = 2;
2221         else
2222                 hf = 1;
2223         if (height > out_height)
2224                 vf = 2;
2225         else
2226                 vf = 1;
2227
2228         return pclk * vf * hf;
2229 }
2230
2231 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2232                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2233 {
2234         /*
2235          * If the overlay/writeback is in mem to mem mode, there are no
2236          * downscaling limitations with respect to pixel clock, return 1 as
2237          * required core clock to represent that we have sufficient enough
2238          * core clock to do maximum downscaling
2239          */
2240         if (mem_to_mem)
2241                 return 1;
2242
2243         if (width > out_width)
2244                 return DIV_ROUND_UP(pclk, out_width) * width;
2245         else
2246                 return pclk;
2247 }
2248
2249 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2250                 const struct omap_video_timings *mgr_timings,
2251                 u16 width, u16 height, u16 out_width, u16 out_height,
2252                 enum omap_color_mode color_mode, bool *five_taps,
2253                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2254                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2255 {
2256         int error;
2257         u16 in_width, in_height;
2258         int min_factor = min(*decim_x, *decim_y);
2259         const int maxsinglelinewidth =
2260                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2261
2262         *five_taps = false;
2263
2264         do {
2265                 in_height = height / *decim_y;
2266                 in_width = width / *decim_x;
2267                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2268                                 in_height, out_width, out_height, mem_to_mem);
2269                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2270                         *core_clk > dispc_core_clk_rate());
2271                 if (error) {
2272                         if (*decim_x == *decim_y) {
2273                                 *decim_x = min_factor;
2274                                 ++*decim_y;
2275                         } else {
2276                                 swap(*decim_x, *decim_y);
2277                                 if (*decim_x < *decim_y)
2278                                         ++*decim_x;
2279                         }
2280                 }
2281         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2282
2283         if (error) {
2284                 DSSERR("failed to find scaling settings\n");
2285                 return -EINVAL;
2286         }
2287
2288         if (in_width > maxsinglelinewidth) {
2289                 DSSERR("Cannot scale max input width exceeded");
2290                 return -EINVAL;
2291         }
2292         return 0;
2293 }
2294
2295 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2296                 const struct omap_video_timings *mgr_timings,
2297                 u16 width, u16 height, u16 out_width, u16 out_height,
2298                 enum omap_color_mode color_mode, bool *five_taps,
2299                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2300                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2301 {
2302         int error;
2303         u16 in_width, in_height;
2304         const int maxsinglelinewidth =
2305                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2306
2307         do {
2308                 in_height = height / *decim_y;
2309                 in_width = width / *decim_x;
2310                 *five_taps = in_height > out_height;
2311
2312                 if (in_width > maxsinglelinewidth)
2313                         if (in_height > out_height &&
2314                                                 in_height < out_height * 2)
2315                                 *five_taps = false;
2316 again:
2317                 if (*five_taps)
2318                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2319                                                 in_width, in_height, out_width,
2320                                                 out_height, color_mode);
2321                 else
2322                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2323                                         in_height, out_width, out_height,
2324                                         mem_to_mem);
2325
2326                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2327                                 pos_x, in_width, in_height, out_width,
2328                                 out_height, *five_taps);
2329                 if (error && *five_taps) {
2330                         *five_taps = false;
2331                         goto again;
2332                 }
2333
2334                 error = (error || in_width > maxsinglelinewidth * 2 ||
2335                         (in_width > maxsinglelinewidth && *five_taps) ||
2336                         !*core_clk || *core_clk > dispc_core_clk_rate());
2337
2338                 if (!error) {
2339                         /* verify that we're inside the limits of scaler */
2340                         if (in_width / 4 > out_width)
2341                                         error = 1;
2342
2343                         if (*five_taps) {
2344                                 if (in_height / 4 > out_height)
2345                                         error = 1;
2346                         } else {
2347                                 if (in_height / 2 > out_height)
2348                                         error = 1;
2349                         }
2350                 }
2351
2352                 if (error)
2353                         ++*decim_y;
2354         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2355
2356         if (error) {
2357                 DSSERR("failed to find scaling settings\n");
2358                 return -EINVAL;
2359         }
2360
2361         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2362                                 in_height, out_width, out_height, *five_taps)) {
2363                         DSSERR("horizontal timing too tight\n");
2364                         return -EINVAL;
2365         }
2366
2367         if (in_width > (maxsinglelinewidth * 2)) {
2368                 DSSERR("Cannot setup scaling");
2369                 DSSERR("width exceeds maximum width possible");
2370                 return -EINVAL;
2371         }
2372
2373         if (in_width > maxsinglelinewidth && *five_taps) {
2374                 DSSERR("cannot setup scaling with five taps");
2375                 return -EINVAL;
2376         }
2377         return 0;
2378 }
2379
2380 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2381                 const struct omap_video_timings *mgr_timings,
2382                 u16 width, u16 height, u16 out_width, u16 out_height,
2383                 enum omap_color_mode color_mode, bool *five_taps,
2384                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2385                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2386 {
2387         u16 in_width, in_width_max;
2388         int decim_x_min = *decim_x;
2389         u16 in_height = height / *decim_y;
2390         const int maxsinglelinewidth =
2391                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2392         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2393
2394         if (mem_to_mem) {
2395                 in_width_max = out_width * maxdownscale;
2396         } else {
2397                 in_width_max = dispc_core_clk_rate() /
2398                                         DIV_ROUND_UP(pclk, out_width);
2399         }
2400
2401         *decim_x = DIV_ROUND_UP(width, in_width_max);
2402
2403         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2404         if (*decim_x > *x_predecim)
2405                 return -EINVAL;
2406
2407         do {
2408                 in_width = width / *decim_x;
2409         } while (*decim_x <= *x_predecim &&
2410                         in_width > maxsinglelinewidth && ++*decim_x);
2411
2412         if (in_width > maxsinglelinewidth) {
2413                 DSSERR("Cannot scale width exceeds max line width");
2414                 return -EINVAL;
2415         }
2416
2417         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2418                                 out_width, out_height, mem_to_mem);
2419         return 0;
2420 }
2421
2422 #define DIV_FRAC(dividend, divisor) \
2423         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2424
2425 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2426                 enum omap_overlay_caps caps,
2427                 const struct omap_video_timings *mgr_timings,
2428                 u16 width, u16 height, u16 out_width, u16 out_height,
2429                 enum omap_color_mode color_mode, bool *five_taps,
2430                 int *x_predecim, int *y_predecim, u16 pos_x,
2431                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2432 {
2433         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2434         const int max_decim_limit = 16;
2435         unsigned long core_clk = 0;
2436         int decim_x, decim_y, ret;
2437
2438         if (width == out_width && height == out_height)
2439                 return 0;
2440
2441         if (pclk == 0 || mgr_timings->pixelclock == 0) {
2442                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2443                 return -EINVAL;
2444         }
2445
2446         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2447                 return -EINVAL;
2448
2449         if (mem_to_mem) {
2450                 *x_predecim = *y_predecim = 1;
2451         } else {
2452                 *x_predecim = max_decim_limit;
2453                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2454                                 dss_has_feature(FEAT_BURST_2D)) ?
2455                                 2 : max_decim_limit;
2456         }
2457
2458         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2459             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2460             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2461             color_mode == OMAP_DSS_COLOR_CLUT8) {
2462                 *x_predecim = 1;
2463                 *y_predecim = 1;
2464                 *five_taps = false;
2465                 return 0;
2466         }
2467
2468         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2469         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2470
2471         if (decim_x > *x_predecim || out_width > width * 8)
2472                 return -EINVAL;
2473
2474         if (decim_y > *y_predecim || out_height > height * 8)
2475                 return -EINVAL;
2476
2477         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2478                 out_width, out_height, color_mode, five_taps,
2479                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2480                 mem_to_mem);
2481         if (ret)
2482                 return ret;
2483
2484         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2485                 width, height,
2486                 out_width, out_height,
2487                 out_width / width, DIV_FRAC(out_width, width),
2488                 out_height / height, DIV_FRAC(out_height, height),
2489
2490                 decim_x, decim_y,
2491                 width / decim_x, height / decim_y,
2492                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2493                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2494
2495                 *five_taps ? 5 : 3,
2496                 core_clk, dispc_core_clk_rate());
2497
2498         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2499                 DSSERR("failed to set up scaling, "
2500                         "required core clk rate = %lu Hz, "
2501                         "current core clk rate = %lu Hz\n",
2502                         core_clk, dispc_core_clk_rate());
2503                 return -EINVAL;
2504         }
2505
2506         *x_predecim = decim_x;
2507         *y_predecim = decim_y;
2508         return 0;
2509 }
2510
2511 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2512                 const struct omap_overlay_info *oi,
2513                 const struct omap_video_timings *timings,
2514                 int *x_predecim, int *y_predecim)
2515 {
2516         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2517         bool five_taps = true;
2518         bool fieldmode = false;
2519         u16 in_height = oi->height;
2520         u16 in_width = oi->width;
2521         bool ilace = timings->interlace;
2522         u16 out_width, out_height;
2523         int pos_x = oi->pos_x;
2524         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2525         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2526
2527         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2528         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2529
2530         if (ilace && oi->height == out_height)
2531                 fieldmode = true;
2532
2533         if (ilace) {
2534                 if (fieldmode)
2535                         in_height /= 2;
2536                 out_height /= 2;
2537
2538                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2539                                 in_height, out_height);
2540         }
2541
2542         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2543                 return -EINVAL;
2544
2545         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2546                         in_height, out_width, out_height, oi->color_mode,
2547                         &five_taps, x_predecim, y_predecim, pos_x,
2548                         oi->rotation_type, false);
2549 }
2550 EXPORT_SYMBOL(dispc_ovl_check);
2551
2552 static int dispc_ovl_setup_common(enum omap_plane plane,
2553                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2554                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2555                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2556                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2557                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2558                 bool replication, const struct omap_video_timings *mgr_timings,
2559                 bool mem_to_mem)
2560 {
2561         bool five_taps = true;
2562         bool fieldmode = false;
2563         int r, cconv = 0;
2564         unsigned offset0, offset1;
2565         s32 row_inc;
2566         s32 pix_inc;
2567         u16 frame_width, frame_height;
2568         unsigned int field_offset = 0;
2569         u16 in_height = height;
2570         u16 in_width = width;
2571         int x_predecim = 1, y_predecim = 1;
2572         bool ilace = mgr_timings->interlace;
2573         unsigned long pclk = dispc_plane_pclk_rate(plane);
2574         unsigned long lclk = dispc_plane_lclk_rate(plane);
2575
2576         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2577                 return -EINVAL;
2578
2579         switch (color_mode) {
2580         case OMAP_DSS_COLOR_YUV2:
2581         case OMAP_DSS_COLOR_UYVY:
2582         case OMAP_DSS_COLOR_NV12:
2583                 if (in_width & 1) {
2584                         DSSERR("input width %d is not even for YUV format\n",
2585                                 in_width);
2586                         return -EINVAL;
2587                 }
2588                 break;
2589
2590         default:
2591                 break;
2592         }
2593
2594         out_width = out_width == 0 ? width : out_width;
2595         out_height = out_height == 0 ? height : out_height;
2596
2597         if (ilace && height == out_height)
2598                 fieldmode = true;
2599
2600         if (ilace) {
2601                 if (fieldmode)
2602                         in_height /= 2;
2603                 pos_y /= 2;
2604                 out_height /= 2;
2605
2606                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2607                         "out_height %d\n", in_height, pos_y,
2608                         out_height);
2609         }
2610
2611         if (!dss_feat_color_mode_supported(plane, color_mode))
2612                 return -EINVAL;
2613
2614         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2615                         in_height, out_width, out_height, color_mode,
2616                         &five_taps, &x_predecim, &y_predecim, pos_x,
2617                         rotation_type, mem_to_mem);
2618         if (r)
2619                 return r;
2620
2621         in_width = in_width / x_predecim;
2622         in_height = in_height / y_predecim;
2623
2624         if (x_predecim > 1 || y_predecim > 1)
2625                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2626                         x_predecim, y_predecim, in_width, in_height);
2627
2628         switch (color_mode) {
2629         case OMAP_DSS_COLOR_YUV2:
2630         case OMAP_DSS_COLOR_UYVY:
2631         case OMAP_DSS_COLOR_NV12:
2632                 if (in_width & 1) {
2633                         DSSDBG("predecimated input width is not even for YUV format\n");
2634                         DSSDBG("adjusting input width %d -> %d\n",
2635                                 in_width, in_width & ~1);
2636
2637                         in_width &= ~1;
2638                 }
2639                 break;
2640
2641         default:
2642                 break;
2643         }
2644
2645         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2646                         color_mode == OMAP_DSS_COLOR_UYVY ||
2647                         color_mode == OMAP_DSS_COLOR_NV12)
2648                 cconv = 1;
2649
2650         if (ilace && !fieldmode) {
2651                 /*
2652                  * when downscaling the bottom field may have to start several
2653                  * source lines below the top field. Unfortunately ACCUI
2654                  * registers will only hold the fractional part of the offset
2655                  * so the integer part must be added to the base address of the
2656                  * bottom field.
2657                  */
2658                 if (!in_height || in_height == out_height)
2659                         field_offset = 0;
2660                 else
2661                         field_offset = in_height / out_height / 2;
2662         }
2663
2664         /* Fields are independent but interleaved in memory. */
2665         if (fieldmode)
2666                 field_offset = 1;
2667
2668         offset0 = 0;
2669         offset1 = 0;
2670         row_inc = 0;
2671         pix_inc = 0;
2672
2673         if (plane == OMAP_DSS_WB) {
2674                 frame_width = out_width;
2675                 frame_height = out_height;
2676         } else {
2677                 frame_width = in_width;
2678                 frame_height = height;
2679         }
2680
2681         if (rotation_type == OMAP_DSS_ROT_TILER)
2682                 calc_tiler_rotation_offset(screen_width, frame_width,
2683                                 color_mode, fieldmode, field_offset,
2684                                 &offset0, &offset1, &row_inc, &pix_inc,
2685                                 x_predecim, y_predecim);
2686         else if (rotation_type == OMAP_DSS_ROT_DMA)
2687                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2688                                 frame_width, frame_height,
2689                                 color_mode, fieldmode, field_offset,
2690                                 &offset0, &offset1, &row_inc, &pix_inc,
2691                                 x_predecim, y_predecim);
2692         else
2693                 calc_vrfb_rotation_offset(rotation, mirror,
2694                                 screen_width, frame_width, frame_height,
2695                                 color_mode, fieldmode, field_offset,
2696                                 &offset0, &offset1, &row_inc, &pix_inc,
2697                                 x_predecim, y_predecim);
2698
2699         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2700                         offset0, offset1, row_inc, pix_inc);
2701
2702         dispc_ovl_set_color_mode(plane, color_mode);
2703
2704         dispc_ovl_configure_burst_type(plane, rotation_type);
2705
2706         dispc_ovl_set_ba0(plane, paddr + offset0);
2707         dispc_ovl_set_ba1(plane, paddr + offset1);
2708
2709         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2710                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2711                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2712         }
2713
2714         if (dispc.feat->last_pixel_inc_missing)
2715                 row_inc += pix_inc - 1;
2716
2717         dispc_ovl_set_row_inc(plane, row_inc);
2718         dispc_ovl_set_pix_inc(plane, pix_inc);
2719
2720         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2721                         in_height, out_width, out_height);
2722
2723         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2724
2725         dispc_ovl_set_input_size(plane, in_width, in_height);
2726
2727         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2728                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2729                                    out_height, ilace, five_taps, fieldmode,
2730                                    color_mode, rotation);
2731                 dispc_ovl_set_output_size(plane, out_width, out_height);
2732                 dispc_ovl_set_vid_color_conv(plane, cconv);
2733         }
2734
2735         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2736                         color_mode);
2737
2738         dispc_ovl_set_zorder(plane, caps, zorder);
2739         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2740         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2741
2742         dispc_ovl_enable_replication(plane, caps, replication);
2743
2744         return 0;
2745 }
2746
2747 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2748                 bool replication, const struct omap_video_timings *mgr_timings,
2749                 bool mem_to_mem)
2750 {
2751         int r;
2752         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2753         enum omap_channel channel;
2754
2755         channel = dispc_ovl_get_channel_out(plane);
2756
2757         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2758                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2759                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2760                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2761                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2762
2763         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2764                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2765                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2766                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2767                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2768
2769         return r;
2770 }
2771 EXPORT_SYMBOL(dispc_ovl_setup);
2772
2773 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2774                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2775 {
2776         int r;
2777         u32 l;
2778         enum omap_plane plane = OMAP_DSS_WB;
2779         const int pos_x = 0, pos_y = 0;
2780         const u8 zorder = 0, global_alpha = 0;
2781         const bool replication = false;
2782         bool truncation;
2783         int in_width = mgr_timings->x_res;
2784         int in_height = mgr_timings->y_res;
2785         enum omap_overlay_caps caps =
2786                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2787
2788         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2789                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2790                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2791                 wi->mirror);
2792
2793         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2794                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2795                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2796                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2797                 replication, mgr_timings, mem_to_mem);
2798
2799         switch (wi->color_mode) {
2800         case OMAP_DSS_COLOR_RGB16:
2801         case OMAP_DSS_COLOR_RGB24P:
2802         case OMAP_DSS_COLOR_ARGB16:
2803         case OMAP_DSS_COLOR_RGBA16:
2804         case OMAP_DSS_COLOR_RGB12U:
2805         case OMAP_DSS_COLOR_ARGB16_1555:
2806         case OMAP_DSS_COLOR_XRGB16_1555:
2807         case OMAP_DSS_COLOR_RGBX16:
2808                 truncation = true;
2809                 break;
2810         default:
2811                 truncation = false;
2812                 break;
2813         }
2814
2815         /* setup extra DISPC_WB_ATTRIBUTES */
2816         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2817         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2818         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2819         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2820
2821         return r;
2822 }
2823
2824 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2825 {
2826         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2827
2828         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2829
2830         return 0;
2831 }
2832 EXPORT_SYMBOL(dispc_ovl_enable);
2833
2834 bool dispc_ovl_enabled(enum omap_plane plane)
2835 {
2836         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2837 }
2838 EXPORT_SYMBOL(dispc_ovl_enabled);
2839
2840 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2841 {
2842         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2843         /* flush posted write */
2844         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2845 }
2846 EXPORT_SYMBOL(dispc_mgr_enable);
2847
2848 bool dispc_mgr_is_enabled(enum omap_channel channel)
2849 {
2850         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2851 }
2852 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2853
2854 void dispc_wb_enable(bool enable)
2855 {
2856         dispc_ovl_enable(OMAP_DSS_WB, enable);
2857 }
2858
2859 bool dispc_wb_is_enabled(void)
2860 {
2861         return dispc_ovl_enabled(OMAP_DSS_WB);
2862 }
2863
2864 static void dispc_lcd_enable_signal_polarity(bool act_high)
2865 {
2866         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2867                 return;
2868
2869         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2870 }
2871
2872 void dispc_lcd_enable_signal(bool enable)
2873 {
2874         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2875                 return;
2876
2877         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2878 }
2879
2880 void dispc_pck_free_enable(bool enable)
2881 {
2882         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2883                 return;
2884
2885         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2886 }
2887
2888 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2889 {
2890         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2891 }
2892
2893
2894 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2895 {
2896         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2897 }
2898
2899 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2900 {
2901         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2902 }
2903
2904
2905 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2906 {
2907         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2908 }
2909
2910 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2911                 enum omap_dss_trans_key_type type,
2912                 u32 trans_key)
2913 {
2914         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2915
2916         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2917 }
2918
2919 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2920 {
2921         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2922 }
2923
2924 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2925                 bool enable)
2926 {
2927         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2928                 return;
2929
2930         if (ch == OMAP_DSS_CHANNEL_LCD)
2931                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2932         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2933                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2934 }
2935
2936 void dispc_mgr_setup(enum omap_channel channel,
2937                 const struct omap_overlay_manager_info *info)
2938 {
2939         dispc_mgr_set_default_color(channel, info->default_color);
2940         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2941         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2942         dispc_mgr_enable_alpha_fixed_zorder(channel,
2943                         info->partial_alpha_enabled);
2944         if (dss_has_feature(FEAT_CPR)) {
2945                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2946                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2947         }
2948 }
2949 EXPORT_SYMBOL(dispc_mgr_setup);
2950
2951 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2952 {
2953         int code;
2954
2955         switch (data_lines) {
2956         case 12:
2957                 code = 0;
2958                 break;
2959         case 16:
2960                 code = 1;
2961                 break;
2962         case 18:
2963                 code = 2;
2964                 break;
2965         case 24:
2966                 code = 3;
2967                 break;
2968         default:
2969                 BUG();
2970                 return;
2971         }
2972
2973         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2974 }
2975
2976 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2977 {
2978         u32 l;
2979         int gpout0, gpout1;
2980
2981         switch (mode) {
2982         case DSS_IO_PAD_MODE_RESET:
2983                 gpout0 = 0;
2984                 gpout1 = 0;
2985                 break;
2986         case DSS_IO_PAD_MODE_RFBI:
2987                 gpout0 = 1;
2988                 gpout1 = 0;
2989                 break;
2990         case DSS_IO_PAD_MODE_BYPASS:
2991                 gpout0 = 1;
2992                 gpout1 = 1;
2993                 break;
2994         default:
2995                 BUG();
2996                 return;
2997         }
2998
2999         l = dispc_read_reg(DISPC_CONTROL);
3000         l = FLD_MOD(l, gpout0, 15, 15);
3001         l = FLD_MOD(l, gpout1, 16, 16);
3002         dispc_write_reg(DISPC_CONTROL, l);
3003 }
3004
3005 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3006 {
3007         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3008 }
3009
3010 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3011                 const struct dss_lcd_mgr_config *config)
3012 {
3013         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3014
3015         dispc_mgr_enable_stallmode(channel, config->stallmode);
3016         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3017
3018         dispc_mgr_set_clock_div(channel, &config->clock_info);
3019
3020         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3021
3022         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3023
3024         dispc_mgr_set_lcd_type_tft(channel);
3025 }
3026 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3027
3028 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3029 {
3030         return width <= dispc.feat->mgr_width_max &&
3031                 height <= dispc.feat->mgr_height_max;
3032 }
3033
3034 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3035                 int vsw, int vfp, int vbp)
3036 {
3037         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3038                         hfp < 1 || hfp > dispc.feat->hp_max ||
3039                         hbp < 1 || hbp > dispc.feat->hp_max ||
3040                         vsw < 1 || vsw > dispc.feat->sw_max ||
3041                         vfp < 0 || vfp > dispc.feat->vp_max ||
3042                         vbp < 0 || vbp > dispc.feat->vp_max)
3043                 return false;
3044         return true;
3045 }
3046
3047 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3048                 unsigned long pclk)
3049 {
3050         if (dss_mgr_is_lcd(channel))
3051                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3052         else
3053                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3054 }
3055
3056 bool dispc_mgr_timings_ok(enum omap_channel channel,
3057                 const struct omap_video_timings *timings)
3058 {
3059         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3060                 return false;
3061
3062         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3063                 return false;
3064
3065         if (dss_mgr_is_lcd(channel)) {
3066                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3067                 if (timings->interlace)
3068                         return false;
3069
3070                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3071                                 timings->hbp, timings->vsw, timings->vfp,
3072                                 timings->vbp))
3073                         return false;
3074         }
3075
3076         return true;
3077 }
3078
3079 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3080                 int hfp, int hbp, int vsw, int vfp, int vbp,
3081                 enum omap_dss_signal_level vsync_level,
3082                 enum omap_dss_signal_level hsync_level,
3083                 enum omap_dss_signal_edge data_pclk_edge,
3084                 enum omap_dss_signal_level de_level,
3085                 enum omap_dss_signal_edge sync_pclk_edge)
3086
3087 {
3088         u32 timing_h, timing_v, l;
3089         bool onoff, rf, ipc, vs, hs, de;
3090
3091         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3092                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3093                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3094         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3095                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3096                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3097
3098         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3099         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3100
3101         switch (vsync_level) {
3102         case OMAPDSS_SIG_ACTIVE_LOW:
3103                 vs = true;
3104                 break;
3105         case OMAPDSS_SIG_ACTIVE_HIGH:
3106                 vs = false;
3107                 break;
3108         default:
3109                 BUG();
3110         }
3111
3112         switch (hsync_level) {
3113         case OMAPDSS_SIG_ACTIVE_LOW:
3114                 hs = true;
3115                 break;
3116         case OMAPDSS_SIG_ACTIVE_HIGH:
3117                 hs = false;
3118                 break;
3119         default:
3120                 BUG();
3121         }
3122
3123         switch (de_level) {
3124         case OMAPDSS_SIG_ACTIVE_LOW:
3125                 de = true;
3126                 break;
3127         case OMAPDSS_SIG_ACTIVE_HIGH:
3128                 de = false;
3129                 break;
3130         default:
3131                 BUG();
3132         }
3133
3134         switch (data_pclk_edge) {
3135         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3136                 ipc = false;
3137                 break;
3138         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3139                 ipc = true;
3140                 break;
3141         default:
3142                 BUG();
3143         }
3144
3145         /* always use the 'rf' setting */
3146         onoff = true;
3147
3148         switch (sync_pclk_edge) {
3149         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3150                 rf = false;
3151                 break;
3152         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3153                 rf = true;
3154                 break;
3155         default:
3156                 BUG();
3157         }
3158
3159         l = FLD_VAL(onoff, 17, 17) |
3160                 FLD_VAL(rf, 16, 16) |
3161                 FLD_VAL(de, 15, 15) |
3162                 FLD_VAL(ipc, 14, 14) |
3163                 FLD_VAL(hs, 13, 13) |
3164                 FLD_VAL(vs, 12, 12);
3165
3166         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3167
3168         if (dispc.syscon_pol) {
3169                 const int shifts[] = {
3170                         [OMAP_DSS_CHANNEL_LCD] = 0,
3171                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3172                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3173                 };
3174
3175                 u32 mask, val;
3176
3177                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3178                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3179
3180                 mask <<= 16 + shifts[channel];
3181                 val <<= 16 + shifts[channel];
3182
3183                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3184                         mask, val);
3185         }
3186 }
3187
3188 /* change name to mode? */
3189 void dispc_mgr_set_timings(enum omap_channel channel,
3190                 const struct omap_video_timings *timings)
3191 {
3192         unsigned xtot, ytot;
3193         unsigned long ht, vt;
3194         struct omap_video_timings t = *timings;
3195
3196         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3197
3198         if (!dispc_mgr_timings_ok(channel, &t)) {
3199                 BUG();
3200                 return;
3201         }
3202
3203         if (dss_mgr_is_lcd(channel)) {
3204                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3205                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3206                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3207
3208                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3209                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3210
3211                 ht = timings->pixelclock / xtot;
3212                 vt = timings->pixelclock / xtot / ytot;
3213
3214                 DSSDBG("pck %u\n", timings->pixelclock);
3215                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3216                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3217                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3218                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3219                         t.de_level, t.sync_pclk_edge);
3220
3221                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3222         } else {
3223                 if (t.interlace == true)
3224                         t.y_res /= 2;
3225         }
3226
3227         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3228 }
3229 EXPORT_SYMBOL(dispc_mgr_set_timings);
3230
3231 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3232                 u16 pck_div)
3233 {
3234         BUG_ON(lck_div < 1);
3235         BUG_ON(pck_div < 1);
3236
3237         dispc_write_reg(DISPC_DIVISORo(channel),
3238                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3239
3240         if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3241                         channel == OMAP_DSS_CHANNEL_LCD)
3242                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3243 }
3244
3245 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3246                 int *pck_div)
3247 {
3248         u32 l;
3249         l = dispc_read_reg(DISPC_DIVISORo(channel));
3250         *lck_div = FLD_GET(l, 23, 16);
3251         *pck_div = FLD_GET(l, 7, 0);
3252 }
3253
3254 unsigned long dispc_fclk_rate(void)
3255 {
3256         struct dss_pll *pll;
3257         unsigned long r = 0;
3258
3259         switch (dss_get_dispc_clk_source()) {
3260         case OMAP_DSS_CLK_SRC_FCK:
3261                 r = dss_get_dispc_clk_rate();
3262                 break;
3263         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3264                 pll = dss_pll_find("dsi0");
3265                 if (!pll)
3266                         pll = dss_pll_find("video0");
3267
3268                 r = pll->cinfo.clkout[0];
3269                 break;
3270         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3271                 pll = dss_pll_find("dsi1");
3272                 if (!pll)
3273                         pll = dss_pll_find("video1");
3274
3275                 r = pll->cinfo.clkout[0];
3276                 break;
3277         default:
3278                 BUG();
3279                 return 0;
3280         }
3281
3282         return r;
3283 }
3284
3285 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3286 {
3287         struct dss_pll *pll;
3288         int lcd;
3289         unsigned long r;
3290         u32 l;
3291
3292         if (dss_mgr_is_lcd(channel)) {
3293                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3294
3295                 lcd = FLD_GET(l, 23, 16);
3296
3297                 switch (dss_get_lcd_clk_source(channel)) {
3298                 case OMAP_DSS_CLK_SRC_FCK:
3299                         r = dss_get_dispc_clk_rate();
3300                         break;
3301                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3302                         pll = dss_pll_find("dsi0");
3303                         if (!pll)
3304                                 pll = dss_pll_find("video0");
3305
3306                         r = pll->cinfo.clkout[0];
3307                         break;
3308                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3309                         pll = dss_pll_find("dsi1");
3310                         if (!pll)
3311                                 pll = dss_pll_find("video1");
3312
3313                         r = pll->cinfo.clkout[0];
3314                         break;
3315                 default:
3316                         BUG();
3317                         return 0;
3318                 }
3319
3320                 return r / lcd;
3321         } else {
3322                 return dispc_fclk_rate();
3323         }
3324 }
3325
3326 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3327 {
3328         unsigned long r;
3329
3330         if (dss_mgr_is_lcd(channel)) {
3331                 int pcd;
3332                 u32 l;
3333
3334                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3335
3336                 pcd = FLD_GET(l, 7, 0);
3337
3338                 r = dispc_mgr_lclk_rate(channel);
3339
3340                 return r / pcd;
3341         } else {
3342                 return dispc.tv_pclk_rate;
3343         }
3344 }
3345
3346 void dispc_set_tv_pclk(unsigned long pclk)
3347 {
3348         dispc.tv_pclk_rate = pclk;
3349 }
3350
3351 unsigned long dispc_core_clk_rate(void)
3352 {
3353         return dispc.core_clk_rate;
3354 }
3355
3356 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3357 {
3358         enum omap_channel channel;
3359
3360         if (plane == OMAP_DSS_WB)
3361                 return 0;
3362
3363         channel = dispc_ovl_get_channel_out(plane);
3364
3365         return dispc_mgr_pclk_rate(channel);
3366 }
3367
3368 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3369 {
3370         enum omap_channel channel;
3371
3372         if (plane == OMAP_DSS_WB)
3373                 return 0;
3374
3375         channel = dispc_ovl_get_channel_out(plane);
3376
3377         return dispc_mgr_lclk_rate(channel);
3378 }
3379
3380 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3381 {
3382         int lcd, pcd;
3383         enum omap_dss_clk_source lcd_clk_src;
3384
3385         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3386
3387         lcd_clk_src = dss_get_lcd_clk_source(channel);
3388
3389         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3390                 dss_get_generic_clk_source_name(lcd_clk_src),
3391                 dss_feat_get_clk_source_name(lcd_clk_src));
3392
3393         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3394
3395         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3396                 dispc_mgr_lclk_rate(channel), lcd);
3397         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3398                 dispc_mgr_pclk_rate(channel), pcd);
3399 }
3400
3401 void dispc_dump_clocks(struct seq_file *s)
3402 {
3403         int lcd;
3404         u32 l;
3405         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3406
3407         if (dispc_runtime_get())
3408                 return;
3409
3410         seq_printf(s, "- DISPC -\n");
3411
3412         seq_printf(s, "dispc fclk source = %s (%s)\n",
3413                         dss_get_generic_clk_source_name(dispc_clk_src),
3414                         dss_feat_get_clk_source_name(dispc_clk_src));
3415
3416         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3417
3418         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3419                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3420                 l = dispc_read_reg(DISPC_DIVISOR);
3421                 lcd = FLD_GET(l, 23, 16);
3422
3423                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3424                                 (dispc_fclk_rate()/lcd), lcd);
3425         }
3426
3427         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3428
3429         if (dss_has_feature(FEAT_MGR_LCD2))
3430                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3431         if (dss_has_feature(FEAT_MGR_LCD3))
3432                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3433
3434         dispc_runtime_put();
3435 }
3436
3437 static void dispc_dump_regs(struct seq_file *s)
3438 {
3439         int i, j;
3440         const char *mgr_names[] = {
3441                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3442                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3443                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3444                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3445         };
3446         const char *ovl_names[] = {
3447                 [OMAP_DSS_GFX]          = "GFX",
3448                 [OMAP_DSS_VIDEO1]       = "VID1",
3449                 [OMAP_DSS_VIDEO2]       = "VID2",
3450                 [OMAP_DSS_VIDEO3]       = "VID3",
3451         };
3452         const char **p_names;
3453
3454 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3455
3456         if (dispc_runtime_get())
3457                 return;
3458
3459         /* DISPC common registers */
3460         DUMPREG(DISPC_REVISION);
3461         DUMPREG(DISPC_SYSCONFIG);
3462         DUMPREG(DISPC_SYSSTATUS);
3463         DUMPREG(DISPC_IRQSTATUS);
3464         DUMPREG(DISPC_IRQENABLE);
3465         DUMPREG(DISPC_CONTROL);
3466         DUMPREG(DISPC_CONFIG);
3467         DUMPREG(DISPC_CAPABLE);
3468         DUMPREG(DISPC_LINE_STATUS);
3469         DUMPREG(DISPC_LINE_NUMBER);
3470         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3471                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3472                 DUMPREG(DISPC_GLOBAL_ALPHA);
3473         if (dss_has_feature(FEAT_MGR_LCD2)) {
3474                 DUMPREG(DISPC_CONTROL2);
3475                 DUMPREG(DISPC_CONFIG2);
3476         }
3477         if (dss_has_feature(FEAT_MGR_LCD3)) {
3478                 DUMPREG(DISPC_CONTROL3);
3479                 DUMPREG(DISPC_CONFIG3);
3480         }
3481         if (dss_has_feature(FEAT_MFLAG))
3482                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3483
3484 #undef DUMPREG
3485
3486 #define DISPC_REG(i, name) name(i)
3487 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3488         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3489         dispc_read_reg(DISPC_REG(i, r)))
3490
3491         p_names = mgr_names;
3492
3493         /* DISPC channel specific registers */
3494         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3495                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3496                 DUMPREG(i, DISPC_TRANS_COLOR);
3497                 DUMPREG(i, DISPC_SIZE_MGR);
3498
3499                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3500                         continue;
3501
3502                 DUMPREG(i, DISPC_TIMING_H);
3503                 DUMPREG(i, DISPC_TIMING_V);
3504                 DUMPREG(i, DISPC_POL_FREQ);
3505                 DUMPREG(i, DISPC_DIVISORo);
3506
3507                 DUMPREG(i, DISPC_DATA_CYCLE1);
3508                 DUMPREG(i, DISPC_DATA_CYCLE2);
3509                 DUMPREG(i, DISPC_DATA_CYCLE3);
3510
3511                 if (dss_has_feature(FEAT_CPR)) {
3512                         DUMPREG(i, DISPC_CPR_COEF_R);
3513                         DUMPREG(i, DISPC_CPR_COEF_G);
3514                         DUMPREG(i, DISPC_CPR_COEF_B);
3515                 }
3516         }
3517
3518         p_names = ovl_names;
3519
3520         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3521                 DUMPREG(i, DISPC_OVL_BA0);
3522                 DUMPREG(i, DISPC_OVL_BA1);
3523                 DUMPREG(i, DISPC_OVL_POSITION);
3524                 DUMPREG(i, DISPC_OVL_SIZE);
3525                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3526                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3527                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3528                 DUMPREG(i, DISPC_OVL_ROW_INC);
3529                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3530
3531                 if (dss_has_feature(FEAT_PRELOAD))
3532                         DUMPREG(i, DISPC_OVL_PRELOAD);
3533                 if (dss_has_feature(FEAT_MFLAG))
3534                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3535
3536                 if (i == OMAP_DSS_GFX) {
3537                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3538                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3539                         continue;
3540                 }
3541
3542                 DUMPREG(i, DISPC_OVL_FIR);
3543                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3544                 DUMPREG(i, DISPC_OVL_ACCU0);
3545                 DUMPREG(i, DISPC_OVL_ACCU1);
3546                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3547                         DUMPREG(i, DISPC_OVL_BA0_UV);
3548                         DUMPREG(i, DISPC_OVL_BA1_UV);
3549                         DUMPREG(i, DISPC_OVL_FIR2);
3550                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3551                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3552                 }
3553                 if (dss_has_feature(FEAT_ATTR2))
3554                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3555         }
3556
3557 #undef DISPC_REG
3558 #undef DUMPREG
3559
3560 #define DISPC_REG(plane, name, i) name(plane, i)
3561 #define DUMPREG(plane, name, i) \
3562         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3563         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3564         dispc_read_reg(DISPC_REG(plane, name, i)))
3565
3566         /* Video pipeline coefficient registers */
3567
3568         /* start from OMAP_DSS_VIDEO1 */
3569         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3570                 for (j = 0; j < 8; j++)
3571                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3572
3573                 for (j = 0; j < 8; j++)
3574                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3575
3576                 for (j = 0; j < 5; j++)
3577                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3578
3579                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3580                         for (j = 0; j < 8; j++)
3581                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3582                 }
3583
3584                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3585                         for (j = 0; j < 8; j++)
3586                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3587
3588                         for (j = 0; j < 8; j++)
3589                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3590
3591                         for (j = 0; j < 8; j++)
3592                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3593                 }
3594         }
3595
3596         dispc_runtime_put();
3597
3598 #undef DISPC_REG
3599 #undef DUMPREG
3600 }
3601
3602 /* calculate clock rates using dividers in cinfo */
3603 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3604                 struct dispc_clock_info *cinfo)
3605 {
3606         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3607                 return -EINVAL;
3608         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3609                 return -EINVAL;
3610
3611         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3612         cinfo->pck = cinfo->lck / cinfo->pck_div;
3613
3614         return 0;
3615 }
3616
3617 bool dispc_div_calc(unsigned long dispc,
3618                 unsigned long pck_min, unsigned long pck_max,
3619                 dispc_div_calc_func func, void *data)
3620 {
3621         int lckd, lckd_start, lckd_stop;
3622         int pckd, pckd_start, pckd_stop;
3623         unsigned long pck, lck;
3624         unsigned long lck_max;
3625         unsigned long pckd_hw_min, pckd_hw_max;
3626         unsigned min_fck_per_pck;
3627         unsigned long fck;
3628
3629 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3630         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3631 #else
3632         min_fck_per_pck = 0;
3633 #endif
3634
3635         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3636         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3637
3638         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3639
3640         pck_min = pck_min ? pck_min : 1;
3641         pck_max = pck_max ? pck_max : ULONG_MAX;
3642
3643         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3644         lckd_stop = min(dispc / pck_min, 255ul);
3645
3646         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3647                 lck = dispc / lckd;
3648
3649                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3650                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3651
3652                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3653                         pck = lck / pckd;
3654
3655                         /*
3656                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3657                          * clock, which means we're configuring DISPC fclk here
3658                          * also. Thus we need to use the calculated lck. For
3659                          * OMAP4+ the DISPC fclk is a separate clock.
3660                          */
3661                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3662                                 fck = dispc_core_clk_rate();
3663                         else
3664                                 fck = lck;
3665
3666                         if (fck < pck * min_fck_per_pck)
3667                                 continue;
3668
3669                         if (func(lckd, pckd, lck, pck, data))
3670                                 return true;
3671                 }
3672         }
3673
3674         return false;
3675 }
3676
3677 void dispc_mgr_set_clock_div(enum omap_channel channel,
3678                 const struct dispc_clock_info *cinfo)
3679 {
3680         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3681         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3682
3683         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3684 }
3685
3686 int dispc_mgr_get_clock_div(enum omap_channel channel,
3687                 struct dispc_clock_info *cinfo)
3688 {
3689         unsigned long fck;
3690
3691         fck = dispc_fclk_rate();
3692
3693         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3694         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3695
3696         cinfo->lck = fck / cinfo->lck_div;
3697         cinfo->pck = cinfo->lck / cinfo->pck_div;
3698
3699         return 0;
3700 }
3701
3702 u32 dispc_read_irqstatus(void)
3703 {
3704         return dispc_read_reg(DISPC_IRQSTATUS);
3705 }
3706 EXPORT_SYMBOL(dispc_read_irqstatus);
3707
3708 void dispc_clear_irqstatus(u32 mask)
3709 {
3710         dispc_write_reg(DISPC_IRQSTATUS, mask);
3711 }
3712 EXPORT_SYMBOL(dispc_clear_irqstatus);
3713
3714 u32 dispc_read_irqenable(void)
3715 {
3716         return dispc_read_reg(DISPC_IRQENABLE);
3717 }
3718 EXPORT_SYMBOL(dispc_read_irqenable);
3719
3720 void dispc_write_irqenable(u32 mask)
3721 {
3722         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3723
3724         /* clear the irqstatus for newly enabled irqs */
3725         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3726
3727         dispc_write_reg(DISPC_IRQENABLE, mask);
3728 }
3729 EXPORT_SYMBOL(dispc_write_irqenable);
3730
3731 void dispc_enable_sidle(void)
3732 {
3733         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3734 }
3735
3736 void dispc_disable_sidle(void)
3737 {
3738         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3739 }
3740
3741 static void _omap_dispc_initial_config(void)
3742 {
3743         u32 l;
3744
3745         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3746         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3747                 l = dispc_read_reg(DISPC_DIVISOR);
3748                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3749                 l = FLD_MOD(l, 1, 0, 0);
3750                 l = FLD_MOD(l, 1, 23, 16);
3751                 dispc_write_reg(DISPC_DIVISOR, l);
3752
3753                 dispc.core_clk_rate = dispc_fclk_rate();
3754         }
3755
3756         /* FUNCGATED */
3757         if (dss_has_feature(FEAT_FUNCGATED))
3758                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3759
3760         dispc_setup_color_conv_coef();
3761
3762         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3763
3764         dispc_init_fifos();
3765
3766         dispc_configure_burst_sizes();
3767
3768         dispc_ovl_enable_zorder_planes();
3769
3770         if (dispc.feat->mstandby_workaround)
3771                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3772
3773         if (dss_has_feature(FEAT_MFLAG))
3774                 dispc_init_mflag();
3775 }
3776
3777 static const struct dispc_features omap24xx_dispc_feats = {
3778         .sw_start               =       5,
3779         .fp_start               =       15,
3780         .bp_start               =       27,
3781         .sw_max                 =       64,
3782         .vp_max                 =       255,
3783         .hp_max                 =       256,
3784         .mgr_width_start        =       10,
3785         .mgr_height_start       =       26,
3786         .mgr_width_max          =       2048,
3787         .mgr_height_max         =       2048,
3788         .max_lcd_pclk           =       66500000,
3789         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3790         .calc_core_clk          =       calc_core_clk_24xx,
3791         .num_fifos              =       3,
3792         .no_framedone_tv        =       true,
3793         .set_max_preload        =       false,
3794         .last_pixel_inc_missing =       true,
3795 };
3796
3797 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3798         .sw_start               =       5,
3799         .fp_start               =       15,
3800         .bp_start               =       27,
3801         .sw_max                 =       64,
3802         .vp_max                 =       255,
3803         .hp_max                 =       256,
3804         .mgr_width_start        =       10,
3805         .mgr_height_start       =       26,
3806         .mgr_width_max          =       2048,
3807         .mgr_height_max         =       2048,
3808         .max_lcd_pclk           =       173000000,
3809         .max_tv_pclk            =       59000000,
3810         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3811         .calc_core_clk          =       calc_core_clk_34xx,
3812         .num_fifos              =       3,
3813         .no_framedone_tv        =       true,
3814         .set_max_preload        =       false,
3815         .last_pixel_inc_missing =       true,
3816 };
3817
3818 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3819         .sw_start               =       7,
3820         .fp_start               =       19,
3821         .bp_start               =       31,
3822         .sw_max                 =       256,
3823         .vp_max                 =       4095,
3824         .hp_max                 =       4096,
3825         .mgr_width_start        =       10,
3826         .mgr_height_start       =       26,
3827         .mgr_width_max          =       2048,
3828         .mgr_height_max         =       2048,
3829         .max_lcd_pclk           =       173000000,
3830         .max_tv_pclk            =       59000000,
3831         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3832         .calc_core_clk          =       calc_core_clk_34xx,
3833         .num_fifos              =       3,
3834         .no_framedone_tv        =       true,
3835         .set_max_preload        =       false,
3836         .last_pixel_inc_missing =       true,
3837 };
3838
3839 static const struct dispc_features omap44xx_dispc_feats = {
3840         .sw_start               =       7,
3841         .fp_start               =       19,
3842         .bp_start               =       31,
3843         .sw_max                 =       256,
3844         .vp_max                 =       4095,
3845         .hp_max                 =       4096,
3846         .mgr_width_start        =       10,
3847         .mgr_height_start       =       26,
3848         .mgr_width_max          =       2048,
3849         .mgr_height_max         =       2048,
3850         .max_lcd_pclk           =       170000000,
3851         .max_tv_pclk            =       185625000,
3852         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3853         .calc_core_clk          =       calc_core_clk_44xx,
3854         .num_fifos              =       5,
3855         .gfx_fifo_workaround    =       true,
3856         .set_max_preload        =       true,
3857 };
3858
3859 static const struct dispc_features omap54xx_dispc_feats = {
3860         .sw_start               =       7,
3861         .fp_start               =       19,
3862         .bp_start               =       31,
3863         .sw_max                 =       256,
3864         .vp_max                 =       4095,
3865         .hp_max                 =       4096,
3866         .mgr_width_start        =       11,
3867         .mgr_height_start       =       27,
3868         .mgr_width_max          =       4096,
3869         .mgr_height_max         =       4096,
3870         .max_lcd_pclk           =       170000000,
3871         .max_tv_pclk            =       186000000,
3872         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3873         .calc_core_clk          =       calc_core_clk_44xx,
3874         .num_fifos              =       5,
3875         .gfx_fifo_workaround    =       true,
3876         .mstandby_workaround    =       true,
3877         .set_max_preload        =       true,
3878 };
3879
3880 static int dispc_init_features(struct platform_device *pdev)
3881 {
3882         const struct dispc_features *src;
3883         struct dispc_features *dst;
3884
3885         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3886         if (!dst) {
3887                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3888                 return -ENOMEM;
3889         }
3890
3891         switch (omapdss_get_version()) {
3892         case OMAPDSS_VER_OMAP24xx:
3893                 src = &omap24xx_dispc_feats;
3894                 break;
3895
3896         case OMAPDSS_VER_OMAP34xx_ES1:
3897                 src = &omap34xx_rev1_0_dispc_feats;
3898                 break;
3899
3900         case OMAPDSS_VER_OMAP34xx_ES3:
3901         case OMAPDSS_VER_OMAP3630:
3902         case OMAPDSS_VER_AM35xx:
3903         case OMAPDSS_VER_AM43xx:
3904                 src = &omap34xx_rev3_0_dispc_feats;
3905                 break;
3906
3907         case OMAPDSS_VER_OMAP4430_ES1:
3908         case OMAPDSS_VER_OMAP4430_ES2:
3909         case OMAPDSS_VER_OMAP4:
3910                 src = &omap44xx_dispc_feats;
3911                 break;
3912
3913         case OMAPDSS_VER_OMAP5:
3914         case OMAPDSS_VER_DRA7xx:
3915                 src = &omap54xx_dispc_feats;
3916                 break;
3917
3918         default:
3919                 return -ENODEV;
3920         }
3921
3922         memcpy(dst, src, sizeof(*dst));
3923         dispc.feat = dst;
3924
3925         return 0;
3926 }
3927
3928 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3929 {
3930         if (!dispc.is_enabled)
3931                 return IRQ_NONE;
3932
3933         return dispc.user_handler(irq, dispc.user_data);
3934 }
3935
3936 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3937 {
3938         int r;
3939
3940         if (dispc.user_handler != NULL)
3941                 return -EBUSY;
3942
3943         dispc.user_handler = handler;
3944         dispc.user_data = dev_id;
3945
3946         /* ensure the dispc_irq_handler sees the values above */
3947         smp_wmb();
3948
3949         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3950                              IRQF_SHARED, "OMAP DISPC", &dispc);
3951         if (r) {
3952                 dispc.user_handler = NULL;
3953                 dispc.user_data = NULL;
3954         }
3955
3956         return r;
3957 }
3958 EXPORT_SYMBOL(dispc_request_irq);
3959
3960 void dispc_free_irq(void *dev_id)
3961 {
3962         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3963
3964         dispc.user_handler = NULL;
3965         dispc.user_data = NULL;
3966 }
3967 EXPORT_SYMBOL(dispc_free_irq);
3968
3969 /* DISPC HW IP initialisation */
3970 static int dispc_bind(struct device *dev, struct device *master, void *data)
3971 {
3972         struct platform_device *pdev = to_platform_device(dev);
3973         u32 rev;
3974         int r = 0;
3975         struct resource *dispc_mem;
3976         struct device_node *np = pdev->dev.of_node;
3977
3978         dispc.pdev = pdev;
3979
3980         spin_lock_init(&dispc.control_lock);
3981
3982         r = dispc_init_features(dispc.pdev);
3983         if (r)
3984                 return r;
3985
3986         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3987         if (!dispc_mem) {
3988                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3989                 return -EINVAL;
3990         }
3991
3992         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3993                                   resource_size(dispc_mem));
3994         if (!dispc.base) {
3995                 DSSERR("can't ioremap DISPC\n");
3996                 return -ENOMEM;
3997         }
3998
3999         dispc.irq = platform_get_irq(dispc.pdev, 0);
4000         if (dispc.irq < 0) {
4001                 DSSERR("platform_get_irq failed\n");
4002                 return -ENODEV;
4003         }
4004
4005         if (np && of_property_read_bool(np, "syscon-pol")) {
4006                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4007                 if (IS_ERR(dispc.syscon_pol)) {
4008                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4009                         return PTR_ERR(dispc.syscon_pol);
4010                 }
4011
4012                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4013                                 &dispc.syscon_pol_offset)) {
4014                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4015                         return -EINVAL;
4016                 }
4017         }
4018
4019         pm_runtime_enable(&pdev->dev);
4020
4021         r = dispc_runtime_get();
4022         if (r)
4023                 goto err_runtime_get;
4024
4025         _omap_dispc_initial_config();
4026
4027         rev = dispc_read_reg(DISPC_REVISION);
4028         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4029                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4030
4031         dispc_runtime_put();
4032
4033         dss_init_overlay_managers();
4034
4035         dss_debugfs_create_file("dispc", dispc_dump_regs);
4036
4037         return 0;
4038
4039 err_runtime_get:
4040         pm_runtime_disable(&pdev->dev);
4041         return r;
4042 }
4043
4044 static void dispc_unbind(struct device *dev, struct device *master,
4045                                void *data)
4046 {
4047         pm_runtime_disable(dev);
4048
4049         dss_uninit_overlay_managers();
4050 }
4051
4052 static const struct component_ops dispc_component_ops = {
4053         .bind   = dispc_bind,
4054         .unbind = dispc_unbind,
4055 };
4056
4057 static int dispc_probe(struct platform_device *pdev)
4058 {
4059         return component_add(&pdev->dev, &dispc_component_ops);
4060 }
4061
4062 static int dispc_remove(struct platform_device *pdev)
4063 {
4064         component_del(&pdev->dev, &dispc_component_ops);
4065         return 0;
4066 }
4067
4068 static int dispc_runtime_suspend(struct device *dev)
4069 {
4070         dispc.is_enabled = false;
4071         /* ensure the dispc_irq_handler sees the is_enabled value */
4072         smp_wmb();
4073         /* wait for current handler to finish before turning the DISPC off */
4074         synchronize_irq(dispc.irq);
4075
4076         dispc_save_context();
4077
4078         return 0;
4079 }
4080
4081 static int dispc_runtime_resume(struct device *dev)
4082 {
4083         /*
4084          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4085          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4086          * _omap_dispc_initial_config(). We can thus use it to detect if
4087          * we have lost register context.
4088          */
4089         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4090                 _omap_dispc_initial_config();
4091
4092                 dispc_restore_context();
4093         }
4094
4095         dispc.is_enabled = true;
4096         /* ensure the dispc_irq_handler sees the is_enabled value */
4097         smp_wmb();
4098
4099         return 0;
4100 }
4101
4102 static const struct dev_pm_ops dispc_pm_ops = {
4103         .runtime_suspend = dispc_runtime_suspend,
4104         .runtime_resume = dispc_runtime_resume,
4105 };
4106
4107 static const struct of_device_id dispc_of_match[] = {
4108         { .compatible = "ti,omap2-dispc", },
4109         { .compatible = "ti,omap3-dispc", },
4110         { .compatible = "ti,omap4-dispc", },
4111         { .compatible = "ti,omap5-dispc", },
4112         { .compatible = "ti,dra7-dispc", },
4113         {},
4114 };
4115
4116 static struct platform_driver omap_dispchw_driver = {
4117         .probe          = dispc_probe,
4118         .remove         = dispc_remove,
4119         .driver         = {
4120                 .name   = "omapdss_dispc",
4121                 .pm     = &dispc_pm_ops,
4122                 .of_match_table = dispc_of_match,
4123                 .suppress_bind_attrs = true,
4124         },
4125 };
4126
4127 int __init dispc_init_platform_driver(void)
4128 {
4129         return platform_driver_register(&omap_dispchw_driver);
4130 }
4131
4132 void dispc_uninit_platform_driver(void)
4133 {
4134         platform_driver_unregister(&omap_dispchw_driver);
4135 }